Pattern recognition device and automatic extinction ratio control system

Abstract

This invention provides a pattern recognition device and an automatic extinction ratio control system. In the pattern recognition device, the conversion module can convert the differential input signal and output a pattern reference signal. The pattern counter can count the number of times the pattern reference signal flips from 0 to 1 within one sampling clock cycle. The output counting result includes information about short pattern signals, avoiding the problem of short pattern signal loss. The processing module determines the final control signal based on the counting result, the preset control reference value, and the pre-received working status identifier and burst signal identifier, and sends it to the preset automatic extinction ratio control circuit, which can improve the stability of the loop control of the automatic extinction ratio control circuit.

Description

Technical Field

[0001] This invention relates to the field of laser technology, and in particular to a pattern recognition device and an automatic extinction ratio control system. Background Technology

[0002] In the Automatic Exposure Control (AER) scheme used in high-speed laser driver circuits exceeding 10Gbps, the large parasitic capacitance of the MPD (Motor Photo Diode) output in the feedback loop, coupled with the need for low power consumption and high reliability in the AER loop, often prevents the design of a high-speed TIA (Transimpedance Amplifier) ​​to reduce input impedance. This results in excessively low bandwidth at the TIA input, making it impossible to identify high-speed signals with short code patterns such as 0101, and even more difficult to correctly determine the characteristics of the feedback signal. Furthermore, due to the loss of short code pattern signals in feedback, in some cases, such as the ONU (Optical Network Unit) registration phase of a PON (Passive Optical Network) system, there may be prolonged short code patterns, leading to unidirectional overshoot in the AER loop, decreased stability, and even AER loop malfunction due to the excessive duration of short code pattern signals. Summary of the Invention

[0003] The purpose of this invention is to provide a pattern recognition device and an automatic extinction ratio control system to improve the stability of the loop control of the automatic extinction ratio control circuit.

[0004] This invention provides a pattern recognition device, comprising: a conversion module for receiving a differential input signal, converting the differential input signal, and outputting a pattern reference signal; a sampling clock for generating a clock signal; a pattern counter for receiving the pattern reference signal and the clock signal, counting the number of times the pattern reference signal flips from 0 to 1 within the current sampling clock cycle, and outputting a counting result; wherein the counting result indicates whether a short pattern signal exists in the differential input signal within the sampling clock cycle; and a processing module for receiving the counting result, and outputting a control signal based on the counting result, a preset control reference value, and a pre-received working status identifier and burst signal identifier, sending the control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit determines whether to freeze the current control value output by the automatic extinction ratio control circuit based on the control signal; wherein the working status identifier indicates whether the automatic extinction ratio control circuit is in a working state, and the burst signal identifier indicates whether the differential input signal is a burst packet signal.

[0005] Furthermore, the processing module includes: a digital comparator, used to receive the counting result, compare the counting result with a preset control reference value, and output a comparison result; and a signal generation module, used to receive the comparison result, perform logical processing on the comparison result, a pre-received working status identifier, and a burst signal identifier, and output a control signal.

[0006] Furthermore, the signal generation module includes: a first AND gate, used to perform logical operations on the comparison result and the pre-received working status identifier, and output a first logical signal; a NOT gate, used to perform logical operations on the first logical signal, and output a second logical signal; and a second AND gate, used to perform logical operations on the second logical signal and the burst signal identifier, and output a control signal.

[0007] Furthermore, when the counting result is less than the control reference value, the comparison result is low; when the counting result is greater than the control reference value, the comparison result is high; when the counting result is equal to the control reference value, the comparison result of the previous output is maintained.

[0008] Furthermore, the differential input signal is a CML logic signal, and the code pattern reference signal is a CMOS logic signal.

[0009] Furthermore, the code pattern counter is also used to: after sending the counting result corresponding to the current sampling clock cycle to the processing module, wait for a preset time and clear the counting result; take the next sampling clock cycle as the new current sampling clock cycle and repeatedly perform the step of counting the number of times the code pattern reference signal flips from 0 to 1 within the current sampling clock cycle.

[0010] Furthermore, the sampling clock period of the clock signal is less than or equal to a first preset period and greater than a second preset period; wherein, the first preset period is greater than the second preset period; the first preset period is the preset shortest clock period corresponding to the automatic extinction ratio control circuit; and the second preset period is the period corresponding to the preset highest rate code reference signal.

[0011] Furthermore, the processing module is also configured to: if the control signal is low, send the low-level control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit freezes the current control value output by the automatic extinction ratio control circuit according to the low-level control signal; if the control signal is high, send the high-level control signal to the automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit adjusts the current control value output by the automatic extinction ratio control circuit according to the high-level control signal.

[0012] Furthermore, all the switching transistors in the conversion module are high-speed switching transistors.

[0013] This invention provides an automatic extinction ratio control system, comprising: a laser driving unit, a switching unit, a current source, a laser, a laser feedback unit, a reference signal unit, an automatic extinction ratio control circuit, and a pattern recognition device as described above; the laser driving unit receives a differential input signal and outputs a switching control signal, controlling the switching unit to turn on or off according to the switching control signal; the current source provides current to the laser when the switching unit is turned on, enabling the laser to emit laser light; the laser feedback unit generates a feedback signal based on the laser light emitted by the laser and sends it to the automatic extinction ratio control circuit. The control circuit includes a reference signal unit for generating a preset reference signal and sending it to the automatic extinction ratio control circuit. The pattern recognizer receives the differential input signal, a preset control reference value, a working status identifier, and a burst signal identifier. Based on these parameters, it outputs a control signal and sends it to the automatic extinction ratio control circuit. The automatic extinction ratio control circuit outputs a current control value based on the feedback signal, the preset reference signal, and the control signal, thereby adjusting the current of the current source according to the current control value.

[0014] This invention provides a pattern recognition device and an automatic extinction ratio control system. In the pattern recognition device, the conversion module can convert the differential input signal and output a pattern reference signal. The pattern counter can count the number of times the pattern reference signal flips from 0 to 1 within one sampling clock cycle. The output counting result includes information about short pattern signals, avoiding the problem of short pattern signal loss. The processing module determines the final control signal based on the counting result, the preset control reference value, and the pre-received working status identifier and burst signal identifier, and sends it to the preset automatic extinction ratio control circuit, which can improve the stability of the loop control of the automatic extinction ratio control circuit. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a pattern recognizer provided in an embodiment of the present invention;

[0017] Figure 2 A circuit diagram of a signal generation module provided in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the structure of a pattern recognizer provided in an embodiment of the present invention;

[0019] Figure 4 A schematic diagram of a CML to CMOS circuit provided in an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of an automatic extinction ratio control system provided in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of an automatic extinction ratio control system in the prior art. Detailed Implementation

[0022] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Related technologies suffer from problems such as insufficient bandwidth, which prevents the identification of high-speed signals with short code patterns like 0101 and makes it impossible to correctly determine the characteristics of feedback signals. They also suffer from deterioration of AER loop stability. Based on this, this invention provides a code pattern recognizer and an automatic extinction ratio control system, which can be applied to laser driving control scenarios.

[0024] To facilitate understanding of this embodiment, a code pattern recognizer disclosed in this embodiment of the invention will first be introduced, such as... Figure 1 As shown, the code pattern recognizer includes: a conversion module 10, a sampling clock 11, a code pattern counter 12, and a processing module 13.

[0025] The conversion module 10 is used to receive differential input signals, convert the differential input signals, and output a code reference signal. The conversion module 10 is a high-speed differential input to single-ended output circuit, implemented using analog circuitry. The differential input signals are CML (Current Mode Logic) logic signals, and the code reference signals are CMOS (Complementary Metal Oxide Semiconductor) logic signals. In practical applications, laser drivers with speeds exceeding 10Gbps typically require a differential signal amplifier with a CML logic architecture in the main path due to bandwidth considerations. To facilitate subsequent signal extraction and processing, the differential CML logic signals need to be converted to CMOS logic signals. That is, the input of the conversion module 10 is a differential input signal at the CML logic level, and the output is a code reference signal at the CMOS logic level. This code reference signal is then sent to the code counter 12. In some scenarios, if the architecture uses an inverter as the main path, since the output of the inverter is 0 or 1, the output of the inverter can be directly sent to the subsequently connected code counter 12.

[0026] The sampling clock 11 is used to generate a clock signal. The sampling clock 11 is usually provided by a high-precision crystal oscillator, phase-locked loop or clock generator. It can be used to generate a clock signal and send the clock signal to the code counter 12. The clock signal is usually a low-speed signal.

[0027] The pattern counter 12 receives the pattern reference signal and the clock signal, counts the number of times the pattern reference signal flips from 0 to 1 within the current sampling clock cycle, and outputs the count result. The count result indicates whether a short pattern signal exists in the differential input signal within the sampling clock cycle. The sampling clock cycle can be understood as the time interval between two adjacent rising or falling edges of the clock signal. The pattern counter 12 is typically implemented using digital circuitry. After receiving the pattern reference signal and the clock signal, it calculates the number of times the pattern reference signal flips from 0 to 1 within the current sampling clock cycle, obtains the count result, and outputs it. Since the pattern reference signal originates from an internal high-speed circuit branch, i.e., is converted by the conversion module 10, it does not require MPD (Multi-Level Digitizer), thus eliminating the problem of pattern loss. The rising edge of the sampling clock triggers the pattern counter 12 to output the count result, which is typically multi-bit and can be designed according to actual needs, such as 8 bits. In a 10Gbps laser driver circuit, the period of the shortest code pattern, 0101, is 200ps. When the sampling clock frequency is 20MHz, the maximum number of 0-to-1 transitions that can be calculated in one cycle is 250. Therefore, the designed output bit width must be greater than 250. Through calculation, the minimum output bit width in the example is 8 bits, which is 2^8 = 256.

[0028] The processing module 13 is used to receive the counting result, and output a control signal based on the counting result, a preset control reference value, and a pre-received working status identifier and burst signal identifier. The control signal is sent to a preset automatic extinction ratio control circuit so that the automatic extinction ratio control circuit determines whether to freeze the current control value output by the automatic extinction ratio control circuit based on the control signal. The working status identifier is used to indicate whether the automatic extinction ratio control circuit is in working state, and the burst signal identifier is used to indicate whether the differential input signal is a burst packet signal.

[0029] The aforementioned control reference value can be set according to actual needs, and the number of digits in the control reference value needs to be the same as the number of digits in the counting result. The aforementioned working status indicator can be used to indicate whether the automatic extinction ratio control circuit is in working state. The automatic extinction ratio control circuit can send the corresponding working status indicator to the processing module 13 according to its own working state. For example, if the working status indicator is 0, it can be considered that the automatic extinction ratio control circuit has not started working; if the working status indicator is 1, it can be considered that the automatic extinction ratio control circuit has started working. The aforementioned burst signal indicator is used to indicate whether the differential input signal is a burst packet signal. The burst packet signal can be understood as a non-continuous, intermittently transmitted data packet signal. The burst signal indicator can be sent to the processing module 13 by an external host computer. For example, if the burst signal indicator is 0, it can be considered that the differential input signal is a burst packet signal; if the burst signal indicator is 1, it can be considered that the differential input signal is not a burst packet signal. In actual implementation, after receiving the counting result, the processing module 13 can process it in conjunction with the pre-received control reference value, working status indicator and sudden signal indicator, and output a control signal. This control signal may be 0 or 1. The control signal can be sent to the automatic extinction ratio control circuit. The automatic extinction ratio control circuit can then determine whether to freeze the output current control value based on the control signal. For example, when the control signal is 0, the automatic extinction ratio control circuit can freeze the output current control value. When the control signal is 1, the automatic extinction ratio control circuit can work normally to adjust the output current control value.

[0030] In the aforementioned pattern recognition device, the conversion module can convert the differential input signal and output a pattern reference signal. The pattern counter can count the number of times the pattern reference signal flips from 0 to 1 within one sampling clock cycle. The output counting result contains information about short pattern signals, avoiding the problem of short pattern signal loss. The processing module determines the final control signal based on the counting result, the preset control reference value, and the pre-received working status identifier and burst signal identifier, and sends it to the preset automatic extinction ratio control circuit, which can improve the stability of the loop control of the automatic extinction ratio control circuit.

[0031] Furthermore, the processing module includes a digital comparator and a signal generation module; the digital comparator is used to receive the counting result, compare the counting result with a preset control reference value, and output a comparison result; in actual implementation, the digital comparator is usually implemented using digital circuits; the control reference value can be stored in a register in advance, the digital comparator can obtain the control reference value from the register, compare it with the received counting result, and output a comparison result, i.e., a code pattern detection value, which may be a low level or a high level.

[0032] Specifically, when the counting result is less than the control reference value, the comparison result is low; when the counting result is greater than the control reference value, the comparison result is high; when the counting result is equal to the control reference value, the comparison result of the previous output is maintained, that is, the comparison result corresponding to the previous logic is maintained.

[0033] The signal generation module receives the comparison result, performs logical processing on the comparison result, the pre-received operating status identifier, and the burst signal identifier, and outputs a control signal. In actual implementation, the signal generation module can be composed of logic gate circuits. After receiving the comparison result, the signal generation module can perform corresponding logical processing on the comparison result, the operating status identifier, and the burst signal identifier, and output the final control signal.

[0034] Furthermore, the signal generation module includes: a first AND gate, a NOT gate, and a second AND gate;

[0035] The first AND gate is used to perform a logical operation on the comparison result and the pre-received working status flag, and output a first logic signal. Specifically, the first AND gate can receive the comparison result, perform an AND logical operation on the comparison result and the working status flag, and generate a first logic signal. For example, if both the comparison result and the working status flag are high, the first logic signal is high; if either the comparison result or the working status flag is low, or both are low, the first logic signal is low. The first AND gate sends the generated first logic signal to the NOT gate.

[0036] The NOT gate is used to perform logical operations on the first logic signal and output a second logic signal. For example, if the first logic signal is high, the second logic signal output after processing by the NOT gate is low; if the first logic signal is low, the second logic signal output after processing by the NOT gate is high. The NOT gate sends the generated second logic signal to the second AND gate.

[0037] The second AND gate is used to perform logical operations on the second logic signal and the burst signal identifier to output a control signal. Specifically, after receiving the second logic signal, the second AND gate can perform an AND operation on the second logic signal and the burst signal identifier to generate a control signal. For example, if both the second logic signal and the burst signal identifier are high, the control signal is high; if either the second logic signal or the burst signal identifier is low, or both are low, the control signal is low.

[0038] like Figure 2The circuit diagram of a signal generation module shown is as follows: the comparison result and the AER start signal (corresponding to the above working status indicator) are processed by the first AND gate, and the output first logic signal is then processed by the NOT gate to output the second logic signal. The second logic signal and the BEN signal (corresponding to the above burst signal indicator) are processed by the second AND gate to output the control signal.

[0039] As can be seen from the above embodiments, when a short code pattern signal exists, the number of toggles from 0 to 1 in the code pattern reference signal will be greater. When the counting result is greater than the control reference value, the comparison result output by the digital comparator is high. After logic processing by the signal generation module, the output control signal is 0. In this case, the current control value output by the automatic extinction ratio control circuit will be frozen. When the BEN signal is 0, the control signal is also 0. In this case, the current control value output by the automatic extinction ratio control circuit will also be frozen.

[0040] Furthermore, the code pattern counter is also used for: after sending the counting result corresponding to the current sampling clock cycle to the processing module, waiting for a preset time, clearing the counting result; taking the next sampling clock cycle as the new current sampling clock cycle, and repeatedly performing the step of counting the number of toggles from 0 to 1 in the code pattern reference signal within the current sampling clock cycle. This preset time can be set according to the actual application. Typically, within this preset time, the processing module can complete the corresponding processing based on the received counting result and output a control signal. In actual implementation, after sending the counting result corresponding to the current sampling clock cycle to the processing module, the code pattern counter can delay for a preset time, then clear the counting result corresponding to the current sampling clock cycle, and take the next sampling clock cycle as the new current sampling clock cycle, repeatedly performing the process of counting the number of toggles to output a new counting result. After processing by the processing module, a corresponding control signal is output.

[0041] Furthermore, the sampling clock period of the clock signal is less than or equal to a first preset period and greater than a second preset period; wherein, the first preset period is greater than the second preset period; the first preset period is the preset shortest clock period corresponding to the automatic extinction ratio control circuit; the second preset period is the period corresponding to the preset highest rate code reference signal; usually, the first and second preset periods can be obtained in advance. In practical applications, when setting the sampling clock period, it is usually necessary for the sampling clock period to be less than or equal to the first preset period and much longer than the second preset period. For example, in a 10Gbps laser driver circuit, the highest rate generated by the 0101 code pattern has a period of 200ps. The fastest control frequency of an automatic extinction ratio control circuit, i.e., AER, is 20MHz (period of 50ns), therefore it is recommended that the sampling clock frequency be set faster than 20MHz.

[0042] Furthermore, the processing module is also configured to: if the control signal is low, send the low-level control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit freezes the current control value output by the automatic extinction ratio control circuit according to the low-level control signal; if the control signal is high, send the high-level control signal to the automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit adjusts the current control value output by the automatic extinction ratio control circuit according to the high-level control signal.

[0043] In this embodiment, the processing module finally outputs a 1-bit control signal. When the control signal is 0, the current control value output by the automatic extinction ratio control circuit is frozen. When the control signal is 1, the automatic extinction ratio control circuit continues to work normally.

[0044] Furthermore, the switching transistors in the conversion module are all high-speed switching transistors; typically, the switching transistors in the code counter also use high-speed switching transistors. Specifically, high-speed switching transistors can be high-speed transistors, etc. High-speed transistors generally refer to transistors with operating frequencies between several hundred megahertz and several gigahertz. Using high-speed switching transistors can meet the application requirements of high-speed laser drive circuits exceeding 10Gbps.

[0045] For ease of understanding, see Figure 3 The diagram shows the structure of a pattern recognition device, which consists of the following parts: a CML to CMOS circuit (analog circuit; corresponding to the above conversion module), a pattern counter (digital circuit), a sampling clock (analog circuit), a digital comparator (digital circuit), and a control signal generator (digital circuit; corresponding to the above signal generation module).

[0046] The input to the CML-to-CMOS circuit is a differential input signal at CML logic level, and its output is a CMOS logic code reference signal, such as... Figure 4 The diagram shows a CML-to-CMOS circuit, including switches P1, P2, P3, P4, P5, and P6, and switches N1, N2, N3, N4, N5, and N6. Switches P1 to P6 can be P-channel MOSFETs, and switches N1 to N6 can be N-channel MOSFETs. A current source is also included. The gates of switches N1 and N2 can be connected to Vin+ and Vin-, respectively, representing the differential input signals. The common terminal of switches P6 and N6 outputs Vo, representing the code reference signal. For detailed operating principles, please refer to relevant technologies; further details are omitted here.

[0047] A sampling clock is used to generate a clock signal; a code pattern counter is used to receive the code pattern reference signal and the clock signal, and count the number of times the code pattern reference signal flips from 0 to 1 within the current sampling clock cycle, and output the counting result; a digital comparator compares the counting result with a preset control reference value and outputs the comparison result; a control signal generation circuit performs logical processing on the comparison result, the AER start signal, and the BEN signal, and outputs a control signal.

[0048] The present invention discloses an automatic extinction ratio control system, the system comprising: a laser driving unit, a switching unit, a current source, a laser, a laser feedback unit, a reference signal unit, an automatic extinction ratio control circuit, and a code pattern recognizer as described in any of the above embodiments;

[0049] The laser driving unit is used to receive differential input signals, output switch control signals, and control the switching unit to turn on or off according to the switch control signals.

[0050] The current source is used to provide current to the laser when the switching unit is turned on, so that the laser emits laser light;

[0051] The laser feedback unit is used to generate a feedback signal based on the laser emitted by the laser and send it to the automatic extinction ratio control circuit.

[0052] The reference signal unit is used to generate a preset reference signal and send the preset reference signal to the automatic extinction ratio control circuit;

[0053] The code pattern recognizer is used to receive the differential input signal, the preset control reference value, the working status identifier and the burst signal identifier, and output a control signal according to the differential input signal, the control reference value, the working status identifier and the burst signal identifier, and send the control signal to the automatic extinction ratio control circuit.

[0054] The automatic extinction ratio control circuit is used to output a current control value based on the feedback signal, the preset reference signal and the control signal, so as to adjust the current of the current source according to the current control value.

[0055] In the automatic extinction ratio control system, the IMODDAC value (corresponding to the aforementioned current control value) is initial before the AER starts operating. After the AER starts operating, it adjusts the IMODDAC value from this initial value. Therefore, the AER start signal determines whether the pattern detection value is emitted. The combinational logic uses AND logic to ensure that when the AER start signal = 0, no pattern detection related information is output to subsequent circuits. When the AER start signal = 1, pattern detection related information is allowed to be generated.

[0056] For burst systems, the burst mode uses the BEN signal to indicate a burst, and the value of the BEN signal freezes or releases the IMODDAC value of the AER. In a conventional AER circuit, the BEN signal is directly used as a control signal. When BEN=0, the IMODDAC value output by the AER control circuit is frozen; when BEN=1, the AER control circuit continues to operate, and the output IMODDAC value is adjusted based on the previously frozen value. For continuous systems, the BEN signal is constant (1), therefore there is no freezing.

[0057] In this scheme, the final output is a 1-bit control signal, which is sent to the AER control circuit. When the control signal = 0, the IMODDAC value output by the AER control circuit is frozen; when the control signal = 1, the AER control circuit continues to operate. That is, in addition to freezing the AER control circuit when BEN = 0, it also freezes it simultaneously when a short code pattern is detected. For continuous systems, when the BEN signal input is a constant 1, it is additionally modulated to include information from the code pattern recognizer. Therefore, continuous systems freeze the AER control circuit when a short code pattern is detected.

[0058] The pattern recognizer calculates the number of times the pattern reference signal flips from 0 to 1 within a fixed sampling clock cycle, compares it with the control reference value, and then outputs a control signal to provide to the AER control circuit.

[0059] When the control signal is 1 (i.e., during the long code period, the bandwidth of the AER feedback circuit is sufficient to capture the low-speed feedback signal), the AER control circuit works normally.

[0060] When the control signal is 0 (i.e., during the short code period, the bandwidth of the AER feedback circuit is insufficient to capture the high-speed feedback signal), the AER control circuit suspends operation. The IMODDAC value output by the AER control circuit is temporarily frozen, and it is only released from freezing and resumes operation when the control signal is 1.

[0061] This solution avoids problems caused by excessive MPD capacitance in the use of short patterns over extended periods by employing pattern recognition. During longer durations of short patterns, the AER control circuit is paused and the AER output is frozen. After the longer pattern is restored, the AER control circuit resumes operation and dynamically adjusts the IMODDAC value from the frozen value. Furthermore, because this solution avoids the impact of AER loop bandwidth, current extinction ratio circuit designs and MPD devices can still be used for laser systems with speeds exceeding 10Gbps, significantly reducing design costs. Since the pattern recognizer directly processes the extracted high-speed signal after conversion to digital CMOS logic, its 50ns-100ns response time is very fast for burst packet lengths as short as 200ns, making it highly suitable for burst mode applications. It eliminates the need for lengthy pattern practice and extensive analog circuitry at the feedback end for pattern identification, reducing misjudgments and making it suitable for mass production.

[0062] This solution designs a circuit for high-speed laser driver circuits to ensure that even with long-duration short code patterns, the AER control circuit will not continuously adjust the IMODDAC value in one direction, preventing the IMODDAC value from becoming excessive. Simultaneously, for application at the ONU end of the PON system, it achieves a fast response to burst packet signals. Therefore, this solution avoids bandwidth issues while ensuring the fast response requirements of the automatic extinction ratio control circuit.

[0063] like Figure 5The diagram shows an automatic extinction ratio control system. The diode on the left corresponds to the laser. The input of the high-speed laser driver D (corresponding to the laser driver unit mentioned above) is a code pattern, and its output is a modulation signal used to adjust the on / off state of the switch unit S. After the switch unit S is turned on, the current from the current source I1 is supplied to the laser Z1. The intensity of the laser emitted by the laser Z1 can be controlled according to the magnitude of the current, and the magnitude of the current is proportional to the laser intensity. After receiving the laser signal from laser Z1, diode Z2 converts it into a current signal, which is then converted into a voltage signal via TIA1 and resistor R1. This voltage signal is sent as a feedback signal to the AER control circuit. Diode Z2, TIA1, and resistor R1 form the laser feedback unit; current source I2, TIA2, and resistor R2 form the reference signal unit, used to generate a preset reference signal; the pattern recognizer receives the differential input signal, the preset control reference value, the operating status indicator, and the burst signal indicator, and outputs a control signal based on these parameters. The AER control circuit (corresponding to the aforementioned automatic extinction ratio control circuit) outputs an IMODDAC value based on the feedback signal, the preset reference signal, and the control signal. If the control signal is 1 and the preset reference signal is greater than the feedback signal, the IMODDAC value is increased to increase the current of current source I1, thereby increasing the laser intensity of laser Z1. The amplitude or phase of the preset reference signal and the feedback signal are compared in the AER control circuit, and the IMODDAC value is fed back to ensure that the extinction ratio of the laser Z1 output signal remains consistent at all temperatures.

[0064] like Figure 6 The diagram shown is a schematic of an automatic extinction ratio control system in the prior art, and... Figure 5 In contrast, this diagram directly sends the BEN signal as a control signal to the AER control circuit. The BEN signal is specific to the burst mode circuit; in the continuous mode circuit, the BEN signal is a constant 1. This system diagram suffers from the problem that the input bandwidth of TIA1 is too low, making it unable to recognize high-speed signals with short code patterns such as 0101. Furthermore, it cannot correctly determine the characteristics of the feedback signal, such as signal amplitude and phase, leading to a decrease in the stability of the AER loop. However, using... Figure 5 The control system in the system can solve the above problems.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pattern recognition device, characterized in that, include: The conversion module is used to receive differential input signals, perform conversion processing on the differential input signals, and output a code pattern reference signal; The sampling clock is used to generate the clock signal; A pattern counter is used to receive the pattern reference signal and the clock signal, and count the number of times the pattern reference signal flips from 0 to 1 within the current sampling clock cycle, and output the counting result; wherein, the counting result is used to indicate whether there is a short pattern signal in the differential input signal within the sampling clock cycle; The processing module is configured to receive the counting result, and based on the counting result, a preset control reference value, and pre-received operating status identifier and burst signal identifier, output a control signal and send the control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit determines whether to freeze the current control value output by the automatic extinction ratio control circuit according to the control signal; wherein, the operating status identifier is used to indicate whether the automatic extinction ratio control circuit is in operating state, and the burst signal identifier is used to indicate whether the differential input signal is a burst packet signal; The processing module includes: A digital comparator is used to receive the counting result, compare the counting result with a preset control reference value, and output the comparison result. The signal generation module is used to receive the comparison result, perform logical processing on the comparison result, the pre-received working status identifier and the burst signal identifier, and output a control signal; The signal generation module includes: The first AND gate is used to perform logical operations on the comparison result and the pre-received working status identifier, and output a first logical signal; The NOT gate is used to perform logical operations on the first logic signal and output the second logic signal. The second AND gate is used to perform logical operations on the second logic signal and the burst signal identifier, and output a control signal.

2. The code pattern recognizer according to claim 1, characterized in that, When the counting result is less than the control reference value, the comparison result is at a low level; When the counting result is greater than the control reference value, the comparison result is at a high level; When the counting result is equal to the control reference value, the comparison result of the previous output is maintained.

3. The code pattern recognizer according to claim 1, characterized in that, The differential input signal is a CML logic signal, and the code reference signal is a CMOS logic signal.

4. The code pattern recognizer according to claim 1, characterized in that, The code counter is also used for: After sending the counting result corresponding to the current sampling clock cycle to the processing module, wait for a preset time and then clear the counting result; The next sampling clock cycle is used as the new current sampling clock cycle, and the step of counting the number of times the code reference signal flips from 0 to 1 within the current sampling clock cycle is repeated.

5. The code pattern recognizer according to claim 1, characterized in that, The sampling clock period of the clock signal is less than or equal to a first preset period and greater than a second preset period; wherein, the first preset period is greater than the second preset period; the first preset period is the preset shortest clock period corresponding to the automatic extinction ratio control circuit; and the second preset period is the period corresponding to the preset highest rate code reference signal.

6. The code pattern recognizer according to claim 1, characterized in that, The processing module is also used for: If the control signal is low, the low-level control signal is sent to the preset automatic extinction ratio control circuit so that the automatic extinction ratio control circuit freezes the current control value output by the automatic extinction ratio control circuit according to the low-level control signal. If the control signal is high, the high-level control signal is sent to the automatic extinction ratio control circuit so that the automatic extinction ratio control circuit adjusts the current control value output by the automatic extinction ratio control circuit according to the high-level control signal.

7. The code pattern recognizer according to claim 1, characterized in that, The switching transistors in the conversion module are all high-speed switching transistors.

8. An automatic extinction ratio control system, characterized in that, The system includes: a laser driving unit, a switching unit, a current source, a laser, a laser feedback unit, a reference signal unit, an automatic extinction ratio control circuit, and a pattern recognition device as described in any one of claims 1-7. The laser driving unit is used to receive differential input signals, output switch control signals, and control the switching unit to turn on or off according to the switch control signals. The current source is used to provide current to the laser when the switching unit is turned on, so that the laser emits laser light; The laser feedback unit is used to generate a feedback signal based on the laser emitted by the laser and send it to the automatic extinction ratio control circuit. The reference signal unit is used to generate a preset reference signal and send the preset reference signal to the automatic extinction ratio control circuit; The code pattern recognizer is used to receive the differential input signal, the preset control reference value, the working status identifier and the burst signal identifier, and output a control signal according to the differential input signal, the control reference value, the working status identifier and the burst signal identifier, and send the control signal to the automatic extinction ratio control circuit. The automatic extinction ratio control circuit is used to output a current control value based on the feedback signal, the preset reference signal and the control signal, so as to adjust the current of the current source according to the current control value.

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