Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a device isolation pattern in a substrate and defining an active portion extending in a first direction, a first impurity region on a central region of the active portion, a second impurity region on an edge of the active portion, a bit line connected to the first impurity region and extending across the active portion in a second direction, and a gate line connected to the bit line. A bit line cover pattern on the bit line, a storage node contact in contact with each of the second impurity regions, a diffusion barrier pattern covering a top surface of the bit line cover pattern and a top surface of the storage node contact, and a landing pad on the diffusion barrier pattern. The top surface of the diffusion barrier pattern is flat.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and a method of manufacturing the same. Background Art

[0002] Semiconductor devices play an important role in the electronics industry due to their small size, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be classified as any of semiconductor memory devices that store logic data, semiconductor logic devices that process operations on logic data, and hybrid semiconductor devices having both memory elements and logic elements.

[0003] Recently, the demand for high speed and low power consumption in electronic products requires that semiconductor devices embedded in these products have high operating speeds and / or low operating voltages. To meet these requirements, semiconductor devices have become increasingly integrated. This high level of integration can lead to reduced reliability. Therefore, various studies have been conducted to improve the reliability of semiconductor devices. Summary of the Invention

[0004] Some example embodiments of the inventive concepts provide semiconductor devices having increased reliability.

[0005] Some example embodiments of the inventive concepts provide methods of fabricating semiconductor devices having increased reliability.

[0006] Example embodiments of the inventive concept are not limited to the above-mentioned ones, and other example embodiments not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to an example embodiment of the present invention, a semiconductor device includes: a plurality of device isolation patterns in a substrate, the device isolation patterns defining a plurality of active portions, the active patterns extending in a first direction; a first impurity region on a central area of ​​each active portion; a plurality of second impurity regions on an edge of each active portion; a bit line connected to the first impurity region, the bit line extending across the active portion in a second direction, the second direction intersecting the first direction; a bit line capping pattern on the bit line; a storage node contact contacting each second impurity region; a diffusion barrier pattern covering a top surface of the bit line capping pattern and a top surface of the storage node contact; and a landing pad on the diffusion barrier pattern, wherein the top surface of the diffusion barrier pattern is flat.

[0008] According to an example embodiment of the present invention, a semiconductor device includes: a plurality of device isolation patterns in a substrate, the device isolation patterns defining a plurality of active portions, the active portions extending in a first direction; a plurality of word lines in the substrate, the word lines extending across the active portions in a second direction, the second direction intersecting the first direction; a first impurity region on a central area of ​​each active portion; a plurality of second impurity regions on an edge of each active portion; a bit line connected to the first impurity region, the bit line extending across the word line in the second direction; a bit line capping pattern on the bit line; a bit line spacer covering a sidewall of the bit line and a sidewall of the bit line capping pattern; a storage node contact contacting each second impurity region; a diffusion barrier pattern covering a top surface of the bit line capping pattern, a top surface of the storage node contact, and a top surface and sidewalls of the bit line spacer; and a landing pad on the diffusion barrier pattern, wherein the diffusion barrier pattern has a first thickness on a top surface of the bit line capping pattern and a second thickness on a sidewall of the bit line capping pattern, and the second thickness is greater than the first thickness.

[0009] According to an example embodiment of the present invention, a semiconductor device includes: a plurality of device isolation patterns in a substrate, the device isolation patterns defining a plurality of active portions, the active portions extending in a first direction; a first impurity region on a central area of ​​each active portion; a plurality of second impurity regions on an edge of each active portion; a bit line connected to the first impurity region, the bit line extending across the active portion in a second direction, the second direction intersecting the first direction; a bit line capping pattern located on the bit line; a bit line spacer covering a sidewall of the bit line and a sidewall of the bit line capping pattern; a storage node contact contacting each of the second impurity regions; a first sub-diffusion barrier pattern covering a top surface of the storage node contact and a sidewall of the bit line spacer; a second sub-diffusion barrier pattern covering a top surface of the first sub-diffusion barrier pattern and the bit line capping pattern, and a landing pad on the first and second sub-diffusion barrier patterns.

[0010] According to an example embodiment of the present inventive concept, a method for manufacturing a semiconductor device includes: forming a plurality of device isolation patterns in a substrate to define active portions; forming a plurality of first impurity regions and a plurality of second impurity regions on the active portions; forming a plurality of bit lines on the substrate and forming a plurality of bit line capping patterns on the bit lines, the bit lines extending across the active portions and contacting corresponding first impurity regions in the first impurity regions; forming a plurality of bit line spacers to cover sidewalls of the bit lines and sidewalls of the bit line capping patterns; forming storage node contacts respectively contacting the second impurity regions between adjacent pairs of bit lines, and planarizing top surfaces of the bit lines and top surfaces of the bit line spacers. ; removing the upper portion of the storage node contact to expose the upper side wall of the bit line spacer; forming a first diffusion barrier layer on the front surface of the substrate; removing the first diffusion barrier layer on the bit line cover pattern and the bit line spacer and forming a first sub-diffusion barrier pattern on the side wall of the bit line spacer; forming a second diffusion barrier layer on the first sub-diffusion barrier pattern, the bit line cover pattern and the bit line spacer; forming a landing pad layer on the second diffusion barrier layer; and patterning the landing pad layer, the first sub-diffusion barrier pattern, and the second diffusion barrier layer to expose the upper side wall of the bit line spacer and the upper side wall of the bit line cover pattern, and form the diffusion barrier pattern and the landing pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A plan view showing a semiconductor device according to example embodiments of the inventive concepts is shown.

[0012] Figure 2 Shown along Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0013] Figure 3A and Figure 3B Shows the display Figure 2 An enlarged view of part P1.

[0014] Figures 4A to 4I A cross-sectional view is shown showing the fabrication process according to an example embodiment. Figure 2 Method for a semiconductor device.

[0015] Figure 5 shows an example embodiment along Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0016] Figure 6 Shows the display Figure 5 An enlarged view of part P2.

[0017] Figure 7 shows an example embodiment along Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0018] Figure 8shows an example embodiment along Figure 1 A cross-sectional view taken along lines AA' and BB'. DETAILED DESCRIPTION

[0019] Some example embodiments of the present inventive concept will now be described in detail with reference to the accompanying drawings to help clearly explain the present inventive concept.

[0020] Although the terms "same," "equal," or "same" are used in the description of example embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that within an expected manufacturing or operating tolerance (e.g., ±10%), the element or value is the same as the other element.

[0021] When the terms "about," "substantially," or "approximately" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the terms "about," "substantially," or "approximately" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather that the tolerance of the shape is within the scope of the present disclosure. Furthermore, regardless of whether a numerical value or shape is modified as "about" or "substantially," it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0022] Figure 1 A plan view showing a semiconductor device according to example embodiments of the inventive concepts is shown. Figure 2 Shown along Figure 1 A cross-sectional view taken along lines AA' and BB'. Figure 3A and Figure 3B Shows the display Figure 2 An enlarged view of part P1.

[0023] Reference Figure 1 and Figure 2 , a substrate 1 may be provided. For example, the substrate 1 may be a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate 1 may be provided with a device isolation pattern STI defining an active portion ACT therein. Each active portion ACT may have an isolated shape. In a plan view, each active portion ACT may have a rod shape elongated along a first direction D1. When viewed in a plan view, the active portions ACT may respectively correspond to portions of the substrate 1 surrounded by the device isolation pattern STI. The active portions ACT may be arranged parallel to each other in the first direction D1, so that one of the active portions ACT may have an end portion adjacent to a center portion of an adjacent one of the active portions ACT.

[0024] The substrate 1 may include a semiconductor material. For example, the substrate 1 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The device isolation pattern STI may include one or more of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride).

[0025] The word lines WL may extend across the active portion ACT. The word lines WL may be disposed in grooves formed in the device isolation pattern STI and the active portion ACT. The word lines WL may extend in a second direction D2 intersecting the first direction D1 and may be parallel to each other in a third direction D3 intersecting the first direction D1 and the second direction D2. The word lines WL may be formed of a conductive material. A gate dielectric layer 12 may be disposed between each of the word lines WL and the inner surface of each groove. Although not shown, the groove may have its bottom surface positioned relatively deep in the device isolation pattern STI and relatively shallow in the active portion ACT. The gate dielectric layer 12 may include at least one selected from thermal oxide, silicon nitride, silicon oxynitride, and a high-k dielectric. Each of the word lines WL may have a curved bottom surface.

[0026] The first impurity region 3a can be arranged in the active portion ACT between a pair of word lines WL, and a pair of second impurity regions 3b can be arranged in opposite edge portions of the active portion ACT. The first impurity region 3a and the second impurity region 3b can be doped with, for example, n-type impurities. A transistor can be formed by each word line WL and an adjacent pair of first impurity regions 3a and second impurity regions 3b. When the word lines WL are arranged in the grooves, each of the word lines WL can have a channel region thereunder, and the channel length of the channel region is increased within a limited planar area. Therefore, the short channel effect can be minimized. However, the present invention is not limited to this, and the arrangement of the word lines WL can be changed in various ways.

[0027] The word lines WL may have a top surface lower than the top surface of the active portion ACT. Word line capping patterns 14 may be provided on the word lines WL, respectively. The word line capping patterns 14 may have a linear shape extending along the longitudinal direction of the corresponding word lines WL and may cover the entire top surface of the word lines WL. The grooves may have an inner space not occupied by the word lines WL, and the word line capping patterns 14 may fill the unoccupied inner space of the grooves. The word line capping patterns 14 may be formed of, for example, a silicon nitride layer.

[0028] An interlayer dielectric pattern 30 may be provided on the substrate 1. The interlayer dielectric pattern 30 may be formed of a single layer or multiple layers including at least one selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The interlayer dielectric pattern 30 may be formed to have an island shape spaced apart from each other when viewed in a plan view. In some example embodiments, the interlayer dielectric pattern 30 may be formed to have a grid shape when viewed in a plan view. The interlayer dielectric pattern 30 may be formed to cover end portions of two adjacent active portions ACT.

[0029] Upper portions of the substrate 1, the device isolation pattern STI, and the word line capping pattern 14 may be partially recessed to form a first groove R1. The first groove R1 may have a grid shape when viewed in a plan view. The first groove R1 may have sidewalls aligned with sidewalls of the interlayer dielectric pattern 30.

[0030] The bit line BL may be disposed on the interlayer dielectric pattern 30. The bit line BL may extend across the word line capping pattern 14 and the word line WL. Figure 1 As disclosed in , the bit lines BL may extend in the third direction D3. The bit lines BL may be spaced apart from each other (eg, parallel to each other) in the second direction D2.

[0031] The bit line BL may include a bit line polysilicon pattern 32, a bit line diffusion barrier pattern 34, and a bit line wiring pattern 36 stacked in sequence. The bit line polysilicon pattern 32 may include doped polysilicon. The bit line diffusion barrier pattern 34 may include at least one selected from titanium, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum, tantalum nitride, and tungsten nitride. The bit line wiring pattern 36 may include a metal such as tungsten, aluminum, or copper. A bit line capping pattern 38 may be disposed on the bit line BL. The bit line capping pattern 38 may be formed of a dielectric material, such as a silicon nitride layer.

[0032] The bit line contact DC may be provided in the first groove R1 intersecting the bit line BL. The bit line contact DC may have a top surface substantially at the same level as the top surface of the bit line polysilicon pattern 32. The bit line contact DC may include at least one selected from impurity-doped polysilicon, impurity-undoped polysilicon, and a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, and Ir). When the bit line is formed along the groove R1, the top surface of the bit line polysilicon pattern 32 may be substantially the same level as the top surface of the bit line polysilicon pattern 32. Figure 2 When viewed in a cross section taken along line BB′, the bit line contact DC may have a sidewall in contact with a sidewall of the interlayer dielectric pattern 30. Figure 1 As shown in the plan view of FIG, a portion of a sidewall of the bit line contact DC may be concave. The bit line contact DC may electrically connect the first impurity region 3a and the bit line BL to each other.

[0033] The first recess R1 may have an empty space not occupied by the bit line contact DC, and the empty space of the first recess R1 may be occupied by the lower buried dielectric pattern 27. The lower buried dielectric pattern 27 may be formed of a single layer or multiple layers including at least one selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0034] The storage node contacts BC may be disposed between a pair of adjacent bit lines BL. The storage node contacts BC may be spaced apart from each other. The storage node contacts BC may include impurity-doped polysilicon or impurity-undoped polysilicon. Unlike shown, each storage node contact BC may have a concave top surface. A dielectric pattern (not shown) may be disposed between the bit lines BL, more specifically between the storage node contacts BC.

[0035] The bit line spacer BSP may be interposed between the bit line BL and the storage node contact BC. The bit line spacer BSP may cover the sidewalls of the bit line contact DC, the sidewalls of the bit line BL, and the sidewalls of the bit line capping pattern 38. When viewed in a plan view, the bit line spacer BSP may extend in a third direction D3 along the sidewalls of the bit line BL, as shown in FIG. Figure 1 shown.

[0036] The bit line spacer BSP may include a first subspacer 21, a second subspacer 23, and a third subspacer 25 sequentially arranged from the sidewall of the bit line BL. The first subspacer 21 and the third subspacer 25 may include a material having an etching selectivity relative to the second subspacer 23. For example, the first subspacer 21 and the third subspacer 25 may include silicon nitride. The second subspacer 23 may include silicon oxide. In some example embodiments, the second subspacer 23 may be an air gap.

[0037] The first subspacer 21 may extend downward to cover the sidewall of the bit line contact DC. The first subspacer 21 may be interposed between the lower buried dielectric pattern 27 and the device isolation pattern STI. Figure 2 As shown in the cross-sectional view taken along line AA' of FIG, the bit line spacer BSP and the bit line capping pattern 38 may each have a flat top surface. The top surface of the bit line capping pattern 38 may be coplanar with the top surfaces of the first sub-spacer 21, the second sub-spacer 23, and the third sub-spacer 25.

[0038] The storage node ohmic layer 40 may be disposed on the storage node contact BC. The storage node ohmic layer 40 may include a metal silicide. A diffusion barrier pattern 60 may be disposed on the storage node ohmic layer 40. The diffusion barrier pattern 60 may have a single-layer or multi-layer structure selected from, for example, at least one of titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tungsten nitride, molybdenum, and molybdenum nitride.

[0039] The diffusion barrier pattern 60 may cover the top surface of the storage node ohmic layer 40 and sidewalls of the third subspacer 25. The diffusion barrier pattern 60 may extend to cover the top surface of the bit line capping pattern 38 and the top surfaces of the first, second, and third subspacers 21, 23, and 25.

[0040] A landing pad LP may be disposed on the diffusion barrier pattern 60. The landing pad LP may cover the top surface of the bitline capping pattern 38 and the top surface of the bitline spacer BSP. The diffusion barrier pattern 60 may be interposed between the bitline capping pattern 38 and the landing pad LP, and between the bitline spacer BSP and the landing pad LP. The diffusion barrier pattern 60 may electrically connect the storage node contact BC to the landing pad LP. The diffusion barrier pattern 60 may be referred to as a conductive pattern or a pad connection pattern.

[0041] The center of the landing pad LP may be offset in the second direction D2 away from the center of the storage node contact BC. A portion of the bit line BL may vertically overlap the landing pad LP. A portion of the lower end of the landing pad LP may be located at a level higher than the top surface of the bit line capping pattern 38. The landing pad LP may be provided in plurality. The landing pad LP may include a metal such as tungsten.

[0042] On the storage node contact BC, a landing pad isolation pattern 50 may be provided between the landing pads LP to separate the landing pads LP from each other. A portion of the landing pad isolation pattern 50 may penetrate a portion of the bit line capping pattern 38. A portion of the landing pad isolation pattern 50 may extend downward to contact an upper portion of the second subspacer 23. The landing pad isolation pattern 50 may have a single-layer or multi-layer structure selected from, for example, at least one of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and a porous layer.

[0043] The data storage element DSP may be disposed on the landing pad LP. The data storage element DSP may be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device may be a dynamic random access memory (DRAM). In some example embodiments, the data storage element DSP may include a magnetic tunnel junction pattern. In some example embodiments, the data storage element DSP may include a phase change material or a variable resistance material.

[0044] refer to Figure 2 and Figure 3AThe diffusion barrier pattern 60 may include a first portion 60a, a second portion 60b, and a third portion 60c. The first portion 60a may cover the top surface BSP_s of the bitline spacer BSP and the top surface 38_s of the bitline capping pattern 38. The first portion 60a may have a first thickness T1. The second portion 60b may cover the upper sidewalls of the bitline spacer BSP and may have a second thickness T2 greater than the first thickness T1. The third portion 60c may be disposed below the second portion 60b and may cover the sidewalls of the bitline spacer BSP. The third portion 60c may have a third thickness T3 greater than the first thickness T1 and less than the second thickness T2.

[0045] In the semiconductor device according to this example embodiment, the diffusion barrier pattern 60 may be configured such that the second thickness T2 and the third thickness T3 of the portions 60b and 60c covering the sidewalls of the bit line spacer BSP are greater than the first thickness T1, thereby enabling connection between the landing pad LP and the storage node contact BC without interruption. Consequently, malfunctions of the semiconductor device may be reduced or prevented, and the reliability of the semiconductor device may be improved.

[0046] The top surface BSP_s of the bit line spacer BSP may be flat, and the top surface 38_s of the bit line capping pattern 38 may be flat. The top surface BSP_s of the bit line spacer BSP may be coplanar with the top surface 38_s of the bit line capping pattern 38. A portion of the diffusion barrier pattern 60 located on the bit line capping pattern 38 and the bit line spacer BSP may have a flat top surface 60_s, as shown in FIG. Figure 3A In some example embodiments, the diffusion barrier pattern 60 located on the bit line capping pattern 38 and the bit line spacer BSP may have a top surface 60_s having an uneven structure, as shown in FIG. Figure 3B shown.

[0047] Figures 4A to 4I Shows the display manufacturing Figure 2 A cross-sectional view of a method for manufacturing a semiconductor device.

[0048] refer to Figure 4A , a device isolation pattern STI may be formed in the substrate 1 to define an active portion ACT. A device isolation trench may be formed in the substrate 1, and the device isolation pattern STI may fill the device isolation trench. The active portion ACT and the device isolation pattern STI may be patterned to form a groove.

[0049] Word lines WL may be formed in the grooves accordingly. A pair of word lines WL may extend across the active portion ACT. Before forming the word lines WL, a gate dielectric layer 12 may be formed on the inner surface of each groove. The gate dielectric layer 12 may be formed by one or more of a thermal oxidation process, a chemical vapor deposition process, and an atomic layer deposition process. A gate conductive layer may be stacked to fill the grooves, and the gate conductive layer may be etched back to form the word lines WL. A dielectric layer such as a silicon nitride layer may be stacked on the substrate 1 to fill the grooves, and then the dielectric layer may be etched to form a word line cap pattern 14 on the corresponding word lines WL.

[0050] The wordline capping pattern 14 and the device isolation pattern STI can be used as masks to implant the active portion ACT with dopants, thereby forming the first impurity region 3a and the second impurity region 3b. A dielectric layer and a first polysilicon layer can be sequentially formed on the front surface of the substrate 1. The first polysilicon layer can be patterned to form a polysilicon mask pattern, and the polysilicon mask pattern can be used to etch the device isolation pattern STI, the substrate 1, and the wordline capping pattern 14 to simultaneously form a first recess R1 and an interlayer dielectric pattern 30. The first recess R1 can expose the first impurity region 3a.

[0051] A bit line BL including a bit line polysilicon pattern 32, a bit line diffusion barrier pattern 34, and a bit line wiring pattern 36 may be formed on the front surface of the substrate 1. A bit line contact DC and a bit line capping pattern 38 may be formed on the front surface of the substrate 1. The above-mentioned etching process may partially expose the top surface of the interlayer dielectric pattern 30, and may also partially expose the inner sidewall and bottom surface of the first groove R1.

[0052] A first spacer layer may be conformally formed on the front surface of the substrate 1. The first spacer layer may conformally cover the top surface of the interlayer dielectric pattern 30 and may also conformally cover the bottom surface and inner sidewalls of the first recess R1. A buried dielectric layer may be stacked on the front surface of the substrate 1 to fill the first recess R1, and then a first anisotropic etching process may be employed to form the first sub-spacers 21 while leaving the lower buried dielectric pattern 27 in the first recess R1.

[0053] A second spacer layer may be conformally stacked on the front surface of the substrate 1, and then a second anisotropic etching process may be used to form second sub-spacers 23 covering the sidewalls of the first sub-spacers 21. The second sub-spacers 23 may include a material having an etching selectivity relative to the first sub-spacers 21. The second anisotropic etching process for forming the second sub-spacers 23 may expose the top surface of the interlayer dielectric pattern 30.

[0054] A third spacer layer may be conformally stacked on the front surface of the substrate 1, and then a third anisotropic etching process may be used to form third sub-spacers 25 covering the sidewalls of the second sub-spacers 23. The third anisotropic etching process for forming the third sub-spacers 25 may expose the top surface of the interlayer dielectric pattern 30. The first sub-spacers 21, the second sub-spacers 23, and the third sub-spacers 25 may constitute bit line spacers BSP on the sidewalls of the bit lines BL.

[0055] An impurity-doped second polysilicon layer 70 may be stacked on the front surface of the substrate 1 , thereby filling the space between the bit lines BL.

[0056] refer to Figure 4B , a planarization process can be completed by performing a first chemical mechanical polishing (CMP) process on the top surfaces of the bit lines BL, the bit line spacers BSP, and the second polysilicon layer 70. Thus, the preliminary storage node contacts 72 can be formed, and the top surfaces 38_s of the bit line capping patterns 38, the top surfaces BSP_s of the bit line spacers BSP, and the top surfaces 72_s of the preliminary storage node contacts 72 can be planarized. The top surfaces 38_s of the bit line capping patterns 38 can be coplanar with the top surfaces BSP_s of the bit line spacers BSP and the top surfaces 72_s of the preliminary storage node contacts 72. Although not shown, the first CMP process can reduce the height (level) of the top surfaces 38_s of the bit line capping patterns 38 and the top surfaces BSP_s of the bit line spacers BSP, and thus can reduce the step difference between the data storage element DSP described later and the core / peripheral region of the semiconductor device.

[0057] refer to Figure 4C The preliminary storage node contact 72 may be etched to form a storage node contact BC, while simultaneously exposing the sidewalls of the third subspacer 25, the top surface BSP_s of the bit line spacer BSP, and the top surface 38_s of the bit line capping pattern 38. A storage node ohmic layer 40 may be formed on the top surface of the storage node contact BC. The storage node ohmic layer 40 may be formed of cobalt silicide. For example, after forming a cobalt layer on the front surface of the substrate 1, the cobalt layer may be heat-treated to react with the silicon of the storage node contact BC to form a cobalt silicide layer. The unreacted cobalt layer may then be removed to form the storage node ohmic layer 40.

[0058] refer to Figure 4D, the first diffusion barrier layer 61m may be conformally formed on the front surface of the substrate 1. In some example embodiments, the storage node ohmic layer 40 and the first diffusion barrier layer 61m may be formed simultaneously with each other. For example, a titanium (Ti) layer and a titanium nitride (TiN) layer may be conformally deposited sequentially to form the first diffusion barrier layer 61m on the top surface of the storage node contact BC. In this step, the temperature of the deposition process may cause the Ti or TiN and silicon of the storage node contact BC to react with each other to form the storage node ohmic layer 40 formed of TiSi or TiSiN at the interface between the first diffusion barrier layer 61m and the storage node contact BC. The first diffusion barrier layer 61m may be formed by, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0059] The first diffusion barrier layer 61m may cover the bit line capping pattern 38, the bit line spacer BSP, and the storage node ohmic layer 40. The first diffusion barrier layer 61m may be formed to have an uneven structure on its top surface 61m_s. A first void V1 may be formed between the storage node contact BC and the top surface 61m_s of the first diffusion barrier layer 61m.

[0060] refer to Figure 4E A second CMP process may be performed to planarize the top surface 61m_s of the first diffusion barrier layer 61m, the top surface 38_s of the bitline capping pattern 38, and the top surface BSP_s of the bitline spacer BSP, thereby removing the first diffusion barrier layer 61m on the bitline capping pattern 38 and the bitline spacer BSP. Consequently, a first sub-diffusion barrier pattern 61 may be formed to cover the sidewalls of the bitline spacer BSP. The top surface 61_s of the first sub-diffusion barrier pattern 61 may be coplanar with the top surface 38_s of the bitline capping pattern 38 and the top surface BSP_s of the bitline spacer BSP.

[0061] The second CMP process may be a pre-planarization process to facilitate the following discussion. Figure 4I In this case, the fourth anisotropic etching process for node separation is performed in the step of Figure 4D The first void V1 formed in the third sub-spacer 25 may cause delamination or disconnection of the first sub-diffusion barrier pattern 61 covering the sidewalls of the third sub-spacer 25 .

[0062] refer to Figure 4F , the second diffusion barrier layer 62m may be conformally formed on the front surface of the substrate 1. The second diffusion barrier layer 62m may be formed by, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0063] The second diffusion barrier layer 62m may cover the bit line capping pattern 38, the bit line spacer BSP, and the storage node ohmic layer 40. The second diffusion barrier layer 62m may cover the top surface and sidewalls of the first sub-diffusion barrier pattern 61. The second diffusion barrier layer 62m may be formed to have an uneven structure on its top surface 62m_s. When the first sub-diffusion barrier pattern 61 and the second diffusion barrier layer 62m include the same material, the first sub-diffusion barrier pattern 61 and the second diffusion barrier layer 62m may be integrally formed as a single integral piece without any interface therebetween (e.g., without any visible interface). In this step, a second gap V2 may be formed between the storage node contact BC and the top surface 62m_s of the second diffusion barrier layer 62m. The second gap V2 may be formed to have a thickness less than 0.01 mm. Figure 4D The dimensions of the first void V1 are depicted.

[0064] Since the second diffusion barrier layer 62m is additionally formed on the first sub-diffusion barrier pattern 61, the diffusion barrier pattern 60, which will be discussed below, can be formed relatively thick on the sidewalls of the bit line spacer BSP, and the second void V2 can have a reduced size. Therefore, process failures such as delamination or disconnection of the diffusion barrier pattern 60 can be reduced or prevented. As a result, the reliability of the semiconductor device can be improved.

[0065] refer to Figure 4G , a third CMP process may be performed to planarize the top surface 62m_s of the second diffusion barrier layer 62m. The top surface 62m_s of the second diffusion barrier layer 62m may be located at a vertical level higher than the vertical level of the top surface 38_s of the bit line capping pattern 38 and the vertical level of the top surface BSP_s of the bit line spacer BSP. However, the present inventive concept is not limited thereto, and the third CMP process may be omitted.

[0066] refer to Figure 4H A landing pad layer LP_m may be formed on the front surface of the substrate 1. The landing pad layer LP_m may be formed by sputtering, physical vapor deposition (PVD), or chemical vapor deposition (CVD). A fourth CMP process may be performed to planarize the landing pad layer LP_m. A mask pattern MK may be formed on the landing pad layer LP_m to define the planar shape of the landing pad LP, as will be discussed below. The mask pattern MK may be formed to vertically overlap the bit line BL and the storage node contact BC.

[0067] refer to Figure 4I, the mask pattern MK can be used as an etching mask to perform a fourth anisotropic etching process to partially remove the landing pad layer LP_m, the first sub-diffusion barrier pattern 61, and the second diffusion barrier layer 62m, thereby forming the landing pad LP and the diffusion barrier pattern 60, and also forming a second groove R2 exposing the diffusion barrier pattern 60. The diffusion barrier pattern 60 may include a first sub-diffusion barrier pattern 61 and a second sub-diffusion barrier pattern 62. When the first sub-diffusion barrier pattern 61 and the second sub-diffusion barrier pattern 62 are formed of the same material, the first sub-diffusion barrier pattern 61 and the second sub-diffusion barrier pattern 62 may be integrally connected into a single integral piece without any interface (e.g., without any visible interface), and this is the case in Figure 3A and 3B Shown in.

[0068] In the fourth anisotropic etching process, the bit line capping pattern 38 and the bit line spacer BSP may also be partially removed to expose top surfaces and upper sidewalls thereof. The fourth anisotropic etching process may achieve node separation on the substrate 1 .

[0069] Return Reference Figure 2 , the mask pattern MK may be removed. The second groove R2 may be filled with a dielectric material to form a landing pad isolation pattern 50. Thereafter, a data storage element DSP may be formed on the landing pad LP. Thus, a device such as Figure 1 and Figure 2 The semiconductor device shown.

[0070] Figure 5 shows an example embodiment along Figure 1 A cross-sectional view taken along lines AA' and BB'. Figure 6 Shown Figure 5 An enlarged view of part P2.

[0071] refer to Figure 1 、 Figure 5 and Figure 6 In some example embodiments, the diffusion barrier pattern 60 may include a first sub-diffusion barrier pattern 61 and a second sub-diffusion barrier pattern 62. The first sub-diffusion barrier pattern 61 may cover the top surface of the storage node ohmic layer 40 and the sidewalls of the bit line spacer BSP. The first sub-diffusion barrier pattern 61 may have a flat top surface 61_s. The top surface 61_s of the first sub-diffusion barrier pattern 61 may be coplanar with the top surface BSP_s of the bit line spacer BSP and the top surface 38_s of the bit line capping pattern 38.

[0072] The second sub-diffusion barrier pattern 62 may cover the sidewalls and a portion of the bottom surface of the first sub-diffusion barrier pattern 61. The second sub-diffusion barrier pattern 62 may extend to cover the top surface 61_s of the first sub-diffusion barrier pattern 61, the top surface BSP_s of the bit line spacer BSP, and the top surface 38_s of the bit line capping pattern 38. The second sub-diffusion barrier pattern 62 may have a flat top surface 62_s. In some example embodiments, unlike the illustrated embodiment, the second sub-diffusion barrier pattern 62 may have an uneven structure on the top surface 62_s.

[0073] The first sub-diffusion barrier pattern 61 and the second sub-diffusion barrier pattern 62 may include materials different from each other. In this case, an interface may exist between the first sub-diffusion barrier pattern 61 and the second sub-diffusion barrier pattern 62. The second sub-diffusion barrier pattern 62 may be additionally provided on the first sub-diffusion barrier pattern 61, thereby reducing or preventing disconnection failure of the diffusion barrier pattern 60 occurring on the sidewall of the bit line spacer BSP. Therefore, the semiconductor device may be free of failures and may have improved reliability. Other configurations may be similar to those described above. Figure 1 、 Figure 2 and Figure 3A The configurations discussed are the same or similar.

[0074] Figure 7 shows an example embodiment along Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0075] refer to Figure 1 and Figure 7 In some example embodiments, the bit line spacer BSP may include a first subspacer 21, a second subspacer 23, and a third subspacer 25 sequentially disposed from the sidewall of the bit line BL. The first subspacer 21 may cover the sidewall of the bit line BL and the sidewall of the bit line capping pattern 38. The first subspacer 21 may extend to cover the inner sidewall and bottom surface of the first recess R1. The second subspacer 23 may cover the lower sidewall of the first subspacer 21 and expose the upper sidewall of the first subspacer 21. The first subspacer 21 may extend to cover the bottom surface of the second subspacer 23. The third subspacer 25 may cover the sidewall of the second subspacer 23. Unlike shown, the lower end of the first subspacer 21 may be in contact with the third subspacer 25.

[0076] As along Figure 7As shown in the cross-sectional view taken along line AA', the upper end of the first subspacer 21 may be higher than the upper ends of the second subspacer 23 and the third subspacer 25. The upper sidewall of the first subspacer 21 may not be covered by the second subspacer 23 and the third subspacer 25. The second subspacer 23 may include a material different from that of the first subspacer 21 and the third subspacer 25. For example, the first subspacer 21 and the third subspacer 25 may include silicon nitride. The second subspacer 23 may include silicon oxide. In some example embodiments, the second subspacer 23 may be an air gap.

[0077] Although not shown, a fourth subspacer may be additionally provided to cover the upper sidewall of the first subspacer 21 and the top surface of the second subspacer 23. The fourth subspacer may serve to reinforce the thin upper portion of the first subspacer 21.

[0078] The diffusion barrier pattern 60 may cover the top surface of the storage node ohmic layer 40 and the sidewalls of the third subspacer 25. The diffusion barrier pattern 60 may cover the upper sidewalls of the first subspacer 21 and the second subspacer 23. The diffusion barrier pattern 60 may extend to cover the top surface of the bit line capping pattern 38. Other configurations may be similar to those of the reference Figure 1 、 2 , 3A and 3B are the same or similar to those discussed.

[0079] Figure 8 shows an example embodiment along Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0080] refer to Figure 1 、 Figure 7 and Figure 8 , Figure 8 The semiconductor device may have a structure in which the diffusion barrier pattern 60 includes Figure 7 The first sub-diffusion barrier pattern 61 and the second sub-diffusion barrier pattern 62 in the structure of FIG. The first sub-diffusion barrier pattern 61 may cover the top surface of the storage node ohmic layer 40 and the sidewalls of the third sub-spacer 25. The first sub-diffusion barrier pattern 61 may cover the upper sidewalls of the first sub-spacer 21 and the second sub-spacer 23. The first sub-diffusion barrier pattern 61 may have a flat top surface. The top surface of the first sub-diffusion barrier pattern 61 may be coplanar with the top surface of the bit line spacer BSP and the top surface of the bit line capping pattern 38.

[0081] The second sub-diffusion barrier pattern 62 may cover sidewalls of the first sub-diffusion barrier pattern 61 and a portion of the bottom surface contacting the storage node ohmic layer 40. The second sub-diffusion barrier pattern 62 may cover top surfaces of the first sub-diffusion barrier pattern 61 and the bit line capping pattern 38.

[0082] The first sub-diffusion barrier pattern 61 and the second sub-diffusion barrier pattern 62 may include materials different from each other. In this case, an interface may exist between the first sub-diffusion barrier pattern 61 and the second sub-diffusion barrier pattern 62. Other configurations may be similar to those of reference Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B and Figure 7 The configurations discussed are the same or similar.

[0083] In a semiconductor device according to the present invention, a diffusion barrier pattern connecting a landing pad to a storage node contact can be formed relatively thickly on the sidewalls of a bitline spacer. Consequently, disconnection failures of the diffusion barrier pattern on the sidewalls of the bitline spacer can be reduced or prevented. Consequently, semiconductor device failures can be reduced or prevented, thereby improving the reliability of the semiconductor device.

[0084] In the method for manufacturing a semiconductor device according to the present invention, a second sub-diffusion barrier layer can be formed on the first sub-diffusion barrier pattern. This reduces the size of the gaps between bit line spacers and increases the thickness of the diffusion barrier pattern compared to forming only the first sub-diffusion barrier pattern. Consequently, disconnection failures of the diffusion barrier pattern on the sidewalls of the bit line spacers can be reduced or prevented. Consequently, the reliability of the semiconductor device can be improved.

[0085] Although some exemplary embodiments of the present invention have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present invention. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the present invention.

[0086] CROSS-REFERENCE TO RELATED APPLICATIONS

[0087] This application claims the benefit of Korean Patent Application No. 10-2024-0026473 filed on February 23, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: a plurality of device isolation patterns in the substrate, the device isolation patterns defining a plurality of active portions, the active portions extending in a first direction; a first impurity region on a central region of each of the active portions; a plurality of second impurity regions on an edge of each of the active portions; a bit line connected to the first impurity region, the bit line extending across the active portion in a second direction, the second direction intersecting the first direction; a bit line cap pattern on the bit line; a storage node contact in contact with each of the second impurity regions; a diffusion barrier pattern covering a top surface of the bit line capping pattern and a top surface of the storage node contact; as well as a landing pad on the diffusion barrier pattern, A top surface of the diffusion barrier pattern is flat.

2. The device according to claim 1, further comprising: a bit line spacer covering a sidewall of the bit line and a sidewall of the bit line capping pattern, wherein a top surface of the bit line spacer is flat, and wherein the top surface of the bit line capping pattern is coplanar with the top surface of the bit line spacer.

3. The device according to claim 2, wherein The diffusion barrier pattern includes a first portion and a second portion, The first portion covers the top surface of the bit line spacer and has a first thickness, and The second portion covers an upper sidewall of the bit line spacer and has a second thickness greater than the first thickness.

4. The device according to claim 3, wherein The diffusion barrier pattern further includes a third portion below the second portion, the third portion covering a sidewall of the bit line spacer, and The third portion has a third thickness that is greater than the first thickness and less than the second thickness.

5. The device according to claim 3, wherein The diffusion barrier pattern has the first thickness on the bit line capping pattern. 6 . The device of claim 1 , wherein a lower end of the landing pad is at a level higher than that of the top surface of the bit line capping pattern.

7. The device according to claim 1, wherein The landing pad includes a plurality of landing pads, The storage node contact includes a plurality of storage node contacts, and The device further includes landing pad isolation patterns respectively on the storage node contacts and respectively between adjacent pairs of the bonding pads.

8. The device according to claim 1, wherein the diffusion barrier pattern comprises: a first sub-diffusion barrier pattern covering a sidewall of the bit line capping pattern; as well as a second sub-diffusion barrier pattern covering the top surface of the bit line capping pattern and sidewalls of the first sub-diffusion barrier pattern, The first sub-diffusion barrier pattern and the second sub-diffusion barrier pattern include different materials from each other.

9. The device according to claim 1, further comprising: a bit line spacer covering a sidewall of the bit line and a sidewall of the bit line capping pattern, wherein the bit line spacer comprises: a first sub-spacer covering the sidewall of the bit line, a second subspacer covering a lower sidewall of the first subspacer and exposing an upper sidewall of the first subspacer, and The third sub-spacer covers the sidewalls of the second sub-spacer.

10. A semiconductor device comprising: a plurality of device isolation patterns in the substrate, the device isolation patterns defining a plurality of active portions, the active portions extending in a first direction; a plurality of word lines in the substrate, the word lines extending across the active portion in a second direction, the second direction intersecting the first direction; a first impurity region on a central region of each of the active portions; a plurality of second impurity regions on an edge of each of the active portions; a bit line connected to the first impurity region, the bit line extending across the word line in the second direction; a bit line cap pattern on the bit line; a bit line spacer covering a sidewall of the bit line and a sidewall of the bit line capping pattern; a storage node contact in contact with each of the second impurity regions; a diffusion barrier pattern covering a top surface of the bit line capping pattern, a top surface of the storage node contact, and a top surface and sidewalls of the bit line spacer; as well as a landing pad on the diffusion barrier pattern, The diffusion barrier pattern has a first thickness on the top surface of the bit line capping pattern and a second thickness on the sidewall of the bit line capping pattern, the second thickness being greater than the first thickness.

11. The device according to claim 10, wherein The top surface of the bit line capping pattern is flat, The top surface of the bit line spacer is flat, and wherein the top surface of the bit line capping pattern is coplanar with the top surface of the bit line spacer.

12. The device according to claim 10, wherein The diffusion barrier pattern has the first thickness on the top surface of the bit line spacer.

13. The device according to claim 10, wherein the diffusion barrier pattern comprises: a first portion on an upper sidewall of the bit line spacer; as well as a second portion below the first portion and having the second thickness, The first portion has a third thickness greater than the second thickness. 14 . The device of claim 10 , wherein a portion of the diffusion barrier pattern on the bit line capping pattern has a flat top surface. 15 . The device of claim 10 , wherein a top surface of the diffusion barrier pattern on the bit line capping pattern has an uneven structure.

16. The device according to claim 10, wherein The bit line spacer comprises: a first sub-spacer covering the sidewall of the bit line; a second sub-spacer covering a lower sidewall of the first sub-spacer and exposing an upper sidewall of the first sub-spacer; and The third sub-spacer covers the sidewalls of the second sub-spacer.

17. A semiconductor device comprising: a plurality of device isolation patterns in the substrate, the device isolation patterns defining a plurality of active portions, the active portions extending in a first direction; a first impurity region on a central region of each of the active portions; a plurality of second impurity regions on an edge of each of the active portions; a bit line connected to the first impurity region, the bit line extending across the active portion in a second direction, the second direction intersecting the first direction; a bit line cap pattern on the bit line; a bit line spacer covering a sidewall of the bit line and a sidewall of the bit line capping pattern; a storage node contact in contact with each of the second impurity regions; a first sub-diffusion barrier pattern covering a top surface of the storage node contact and a sidewall of the bit line spacer; a second sub-diffusion barrier pattern covering top surfaces of the first sub-diffusion barrier pattern and the bit line capping pattern; as well as Landing pads are formed on the first and second sub-diffusion barrier patterns. 18 . The device of claim 17 , wherein top surfaces of the first sub-diffusion barrier pattern, the top surface of the bit line capping pattern, and top surfaces of the bit line spacers are flat and coplanar with each other. 19 . The device of claim 17 , wherein the second sub-diffusion barrier pattern extends to cover the top surface of the bit line capping pattern, a top surface of the bit line spacer, and a top surface of the first sub-diffusion barrier pattern. 20 . The device of claim 17 , wherein the first sub-diffusion barrier pattern and the second sub-diffusion barrier pattern comprise different materials from each other.

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