Chromium-silicon thin-film resistor structure and preparation method thereof

Abstract

The invention belongs to the technical field of silicon microelectronics, and discloses a chromium-silicon thin-film resistor structure and a preparation method thereof. The silicon dioxide insulating layer is formed on the surface of the substrate silicon wafer; the chromium-silicon resistance layer and the metal barrier layer are sequentially stacked on the silicon dioxide insulation layer, and the chromium-silicon resistance layer is provided with a preset resistance pattern; the metal connecting line layer covers the metal barrier layer, and a metal interconnection structure is formed on the metal connecting line layer; the silicon dioxide passivation layer and the silicon nitride passivation layer sequentially cover the metal wiring layer, only the silicon dioxide passivation layer is reserved in a region right above the chromium-silicon resistance layer, and an opening structure is formed in a region, corresponding to the chromium-silicon resistance layer, of the silicon nitride passivation layer. The invention aims to improve the resistance stability of the resistor.

Description

Technical Field

[0001] The present invention belongs to the technical field of silicon microelectronics, and in particular relates to a chromium silicon thin film resistor structure and a preparation method thereof. Background Art

[0002] High-precision and high-stability CrSi thin film resistors (CrSiThin Film Resistor) are high-precision resistor devices widely used in high-precision analog circuits. The manufacturing of CrSi thin film resistors involves several key steps, including thin film deposition, photolithography, etching, and alloying. To meet the requirements of high precision and high stability, a reasonable structural design can effectively optimize the resistor's electrical performance, reduce the impact of external factors on the resistor value, and thus improve the resistor's overall performance.

[0003] During the aging process of thin-film resistors, it was discovered that after a certain period of use at a certain temperature and under a certain electrical stress, the resistance of the thin-film resistor becomes unstable. This resistance instability not only affects the performance of the resistor itself but can also affect the stability of the entire circuit system, even causing the circuit to malfunction. Traditional methods for thin-film resistor structure and layout design often do not specifically remove the silicon nitride dielectric above the thin-film resistor. This makes the resistor prone to resistance deviation during the subsequent aging process. When the deviation is large, it can even cause the corresponding circuit indicators to exceed the tolerance, seriously affecting the performance of the circuit system. Summary of the Invention

[0004] In response to the problems existing in the prior art, the present invention provides a chromium silicon thin film resistor structure and a preparation method, the purpose of which is to improve the resistance stability of the resistor.

[0005] In order to solve the above technical problems, the present invention is implemented through the following technical solutions:

[0006] According to a first aspect of the present invention, there is provided a chromium silicon thin film resistor structure, comprising:

[0007] substrate silicon wafer;

[0008] A silicon dioxide insulating layer formed on the surface of the base silicon wafer;

[0009] a chromium silicon resistance layer and a metal barrier layer sequentially stacked on the silicon dioxide insulation layer, wherein the chromium silicon resistance layer has a predetermined resistance pattern;

[0010] A metal wiring layer covering the metal barrier layer, wherein the metal wiring layer forms a metal interconnection structure;

[0011] A silicon dioxide passivation layer and a silicon nitride passivation layer are sequentially covered on the metal wiring layer, wherein only the silicon dioxide passivation layer is retained in the area directly above the chromium silicon resistor layer, and the silicon nitride passivation layer forms an opening structure in the area corresponding to the chromium silicon resistor layer.

[0012] In a possible implementation manner of the first aspect, the boundary of the opening structure expands outward from the boundary of the chromium silicon resistor layer by 10 micrometers to 20 micrometers.

[0013] In a possible implementation manner of the first aspect, the thickness of the silicon dioxide passivation layer is 5000 angstroms to 7000 angstroms.

[0014] In a possible implementation manner of the first aspect, the thickness of the silicon nitride passivation layer is 2000 angstroms to 3000 angstroms.

[0015] In a possible implementation manner of the first aspect, the metal barrier layer is a tungsten-titanium thin film with a thickness of 600 angstroms to 900 angstroms.

[0016] In a possible implementation of the first aspect, the thickness of the chromium silicon resistance layer is 100 angstroms to 300 angstroms.

[0017] In a possible implementation manner of the first aspect, the thickness of the silicon dioxide insulating layer is 10,000 angstroms to 15,000 angstroms.

[0018] In a possible implementation manner of the first aspect, the metal wiring layer is an aluminum layer and has a thickness of 10,000 angstroms to 15,000 angstroms.

[0019] According to a second aspect of the present invention, a method for preparing a chromium silicon thin film resistor structure is provided, comprising:

[0020] S1, growing a silicon dioxide insulating layer on the surface of the base silicon wafer;

[0021] S2, sequentially depositing a chromium silicon resistance layer and a metal barrier layer on the silicon dioxide insulating layer;

[0022] S3, performing photolithography and etching on the chromium silicon resistor layer to form a predetermined resistor pattern;

[0023] S4, depositing a metal wiring layer and forming a metal interconnect structure by photolithography and etching;

[0024] S5, sequentially depositing a silicon dioxide passivation layer and a silicon nitride passivation layer on the metal interconnect structure;

[0025] S6. Remove the silicon nitride passivation layer 7 covering the chromium silicon resistor layer through photolithography and etching processes.

[0026] In a possible implementation of the second aspect, in step S6, the etching range is 10 microns to 20 microns beyond the boundary of the chromium silicon resistor layer.

[0027] Compared with the prior art, the present invention has at least the following beneficial effects:

[0028] The present invention provides a chromium silicon thin film resistor structure, which effectively solves the problem of unstable resistance value by retaining only the silicon dioxide passivation layer in the area directly above the chromium silicon resistor layer in the chromium silicon thin film resistor structure, and forming an opening structure in the silicon nitride passivation layer in the area corresponding to the chromium silicon resistor layer, that is, removing the silicon nitride passivation layer above the chromium silicon resistor layer in a targeted manner. Experimental results show that the rate of change of resistance before and after aging is reduced from 0.1% before removing the silicon nitride passivation layer to 0.01%, which fully demonstrates that removing the silicon nitride passivation layer above the chromium silicon resistor layer can greatly improve the stability of the resistance value, so that the resistor can maintain a relatively constant resistance value under different usage conditions, thereby ensuring the stability of the performance of the circuit system. In summary, the chromium silicon thin film resistor structure of the present invention effectively improves the stability of the resistance value by removing the silicon nitride passivation layer above the chromium silicon resistor layer, thereby improving the overall performance of the circuit system.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the specific embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a chromium silicon thin film resistor structure according to the present invention;

[0032] Figure 2 Schematic diagram of the thin film resistor layout.

[0033] In the figure: 1-base silicon wafer; 2-silicon dioxide insulation layer; 3-chromium silicon resistor layer; 4-metal barrier layer; 5-metal wiring layer; 6-silicon dioxide passivation layer; 7-silicon nitride passivation layer; 8-silicon nitride etching pattern; 9-metal wiring pattern; 10-chromium silicon resistor pattern. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] Example 1

[0036] A chromium silicon thin film resistor structure is prepared as follows:

[0037] A 10,000-angstrom thick silicon dioxide insulating layer 2 is grown on the surface of a substrate silicon wafer 1 using atmospheric pressure chemical vapor deposition. The silicon dioxide insulating layer 2 acts as an insulating medium between the resistor and the substrate, effectively isolating the resistor from the substrate and preventing leakage.

[0038] A chromium-silicon resistor layer 3 and a metal barrier layer 4 are sequentially deposited on the silicon dioxide insulating layer 2. The chromium-silicon resistor layer 3 is 100 angstroms thick, while the metal barrier layer 4, a tungsten-titanium thin film, is 600 angstroms thick. The metal barrier layer 4 prevents metal diffusion from affecting the resistor layer during subsequent processes, ensuring resistor stability.

[0039] The chromium-silicon resistor layer 3 and the metal barrier layer 4 are subjected to photolithography and etching processes to form a predetermined resistor pattern. It should be understood that, using the chromium-silicon resistor pattern 10, the photolithography process transfers the resistor pattern to the photoresist through steps such as exposure and development. The etching process then removes excess chromium-silicon material according to the photoresist pattern, thereby obtaining the desired resistor pattern.

[0040] A metal wiring layer 5 is deposited, made of aluminum and having a thickness of 15,000 angstroms. A metal interconnect structure is then formed using the metal wiring pattern 9 through photolithography and etching processes to achieve electrical connections between the resistor and other circuit components.

[0041] A silicon dioxide passivation layer 6 and a silicon nitride passivation layer 7 are sequentially deposited on the metal interconnect structure. The thickness of the silicon dioxide passivation layer 6 is 5000 angstroms, and the thickness of the silicon nitride passivation layer 7 is 2000 angstroms. The passivation layers protect the resistors and metal interconnects from damage from the external environment.

[0042] The silicon nitride passivation layer 7 covering the chromium silicon resistor layer 3 is removed through photolithography and etching. A silicon nitride etching pattern 8 is used for etching, extending 10 microns beyond the boundary of the chromium silicon resistor layer 3. This ensures that only the silicon dioxide passivation layer 6 remains above the resistor layer, thereby improving the resistor's aging stability.

[0043] Perform solder joint photolithography and etching to prepare for subsequent circuit packaging and testing.

[0044] Example 2

[0045] A chromium silicon thin film resistor structure is prepared as follows:

[0046] A silicon wafer 1 is selected as a substrate, and a silicon dioxide insulating layer 2 with a thickness of 15,000 angstroms is grown on the surface of the substrate using a plasma-enhanced chemical vapor deposition process. This process has a high deposition rate and good film quality.

[0047] On the silicon dioxide insulating layer 2, a chromium silicon resistor layer 3 and a metal barrier layer 4 are sequentially deposited. The thickness of the chromium silicon resistor layer 3 is 300 angstroms, and the metal barrier layer 4 is a tungsten titanium thin film with a thickness of 900 angstroms.

[0048] The chromium silicon resistor layer 3 and the metal barrier layer 4 are subjected to photolithography and etching processes to form a predetermined resistor pattern.

[0049] A metal wiring layer 5 is deposited, made of aluminum with a thickness of 15,000 angstroms, and then a metal interconnection structure is formed through photolithography and etching processes.

[0050] A silicon dioxide passivation layer 6 and a silicon nitride passivation layer 7 are sequentially deposited on the metal interconnect structure. The thickness of the silicon dioxide passivation layer 6 is 7000 angstroms, and the thickness of the silicon nitride passivation layer 7 is 3000 angstroms.

[0051] The silicon nitride passivation layer 7 covering the chromium silicon resistor layer 3 is removed through photolithography and etching processes. The etching range is 20 microns beyond the boundary of the chromium silicon resistor layer 3 to ensure that only the silicon dioxide passivation layer 6 remains in the area above the resistor layer, improving the aging stability of the resistor.

[0052] Perform solder joint photolithography and etching to prepare for subsequent circuit packaging and testing.

[0053] Through the above-described embodiments, a chromium-silicon thin-film resistor structure with high precision and high stability can be fabricated. By removing the silicon nitride passivation layer above the chromium-silicon resistor layer, this structure effectively reduces the instability of the resistor's value during the aging process, improving the resistor's overall performance and making it suitable for applications such as high-precision analog circuits.

[0054] In the description of the present invention, it should be understood that the terms "upper", "lower", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0056] In the present invention, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can mean fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0057] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0058] In the present invention, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0059] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A chromium silicon thin film resistor structure, characterized in that: include: Base silicon wafer (1); A silicon dioxide insulating layer (2) formed on the surface of the base silicon wafer (1); A chromium silicon resistance layer (3) and a metal barrier layer (4) are sequentially stacked on the silicon dioxide insulation layer (2), wherein the chromium silicon resistance layer (3) has a predetermined resistance pattern; a metal wiring layer (5) covering the metal barrier layer (4), the metal wiring layer (5) forming a metal interconnection structure; A silicon dioxide passivation layer (6) and a silicon nitride passivation layer (7) are sequentially covered on the metal wiring layer (5), wherein only the silicon dioxide passivation layer (6) is retained in the area directly above the chromium silicon resistor layer (3), and the silicon nitride passivation layer (7) forms an opening structure in the area corresponding to the chromium silicon resistor layer (3).

2. The chromium silicon thin film resistor structure according to claim 1, characterized in that: The boundary of the opening structure extends outward by 10 micrometers to 20 micrometers relative to the boundary of the chromium silicon resistance layer (3).

3. The chromium silicon thin film resistor structure according to claim 1, characterized in that: The thickness of the silicon dioxide passivation layer (6) is 5000 angstroms to 7000 angstroms.

4. The chromium silicon thin film resistor structure according to claim 1, characterized in that: The thickness of the silicon nitride passivation layer (7) is 2000 angstroms to 3000 angstroms.

5. The chromium silicon thin film resistor structure according to claim 1, characterized in that: The metal barrier layer (4) is a tungsten-titanium thin film with a thickness of 600 angstroms to 900 angstroms.

6. The chromium silicon thin film resistor structure according to claim 1, characterized in that: The thickness of the chromium silicon resistance layer (3) is 100 angstroms to 300 angstroms.

7. The chromium silicon thin film resistor structure according to claim 1, characterized in that: The thickness of the silicon dioxide insulating layer (2) is 10,000 angstroms to 15,000 angstroms.

8. The chromium silicon thin film resistor structure according to claim 1, characterized in that: The metal wiring layer (5) is an aluminum layer with a thickness of 10,000 angstroms to 15,000 angstroms.

9. A method for preparing a chromium silicon thin film resistor structure, characterized in that: include: S1, growing a silicon dioxide insulating layer (2) on the surface of a base silicon wafer (1); S2, sequentially depositing a chromium silicon resistance layer (3) and a metal barrier layer (4) on the silicon dioxide insulating layer (2); S3, performing photolithography and etching on the chromium silicon resistance layer (3) to form a predetermined resistance pattern; S4, depositing a metal wiring layer (5), and forming a metal interconnection structure by photolithography and etching; S5, sequentially depositing a silicon dioxide passivation layer (6) and a silicon nitride passivation layer (7) on the metal interconnect structure; S6. Remove the silicon nitride passivation layer 7 covering the chromium silicon resistor layer (3) through photolithography and etching processes.

10. The method for structural design of a high-precision chromium silicon thin film resistor according to claim 9, characterized in that: In step S6, the etching range is 10 microns to 20 microns outside the boundary of the chromium silicon resistor layer (3).

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