Preparation method of metal oxide semiconductor field effect transistor and transistor

Abstract

The invention discloses a preparation method of a metal oxide semiconductor field effect transistor and the transistor, and belongs to the technical field of semiconductor devices, the surface of a substrate is pretreated through a chemical oxidation method, nucleation and growth of an insulating layer can be promoted, interface characteristics can be improved, the quality of an ultrathin insulating layer can be improved, and the contact resistivity can be effectively reduced. According to the main technical scheme, the method comprises the following steps: preparing a heavily doped intermediate device in a source region and a drain region; performing ozone treatment on the source electrode region and the drain electrode region of the intermediate device; depositing an insulating layer on the intermediate device; depositing a metal layer on the insulating layer; and carrying out heat treatment on the intermediate device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor device technology, and specifically relates to a method for preparing a metal oxide semiconductor field effect transistor and a transistor. Background Art

[0002] Amidst the rapid advancement of semiconductor technology, complementary metal-oxide-semiconductor (CMOS) technology continues to advance towards smaller dimensions. As technology nodes reach 16 / 14nm and below, the source-drain contact resistance becomes increasingly critical to device performance. Contact resistance can be reduced primarily by increasing the contact area and reducing the contact resistivity. Among the many methods for reducing contact resistivity, reducing the Schottky barrier height is a crucial approach. However, the Fermi level pinning effect prevents the Schottky barrier height from being altered simply by adjusting the metal work function, posing a significant challenge to reducing contact resistivity. Therefore, when constructing ohmic contacts on semiconductor substrates, effectively releasing or mitigating the pinned Fermi level becomes a key issue in overcoming technical bottlenecks.

[0003] In order to solve the above problems, the metal-insulator-semiconductor (MIS) structure came into being. By introducing an insulating layer between the metal and the semiconductor, it successfully blocked the penetration of free-moving electron waves into the semiconductor, significantly reduced the states (MIGS) introduced by the metal in the semiconductor band gap, and thus released the Fermi level pinning.

[0004] Currently, a large amount of theoretical research and rich practical experience have jointly confirmed that in the MIS structure, there is an extremely close correlation between the thickness of the insulating layer and the contact resistivity. In principle, the thinner the insulating layer, the more conducive it is to reducing the contact resistivity, thereby significantly improving device performance. However, in the actual application scenarios of the MIS structure, when trying to reduce the thickness of the insulating layer to an extremely thin level that can meet the ideal contact resistivity, the problem of uneven growth of the insulating layer is frequently encountered. Uneven growth of the insulating layer will cause its quality to be greatly reduced, which is specifically manifested in inconsistent thickness and internal defects. This poor quality of the insulating layer will seriously damage the interface characteristics between the insulating layer and the semiconductor and metal, hindering the transmission of carriers at the interface and exacerbating the scattering phenomenon. The end result is that even if the thickness of the insulating layer is theoretically reduced, the contact resistivity is still difficult to effectively improve due to the deterioration of the interface characteristics, which seriously restricts the advantages of the MIS structure in improving device performance. Summary of the Invention

[0005] In view of this, the present application provides a method for preparing a metal oxide semiconductor field effect transistor and a transistor, which pretreats the substrate surface by chemical oxidation, thereby promoting the nucleation and growth of the insulating layer, improving the interface characteristics, and improving the quality of the ultra-thin insulating layer, thereby effectively reducing the contact resistivity.

[0006] To achieve the above objectives, this application mainly provides the following technical solutions:

[0007] In one aspect of the present application, a method for preparing a metal oxide semiconductor field effect transistor is provided, comprising:

[0008] preparing an intermediate device with heavily doped source and drain regions;

[0009] performing ozone treatment on the source region and the drain region of the intermediate device;

[0010] depositing an insulating layer on the intermediate device;

[0011] depositing a metal layer on the insulating layer;

[0012] The intermediate device is heat treated.

[0013] Optionally, after the source region and the drain region of the intermediate device are subjected to ozone treatment, surfaces of the source region and the drain region form a hydrophilic surface state.

[0014] Optionally, the ozone treatment is carried out at room temperature, and the reaction time is 3 to 20 seconds.

[0015] Optionally, the insulating layer is deposited by atomic layer deposition.

[0016] Optionally, the heat treatment temperature is 400-600° C., and the reaction time is 10-60 s.

[0017] In another aspect of the present application, a transistor is provided. The transistor has a metal-insulator-semiconductor structure, and the metal-insulator-semiconductor structure is manufactured using any of the methods described above.

[0018] Optionally, the transistor includes:

[0019] substrate;

[0020] a source region and a drain region located on both sides of the upper portion of the substrate;

[0021] a gate structure located above the substrate and between the source region and the drain region;

[0022] a stack located above the source region and the drain region;

[0023] A metal layer is located above the stack.

[0024] Optionally, the stack is a multi-component gradient structure formed by heat treating the insulating layer between the source region, the drain region and the metal layer, and is used to reduce the contact resistivity between the source region, the drain region and the metal layer.

[0025] Optionally, the insulating layer is a metal oxide layer, the material of the metal oxide layer is zirconium oxide or hafnium oxide, and the thickness of the metal oxide layer is 0.5-2 nm.

[0026] Optionally, the metal layer is made of titanium and / or titanium nitride, and the thickness of the metal layer is 2-10 nm.

[0027] By means of the above technical solution, this application has at least the following beneficial effects:

[0028] The preparation method and transistor of the metal oxide semiconductor field effect transistor provided in the embodiment of the present application can form a hydrophilic surface state on the surface of the source region and the drain region by ozone treatment of the source region and the drain region. This hydrophilic surface state can significantly improve the adsorption and spreading performance of the insulating layer precursor on the surface of the intermediate device, so that the insulating layer can more evenly nucleate and grow on the surface of the intermediate device during the subsequent precipitation process, which is conducive to the growth of a uniform ultra-thin insulating layer. Compared with the uneven growth of the insulating layer in the traditional process, the hydrophilic surface promotes a more regular arrangement of the atoms in the insulating layer, greatly reduces internal defects, and thus improves the quality of the insulating layer. At the same time, it can also improve the properties of the surface of the intermediate device, specifically: on the one hand, it reduces the interface state density, reduces the dangling bonds generated on the semiconductor surface due to incomplete bonding of atoms, and makes the electronic state of the semiconductor surface more stable; on the other hand, it makes the interface characteristics between the subsequently deposited insulating layer and the semiconductor better, reducing the scattering of carriers at the interface. Combined with these positive effects, it can ultimately effectively reduce the contact resistivity and further optimize the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A flowchart of a method for preparing a metal oxide semiconductor field effect transistor according to an optional embodiment of the present application;

[0030] Figure 2 for Figure 1 A schematic flow chart of one of the steps in the preparation method shown;

[0031] Figure 3 for Figure 1 A schematic flow chart of one of the steps in the preparation method shown;

[0032] Figure 4 for Figure 1 A schematic flow chart of one of the steps in the preparation method shown;

[0033] Figure 5 for Figure 1 A schematic flow chart of one of the steps in the preparation method shown;

[0034] Figure 6 for Figure 1 A schematic flow chart of one of the steps in the preparation method shown.

[0035] The reference numerals indicate:

[0036] 1. Substrate; 2. Source region; 3. Drain region; 4. Gate structure; 5. Insulating layer; 6. Metal layer; 7. Stack. DETAILED DESCRIPTION

[0037] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application can be combined with each other.

[0038] In this embodiment, a method for preparing a metal oxide semiconductor field effect transistor is provided. Figure 1 As shown, the method includes:

[0039] Step S101: preparing an intermediate device with heavily doped source region 2 and drain region 3 .

[0040] In this embodiment, see Figure 2 As shown, on a semiconductor substrate 1 (such as a silicon substrate 1), a high concentration of impurity atoms is introduced into specific regions (i.e., the source region 2 and drain region 3 to be formed subsequently) through processes such as ion implantation or diffusion. These impurity atoms can be elements different from the material of the semiconductor substrate 1. For example, in a silicon substrate 1, if an N-type semiconductor region is to be formed, pentavalent elements such as phosphorus (P) and arsenic (As) are usually implanted; if a P-type semiconductor region is to be formed, trivalent elements such as boron (B) are implanted. The purpose of heavy doping is to reduce the resistance of the source region 2 and drain region 3 and form a good ohmic contact, thereby increasing the carrier concentration and enhancing the conductivity of the transistor, enabling it to transmit current more efficiently.

[0041] It should be noted that the choice of substrate 1 material is diverse. In this application, the substrate 1 can be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (SOI), germanium on insulator (GeOI), etc. This application takes silicon as an example to illustrate the specific steps of preparing an intermediate device with heavily doped source region 2 and drain region 3, and clarifies the positional relationship of each structure:

[0042] Step S1011: Prepare a silicon substrate 1 to provide a basic support structure for subsequent device manufacturing. As the foundation of the entire device, the silicon substrate 1 is located at the bottom layer of the entire structure. All subsequent structures will be built based on this substrate 1.

[0043] Step S1012: Shallow trench isolation (STI) is formed to electrically isolate devices and reduce mutual interference. The STI structure is embedded in the silicon substrate 1, forming a regular pattern on the surface of the silicon substrate 1 to separate different device areas. These shallow trenches are filled with insulating material to prevent current leakage and mutual interference between adjacent devices.

[0044] Step S1013: Forming the gate structure 4. This step does not limit the use of gate-first (deposition followed by etching) or gate-last (dummy gate formation followed by replacement gate) processes, and can be flexibly selected based on specific process requirements and design requirements. For the gate-first process, the gate structure 4 is a metal gate / high-k stack (MG / HK); for the gate-last process, the gate structure 4 is a dummy gate structure (amorphous silicon / gate oxide stack), which is subsequently removed through the dummy gate and filled with the metal gate / high-k stack to ultimately form a metal gate / high-k stack gate structure 4. The position of the gate structure 4 corresponds to the source region 2 and drain region 3 to be formed subsequently, and is used to control the current conduction between the source and drain.

[0045] Step S1014: Form a spacer dielectric layer to isolate and protect the device, ensuring stable electrical and physical performance between the various components. The spacer dielectric layer is located on both sides of the gate structure 4 and fits tightly against the gate structure 4. Its function is to isolate the gate from the subsequently formed source region 2, drain region 3, and contact metal, preventing electrical shorts between them and protecting the edges of the gate structure 4.

[0046] Step S1015: An interlayer dielectric (ILD) is formed to provide insulation and support for subsequent metal interconnect processes. The ILD covers the entire formed structure, including the shallow trench isolation, gate structure 4, and spacer dielectric layer. It fills the gaps between these structures and provides a smooth and insulating foundation for subsequent metal interconnection circuits on or within the ILD.

[0047] Step S1016: Form heavily doped source and drain regions and provide areas for silicide formation. Regarding the areas for silicide formation, there is no restriction on using either a silicide-first (source and drain heavily doped and silicide formed directly after gate etching) or a silicide-last (source and drain heavily doped, dielectric deposited to form contact holes, followed by silicide formation) process. Process planning can be tailored to actual conditions. The heavily doped source and drain regions 2 and 3 are located in the silicon substrate 1, on either side of the gate structure 4 / sidewall dielectric layer and bounded by shallow trench isolation (STI). They are formed in the silicon substrate 1 through processes such as ion implantation and are graphically defined between the gate structure 4 and the sidewall dielectric layer.

[0048] Step S201 : performing ozone treatment on the source region 2 and the drain region 3 of the intermediate device.

[0049] In this embodiment, see Figure 3 As shown, the intermediate device containing the heavily doped source and drain regions is placed in an environment containing ozone (O3), which is a strong oxidant. During the treatment process, ozone will chemically react with the surface of the source region 2 and the drain region 3. On the one hand, it can remove pollutants and impurities on the surface and play a role in cleaning the surface; on the other hand, the ozone treatment can form a hydrophilic surface state on the surface of the source and drain regions 3. This hydrophilic surface can significantly improve the adsorption and spreading performance of the intermediate device surface for the precursor of the insulating layer 5, which is conducive to the subsequent growth of a uniform ultra-thin insulating layer 5. At the same time, it can also reduce the interface state density, reduce the dangling bonds generated on the semiconductor surface due to incomplete atomic bonding, alleviate the Fermi pinning effect, and thus reduce the contact resistivity of the source and drain contacts.

[0050] Here, the ozone treatment is carried out at room temperature (such as 20°C, 21°C, 22°C, 23°C, 24°C, 25°C, etc.), and the reaction time is 3s, 4s, 5s, 6s, 7s, 8s, 9s, 10s, 11s, 12s, 13s, 14s, 15s, 16s, 17s, 18s, 19s, 20s, etc. It should be noted that the ozone treatment is carried out at room temperature and no additional heating or cooling operations are required on the intermediate device to reach a specific reaction temperature. Such conditions are relatively mild, which is conducive to reducing the complexity and cost of the process, and also avoids the adverse effects that high or low temperatures may cause to the intermediate device, such as thermal stress, changes in material properties, etc. At the same time, the reaction time is 3 to 20s, which can ensure that the ozone fully reacts with the surface, so that the surface forms a suitable hydrophilic state, and completes the relevant interface improvement process. It is understandable that if the reaction time is too short, an ideal hydrophilic surface and good interface properties may not be formed; while if the reaction time is too long, it may cause problems such as excessive oxidation, which will adversely affect device performance.

[0051] Step S301: depositing an insulating layer 5 on the intermediate device.

[0052] In this embodiment, see Figure 4 As shown, atomic layer deposition (ALD) technology is used to deposit a layer of insulating material on the ozone-treated intermediate device surface to form a uniform, high-quality, ultra-thin insulating layer 5. The function of insulating layer 5 is to form an insulating barrier between the metal layer 6 and the semiconductor, blocking the penetration of free-moving electron waves into the semiconductor and reducing the metal-induced states (MIGS) in the semiconductor band gap, thereby releasing the pinned Fermi level and reducing the contact resistivity.

[0053] Here, the insulating layer 5 is a metal oxide layer, and the material of the metal oxide layer is zirconium oxide (ZrO2) or hafnium oxide (HfO2). The thickness of the insulating layer 5 is 0.5nm, 1.0nm, 1.5nm, 2.0nm, etc. It should be noted that when the thickness of the insulating layer 5 is 0.5 to 2.0nm, it can maintain good interface characteristics while reducing the contact resistivity. It is understandable that if the insulating layer 5 is too thick, it will increase the difficulty of electron tunneling, resulting in increased resistance; and if the insulating layer 5 is too thin, it will be difficult to form a uniform film layer and a uniform interface.

[0054] Step S401 : depositing a metal layer 6 on the insulating layer 5 .

[0055] In this embodiment, see Figure 5 As shown, a layer of metal material is deposited on the surface of the insulating layer 5 using thin film deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) to form a metal layer 6. The metal layer 6 is used to form a good ohmic contact between the source region 2 and the drain region 3 and the hole metal.

[0056] Here, in order to ensure good contact characteristics between the metal layer 6 and the insulating layer 5 and the semiconductor to efficiently transmit current, the metal material forming the metal layer 6 is titanium (Ti), titanium nitride (TiN) or a combination of the two, and the thickness of the metal layer 6 is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc. It should be noted that the thickness of the metal layer 6 is 2 to 10nm, which can ensure good current transmission performance while ensuring stable contact characteristics between the metal layer 6 and the insulating layer 5 and the semiconductor. It is understandable that if the metal layer 6 is too thin, its film uniformity is reduced, and it is easy to cause burr-shaped defects on the interface when forming contact, which increases the source-drain contact resistivity and leads to an increase in RC delay. On the contrary, if the metal layer 6 is too thick, the proportion of low-resistance metal in the hole will be reduced, increasing the size of the contact hole body resistance.

[0057] Step S501: performing heat treatment on the intermediate device.

[0058] In this embodiment, see Figure 6 As shown, the intermediate device with the insulating layer 5 and the metal layer 6 is placed in a high temperature environment for treatment. The purpose of the heat treatment is to promote the interface reaction between the metal layer 6, the insulating layer 5 and the semiconductor, form a more stable contact interface, and optimize the electrical properties of the interface, such as reducing the contact resistance.

[0059] Here, the intermediate device with the insulating layer 5 and the metal layer 6 is heat-treated by a rapid thermal annealing process (RTP) or a laser annealing process. The heat treatment temperature is 400-600° C. and the reaction time is 10-60 seconds.

[0060] It should be noted that after heat treatment, a stack 7 is formed between the source and drain regions 2 and 3 and the metal layer 6. The thickness of the stack 7 is 4 to 20 nm. The stack 7 is a multi-resistance metal silicide layer, and the stack 7 exhibits a multi-component gradient structure. From a technical principle perspective, under the specific temperature and time conditions provided by the rapid thermal annealing process (RTP) or laser annealing process, complex mutual diffusion and chemical reactions occur between metal atoms and silicon atoms. In the temperature range of 400 to 600°C, atoms have sufficient energy to migrate. Metal atoms in the metal layer 6 (such as titanium atoms in titanium and titanium nitride) diffuse into the silicon in the source and drain regions 3, while silicon atoms also diffuse into the metal layer 6. This diffusion does not proceed uniformly, but exhibits different rates and degrees with changes in depth and position, resulting in the formation of a multi-component gradient structure. This gradient structure makes the interface between the metal layer 6 and the semiconductor (source and drain regions 2 and 3) no longer abrupt and discontinuous, but forms a continuous transition region. Due to the presence of the insulating layer, this interdiffusion is relatively slow. At the same time, the modified interface improves the uniformity of the insulating layer, reduces the weak points of diffusion barriers that may exist at the interface, and avoids the unevenness of the silicide film layer.

[0061] By applying the technical solution of this embodiment, ozone treatment of the source region 2 and drain region 3 can form a hydrophilic surface state on the surfaces of the source region 2 and drain region 3. This hydrophilic surface state significantly improves the adsorption and spreading properties of the insulating layer 5 precursor on the intermediate device surface, allowing the insulating layer 5 to nucleate and grow more uniformly on the intermediate device surface during the subsequent deposition process. Compared to the uneven growth of the insulating layer 5 in traditional processes, this hydrophilic surface promotes a more regular atomic arrangement in the insulating layer 5 and significantly reduces internal defects, facilitating the growth of a uniform, high-quality, ultra-thin insulating layer 5. Furthermore, it can improve the properties of the intermediate device surface. Specifically, it reduces the interface state density and dangling bonds generated by incomplete atomic bonding on the semiconductor surface, thus avoiding Fermi level pinning. Furthermore, it improves the interface properties between the subsequently deposited insulating layer 5 and the semiconductor, reducing carrier scattering at the interface. These combined positive effects ultimately effectively reduce contact resistivity and further optimize device performance.

[0062] Furthermore, as a specific implementation of the above-mentioned method for preparing the metal oxide semiconductor field effect transistor, an embodiment of the present application provides a transistor, which is a metal-insulator-semiconductor structure, and the metal-insulator-semiconductor structure is manufactured using any of the above-mentioned methods.

[0063] In this embodiment, the transistor is an N-channel metal-oxide-semiconductor field-effect transistor (NMOS).

[0064] In the above embodiment, see Figure 6 As shown, the transistor includes: a substrate 1; a source region 2 and a drain region 3 located on both sides of the upper portion of the substrate 1; a gate structure 4 located above the substrate 1 and between the source region 2 and the drain region 3; a stack 7 located above the source region 2 and the drain region 3; and a metal layer 6 located above the stack 7.

[0065] Here, the substrate 1 is the basic supporting structure of the entire transistor. As mentioned in the above method, the material of the substrate 1 is diverse, and silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), etc. can be selected. In this embodiment, the silicon substrate 1 is used as an example for explanation. All other structures will be built on the substrate 1. The source region 2 and the drain region 3 are located on both sides of the upper part of the substrate 1. During the preparation process, high concentrations of impurity atoms are introduced into specific areas through processes such as ion implantation or diffusion, thereby forming these two regions. For example, in the silicon substrate 1, if an N-type semiconductor region is to be formed (the source and drain in NMOS are usually N-type), pentavalent elements such as phosphorus (P) and arsenic (As) will be implanted. The source and drain are the input and output terminals of the current in the NMOS transistor. Their heavy doping purpose is to reduce resistance, increase carrier concentration, enhance the conductivity of the transistor, and enable more efficient current transmission. The gate structure 4 is located above the substrate 1 and between the source region 2 and the drain region 3. A gate structure 4 is formed, and the gate structure 4 is used to control the current conduction between the source and the drain. By applying a voltage to the gate, the charge distribution on the semiconductor surface below the gate can be changed, thereby forming or eliminating a conductive channel and realizing control of the switching state of the transistor. The stack 7 is located above the source region 2 and the drain region 3. After the steps of the above-mentioned preparation method, especially after heat treatment, the stack 7 formed between the source region 2 and the drain region 3 and the metal layer 6 is a multi-resistance metal silicide layer, and presents a multi-component gradient structure. This stack 7 structure helps to alleviate the Fermi level pinning between the gold semiconductor contacts, thereby utilizing the metal 6 and the silicide process to achieve a reduction in the Schottky barrier height, thereby reducing the contact resistance. The metal layer 6 is located above the stack 7 and can be deposited on the surface of the insulating layer 5 using thin film deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). Furthermore, the metal material forming the metal layer 6 is generally titanium (Ti), titanium nitride (TiN) or a combination thereof, and a suitable thickness (2-10 nm) can ensure good current transmission performance and stable contact characteristics.

[0066] It is easy for those skilled in the art to understand that, under the premise of no conflict, the above-mentioned advantageous methods can be freely combined and superimposed.

[0067] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application. The above are merely preferred embodiments of the present application. It should be noted that those skilled in the art may make various improvements and variations without departing from the technical principles of the present application, and such improvements and variations shall also be considered within the scope of protection of the present application.

Claims

1. A method for preparing a metal oxide semiconductor field effect transistor, characterized in that: include: preparing an intermediate device with heavily doped source and drain regions; performing ozone treatment on the source region and the drain region of the intermediate device; depositing an insulating layer on the intermediate device; depositing a metal layer on the insulating layer; The intermediate device is heat treated.

2. The method according to claim 1, characterized in that After the source region and the drain region of the intermediate device are subjected to the ozone treatment, surfaces of the source region and the drain region are in a hydrophilic state.

3. The method according to claim 1, characterized in that The ozone treatment is carried out at room temperature, and the reaction time is 3 to 20 seconds.

4. The method according to claim 1, wherein The insulating layer is deposited by atomic layer deposition.

5. The method according to claim 1, wherein The heat treatment temperature is 400-600° C., and the reaction time is 10-60 seconds.

6. A transistor, characterized in that: The transistor is a metal-insulator-semiconductor structure, and the metal-insulator-semiconductor structure is manufactured using the method according to any one of claims 1 to 5.

7. The transistor according to claim 6, wherein: include: substrate; a source region and a drain region located on both sides of the upper portion of the substrate; a gate structure located above the substrate and between the source region and the drain region; a stack located above the source region and the drain region; A metal layer is located above the stack.

8. The transistor according to claim 7, wherein: The stack is a multi-component gradient structure formed by heat-treating the insulating layer between the source region, the drain region and the metal layer, and is used to reduce the contact resistivity between the source region, the drain region and the metal layer.

9. The transistor according to claim 8, wherein The insulating layer is a metal oxide layer. The material of the metal oxide layer is zirconium oxide or hafnium oxide. The thickness of the metal oxide layer is 0.5-2 nm.

10. The transistor according to claim 7, wherein The material of the metal layer is titanium and / or titanium nitride, and the thickness of the metal layer is 2-10 nm.

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