Semiconductor device

Abstract

A semiconductor device includes: a channel layer including a channel suppression region; a barrier layer over the channel layer and including a material having a different energy band gap from the channel layer; a gate electrode over the barrier layer; a protective layer over the gate electrode; a source electrode and a drain electrode located on both sides of the gate electrode and connected to the channel layer; and a field dispersion layer on the protective layer and including a protruding portion adjacent to the channel suppression region, the protruding portion protruding toward the drain electrode from an edge of the field dispersion layer adjacent to the drain electrode.

Description

Technical Field

[0001] The invention discloses a semiconductor device. Background Art

[0002] In modern society, semiconductor devices are closely related to daily life. In particular, the importance of power semiconductor devices used in various fields (such as transportation fields (such as electric vehicles, railways and electric trams), renewable energy systems (such as solar power generation and wind power generation) and mobile devices) is gradually increasing. Power semiconductor devices are semiconductor devices for processing high voltage or high current, and perform functions such as power conversion and control in large power systems or high-power electronic devices. Power semiconductor devices have the ability to handle high electric power and durability, thereby handling large amounts of current and withstanding high voltage. For example, power semiconductor devices can handle voltages of hundreds to thousands of volts and currents of tens of amperes to thousands of amperes. Power semiconductor devices can improve the efficiency of electric energy by reducing power loss. In addition, even in environments such as high temperatures, power semiconductor devices can also operate stably. These power semiconductor devices can be classified according to materials, for example, there are SiC power semiconductor devices and GaN power semiconductor devices. By using SiC or GaN instead of existing silicon wafers (Si wafers) to manufacture power semiconductor devices, the shortcomings of silicon with unstable characteristics at high temperatures can be compensated. SiC power semiconductor devices are resistant to high temperatures and have low power loss, and may be suitable for electric vehicles, renewable energy systems, etc. GaN power semiconductor devices may be expensive, but are efficient in terms of speed and may be suitable for fast charging of mobile devices. Summary of the Invention

[0003] Generally, in some aspects, the present disclosure is directed to semiconductor devices having stable electrical characteristics and improved reliability.

[0004] According to some implementations, the present disclosure relates to a semiconductor device, comprising: a channel layer including a channel suppression region; a barrier layer located above the channel layer and including a material having an energy band gap different from that of the channel layer; a gate electrode located above the barrier layer; a protective layer located above the gate electrode; a source electrode and a drain electrode located on both sides of the gate electrode and connected to the channel layer; and a field dispersion layer located on the protective layer and including a protruding portion adjacent to the channel suppression region, the protruding portion protruding from an edge of the field dispersion layer adjacent to the drain electrode toward the drain electrode.

[0005] According to some implementations, the present disclosure relates to a semiconductor device, comprising: a channel layer comprising GaN; a barrier layer comprising AlGaN located above the channel layer; a gate electrode located above the barrier layer; a protective layer located above the gate electrode; a source electrode and a drain electrode located on both sides of the gate electrode and connected to the channel layer; and a field dispersion layer located on the protective layer and connected to the source electrode, wherein a two-dimensional electron gas is formed in the channel layer between the source electrode and the drain electrode, the channel layer including a channel suppression region in which the two-dimensional electron gas is suppressed, and the field dispersion layer including a protruding portion overlapping with the channel suppression region in a vertical direction with respect to an upper surface of the channel layer.

[0006] According to some embodiments, the present disclosure relates to a semiconductor device including a channel layer including GaN, a barrier layer including AlGaN located above the channel layer, a gate electrode located above the barrier layer, a protective layer located above the gate electrode, a source electrode and a drain electrode located on both sides of the gate electrode and connected to the channel layer, and a field dispersion layer located on the protective layer and connected to the source electrode, wherein a two-dimensional electron gas is formed between the source electrode and the drain electrode in the channel layer, the channel layer includes a channel suppression region in which the two-dimensional electron gas is suppressed, an edge of the field dispersion layer adjacent to the drain electrode overlaps with the channel suppression region, and the channel suppression region overlaps with a doped region including Ar or N in the barrier layer, or overlaps with a recess from which the barrier layer is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example implementations will be clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0008] Figure 1 is a plan view showing an example of a semiconductor device according to some implementations.

[0009] Figure 2 It is shown according to some implementation methods Figure 1 A plan view of an example enlarged view of the AR1 region.

[0010] Figure 3 It is based on some implementation along Figure 1 A cross-sectional view shown along line III-III′ in FIG.

[0011] Figure 4 It is based on some implementation along Figure 1 A cross-sectional view shown along line IV-IV'.

[0012] Figure 5 is a plan view showing an example of a semiconductor device according to some implementations.

[0013] Figure 6 Based on some implementation Figure 5 An enlarged plan view of an example of the AR2 region.

[0014] Figure 7 It is based on some implementation along Figure 5 The cross-sectional view is shown along line VII-VII'.

[0015] Figure 8 is a cross-sectional view showing an example of a semiconductor device according to some implementations.

[0016] Figure 9 is a cross-sectional view showing an example of a semiconductor device according to some implementations.

[0017] Figure 10 is a cross-sectional view showing an example of a semiconductor device according to some implementations.

[0018] Figure 11 is a cross-sectional view showing an example of a semiconductor device according to some implementations.

[0019] Figure 12 is a cross-sectional view showing an example of a semiconductor device according to some implementations.

[0020] Figure 13 and Figure 14 is a plan view showing an example of a semiconductor device according to some implementations.

[0021] Figure 15 is a plan view showing an example of a semiconductor device according to some implementations.

[0022] Figure 16 It is based on some implementation along Figure 15 A cross-sectional view shown along line XVI-XVI'.

[0023] Figure 17 is a plan view showing an example of a semiconductor device according to some implementations.

[0024] Figure 18 It is based on some implementation along Figure 17 A cross-sectional view shown along line XVIII-XVIII'.

[0025] Figure 19 It is based on some implementation along Figure 17 A cross-sectional view shown along line XIX-XIX'. DETAILED DESCRIPTION

[0026] Hereinafter, example implementations will be described in detail with reference to the accompanying drawings. To clearly describe the present disclosure, portions not relevant to the description are omitted, and throughout the specification, the same reference numerals are assigned to the same or similar components. In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for better understanding and ease of description, the present disclosure is not necessarily limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thicknesses of some layers and regions are exaggerated for ease of description.

[0027] Furthermore, it will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, it means there are no intervening elements. Furthermore, "on" or "over" a referenced portion means being above or below the referenced portion, and does not necessarily mean being "over" or "on" the referenced portion in an opposite direction of gravity.

[0028] In addition, unless explicitly described to the contrary, the word "comprise" and its variations will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements. Furthermore, the phrase "in plane" means when the object portion is viewed from above, and the phrase "in cross section" means when a cross section taken by vertically cutting the object portion is viewed from the side.

[0029] Figure 1 is a plan view showing an example of a semiconductor device according to some implementations, Figure 2 It is shown according to some implementation methods Figure 1 A plan view of an example enlarged view of the AR1 region. Figure 3 It is based on some implementation along Figure 1 The cross-sectional view shown on line III-III', Figure 4 It is based on some implementation along Figure 1 A cross-sectional view shown along line IV-IV'.

[0030] exist Figures 1 to 4 In the embodiment, the semiconductor device may include a channel layer 132, a barrier layer 136 located above the channel layer 132, a gate electrode 155 located above the barrier layer 136, a protective layer 140 located above the gate electrode 155, a source electrode and a drain electrode located on both sides of the gate electrode 155 and connected to the channel layer 132, and a field dispersion layer 177 located on the protective layer 140.

[0031] The channel layer 132 is a layer that forms a channel between the source electrode 173 and the drain electrode 175, and a two-dimensional electron gas (2DEG) 134 may be located inside the channel layer 132. The two-dimensional electron gas 134 is a charge transfer model and refers to a group of electrons tightly bound in two dimensions, wherein they can move freely in two dimensions (e.g., the xy plane direction) but cannot move in another dimension (e.g., in the z direction). That is, the two-dimensional electron gas 134 may exist in a three-dimensional space in a two-dimensional paper-like form. The two-dimensional electron gas 134 mainly appears in a semiconductor heterojunction structure and may appear at the interface between the channel layer 132 and the barrier layer 136 in the semiconductor device according to the embodiment. For example, the two-dimensional electron gas 134 may be generated in the portion of the channel layer 132 closest to the barrier layer 136.

[0032] The channel layer 132 may include one or more materials selected from group III-V materials, such as nitride containing at least one of Al, Ga, In, and B. The channel layer 132 may be made of a single layer or multiple layers. The channel layer 132 may be Al x In y Ga 1-x-y N(0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 132 may include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The channel layer 132 may be a layer doped with impurities or a layer not doped with impurities. The thickness of the channel layer 132 may be about several hundred nm or less.

[0033] The channel layer 132 may be located on the substrate 110, and the seed layer 115, the buffer layer 120, and the like may be located between the substrate 110 and the channel layer 132. The substrate 110, the seed layer 115, and the buffer layer 120 are necessary layers for forming the channel layer 132 and may be omitted in some implementations. For example, when a substrate made of GaN is used as the channel layer 132, at least one of the substrate 110, the seed layer 115, and the buffer layer 120 may be omitted. Considering the relatively high price of substrates made of GaN, a substrate 110 made of Si may be used to grow the channel layer 132 containing GaN. In this case, since the lattice structure of Si and the lattice structure of GaN are different, it may not be easy to grow the channel layer 132 directly on the substrate 110. Therefore, the seed layer 115 and the buffer layer 120 may be grown on the substrate 110 first, and then the channel layer 132 may be grown on the buffer layer 120. Additionally, at least one of the substrate 110 , the seed layer 115 , and the buffer layer 120 may be removed from a final structure of the semiconductor device after being used in a manufacturing process.

[0034] The substrate 110 may include a semiconductor material. For example, the substrate 110 may include sapphire, Si, SiC, AlN, GaN, or a combination thereof. The substrate 110 may be a silicon-on-insulator (SOI) substrate. However, the material of the substrate 110 is not limited thereto, and any commonly used substrate may be applied. In some cases, the substrate 110 may include an insulating material. For example, several layers including the channel layer 132 may be first formed on a semiconductor substrate, and then the semiconductor substrate may be removed and replaced with an insulating substrate.

[0035] The seed layer 115 may be located on the substrate 110. The seed layer 115 may be located directly above the substrate 110. However, it is not limited thereto, and another predetermined layer may be further located between the substrate 110 and the seed layer 115. The seed layer 115 is a layer used as a seed for growing the buffer layer 120, and may be made of a lattice structure that becomes a seed of the buffer layer 120. For example, the seed layer 115 may include AlN, but is not limited thereto.

[0036] The buffer layer 120 may be located above the seed layer 115. The buffer layer 120 may be located directly above the seed layer 115. However, not limited thereto, another predetermined layer may be further located between the seed layer 115 and the buffer layer 120. The buffer layer 120 may be located between the seed layer 115 and the channel layer 132. The buffer layer 120 may include one or more materials selected from group III-V materials, such as a nitride containing at least one of Al, Ga, In, and B. The buffer layer 120 may be Al x In y Ga 1-x-y N(0≤x≤1, 0≤y≤1, x+y≤1). For example, the buffer layer 120 may include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The buffer layer 120 may be composed of a single layer or multiple layers. The buffer layer 120 may include a superlattice layer 124 and a high-resistance layer 126 located on the superlattice layer 124. The high-resistance layer 126 may be located above the superlattice layer 124. At least one of the superlattice layer 124 and the high-resistance layer 126 may be omitted. In some implementations, the buffer layer 120 may include not only the superlattice layer 124 and the high-resistance layer 126, but also other additional layers.

[0037] The superlattice layer 124 may be located above the seed layer 115. The superlattice layer 124 may be located directly above the seed layer 115. However, it is not limited thereto, and another predetermined layer may be located between the seed layer 115 and the superlattice layer 124. The superlattice layer 124 may be located between the substrate 110 and the channel layer 132. The superlattice layer 124 may alleviate the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 132, thereby alleviating the tensile stress and compressive stress generated between the substrate 110 and the channel layer 132, and the superlattice layer 124 may be a layer for alleviating stress between all layers formed by growth in the final structure of the semiconductor device according to the embodiment. The superlattice layer 124 may include one or more materials selected from group III-V materials, for example, a nitride containing at least one of Al, Ga, In, and B. The superlattice layer 124 may be Al x In y Ga 1-x-y N(0≤x≤1, 0≤y≤1, x+y≤1). For example, the superlattice layer 124 may include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The superlattice layer 124 may be composed of a single layer or a multilayer. For example, the superlattice layer 124 may have a structure in which a layer made of AlGaN and a layer made of GaN are repeatedly stacked. For example, AlGaN / GaN / AlGaN / GaN / AlGaN / GaN may be stacked in sequence on the seed layer 115 to form the superlattice layer 124. The number of AlGaN layers and GaN layers constituting the superlattice layer 124 may vary, and the material constituting the superlattice layer 124 may vary.

[0038] The high resistance layer 126 may be located above the superlattice layer 124. The high resistance layer 126 may be located directly above the superlattice layer 124. However, it is not limited thereto, and another predetermined layer may be further located between the superlattice layer 124 and the high resistance layer 126. The high resistance layer 126 may be located between the superlattice layer 124 and the channel layer 132. The high resistance layer 126 is used to prevent leakage current from flowing through the channel layer 132, thereby preventing degradation of the semiconductor device according to some implementations. The high resistance layer 126 may be made of a material having low conductivity so that it can be electrically insulated between the substrate 110 and the channel layer 132. The high resistance layer 126 may include one or more materials selected from group III-V materials, for example, a nitride containing at least one of Al, Ga, In, and B. The high resistance layer 126 may be Al x In y Ga 1-x-yN(0≤x≤1, 0≤y≤1, x+y≤1). For example, the high resistance layer 126 may include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The high resistance layer 126 may be composed of a single layer or a multilayer. The high resistance layer 126 may be a layer without doping impurities. However, it is not limited thereto, and the high resistance layer 126 may contain impurities. For example, the high resistance layer 126 may be doped with impurities made of carbon (C), magnesium (Mg), iron (Fe), or a combination thereof. The impurity doping concentration of the high resistance layer 126 may be different from the impurity doping concentration of the channel layer 132.

[0039] The barrier layer 136 may be located above the channel layer 132. The barrier layer 136 may be located directly above the channel layer 132. However, this is not limited to this; another predetermined layer may be further located between the channel layer 132 and the barrier layer 136. The region of the channel layer 132 that overlaps with the barrier layer 136 may be the drift region DTR. The drift region DTR may be located between the source electrode 173 and the drain electrode 175. When a potential difference is generated between the source electrode 173 and the drain electrode 175, carriers may migrate in the drift region DTR. Depending on whether a voltage is applied to the gate electrode 155 and the magnitude of the voltage applied to the gate electrode 155, the semiconductor device according to some implementations may be turned on or off. When no voltage is applied to the gate electrode 155, the two-dimensional electron gas 134 may function as a channel, and current may flow between the source electrode 173 and the drain electrode 175. In other words, carrier migration may occur in the drift region DTR. In addition, when a negative voltage is applied to the gate electrode 155, a depletion region DPR in which the flow of the two-dimensional electron gas 134 is interrupted may occur at the bottom of the gate electrode 155. That is, the semiconductor device according to the embodiment may be a normally-on high electron mobility transistor. However, it is not limited thereto, and the semiconductor device according to some implementations may be a normally-off high electron mobility transistor. In the case of a normally-off high electron mobility transistor, the gate semiconductor layer may be further located between the barrier layer 136 and the gate electrode 155, which will be described later. Figure 8 Described in the description.

[0040] The barrier layer 136 may include a doped region 510. The doped region 510 of the barrier layer 136 may be a region doped with predetermined ions. The doped region 510 of the barrier layer 136 may include Ar, N, etc. For example, the doped region 510 may be formed by implanting Ar, N, etc. into the barrier layer 136 using an ion implantation (IIP) method. The depth of the doped region 510 may correspond to the thickness of the barrier layer 136. That is, the depth of the doped region 510 may be substantially the same as the thickness of the barrier layer 136. However, without limitation thereto, the depth of the doped region 510 may be less than or greater than the thickness of the barrier layer 136. In some implementations, the doped region 510 may also be formed within the channel layer 132. The doped region 510 may be circular in plan. However, without limitation thereto, the planar shape of the doped region 510 may be varied in various ways. For example, the doped region 510 may have a polygonal shape such as a quadrilateral or a hexagon in plan.

[0041] Because the doped region 510 of the barrier layer 136 is doped with Ar, N, or the like, the channel may be suppressed in some regions within the channel layer 132. The channel layer 132 may include a channel suppression region (CRA), and the doped region 510 of the barrier layer 136 may overlap with the channel suppression region (CRA) of the channel layer 132 in the third direction DR3. The channel suppression region (CRA) may be located within the drift region (DTR) and may be a region where the channel is suppressed by the doped region 510. The two-dimensional electron gas 134 may not form in the channel suppression region (CRA). In other words, the flow of the two-dimensional electron gas 134 may be interrupted in the channel suppression region (CRA). In some implementations, the amount of the two-dimensional electron gas 134 in the channel suppression region (CRA) may be extremely small compared to other regions. In other words, the flow of the two-dimensional electron gas 134 in the channel suppression region (CRA) may be significantly reduced.

[0042] The barrier layer 136 may include a plurality of doped regions 510. The plurality of doped regions 510 may be arranged to be spaced apart from each other at predetermined intervals along the second direction DR2. The intervals between the plurality of doped regions 510 may be constant. The shapes, sizes, etc. of the plurality of doped regions 510 may be constant. However, this is not limiting, and at least some of the plurality of doped regions 510 may have different pitches (or intervals), shapes, sizes, etc. To correspond to the plurality of doped regions 510, the channel layer 132 may include a plurality of channel suppression regions CRA. The plurality of channel suppression regions CRA may be arranged to be spaced apart from each other at regular intervals along the second direction DR2.

[0043] The barrier layer 136 may include one or more materials selected from group III-V materials, for example, a nitride containing at least one of Al, Ga, In, and B. The barrier layer 136 may be Al x In yGa 1-x-y N(0≤x≤1, 0≤y≤1, x+y≤1). The barrier layer 136 may include at least one of GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, etc. The energy bandgap of the barrier layer 136 may be adjusted by the composition ratio of Al and / or In.

[0044] The barrier layer 136 may include a semiconductor material having properties different from those of the channel layer 132. The barrier layer 136 may differ from the channel layer 132 in at least one of polarization properties, energy bandgap, and lattice constant. For example, the barrier layer 136 may include a material having a different energy bandgap than the channel layer 132. In this case, the barrier layer 136 may have a higher energy bandgap than the channel layer 132 and may have a higher electric susceptibility than the channel layer 132. Through this barrier layer 136, a two-dimensional electron gas 134 may be induced in the channel layer 132, which has a relatively low electric susceptibility. In this regard, the barrier layer 136 may also be referred to as a channel supply layer or a two-dimensional electron gas supply layer. The two-dimensional electron gas 134 may be formed in a portion of the channel layer 132 located below the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 may have very high electron mobility.

[0045] The barrier layer 136 may be composed of a single layer or multiple layers. When the barrier layer 136 is made of multiple layers, the materials constituting each layer may have different energy band gaps. Therefore, the multiple layers constituting the barrier layer 136 may be arranged so that the energy band gap increases as the multiple layers approach the channel layer 132.

[0046] The gate electrode 155 may be located on the barrier layer 136. The gate electrode 155 may be located directly above the barrier layer 136. The bottom surface of the gate electrode 155 may be in contact with the barrier layer 136. However, this is not limited to this, and another predetermined layer may be further located between the gate electrode 155 and the barrier layer 136. The gate electrode 155 may overlap with some areas of the barrier layer 136. The gate electrode 155 may overlap with a portion of the drift region DTR in the channel layer 132. The gate electrode 155 may be located between the source electrode 173 and the drain electrode 175. The gate electrode 155 may be separated from the source electrode 173 and the drain electrode 175 in a first direction DR1. The first direction DR1 may be a direction parallel to the upper surface of the substrate 110 or the upper surface of the channel layer 132. The gate electrode 155 may be located closer to the source electrode 173 than to the drain electrode 175. For example, a spacing distance between the gate electrode 155 and the source electrode 173 may be smaller than a spacing distance between the gate electrode 155 and the drain electrode 175 .

[0047] The gate electrode 155 may extend in a second direction DR2 that is different from the first direction DR1 in a plane. The second direction DR2 may be a direction parallel to the upper surface of the substrate 110 or the upper surface of the channel layer 132 and may intersect with the first direction DR1. For example, the second direction DR2 may be a direction orthogonal to the first direction DR1. The gate electrode 155 may have a strip shape extending along the second direction DR2.

[0048] The gate electrode 155 may include a conductive material. For example, the gate electrode 155 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. For example, the gate electrode 155 is titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride nitride (Ta The gate electrode 155 may be made of a single layer or a multilayer.

[0049] The superlattice layer 124, the high-resistance layer 126, the channel layer 132, and the barrier layer 136 may be sequentially stacked on the substrate 110. In some implementations, at least one of the superlattice layer 124, the high-resistance layer 126, the channel layer 132, and the barrier layer 136 may be omitted. The superlattice layer 124, the high-resistance layer 126, the channel layer 132, and the barrier layer 136 may be made of the same semiconductor material, and the material composition ratios of the layers may be different, taking into account the role of each layer and the performance required of the semiconductor device.

[0050] In some implementations, the protective layer 140 may be located on the barrier layer 136 and the gate electrode 155. The protective layer 140 may cover the upper surface of the barrier layer 136 and may cover the upper surface and side surfaces of the gate electrode 155. The protective layer 140 may be in contact with the barrier layer 136 and the gate electrode 155. The barrier layer 136 and the gate electrode 155 may be protected by the protective layer 140 and may be separated from other components. The protective layer 140 may include an insulating material. For example, the protective layer 140 may include an oxide such as SiO2 or Al2O3. As another example, the protective layer 140 may include a nitride (such as SiN) or an acidic nitride (such as SiON). The protective layer 140 may be composed of a single layer or multiple layers.

[0051] The source electrode 173 and the drain electrode 175 may be located on the channel layer 132. The source electrode 173 and the drain electrode 175 may be spaced apart from each other, and the gate electrode 155 may be located between the source electrode 173 and the drain electrode 175. The gate electrode 155 is spaced apart from the source electrode 173 and the drain electrode 175. The source electrode 173 may be electrically connected to the channel layer 132 on one side of the gate electrode 155. The drain electrode 175 may be electrically connected to the channel layer 132 on the other side of the gate electrode 155. The source electrode 173 and the drain electrode 175 may be located outside the drift region DTR of the channel layer 132. The interface between the source electrode 173 and the channel layer 132 may be one edge of the drift region DTR. Similarly, the interface between the drain electrode 175 and the channel layer 132 may be the other edge of the drift region DTR. However, the present disclosure is not limited thereto, and the source electrode 173 and the drain electrode 175 may not be located outside the drift region DTR of the channel layer 132. In some implementations, the channel layer 132 may not be recessed, and the source electrode 173 and the drain electrode 175 may be located on the upper surface of the channel layer 132. In some implementations, the barrier layer 136 may not be penetrated, and a portion of the barrier layer 136 may be recessed so that the source electrode 173 and the drain electrode 175 may be located on the upper surface of the barrier layer 136. The bottom surfaces of the source electrode 173 and the drain electrode 175 may be in contact with the upper surface of the barrier layer 136. The portion of the barrier layer 136 in contact with the source electrode 173 and the drain electrode 175 may be doped at a high concentration. In some implementations, carriers passing through the two-dimensional electron gas 134 may pass through a portion of the barrier layer 136 doped with a high concentration (that is, a top portion of the two-dimensional electron gas 134) and may be transferred to the source electrode 173 and the drain electrode 175. The source electrode 173 and the drain electrode 175 may not directly contact the two-dimensional electron gas 134 in a horizontal direction. The horizontal direction may refer to a direction parallel to the upper surface of the channel layer 132 or the barrier layer 136.

[0052] The source electrode 173 and the drain electrode 175 may be located on the protective layer 140. Trenches penetrating the protective layer 140, the barrier layer 136, and the upper surface of the channel layer 132 may be positioned spaced apart from each other on either side of the gate electrode 155. The source electrode 173 and the drain electrode 175 may be located in the trenches, respectively, with the trenches being located on either side of the gate electrode 155. The source electrode 173 and the drain electrode 175 may be formed to fill the trenches. Within the trenches, the source electrode 173 and the drain electrode 175 may contact the channel layer 132 and the barrier layer 136. The channel layer 132 may form the bottom surface and sidewalls of the trench, and the barrier layer 136 may form the sidewalls of the trench. Therefore, the source electrode 173 and the drain electrode 175 may contact the top surface and side surfaces of the channel layer 132. In addition, the source electrode 173 and the drain electrode 175 may contact the side surfaces of the barrier layer 136. In some implementations, the source electrode 173 and the drain electrode 175 may cover side surfaces of the channel layer 132 and the barrier layer 136. The upper surfaces of the source electrode 173 and the drain electrode 175 may protrude from the upper surface of the protection layer 140. In some implementations, at least one of the source electrode 173 and the drain electrode 175 may cover at least a portion of the upper surface of the protection layer 140.

[0053] The source electrode 173 and the drain electrode 175 may be separated in the first direction DR1 , extend in the second direction DR2 , and extend in a direction parallel to the gate electrode 155 .

[0054] The source electrode 173 and the drain electrode 175 may include a conductive material. For example, the source electrode 173 and the drain electrode 175 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. For example, the source electrode 173 and the drain electrode 175 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide (Ta ... Nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) or a combination thereof, but not limited thereto. The source electrode 173 and the drain electrode 175 can be made of a single layer or a multilayer. The source electrode 173 and the drain electrode 175 can be in ohmic contact with the channel layer 132. The region in contact with the source electrode 173 and the drain electrode 175 in the channel layer 132 can be doped at a relatively high concentration compared to other regions.

[0055] The field dispersion layer 177 may be located between the source electrode 173 and the drain electrode 175. The field dispersion layer 177 may overlap the gate electrode 155 in a third direction DR3. The third direction DR3 may be perpendicular to the first direction DR1 and the second direction DR2. For example, the third direction DR3 may be perpendicular to the upper surface of the substrate 110 or the upper surface of the channel layer 132. The gate electrode 155 may be covered by the field dispersion layer 177. The field dispersion layer 177 may be electrically connected to the source electrode 173. The field dispersion layer 177 may include the same material as the source electrode 173 and may be located in the same layer as the source electrode 173. The field dispersion layer 177 may be formed simultaneously with the source electrode 173 in the same process. The interface between the field dispersion layer 177 and the source electrode 173 is not clear, and the field dispersion layer 177 may be formed integrally with the source electrode 173. However, the present invention is not limited thereto, and the field dispersion layer 177 may be a component separate from the source electrode 173. In addition, the field dispersion layer 177 may be located in a different layer from the source electrode 173 and may be formed in a different process. In some implementations, the field dispersion layer 177 may be electrically connected to the gate electrode 155. For example, an opening may be formed in the protective layer 140 that overlaps the gate electrode 155, and the field dispersion layer 177 may be connected to the gate electrode 155 through the opening. In some implementations, the field dispersion layer 177 may not be connected to the source electrode 173. As another example, from a plan view, the field dispersion layer 177 may be located between the gate electrode 155 and the drain electrode 175 and may be floating without being connected to the gate electrode 155 or the drain electrode 175.

[0056] The field spreading layer 177 can be used to disperse the electric field concentrated around the gate electrode 155. When a high voltage is applied to the drain electrode 175 in the gate-off state, the electric field may be concentrated around the gate electrode 155. When the electric field is concentrated on the gate electrode 155, the leakage current may increase and the breakdown voltage may decrease. The electric field concentrated around the gate electrode 155 can be dispersed by the field spreading layer 177, thereby reducing the leakage current and increasing the breakdown voltage.

[0057] The field spreading layer 177 may include a protruding portion 177a that protrudes from an edge of the field spreading layer 177 adjacent to the drain electrode 175 toward the drain electrode 175. The protruding portion 177a may protrude from the edge of the field spreading layer 177 in a first direction DR1 on a plane.

[0058] The protruding portion 177a may be adjacent to the channel suppression region CRA of the channel layer 132. The protruding portion 177a may overlap with the channel suppression region CRA of the channel layer 132 in the third direction DR3. At least a portion of the protruding portion 177a may overlap with the channel suppression region CRA of the channel layer 132 in the third direction DR3. A portion of the protruding portion 177a may overlap with the channel suppression region CRA, and another portion of the protruding portion 177a may not overlap with the channel suppression region CRA. However, it is not limited thereto, and the entire protruding portion 177a may overlap with the channel suppression region CRA. The protruding portion 177a may overlap with at least a portion of the channel suppression region CRA in the third direction DR3. The protruding portion 177a may overlap with a portion of the channel suppression region CRA, and may not overlap with another portion of the channel suppression region CRA. However, it is not limited thereto, and the protruding portion 177a may overlap with the entire channel suppression region CRA.

[0059] The protruding portion 177a may be adjacent to the doped region 510 of the barrier layer 136. The protruding portion 177a may overlap with the doped region 510 of the barrier layer 136 in the third direction DR3. At least a portion of the protruding portion 177a may overlap with the doped region 510 of the barrier layer 136 in the third direction DR3. The protruding portion 177a may overlap with at least a portion of the doped region 510 of the barrier layer 136 in the third direction DR3.

[0060] The protrusion 177a may have a substantially square shape in plan view. However, this is not limited thereto, and the planar shape of the protrusion 177a may be modified in various ways. The protrusion 177a may have a predetermined length Lth along the first direction DR1 and a predetermined width Wth along the second direction DR2. The length Lth of the protrusion 177a along the first direction DR1 may be approximately 0.1 μm or greater and approximately 2 μm or less. The width Wth of the protrusion 177a along the second direction DR2 may be approximately 0.05 μm or greater and approximately 5 μm or less.

[0061] The field dispersion layer 177 may include a plurality of protrusions 177a. The protrusions 177a may be arranged at predetermined intervals along the second direction DR2. The intervals between the protrusions 177a may be constant. The shapes, sizes, etc. of the protrusions 177a may be constant. However, this is not limiting, and at least a portion of the protrusions 177a may have different intervals, shapes, sizes, etc. The protrusions 177a may correspond to a plurality of channel suppression regions CRA, respectively. Each of the protrusions 177a may overlap with a channel suppression region CRA, and the number of the protrusions 177a may correspond to the number of the channel suppression regions CRA. The number of the protrusions 177a may be substantially the same as the number of the channel suppression regions CRA. The protrusions 177a may correspond to a plurality of doped regions 510, respectively. Each of the protrusions 177a may overlap with a doped region 510, and the number of the protrusions 177a may correspond to the number of the doped regions 510. The number of the plurality of protrusion portions 177 a may be substantially the same as the number of the plurality of doping regions 510 .

[0062] In some implementations, a channel suppression region (CRA) may be formed in the channel layer 132 by the doped region 510 formed in the barrier layer 136. The channel suppression region (CRA) may be positioned adjacent to an edge of the field dispersion layer 177 adjacent to the drain electrode 175. Thus, the electric field concentrated at the edge of the field dispersion layer 177 adjacent to the drain electrode 175 may be dispersed. Additionally, in some implementations, a protruding portion 177a may be formed at the edge of the field dispersion layer 177 adjacent to the drain electrode 175 to overlap with the channel suppression region (CRA). Thus, the electric field concentrated at the edge of the field dispersion layer 177 adjacent to the drain electrode 175 may be further dispersed, and degradation of the semiconductor device according to embodiments may be prevented.

[0063] Figure 5 is a plan view showing an example of a semiconductor device according to some implementations. Figure 6 Based on some implementation Figure 5 An enlarged plan view of an example of the AR2 region. Figure 7 It is based on some implementation along Figure 5 A cross-sectional view shown along line VII-VII'.

[0064] because Figures 5 to 7 The implementation shown in Figures 1 to 4 The implementation shown in is substantially the same, so description thereof will be omitted, and differences will be mainly explained. In addition, the same reference numerals are used for the same components as those in the aforementioned embodiment. Figures 5 to 7Some implementations shown in may differ slightly from other implementations in that the channel suppression portion does not overlap the field spreading layer.

[0065] exist Figures 5 to 7 In the embodiment, the doped region 510 of the barrier layer 136 is located near the field dispersion layer 177 and may not overlap with the field dispersion layer 177 in the third direction DR3. The doped region 510 of the barrier layer 136 may not overlap with the protruding portion 177a of the field dispersion layer 177 in the third direction DR3. The doped region 510 of the barrier layer 136 may be separated from the protruding portion 177a of the field dispersion layer 177 in the first direction DR1. The spacing distance between the doped region 510 and the protruding portion 177a along the first direction DR1 may be approximately 0.5 μm or less.

[0066] The channel suppressing region CRA of the channel layer 132 may correspond to the doped region 510 of the barrier layer 136. The channel suppressing region CRA of the channel layer 132 may overlap with the doped region 510 of the barrier layer 136 in the third direction DR3. The channel suppressing region CRA of the channel layer 132 is located near the field dispersion layer 177 and may not overlap with the field dispersion layer 177 in the third direction DR3. The channel suppressing region CRA of the channel layer 132 may not overlap with the protruding portion 177a of the field dispersion layer 177 in the third direction DR3. The channel suppressing region CRA of the channel layer 132 may be separated from the protruding portion 177a of the field dispersion layer 177 in the first direction DR1. A spacing distance Dst between the channel suppressing region CRA and the protruding portion 177a along the first direction DR1 may be approximately 0.5 μm or less.

[0067] The plurality of protrusions 177a may be arranged to be spaced apart at predetermined intervals along the second direction DR2. The plurality of protrusions 177a may correspond to the plurality of channel suppression regions CRA, respectively. Each of the plurality of protrusions 177a may be spaced apart from the channel suppression region CRA in the first direction DR1. The plurality of protrusions 177a may correspond to the plurality of doped regions 510, respectively. Each of the plurality of protrusions 177a may be spaced apart from the doped region 510 in the first direction DR1.

[0068] Figure 8 is a cross-sectional view showing an example of a semiconductor device according to some implementations. Figure 8 The implementation shown in Figures 1 to 4 The implementation shown in is substantially the same, so description thereof will be omitted, and differences will be mainly explained. In addition, the same reference numerals are used for the same components as those in the aforementioned embodiment. Figure 8 The implementation shown in may differ slightly from the previous implementations in that it further includes a gate semiconductor layer.

[0069] exist Figure 8 In the embodiment, the semiconductor device may include a channel layer 132, a barrier layer 136 located above the channel layer 132, a gate electrode 155 located above the barrier layer 136, a protection layer 140 located above the gate electrode 155, a source electrode 173 and a drain electrode 175 located on both sides of the gate electrode 155 and connected to the channel layer 132, and a field spreading layer 177 located on the protection layer 140. The semiconductor device may further include a gate semiconductor layer 152 located between the barrier layer 136 and the gate electrode 155.

[0070] The gate semiconductor layer 152 may be located on the barrier layer 136, and the gate electrode 155 may be located on the gate semiconductor layer 152. The gate electrode 155 may be in Schottky contact with the gate semiconductor layer 152. However, it is not limited thereto, and in some implementations, the gate electrode 155 may be in ohmic contact with the gate semiconductor layer 152. The gate semiconductor layer 152 may overlap with the gate electrode 155 in the third direction DR3.

[0071] The superlattice layer 124, the high-resistance layer 126, the channel layer 132, the barrier layer 136, and the gate semiconductor layer 152 may be sequentially stacked on the substrate 110. In some implementations, at least one of the superlattice layer 124, the high-resistance layer 126, the channel layer 132, the barrier layer 136, and the gate semiconductor layer 152 may be omitted. The superlattice layer 124, the high-resistance layer 126, the channel layer 132, the barrier layer 136, and the gate semiconductor layer 152 may be made of the same semiconductor material, and the material composition ratios of the layers may be different, taking into account the role of each layer, the performance required of the semiconductor device, and the like.

[0072] The gate semiconductor layer 152 may be located between the source electrode 173 and the drain electrode 175. The gate semiconductor layer 152 may be separated from the source electrode 173 and the drain electrode 175. The gate semiconductor layer 152 may be located closer to the source electrode 173 than to the drain electrode 175. For example, the spacing distance between the gate semiconductor layer 152 and the source electrode 173 may be smaller than the spacing distance between the gate semiconductor layer 152 and the drain electrode 175.

[0073] The gate semiconductor layer 152 may include one or more materials selected from Group III-V materials, such as a nitride containing at least one of Al, Ga, In, and B. The gate semiconductor layer 152 may be Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the gate semiconductor layer 152 may include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The gate semiconductor layer 152 may include a material having a different energy bandgap than the barrier layer 136. For example, the gate semiconductor layer 152 may include GaN, and the barrier layer 136 may include AlGaN. The gate semiconductor layer 152 may be doped with predetermined impurities. In some implementations, the impurities doped in the gate semiconductor layer 152 may be p-type dopants that can provide holes. For example, the gate semiconductor layer 152 may include GaN doped with p-type impurities. For example, the gate semiconductor layer 152 may be made of a p-GaN layer. However, this is not limited to this, and the gate semiconductor layer 152 may be a p-AlGaN layer. For example, the impurities doped in the gate semiconductor layer 152 may include Mg, F, Be, Ca, Sr, Ba, Li, Na, Mn, Fe, Co, Cu, Zn, Cd, etc. The gate semiconductor layer 152 may consist of a single layer or a multilayer.

[0074] A depletion region DPR may be formed within the channel layer 132 via the gate semiconductor layer 152. The depletion region DPR may be located within the drift region DTR and may have a narrower width than the drift region DTR. When the gate semiconductor layer 152, having a different energy bandgap than the barrier layer 136, is located on the barrier layer 136, the energy band level of the portion of the barrier layer 136 that overlaps with the gate semiconductor layer 152 may increase. Therefore, the depletion region DPR may be formed in the region of the channel layer 132 that overlaps with the gate semiconductor layer 152. The depletion region DPR may be a region within the channel path of the channel layer 132 where the two-dimensional electron gas 134 is not formed or has a lower electron concentration than the remaining region. In other words, the depletion region DPR may refer to a region within the drift region DTR where the flow of the two-dimensional electron gas 134 is interrupted. When the depletion region DPR appears, current does not flow between the source electrode 173 and the drain electrode 175, and the channel path may be blocked. When a voltage higher than the threshold voltage is applied to the gate electrode 155 and the semiconductor device is turned on, a channel may be generated in the depletion region DPR. Therefore, the movement of carriers may occur in the drift region DTR. When a voltage lower than the threshold voltage is applied to the gate electrode 155 or no voltage is applied, the channel path may be blocked in the depletion region DPR, and carrier movement may not occur.

[0075] In some implementations, the semiconductor device can be a normally-off high electron mobility transistor (HEMT). In a normal state, when no voltage is applied to the gate electrode 155, a depletion region DPR exists, and the semiconductor device can be in an off state. When a voltage higher than the threshold voltage is applied to the gate electrode 155, the depletion region DPR disappears, and the two-dimensional electron gas 134 is not disconnected and can be connected within the drift region DTR. For example, the two-dimensional electron gas 134 can form in the entire channel path between the source electrode 173 and the drain electrode 175, and the semiconductor device can be turned on. In some implementations, the semiconductor device can include semiconductor layers with different electrical polarization characteristics, and the semiconductor layer with a relatively large polarizability can cause the two-dimensional electron gas 134 to reach another semiconductor layer that forms a heterojunction with the semiconductor layer. The two-dimensional electron gas 134 can serve as a channel between the source electrode 173 and the drain electrode 175, and the continuation or interruption of the flow of the two-dimensional electron gas 134 can be controlled by the bias voltage applied to the gate electrode 155. In the gate-off state, the flow of the two-dimensional electron gas 134 is blocked, and thus current may not flow between the source electrode 173 and the drain electrode 175. As the flow of the two-dimensional electron gas 134 continues in the gate-on state, current may flow between the source electrode 173 and the drain electrode 175.

[0076] Figure 9 is a cross-sectional view illustrating an example of a semiconductor device according to some implementations. Figure 9 The components shown in Figures 1 to 4 The elements shown in FIG are substantially the same, so their description will be omitted and the differences will be mainly explained. In addition, the same reference numerals are used for the same parts as the previous implementation. Figure 9 In the embodiment, the doped region 510 is not formed in the barrier layer 136 , but a groove 520 is formed in the barrier layer 136 , which may be slightly different from the previous embodiment.

[0077] exist Figure 9 , the barrier layer 136 may be located above the channel layer 132. A recess 520 may be formed in which at least a portion of the barrier layer 136 is removed. The depth of the recess 520 may correspond to the thickness of the barrier layer 136. The depth of the recess 520 may be substantially the same as the thickness of the barrier layer 136. However, it is not limited thereto, and the depth of the recess 520 may be less than or greater than the thickness of the barrier layer 136. In some implementations, the recess 520 may also be formed in the channel layer 132. The protective layer 140 may be located within the recess 520. For example, the recess 520 may be filled with the protective layer 140.

[0078] In some implementations, the portion where the recess 520 is formed in the barrier layer 136 may correspond to the portion where the doped region 510 is formed in the barrier layer 136 in the previous implementations. In some implementations, the recess 520 of the barrier layer 136 may be similar in position and function to the doped region 510 of the barrier layer 136 in the previous implementations. For example, when the recess 520 is formed in the barrier layer 136, the channel may be suppressed in some regions within the channel layer 132. The recess 520 of the barrier layer 136 may overlap with the channel suppression region CRA of the channel layer 132 in the third direction DR3.

[0079] The protruding portion 177a of the field spreading layer 177 may be adjacent to the groove 520 of the barrier layer 136. The protruding portion 177a may overlap with the groove 520 of the barrier layer 136 in the third direction DR3. At least a portion of the protruding portion 177a may overlap with the groove 520 of the barrier layer 136 in the third direction DR3. The protruding portion 177a may overlap with at least a portion of the groove 520 of the barrier layer 136 in the third direction DR3.

[0080] A plurality of grooves 520 may be formed in the barrier layer 136, and the plurality of grooves 520 may be arranged to be spaced apart along the second direction DR2. The spacing between the plurality of grooves 520, the shapes and sizes of the plurality of grooves 520, etc. may be constant, or at least some of them may be different. The plurality of grooves 520 may respectively correspond to the plurality of protrusions 177a. The plurality of grooves 520 may respectively correspond to the plurality of channel inhibition regions CRA.

[0081] Figure 10 is a cross-sectional view showing an example of a semiconductor device according to some implementations. Figure 10 The components shown in Figures 1 to 4 The embodiments shown in are substantially the same, so description thereof will be omitted and differences will be mainly explained. In addition, the same reference numerals are used for the same components as the previous implementation. Figure 10 In the embodiment, the doped region is not formed in the barrier layer, but the channel suppression pattern is located on the barrier layer, which may be slightly different from the previous embodiment.

[0082] exist Figure 10 In the embodiment, the semiconductor device may include a channel suppression pattern 530 located above the barrier layer 136. The barrier layer 136 may be located between the channel layer 132 and the channel suppression pattern 530. The channel suppression pattern 530 may include one or more materials selected from group III-V materials, such as a nitride containing at least one of Al, Ga, In, and B. The channel suppression pattern 530 may be Al x In y Ga 1-x-yN(0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel suppression pattern 530 may include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The channel suppression pattern 530 may include a material having a different energy band gap from the barrier layer 136. For example, the channel suppression pattern 530 may include GaN, and the barrier layer 136 may include AlGaN. The channel suppression pattern 530 may be doped with predetermined impurities. In this case, the impurities doped in the channel suppression pattern 530 may be P-type dopants that can provide holes. For example, the channel suppression pattern 530 may include GaN doped with P-type impurities. For example, the channel suppression pattern 530 may be made of a p-GaN layer. However, it is not limited thereto, and the channel suppression pattern 530 may be a p-AlGaN layer. For example, the impurities doped in the channel suppressing pattern 530 may be Mg, F, Be, Ca, Sr, Ba, Li, Na, Mn, Fe, Co, Cu, Zn, Cd, etc. The channel suppressing pattern 530 may be made of a single layer or multiple layers.

[0083] In some implementations, the portion where the channel suppression pattern 530 is formed on the barrier layer 136 may correspond to the portion where the doped region 510 is formed on the barrier layer 136 in the previous implementations. In some implementations, the channel suppression pattern 530 may be similar in position and function to the doped region 510 of the barrier layer 136 in the previous embodiments. For example, when the channel suppression pattern 530 is formed on the barrier layer 136, it may suppress the channel in some regions within the channel layer 132. The channel suppression pattern 530 may overlap with the channel suppression region CRA of the channel layer 132 in the third direction DR3.

[0084] The protruding portion 177a of the field dispersion layer 177 may be adjacent to the channel suppression pattern 530. The protruding portion 177a may overlap the channel suppression pattern 530 in the third direction DR3. At least a portion of the protruding portion 177a may overlap the channel suppression pattern 530 in the third direction DR3. The protruding portion 177a may overlap at least a portion of the channel suppression pattern 530 in the third direction DR3.

[0085] A plurality of channel suppression patterns 530 may be located on the barrier layer 136 and may be arranged spaced apart along the second direction DR2. The spacing between the plurality of channel suppression patterns 530, the shapes and sizes of the plurality of channel suppression patterns 530, etc. may be constant, or at least some of them may be different. The plurality of channel suppression patterns 530 may respectively correspond to the plurality of protruding portions 177a. The plurality of channel suppression patterns 530 may respectively correspond to the plurality of channel suppression areas CRA.

[0086] Figure 11is a cross-sectional view showing an example of a semiconductor device according to some implementations. Figure 11 The components shown in Figure 10 The elements shown in FIG5 are substantially the same, so their description will be omitted and the differences will be mainly explained. In addition, the same reference numerals are used for the same parts as the previous implementation. Figure 11 It may be slightly different from the previous implementation in that it further includes a gate semiconductor layer.

[0087] Figure 11 The semiconductor device shown may further include a gate semiconductor layer 152 located between the barrier layer 136 and the gate electrode 155. The gate semiconductor layer 152 may be Figure 8 The gate semiconductor layers 152 shown are the same, and a detailed description of the gate semiconductor layers 152 is omitted.

[0088] The gate semiconductor layer 152 and the channel suppressing pattern 530 may be located above the barrier layer 136. The gate semiconductor layer 152 and the channel suppressing pattern 530 may be located on the same layer. The gate semiconductor layer 152 and the channel suppressing pattern 530 may be formed using the same material and in the same process. Therefore, the gate semiconductor layer 152 and the channel suppressing pattern 530 may include the same material and have substantially the same thickness. By forming the channel suppressing pattern 530 together with the gate semiconductor layer 152 formation process, the process can be simplified and costs can be reduced.

[0089] Figure 12 is a cross-sectional view showing an example of a semiconductor device according to some implementations. Figure 12 The components shown in Figure 11 The elements shown in FIG5 are substantially the same, so their description will be omitted and the differences will be mainly explained. In addition, the same reference numerals are used for the same parts as the previous implementation. Figure 12 The embodiment may be slightly different from the previous embodiment in that the channel suppression pattern includes multiple layers.

[0090] exist Figure 12In the embodiment, the channel suppressing pattern 540 may be located on the barrier layer 136 in the semiconductor device. The channel suppressing pattern 540 may be composed of multiple layers. The channel suppressing pattern 540 may include a first layer 542 and a second layer 544 located above the first layer 542. The first layer 542 of the channel suppressing pattern 540 may be located between the barrier layer 136 and the second layer 544. The first layer 542 of the channel suppressing pattern 540 may be located on the same layer as the gate semiconductor layer 152. The first layer 542 of the channel suppressing pattern 540 may be formed using the same material and in the same process as the gate semiconductor layer 152. Therefore, the first layer 542 of the channel suppressing pattern 540 and the gate semiconductor layer 152 may include the same material and have substantially the same thickness. The second layer 544 of the channel suppressing pattern 540 may be located on the same layer as the gate electrode 155. The second layer 544 of the channel suppressing pattern 540 may be formed using the same material and in the same process as the gate electrode 155. Therefore, the second layer 544 of the channel suppression pattern 540 and the gate electrode 155 may include the same material and have substantially the same thickness.

[0091] The second layer 544 of the channel suppression pattern 540 may be floating. However, it is not limited thereto, and in some implementations, it may be connected to another conductive line so that a predetermined voltage is applied to the second layer 544 of the channel suppression pattern 540 .

[0092] Figure 13 and Figure 14 is a plan view showing an example of a semiconductor device according to some implementations. Figure 13 and Figure 14 The components shown in Figures 1 to 4 The elements shown in FIG are substantially the same, so their description will be omitted and the differences will be mainly explained. In addition, the same reference numerals are used for the same parts as the previous implementation. Figure 13 and Figure 14 In the embodiment, the planar shape of the protruding portion of the field spreading layer may be slightly different from that of the previous implementation.

[0093] exist Figure 13 In the embodiment, the protruding portion 177a of the field dispersion layer 177 may have a triangular shape on a plane. The protruding portion 177a may be formed as an isosceles triangle on a plane. Figure 14 As shown, the protrusion 177a of the field dispersion layer 177 may have a circular shape in a plane. Each of the plurality of protrusions 177a may have a substantially semicircular shape. The plurality of protrusions 177a may have a shape in which edges of the semicircular shape are connected to each other.

[0094] The planar shape of the protruding portion 177 a of the field spreading layer 177 is merely an example, and the planar shape of the protruding portion 177 a may be changed in various ways.

[0095] Figure 15 is a plan view showing an example of a semiconductor device according to some implementations. Figure 16 It is based on some implementation along Figure 15 A cross-sectional view shown along line XVI-XVI′ in FIG.

[0096] because Figure 15 and Figure 16 The components shown in Figure 1 and Figure 4 The elements shown in FIG5 are substantially the same, so their description will be omitted and the differences will be mainly explained. In addition, the same reference numerals are used for the same parts as the previous implementation. Figure 15 and Figure 16 The elements shown in may differ slightly from previous implementations in that the channel suppression region does not overlap with the protruding portion of the field spreading layer.

[0097] exist Figure 15 and Figure 16 , the channel suppression region CRA may be adjacent to an edge of the field dispersion layer 177 adjacent to the drain electrode 175. The channel suppression region CRA may be adjacent to the protruding portion 177a of the field dispersion layer 177. The channel suppression region CRA may overlap with the field dispersion layer 177 in the third direction DR3, and may not overlap with the protruding portion 177a of the field dispersion layer 177 in the third direction DR3.

[0098] In some implementations, at least a portion of the channel suppression region CRA may not be covered by the field spreading layer 177 , and in some implementations, the entire channel suppression region CRA may be covered by the field spreading layer.

[0099] Therefore, the doped region 510 of the barrier layer 136 may overlap with the field dispersion layer 177 in the third direction DR3, and may not overlap with the protruding portion 177a of the field dispersion layer 177 in the third direction DR3. The doped region 510 may be positioned closer to the gate electrode 155 than the protruding portion 177a of the field dispersion layer 177 in the first direction DR1. The entire doped region 510 of the barrier layer 136 may be covered by the field dispersion layer 177. As another example, similar to Figures 9 to 12 , the doping region 510 may be replaced by a groove 520 , a channel suppression pattern 530 , or a channel suppression pattern 540 .

[0100] In some implementations, the channel suppression region CRA may be formed by the doping region 510 of the barrier layer 136. However, it is not limited thereto, and as described in the previous implementations, the channel suppression region CRA may be formed by a groove formed in the barrier layer 136, a channel suppression pattern located on the barrier layer 136, etc. The channel suppression region CRA may be positioned closer to the gate electrode 155 than the protruding portion 177 a of the field dispersion layer 177 in the first direction DR1.

[0101] Figure 17 is a plan view showing an example of a semiconductor device according to some implementations. Figure 18 It is based on some implementation along Figure 17 A cross-sectional view shown along line XVIII-XVIII'. Figure 19 It is based on some implementation along Figure 17 A cross-sectional view shown along line XIX-XIX'.

[0102] because Figures 17 to 19 The components shown in Figures 1 to 4 The elements shown in FIG5 are substantially the same, so their description will be omitted and the differences will be mainly explained. In addition, the same reference numerals are used for the same parts as the previous implementation. Figures 17 to 19 It may differ slightly from the previous implementation in that the field spreading layer does not comprise protruding portions.

[0103] exist Figures 17 to 19 In the embodiment, an edge of the field dispersion layer 177 adjacent to the drain electrode 175 may be formed as a straight line. An edge of the field dispersion layer 177 adjacent to the drain electrode 175 may have a straight line shape parallel to the second direction DR2 on a plane.

[0104] In some implementations, the protruding portion 177 a may be formed from the edge of the field spreading layer 177 . In this embodiment, the protruding portion 177 a may not be formed at the edge of the field spreading layer 177 .

[0105] An edge of the field dispersion layer 177 adjacent to the drain electrode 175 may be adjacent to the channel suppression region CRA. An edge of the field dispersion layer 177 adjacent to the drain electrode 175 may overlap with the channel suppression region CRA in the third direction DR3. An edge of the field dispersion layer 177 adjacent to the drain electrode 175 may be adjacent to the doped region 510 of the barrier layer 136. An edge of the field dispersion layer 177 adjacent to the drain electrode 175 may overlap with the doped region 510 of the barrier layer 136 in the third direction DR3.

[0106] In some implementations, the channel suppression region CRA may be formed by the doped region 510 of the barrier layer 136. However, it is not limited thereto, and as described in the previous implementations, the channel suppression region CRA may be formed by a groove formed in the barrier layer 136, a channel suppression pattern located on the barrier layer 136, etc.

[0107] In some implementations, a gate semiconductor layer 152 may also be applied, wherein the gate semiconductor layer 152 is disposed between the gate electrode 152 and the barrier layer 136. For example, two of the doped region 510, the recess 520, the channel suppression pattern 530, and the channel suppression pattern 540 may be used together in the above implementations. Figure 4 In the embodiment of the present invention, the channel suppression pattern 530 may be formed on the doped region 510. In this case, at least some of the doped region 510 and the channel suppression pattern 530 may overlap in the third direction DR3. In some implementations, the doped region 510 and the channel suppression pattern 530 may not overlap in the third direction DR3. From a plan view, the doped region 510 and the channel suppression pattern 530 may be spaced apart in at least one of the first direction DR1 and the second direction DR2. Therefore, at least one of the doped region 510 and the channel suppression pattern 530 may not overlap with the protruding portion 177a of the field dispersion layer 177 in the third direction DR3. These examples may be similarly applied when two of the structures forming the channel suppression region CRA (the doped region 510, the recess 520, the channel suppression pattern 530, and the channel suppression pattern 540) are used together.

[0108] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of the claims. Certain features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single implementation. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0109] CROSS-REFERENCE TO RELATED APPLICATIONS

[0110] This application claims the benefit of Korean Patent Application No. 10-2024-0024432 filed on February 20, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device comprising: Channel layer, including channel suppression region, a barrier layer located above the channel layer, the barrier layer comprising a material having an energy bandgap different from that of the channel layer, a gate electrode located above the barrier layer, a protective layer located above the gate electrode, a source electrode and a drain electrode located on opposite sides of the gate electrode and connected to the channel layer, and A field spreading layer is located above the protection layer, the field spreading layer including a protruding portion adjacent to the channel suppression region, the protruding portion protruding from an edge of the field spreading layer adjacent to the drain electrode toward the drain electrode.

2. The semiconductor device according to claim 1, in, The source electrode and the drain electrode are spaced apart from each other in a first direction, wherein the gate electrode, the source electrode, and the drain electrode extend in a second direction intersecting the first direction, The protruding portion overlaps with the channel suppression region in a third direction perpendicular to the first direction and the second direction.

3. The semiconductor device according to claim 2, in, The length of the protruding portion along the first direction is 0.1 μm or more and 2 μm or less, and Here, a width of the protruding portion along the second direction is 0.05 μm or more and 5 μm or less.

4. The semiconductor device according to claim 2, in, The barrier layer includes a doped region overlapping the channel suppression region in the third direction, and Wherein, the doped region contains Ar or N.

5. The semiconductor device according to claim 2, wherein The channel suppression region overlaps with the groove in at least a portion of the barrier layer in the third direction. 6 . The semiconductor device according to claim 2 , further comprising a channel suppression pattern overlapping the channel suppression region in the third direction on the barrier layer.

7. The semiconductor device according to claim 6, wherein The channel suppressing pattern includes pGaN.

8. The semiconductor device according to claim 6, further comprising: a gate semiconductor layer, between the barrier layer and the gate electrode, Wherein, the channel suppression pattern includes: First layer; and a second layer located above the first layer, and wherein the first layer of the channel suppression pattern is located on the same layer as the gate semiconductor layer, and The second layer of the channel suppression pattern is located on the same layer as the gate electrode.

9. The semiconductor device according to claim 2, in, The channel layer includes a plurality of channel suppression regions, and The field spreading layer includes a plurality of protruding portions corresponding to a plurality of channel suppression regions respectively.

10. The semiconductor device according to claim 9, in, The plurality of channel suppression regions are equally spaced apart from each other along the second direction, and The plurality of protruding portions are equidistantly spaced from each other along the second direction.

11. The semiconductor device according to claim 1, in, The source electrode and the drain electrode are spaced apart from each other in a first direction, wherein the gate electrode, the source electrode, and the drain electrode extend in a second direction intersecting the first direction, The channel suppression region is spaced apart from the protruding portion in the first direction and does not overlap with the field spreading layer.

12. The semiconductor device according to claim 11, wherein: A separation distance between the channel suppression region and the protruding portion along the first direction is 0.5 μm or less.

13. The semiconductor device according to claim 1, in, The source electrode and the drain electrode are spaced apart from each other in a first direction, wherein the gate electrode, the source electrode, and the drain electrode extend in a second direction intersecting the first direction, The channel suppression region is spaced apart from the protruding portion in the first direction and overlaps with the field spreading layer.

14. The semiconductor device according to claim 1, wherein The protruding portion includes a quadrangular, triangular, or circular planar shape.

15. The semiconductor device according to claim 1, wherein The field spreading layer is integrated with the source electrode and covers an upper surface of the gate electrode.

16. A semiconductor device comprising: The channel layer includes GaN, a barrier layer located above the channel layer and comprising AlGaN, a gate electrode located above the barrier layer, a protective layer located above the gate electrode, a source electrode and a drain electrode located on opposite sides of the gate electrode and connected to the channel layer, and a field spreading layer located on the protection layer and connected to the source electrode, Wherein, a two-dimensional electron gas is formed between the source electrode and the drain electrode in the channel layer, wherein the channel layer includes a channel suppression region in which the two-dimensional electron gas is suppressed, and The field spreading layer includes a protruding portion, and the protruding portion overlaps the channel suppression region in a vertical direction with respect to an upper surface of the channel layer.

17. The semiconductor device according to claim 16, in, The barrier layer includes a doped region, the doped region overlapping the channel suppression region in the vertical direction perpendicular to the upper surface of the channel layer, Wherein, the doped region contains Ar or N.

18. The semiconductor device according to claim 16, wherein The channel suppression region overlaps with the groove in at least a portion of the barrier layer in the vertical direction. 19 . The semiconductor device according to claim 16 , further comprising a channel suppression pattern on the barrier layer to overlap the channel suppression region in the vertical direction perpendicular to the upper surface of the channel layer.

20. A semiconductor device comprising: The channel layer includes GaN, a barrier layer located above the channel layer and comprising AlGaN, a gate electrode located above the barrier layer, a protective layer located above the gate electrode, a source electrode and a drain electrode located on opposite sides of the gate electrode and connected to the channel layer, and a field spreading layer located on the protection layer and connected to the source electrode, Wherein, a two-dimensional electron gas is formed between the source electrode and the drain electrode in the channel layer, wherein the channel layer includes a channel suppression region in which the two-dimensional electron gas is suppressed, wherein an edge of the field spreading layer adjacent to the drain electrode overlaps with the channel suppression region, and The channel suppression region overlaps with a doped region containing Ar or N within the barrier layer, or overlaps with a groove from which the barrier layer is removed.

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