Semiconductor device and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof. The semiconductor device comprises an III-N structure layer, a source electrode, a drain electrode, a grid electrode, at least one conductive unit, a first dielectric layer and a second dielectric layer, along the thickness direction of the semiconductor device, the first dielectric layer is located between the III-N structure layer and the second dielectric layer; the first dielectric layer is provided with a groove, and the groove is provided with a first side wall close to the source electrode and a second side wall close to the drain electrode; the grid electrode and the conductive unit are discontinuously arranged in the groove, the grid electrode at least partially covers the bottommost part of the groove, the conductive unit is arranged on at least one side wall, the grid electrode and the conductive unit are discontinuous, and at least part of the conductive unit is used as a field plate for adjusting electric field distribution; the second dielectric layer at least covers the groove, the grid electrode and the conductive unit. While the function of the field plate is realized, the stray capacitance is reduced, and flexible adjustment of the stray capacitance is realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In modern semiconductor technology, field plate technology is often used to optimize the device structure to increase the breakdown voltage and reduce the peak electric field of semiconductor devices (such as high electron mobility transistors (HEMTs)). Field plate technology is primarily categorized into two types: planar field plates and angled field plates. These designs aim to effectively control the electric field distribution, thereby enhancing the device's voltage tolerance and improving its operational stability.

[0003] However, in semiconductor devices, parasitic parameters between the field plate and other conductive elements, such as parasitic capacitance and parasitic inductance, significantly affect the performance of semiconductor devices. Specifically, parasitic capacitance can cause problems such as signal delay, frequency response degradation, and increased power consumption. Therefore, it is particularly important to accurately control the size of parasitic capacitance. The generation of parasitic capacitance is closely related to the overlap area between the field plate and other conductive elements, which means that the geometric structure of the field plate design plays an important role in the overall performance.

[0004] Currently, most semiconductor devices use a single field plate design, which greatly limits the precise adjustment and optimization of parasitic capacitance. Due to the lack of flexible field plate design solutions, engineers face many challenges in dealing with parasitic parameters and are unable to achieve optimal electrical performance and device stability. Therefore, exploring new field plate structures and designs that can more accurately adjust parasitic capacitance has become a key research direction for improving semiconductor device performance. This requires in-depth analysis of existing technologies to find effective ways to avoid parasitic effects and optimize device performance. Summary of the Invention

[0005] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, which can solve the problem that the parasitic parameters between the field plate and other conductive elements in the semiconductor device are large and difficult to adjust.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising a III-N structure layer, a source, a drain, a gate and at least one conductive unit, a first dielectric layer, and a second dielectric layer; along the thickness direction of the semiconductor device, a first dielectric layer having a thickness is located between the III-N structure layer and the second dielectric layer; the first dielectric layer is provided with a groove, the groove having a first sidewall close to the source and a second sidewall close to the drain; the gate and the at least one conductive unit are intermittently arranged in the groove, the gate at least partially covers the bottom of the groove, the at least one conductive unit is arranged on at least one sidewall of the first sidewall and the second sidewall, and the gate and the at least one conductive unit are discontinuous, wherein at least part of the conductive units are used as field plates for adjusting the electric field distribution; the second dielectric layer at least covers the groove, the gate and the at least one conductive unit.

[0007] According to some embodiments of the present application, optionally, both the first side wall and the second side wall have no steps, and at least one conductive unit is arranged on at least one of the first side wall and the second side wall inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to the thickness direction of the semiconductor device.

[0008] According to some embodiments of the present application, optionally, at least one of the first sidewall and the second sidewall includes n steps, where n≥1 and is an integer; the semiconductor device includes a plurality of conductive units, and the plurality of conductive units are intermittently arranged on the steps of at least one sidewall and are discontinuous on the steps of at least one sidewall.

[0009] According to some embodiments of the present application, optionally, the first side wall includes n1 steps, the second side wall includes n2 steps or no steps, n1≥1, n2≥1, n1 and n2 are both integers; multiple conductive units are discontinuously arranged on the n1 steps of the first side wall, and / or, multiple conductive units are discontinuously arranged on the n2 steps of the second side wall.

[0010] According to some embodiments of the present application, optionally, the number of steps of the first sidewall is the same as or different from the number of steps of the second sidewall.

[0011] According to some embodiments of the present application, optionally, the III-N structure layer includes at least a channel layer and a barrier layer, and a heterojunction is formed between the channel layer and the barrier layer to serve as a channel of the device; along the thickness direction of the semiconductor device, the source and the drain are located between the channel layer and the first dielectric layer, and both the source and the drain form an ohmic electrical contact with the heterojunction.

[0012] According to some embodiments of the present application, optionally, the semiconductor device further includes a substrate, and the III-N structure layer further includes a buffer layer. Along the thickness direction of the semiconductor device, the buffer layer is located on a side of the channel layer away from the barrier layer, and the substrate is located on a side of the buffer layer away from the channel layer; the buffer layer, the channel layer, and the barrier layer are formed by the composition difference between the III-N structure layers, a heterojunction is formed at the interface between the channel layer and the barrier layer, and a 2DEG channel is formed in the heterojunction.

[0013] According to some embodiments of the present application, optionally, the groove penetrates the first dielectric layer, and the gate covers at least the bottom of the groove and extends at least to the steps of the first sidewall and the second sidewall.

[0014] According to some embodiments of the present application, optionally, at least part of the conductive units are inclined field plates inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to a thickness direction of the semiconductor device;

[0015] Alternatively, at least part of the conductive unit is a planar field plate parallel to the horizontal reference plane;

[0016] Alternatively, at least part of the conductive unit includes an inclined portion inclined to the horizontal reference plane and a planar portion parallel to the horizontal reference plane, the inclined portion is used as a slanted field plate, and the planar portion is used as a planar field plate.

[0017] According to some embodiments of the present application, optionally, when the conductive unit is a slanted field plate, the angle between the conductive unit and the horizontal reference plane is greater than 0° and less than 90°, or greater than 90° and less than 180°.

[0018] According to some embodiments of the present application, optionally, the conductive unit is located on at least one step and covers the slope surface between two adjacent steps.

[0019] According to some embodiments of the present application, optionally, the conductive unit located on the i-th step of the first side wall and / or the second side wall also extends to the surface of the i+1-th step, i≤n-1 and is a positive integer; along the thickness direction of the semiconductor device, the step closest to the second dielectric layer is the n-th step; the conductive unit located on the n-th step of the first side wall and / or the second side wall also extends to the surface of the first dielectric layer close to the second dielectric layer.

[0020] According to some embodiments of the present application, optionally, the source and the drain are arranged along a first direction, the source and the drain extend along a second direction, the first direction intersects the second direction, and the first direction and the second direction are both perpendicular to the thickness direction of the semiconductor device; the semiconductor device includes a plurality of conductive units, and the plurality of conductive units are arranged at intervals along the first direction, or at least some of the conductive units are arranged in an array along the first direction and the second direction.

[0021] According to some embodiments of the present application, optionally, multiple conductive units of the semiconductor device are connected to the same potential.

[0022] According to some embodiments of the present application, optionally, the plurality of conductive units are at least partially electrically connected to any one of a gate, a source, or other target potential terminals.

[0023] According to some embodiments of the present application, optionally, the semiconductor device further includes at least one connecting unit, the at least one connecting unit extending along a first direction, the multiple conductive units extending along a second direction, the at least one connecting unit and the multiple conductive units being located in the same conductive layer, and the at least one connecting unit being used to electrically connect the multiple conductive units to the gate.

[0024] According to some embodiments of the present application, optionally, the interface at one end of at least part of the conductive unit is open, and the open end is connected to a potential at any position; or, the interfaces at both ends of at least part of the conductive unit are open, and at least one end of the part of the conductive unit is electrically connected to one end of a functional element inside or outside the semiconductor device, and the other end of at least part of the conductive unit and / or the other end of the functional element is connected to a potential at any position.

[0025] According to some embodiments of the present application, optionally, at least two conductive units of the semiconductor device are connected to different potentials.

[0026] According to some embodiments of the present application, optionally, a portion of the conductive units is electrically connected to the gate, and another portion of the conductive units is electrically connected to the source.

[0027] According to some embodiments of the present application, optionally, at least part of the conductive unit is used as a functional element inside the semiconductor device.

[0028] According to some embodiments of the present application, optionally, a first end of the conductive unit is electrically connected to the gate or the source, a second end of the conductive unit is electrically connected to the target potential end, and the conductive unit is used as a resistor;

[0029] And / or, the conductive unit forms a PN junction, a first end of the conductive unit is electrically connected to the source, a second end of the conductive unit is electrically connected to the drain, and the conductive unit is used to act as a diode;

[0030] And / or, one of the conductive units is electrically connected to the gate, and the other conductive unit is electrically connected to the source or the drain, and the two conductive units are used as capacitors.

[0031] In a second aspect, an embodiment of the present application provides a semiconductor device comprising a III-N structure layer, a source, a drain, a gate and a plurality of conductive units, a first dielectric layer, and a second dielectric layer; along the thickness direction of the semiconductor device, a first dielectric layer having a thickness is located between the III-N structure layer and the second dielectric layer; the gate is covered by the first dielectric layer, or the gate is located in a first groove opened in the first dielectric layer and covered by the second dielectric layer; the first dielectric layer or the second dielectric layer further has a second groove, the second groove having a first sidewall close to the source and a second sidewall close to the drain; a plurality of conductive units are intermittently arranged on the bottom and / or at least one sidewall of the second groove, and are discontinuous in the second groove, wherein at least some of the conductive units are used as field plates for adjusting the electric field distribution.

[0032] According to some embodiments of the present application, optionally, the gate includes one sub-gate or multiple sub-gates; when the gate includes multiple sub-gates, the multiple sub-gates are discontinuously arranged on the surface of the III-N structure layer close to the first dielectric layer or discontinuously arranged in the first groove.

[0033] According to some embodiments of the present application, optionally, both the first side wall and the second side wall have no steps, and a plurality of conductive units are discontinuously arranged at the bottom of the second groove and / or on at least one of the first side wall and the second side wall inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to the thickness direction of the semiconductor device.

[0034] According to some embodiments of the present application, optionally, at least one of the first sidewall and the second sidewall includes n steps, where n≥1 and is an integer; at least part of the conductive unit is discontinuously arranged on the steps of at least one sidewall and is discontinuous on the steps of at least one sidewall.

[0035] According to some embodiments of the present application, optionally, among the multiple conductive units, a first portion of the conductive units is arranged at the bottom of the second groove, a second portion of the conductive units is arranged on the first sidewall, and a third portion of the conductive units is arranged on the second sidewall.

[0036] According to some embodiments of the present application, optionally, at least part of the conductive units are inclined field plates inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to a thickness direction of the semiconductor device;

[0037] Alternatively, at least part of the conductive unit is a planar field plate parallel to the horizontal reference plane;

[0038] Alternatively, at least part of the conductive unit includes an inclined portion inclined to the horizontal reference plane and a planar portion parallel to the horizontal reference plane, the inclined portion is used as a slanted field plate, and the planar portion is used as a planar field plate.

[0039] In a third aspect, an embodiment of the present application provides a method for preparing a semiconductor device, comprising: providing or forming a semiconductor bottom structure, the semiconductor bottom structure comprising at least a III-N structure layer, a source, and a drain; forming a first dielectric layer on the III-N structure layer; opening a groove on the first dielectric layer, the groove having a first sidewall close to the source and a second sidewall close to the drain; forming an intermittently arranged gate and at least one conductive unit in the groove, wherein the gate at least partially covers the bottommost part of the groove, the at least one conductive unit is arranged on at least one sidewall of the first sidewall and the second sidewall, and the gate and the at least one conductive unit are discontinuous, and at least part of the conductive unit is used as a field plate for adjusting the electric field distribution; and forming a second dielectric layer on a side of the first dielectric layer away from the III-N structure layer.

[0040] According to some embodiments of the present application, optionally, a discontinuously set gate and at least one conductive unit are formed in the groove, including: depositing a conductive layer on the bottom and at least one side wall of the groove, and etching the conductive layer into a discontinuously set gate and at least one conductive unit; or, using a mask to block part of the groove, and depositing a discontinuously set gate and at least one conductive unit in the area not blocked by the mask on the bottom and at least one side wall of the groove.

[0041] According to some embodiments of the present application, optionally, the semiconductor bottom structure further includes an insulator layer, and along the thickness direction of the semiconductor device, the insulator layer is located between the III-N structure layer and the first dielectric layer; forming the first dielectric layer on the III-N structure layer includes: forming the insulator layer on the III-N structure layer; forming the first dielectric layer on a side of the insulator layer away from the III-N structure layer, the first dielectric layer covering the source, the drain, and the insulator layer.

[0042] In a fourth aspect, an embodiment of the present application provides a method for preparing a semiconductor device, comprising: providing or forming a semiconductor bottom structure, the semiconductor bottom structure comprising at least a III-N structure layer, a source, and a drain; sequentially forming a gate and a first dielectric layer on the III-N structure layer, the first dielectric layer covering the gate; opening a second groove on the first dielectric layer, the second groove having a first sidewall close to the source and a second sidewall close to the drain; forming a plurality of discontinuously arranged conductive units on the bottom and / or at least one sidewall of the second groove, wherein the plurality of conductive units are discontinuous in the second groove, and at least some of the conductive units are used as field plates for adjusting the electric field distribution.

[0043] In a fifth aspect, an embodiment of the present application provides a method for preparing a semiconductor device, comprising: providing or forming a semiconductor bottom structure, the semiconductor bottom structure comprising at least a III-N structure layer, a source, and a drain; sequentially forming a gate and a first dielectric layer on the III-N structure layer, the first dielectric layer covering the gate; or, forming a first dielectric layer on the III-N structure layer, opening a first groove in the first dielectric layer, and forming a gate in the first groove; forming a second dielectric layer on a side of the first dielectric layer away from the III-N structure layer; opening a second groove in the second dielectric layer, the second groove having a first sidewall close to the source and a second sidewall close to the drain; forming a plurality of conductive units intermittently arranged on the bottom and / or at least one sidewall of the second groove, wherein the plurality of conductive units are discontinuous in the second groove, and wherein at least some of the conductive units are used as field plates for adjusting the electric field distribution.

[0044] The semiconductor device and preparation method provided by the embodiments of the present application, on the one hand, at least part of the conductive units can be used as field plates, which is beneficial to reducing the peak electric field of the semiconductor device and increasing the breakdown voltage of the semiconductor device, thereby achieving a higher voltage withstand specification of the semiconductor device; on the other hand, the gate and at least one conductive unit arranged at intervals replace the original single large-area metal covering, which is beneficial to reducing the overlapping area between the conductive unit and other conductive elements (such as electrodes or electrode interconnections), thereby facilitating the reduction of parasitic capacitance between the conductive unit and other conductive elements (such as electrodes or electrode interconnections), and further facilitating the improvement of the switching speed of the semiconductor device, shortening the response time of the semiconductor device, and reducing power consumption; on the other hand, as the area of ​​the conductive unit is reduced, it is beneficial to reduce the risk of short circuit caused by the introduction of particles or dust into the conductive unit during the production process, thereby improving the yield of the semiconductor device; on the other hand, the number, position and width of the multiple conductive units can be flexibly adjusted according to actual conditions, which is beneficial to flexible adjustment of the parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 A schematic cross-sectional view of a semiconductor device;

[0047] Figure 2 A schematic top view of a semiconductor device provided in an embodiment of the present application;

[0048] Figure 3 For the Figure 2 A schematic cross-sectional view of a semiconductor device in the A1-A2 direction;

[0049] Figure 4 Another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0050] Figure 5 A schematic cross-sectional view of another semiconductor device provided in an embodiment of the present application;

[0051] Figure 6 A schematic cross-sectional view of another semiconductor device provided in an embodiment of the present application;

[0052] Figure 7 For the Figure 2 Another cross-sectional schematic diagram of the semiconductor device in the A1-A2 direction;

[0053] Figure 8 Another schematic top view of a semiconductor device provided in an embodiment of the present application;

[0054] Figure 9 Another schematic top view of a semiconductor device provided in an embodiment of the present application;

[0055] Figure 10 For the Figure 8 A schematic cross-sectional view of a semiconductor device in the B1-B2 direction;

[0056] Figure 11 Another schematic top view of a semiconductor device provided in an embodiment of the present application;

[0057] Figure 12 A schematic diagram of a circuit connection of a conductive unit in a semiconductor device provided in an embodiment of the present application;

[0058] Figure 13 Schematic diagrams of various circuit connections of conductive units in a semiconductor device provided in an embodiment of the present application;

[0059] Figure 14 A schematic cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0060] Figure 15 Another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0061] Figure 16 A schematic cross-sectional view of another semiconductor device provided in an embodiment of the present application;

[0062] Figure 17 A schematic cross-sectional view of another semiconductor device provided in an embodiment of the present application;

[0063] Figure 18 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present application;

[0064] Figure 19 A schematic diagram of step S184 in the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0065] Figure 20 Another schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0066] Figure 21 Another schematic diagram of the process of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0067] Figure 22 A schematic diagram of another process of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0068] Figure 23 A schematic diagram of another process of the method for preparing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0070] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0071] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0072] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0073] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0074] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0075] In modern semiconductor technology, field plate technology is often used to optimize the device structure to increase the breakdown voltage and reduce the peak electric field of semiconductor devices (such as high electron mobility transistors (HEMTs)). Field plate technology is primarily categorized into two types: planar field plates and angled field plates. These designs aim to effectively control the electric field distribution, thereby enhancing the device's voltage tolerance and improving its operational stability.

[0076] However, in semiconductor devices, parasitic parameters between the field plate and other conductive elements, such as parasitic capacitance and parasitic inductance, significantly affect the performance of semiconductor devices. Specifically, parasitic capacitance can cause problems such as signal delay, frequency response degradation, and increased power consumption. Therefore, it is particularly important to accurately control the size of parasitic capacitance. The generation of parasitic capacitance is closely related to the overlap area between the field plate and other conductive elements, which means that the geometric structure of the field plate design plays an important role in the overall performance.

[0077] Currently, most semiconductor devices use a single-structure field plate design, which greatly limits the precise adjustment and optimization of parasitic capacitance. Figure 1 It is a cross-sectional schematic diagram of a semiconductor device. Figure 1As shown, to improve the uniform electric field effect, a stepped field plate 11 can be formed by stacking grooves. However, the area of ​​the stepped field plate 11 is relatively large, so the overlap area between the stepped field plate 11 and other conductive elements (such as electrodes or electrode interconnects) is also large, resulting in a large parasitic capacitance. Parasitic capacitance can cause problems such as signal delay, reduced frequency response, and increased power consumption in semiconductor devices.

[0078] Due to the lack of flexible field plate design solutions, there are currently many challenges in managing parasitic parameters, making it difficult to achieve optimal electrical performance and device stability. Therefore, exploring new field plate structures and designs to more accurately adjust parasitic capacitance has become a key research direction for improving semiconductor device performance.

[0079] In view of the above research findings of the inventors, the embodiments of the present application provide a semiconductor device and a method for preparing the same, which can solve the problem that the parasitic parameters between the field plate and other conductive elements in the semiconductor device are large and difficult to adjust.

[0080] The following first introduces the semiconductor device provided in the embodiments of the present application.

[0081] In a first aspect, an embodiment of the present application provides a semiconductor device 20 . Figure 2 A schematic top view of a semiconductor device provided in an embodiment of the present application. Figure 3 For the Figure 2 A cross-sectional diagram of a semiconductor device in the A1-A2 direction. Figure 2 and Figure 3 As shown, the semiconductor device 20 provided in the embodiment of the present application may include a III-N structure layer 00, a source 21, a drain 22, at least one conductive unit 23, a gate 24, a first dielectric layer 05, and a second dielectric layer 06. The III-N structure layer refers to a film layer where a nitride semiconductor material composed of a group III element (such as aluminum Al, gallium Ga, indium In) and nitrogen (N) is located. In some embodiments, the semiconductor device may be a transistor, such as a high electron mobility transistor (HEMT), and the gate 24 may be used to control the on and off states of the transistor. The III-N structure layer may include film layers of at least two different III-N materials, and a heterojunction may be formed in the III-N structure layer to act as a channel of the semiconductor device (see Figure 3The semiconductor device 20 may be a high electron mobility transistor (HEMT) as shown by the dotted line, such as a two-dimensional electron gas (2DEG) channel. The source 21, the drain 22, the conductive unit 23, and the gate 24 may all be made of conductive materials. The material of the conductive unit 23 may be the same as or different from that of the gate 24, and this is not limited in this application. The first dielectric layer 05 may be a single insulating material or a multi-layer composite insulating material. The second dielectric layer 06 may be a single insulating material or a multi-layer composite insulating material. Insulating materials include, but are not limited to, silicon nitride or silicon dioxide.

[0082] like Figure 3 As shown, along the thickness direction (Z direction) of the semiconductor device, a first dielectric layer 05 having a thickness may be located between the III-N structure layer 00 and the second dielectric layer 06. The source 21 and the drain 22 may both be in electrical contact with the 2DEG of the heterojunction, such as an ohmic contact.

[0083] The first dielectric layer 05 may be provided with a groove C, which may have a first sidewall B1 close to the source 21 and a second sidewall B2 close to the drain 22. The groove C may or may not penetrate the first dielectric layer 05, and this is not limited in this application. The gate 24 and the at least one conductive unit 23 are intermittently arranged in the groove C, that is, the gate 24 and the at least one conductive unit 23 are discontinuous. The gate 24 at least partially covers the bottom of the groove C, and the at least one conductive unit 23 can be arranged on at least one sidewall of the first sidewall B1 and the second sidewall B2. Figure 3 The example in which both the first side wall B1 and the second side wall B2 are provided with the conductive unit 23 is shown. In other embodiments, at least one conductive unit 23 may be provided only on the first side wall B1 or only on the second side wall B2, which is not limited in this application.

[0084] like Figure 3 As shown, the second dielectric layer 06 may at least cover the groove C, the gate 24 and at least one conductive unit 23. In some embodiments, at least part of the conductive unit 23 may be used as a field plate to adjust the electric field distribution.

[0085] As shown in the figure, only some of the conductive units 23 can be used as field plates, or all of the conductive units 23 can be used as field plates. It should be noted that the number, position, and width of the multiple conductive units 23 can be flexibly adjusted according to actual conditions, and this application does not limit this. In addition, the spacing d between any two adjacent conductive units 23 can be equal or unequal, and this application does not limit this.

[0086] In the semiconductor device 20 provided in the embodiment of the present application, on the one hand, at least part of the conductive units can be used as field plates, which is beneficial to reducing the peak electric field of the semiconductor device and increasing the breakdown voltage of the semiconductor device, thereby achieving a higher voltage withstand specification of the semiconductor device; on the other hand, the gate and at least one conductive unit arranged at intervals replace the original single large-area metal covering, which is beneficial to reducing the overlapping area between the conductive unit and other conductive elements (such as electrodes or electrode interconnections), thereby facilitating the reduction of parasitic capacitance between the conductive unit and other conductive elements (such as electrodes or electrode interconnections), and further facilitating the improvement of the switching speed of the semiconductor device, shortening the response time of the semiconductor device, and reducing power consumption; on the other hand, as the area of ​​the conductive unit is reduced, it is beneficial to reduce the risk of short circuit caused by the introduction of particles or dust into the conductive unit during the production process, thereby improving the yield of the semiconductor device; on the other hand, the number, position and width of the multiple conductive units can be flexibly adjusted according to actual conditions, which is beneficial to flexible adjustment of the parasitic capacitance.

[0087] In the embodiment of the present application, the first side wall B1 and the second side wall B2 may have steps or may not have steps, and the present application does not limit this. Figure 4 Another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 4 As shown, in some embodiments, optionally, both the first sidewall B1 and the second sidewall B2 have no steps, and at least one conductive unit 23 may be disposed on at least one of the first sidewall B1 and the second sidewall B2 that is inclined to a horizontal reference plane P. The horizontal reference plane P is perpendicular to a thickness direction Z of the semiconductor device.

[0088] That is, when both the first side wall B1 and the second side wall B2 have no steps, at least one conductive unit 23 can be provided on either the first side wall B1 or the second side wall B2. Alternatively, a conductive unit 23 can be provided on both the first side wall B1 and the second side wall B2.

[0089] Figure 5 This is another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 5 As shown, Figure 4 Unlike the illustrated embodiment, in other embodiments, at least one of the first sidewall B1 and the second sidewall B2 may include n steps T, where n ≥ 1 and is an integer. The semiconductor device 20 may include a plurality of conductive units 23, wherein the plurality of conductive units 23 are intermittently disposed on the steps T of the at least one sidewall, and the plurality of conductive units 23 are discontinuous on the steps T of the at least one sidewall.

[0090] like Figure 3 or Figure 5As shown, for example, in some specific examples, the first side wall B1 may include n1 steps T or no steps, and the second side wall B2 may include n2 steps T, where n1 ≥ 1, n2 ≥ 1, and n1 and n2 are both integers. In other specific examples, the first side wall B1 may include n1 steps T, and the second side wall B2 may include n2 steps T or no steps, where n1 ≥ 1, n2 ≥ 1, and n1 and n2 are both integers. The number of n1 and n2 can be flexibly adjusted according to actual conditions and is not limited in this application.

[0091] The plurality of conductive units 23 may be intermittently arranged on n1 steps T of the first side wall B1, and / or the plurality of conductive units 23 may be intermittently arranged on n2 steps T of the second side wall B2. Figure 3 As shown, in some examples, for example, some conductive units 23 may be discontinuously arranged on n1 steps T of the first side wall B1, and other conductive units 23 may be discontinuously arranged on n2 steps T of the second side wall B2. Figure 5 As shown, in other examples, for example, multiple conductive units 23 can be intermittently provided on n2 steps T of the second side wall B2, the first side wall B1 has no steps, and the first side wall B1 can be provided with the conductive units 23 or not. In still other examples, for example, multiple conductive units 23 can be intermittently provided on n1 steps T of the first side wall B1, the second side wall B2 has no steps, and the second side wall B2 can be provided with the conductive units 23 or not.

[0092] It should be noted that the number of steps on the first sidewall and the number of steps on the second sidewall can be the same or different, and the number of steps T on each sidewall can be flexibly adjusted according to actual conditions, and this application does not limit this. When multiple conductive units 23 are arranged at intervals on the first sidewall B1 and / or the second sidewall B2, the heights of the multiple conductive units 23 arranged at intervals on the multiple steps T of each sidewall along the thickness direction Z of the semiconductor device can gradually increase, gradually decrease, or be staggered, and this application does not limit this.

[0093] like Figure 3 、 Figure 4 or Figure 5 As shown, according to some embodiments of the present application, optionally, the III-N structure layer 00 may include at least a channel layer 03 and a barrier layer 04, and a heterojunction is formed between the channel layer 03 and the barrier layer 04 to serve as a channel of the semiconductor device, such as forming a two-dimensional electron gas 2DEG (see Figure 3(shown by the dashed line). A heterojunction can be a structure composed of two different semiconductor materials, which allows electrons and holes to form a two-dimensional electron gas (2DEG) at the interface. For example, the channel layer 03 can be made of gallium nitride (GaN) or gallium arsenide (GaAs). The barrier layer 04 can be made of aluminum gallium nitride (AlGaN) or aluminum nitride (AlN).

[0094] Along the thickness direction Z of the semiconductor device, the source electrode 21 and the drain electrode 22 may be located between the channel layer 03 and the first dielectric layer 05 , and both the source electrode 21 and the drain electrode 22 may form an ohmic electrical contact with the heterojunction.

[0095] Figure 6 This is another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 6 As shown, Figure 3 Unlike the illustrated embodiment, in other embodiments, the semiconductor device 20 may further include a substrate 01, and the III-N structure layer 00 may further include a buffer layer 02. Along the thickness direction Z of the semiconductor device, the buffer layer 02 may be located on a side of the channel layer 03 away from the barrier layer 04, and the substrate 01 may be located on a side of the buffer layer 02 away from the channel layer 03. That is, along the thickness direction Z of the semiconductor device, the buffer layer 02 may be located between the substrate 01 and the channel layer 03.

[0096] The buffer layer 02 , the channel layer 03 and the barrier layer 04 are formed by the composition difference between the III-N structure layer 00 . A heterojunction is formed at the interface between the channel layer 03 and the barrier layer 04 , and a 2DEG channel is formed in the heterojunction.

[0097] The buffer layer 02 can be used to improve the interface quality between the substrate and the channel layer, reduce stress, and thus enhance device performance. For example, the material of the substrate 01 includes, but is not limited to, sapphire, silicon, silicon nitride, or aluminum nitride. The material of the buffer layer 02 includes, but is not limited to, aluminum nitride, gallium nitride, silicon oxide, or silicon nitride.

[0098] It should be noted that if Figure 3 As shown, in some embodiments, the substrate may be removed, or the substrate and the buffer layer may be removed simultaneously. In this way, the influence of the substrate (especially a foreign substrate, such as a silicon substrate) on the performance of the semiconductor device may be reduced or avoided by removing the substrate.

[0099] like Figure 6As shown, according to some embodiments of the present application, the semiconductor device 20 may optionally further include an insulator layer 07. Along the thickness direction Z of the semiconductor device, the insulator layer 07 may be located between the barrier layer 04 and the first dielectric layer 05. The thickness of the insulator layer 07 may be flexibly adjusted according to actual conditions and is not limited in this application. In this way, by adding the insulator layer 07, leakage current from the gate 24 can be effectively prevented.

[0100] like Figure 3 and Figure 6 As shown, according to some embodiments of the present application, optionally, the groove C may penetrate the first dielectric layer 05 , and the gate 24 may at least cover the bottom of the groove C and extend at least to the steps of the first sidewall B1 and the second sidewall B2 .

[0101] Along the thickness direction Z of the semiconductor device, for example, the step T closest to the barrier layer O4 between the first sidewall B1 and the second sidewall B2 is the first step T1. The gate 24 can extend from the bottom of the groove C to the surface of the first step T1 between the first sidewall B1 and the second sidewall B2. In this way, the gate 24 can be equipped with a slanted field plate x1 inclined with respect to the horizontal reference plane and a flat field plate x2 parallel to the horizontal reference plane, further promoting a uniform electric field and increasing the breakdown voltage of the semiconductor device.

[0102] Combine Figure 2 and Figure 3 As shown, according to some embodiments of the present application, optionally, at least part of the conductive unit 23 may include an inclined portion 23a inclined to the horizontal reference plane P and a planar portion 23b parallel to the horizontal reference plane P. The inclined portion 23a can be used as an inclined field plate, and the planar portion 23b can be used as a planar field plate. The horizontal reference plane P can be perpendicular to the thickness direction Z of the semiconductor device. In some examples, the angle θ between the inclined portion 23a (i.e., the inclined field plate) and the horizontal reference plane P can be greater than 0° and less than 90°, or greater than 90° and less than 180°. The inclination angle of the inclined portion 23a can be flexibly adjusted according to actual conditions, and this application does not limit this.

[0103] Compared to planar field plates, which can only modulate the electric field in a single direction, slanted field plates can modulate the electric field in multiple directions, providing greater operational flexibility. Furthermore, slanted field plates typically have a larger surface area, which means that at the same electric field strength, the electric field can be distributed more evenly, avoiding the problem of excessive electric field concentration at a single point, thereby reducing the risk of electrical breakdown. The combination of slanted and planar field plates can significantly reduce the peak electric field of semiconductor devices, increase the breakdown voltage of semiconductor devices, and thus achieve higher voltage withstand specifications for semiconductor devices.

[0104] Figure 7 For the Figure 2 Another cross-sectional schematic diagram of a semiconductor device in the A1-A2 direction. Figure 7 As shown, it can be understood that according to other embodiments of the present application, optionally, at least part of the conductive unit 23 may also include only the inclined portion 23a inclined to the horizontal reference plane P, that is, at least part of the conductive unit 23 may be an inclined field plate inclined to the horizontal reference plane P. In some examples, when the conductive unit 23 is a inclined field plate, the angle θ between the conductive unit 23 and the horizontal reference plane P may be greater than 0° and less than 90°, or greater than 90° and less than 180°.

[0105] It can be understood that according to some other embodiments of the present application, optionally, at least part of the conductive unit 23 can also only include a planar portion 23b parallel to the horizontal reference plane P, that is, at least part of the conductive unit 23 can be a planar field plate parallel to the horizontal reference plane P.

[0106] like Figure 3 and Figure 7 As shown, the conductive unit 23 can be located on at least one step T and cover the slope surface between two adjacent steps T, thereby forming a slope field plate. Figure 3 、 Figure 5 and Figure 7 As shown, in other specific embodiments, the conductive unit 23 located on the i-th step T of the first side wall B1 and / or the second side wall B2 can also extend to the surface of the i+1-th step T, where i is a positive integer. The i-th step T and the i+1-th step T can be two adjacent steps. Along the thickness direction Z of the semiconductor device, the step T closest to the second dielectric layer 06 is the n-th step Tn. The conductive unit 23 located on the n-th step Tn of the first side wall B1 and / or the second side wall B2 can also extend to the surface of the first dielectric layer 05 close to the second dielectric layer 06. In this way, the conductive unit 23 can not only form a slanted field plate, but also form a planar field plate parallel to the horizontal reference plane P, thereby greatly reducing the peak electric field of the semiconductor device, increasing the breakdown voltage of the semiconductor device, and achieving a higher withstand voltage specification for the semiconductor device.

[0107] It should be noted that, in other embodiments, the semiconductor device may further include third to nth dielectric layers, where n is an integer and is greater than or equal to 3. Along the thickness direction of the semiconductor device, the third to nth dielectric layers may be located on a side of the second dielectric layer away from the first dielectric layer.

[0108] According to some embodiments of the present application, optionally, the plurality of conductive units 23 may extend in a single direction or in multiple directions.

[0109] like Figure 2As shown, according to some embodiments of the present application, the source 21 and the drain 22 may optionally be arranged along a first direction X, and the source 21 and the drain 22 may extend along a second direction Y. The first direction X intersects the second direction Y, and both the first direction X and the second direction Y may be perpendicular to the thickness direction of the semiconductor device. For example, the first direction X may be a row direction, and the second direction Y may be a column direction. The plurality of conductive units 23 may be arranged at intervals along the first direction X.

[0110] Figure 8 Another schematic top view of a semiconductor device provided in an embodiment of the present application. Figure 9 This is another schematic top view of a semiconductor device provided in an embodiment of the present application. Figure 8 and Figure 9 As shown, according to some other embodiments of the present application, optionally, at least part of the conductive units 23 may also be arranged in an array along the first direction X and the second direction Y.

[0111] Figure 10 For the Figure 8 A cross-sectional diagram of a semiconductor device in the B1-B2 direction. Figure 8 and Figure 10 As shown, in some embodiments, a plurality of conductive units 23 may be arranged at intervals on the steps T of the groove C, and at least some of the conductive units 23 may also be arranged in an array along the first direction X and the second direction Y.

[0112] According to some embodiments of the present application, optionally, the plurality of conductive units 23 of the semiconductor device may all be connected to the same potential.

[0113] In this way, the multiple conductive units are all connected to the same potential, which is equivalent to connecting the multiple conductive units in parallel, thereby reducing the parasitic inductance generated by the multiple conductive units.

[0114] In some specific embodiments, the plurality of conductive units 23 may optionally be at least partially electrically connected to any one of the gate 24, the source 21, or other target potential terminals (not shown). The target potential terminal may be another potential connection terminal other than the gate 24 and the source 21. The voltage value of the target potential terminal may be flexibly adjusted according to actual conditions, and this application does not limit this.

[0115] Furthermore, at least some of the conductive units 23 have open interfaces at one end, and at least some of the open ends of the conductive units 23 can be connected to any potential, such as the gate 24, the source 21, or other target potential terminals. It should be noted that the open ends of different conductive units 23 can be connected to the same potential or to different potentials, and this application does not limit this.

[0116] Alternatively, in other examples, at least a portion of the conductive unit 23 has open interfaces at both ends. Optionally, at least one end of the conductive unit 23 can be electrically connected to one end of another functional element (such as a resistor, capacitor, etc.) inside or outside the semiconductor device, and the other end of at least a portion of the conductive unit 23 and / or the other end of the functional element can be connected to a potential at any location. The potential at any location includes, but is not limited to, the gate 24, the source 21, or other target potential terminals, and this application does not limit this.

[0117] The at least partially conductive unit 23 can be connected in series or in parallel with a functional element inside or outside the semiconductor device, and this application does not limit this. For example, when the at least partially conductive unit 23 is connected in series with the functional element, one end of the at least partially conductive unit 23 is electrically connected to one end of the functional element, and the other end of the at least partially conductive unit 23 and the other end of the functional element can be connected to different potentials. For example, when the at least partially conductive unit 23 is connected in parallel with the functional element, one end of the at least partially conductive unit 23 is electrically connected to one end of the functional element, and the other end of the at least partially conductive unit 23 and the other end of the functional element can be connected to the same potential, and so on.

[0118] For example, in some examples, at least a portion of the conductive unit 23 can be electrically connected to the gate 24 via a connecting wire, so that at least a portion of the conductive unit 23 can serve as a field plate for the gate, i.e., a gate field plate. The connecting wire can be located in the same conductive layer as the conductive unit 23 or in another conductive layer, which is not limited in this application.

[0119] For example, in some examples, at least a portion of the conductive unit 23 can be electrically connected to the source 21 via a connecting wire, so that at least a portion of the conductive unit 23 can serve as a field plate for the source, i.e., a source field plate. The connecting wire can be located in the same conductive layer as the conductive unit 23, or in another conductive layer, which is not limited in this application.

[0120] Figure 11 This is another schematic top view of a semiconductor device provided in an embodiment of the present application. Figure 11 As shown, in some specific embodiments, optionally, the semiconductor device 20 may further include at least one connecting unit L1. The number of connecting units L1 may be one or more, and this application is not limited thereto. The at least one connecting unit L1 may be located in the same conductive layer as the multiple conductive units 23. The at least one connecting unit L1 may be used to electrically connect the multiple conductive units 23 to the gate 24. In some examples, the at least one connecting unit L1 may extend along the first direction X, the multiple conductive units 23 may extend along the second direction Y, and the at least one connecting unit L1 may be electrically connected to the multiple conductive units 23.

[0121] In this way, by electrically connecting multiple conductive units to the gate through at least one connecting unit, the voltage drop between the gate and the conductive units can be reduced, and at the same time, when a part of the conductive units is broken, other conductive units can work normally.

[0122] According to some embodiments of the present application, optionally, at least two conductive units 23 of the semiconductor device may be connected to different potentials. For example, at least two conductive units 23 may be connected to different electrodes or different potential terminals.

[0123] Figure 12 This is a schematic diagram of a circuit connection of a conductive unit in a semiconductor device provided in an embodiment of the present application. Figure 12 As shown, in some specific embodiments, a portion of the conductive units 23 can be electrically connected to the gate 24, and another portion of the conductive units 23 can be electrically connected to the source 21. The conductive units 23 electrically connected to the gate 24 can serve as the gate field plate, i.e., the gate field plate. The conductive units 23 electrically connected to the source 21 can serve as the source field plate, i.e., the source field plate.

[0124] According to some embodiments of the present application, optionally, at least part of the conductive unit 23 can also be used as a functional element inside the semiconductor device, such as a resistor, a capacitor and / or a diode.

[0125] Figure 13 Schematic diagrams of various circuit connections of conductive units in a semiconductor device provided in an embodiment of the present application. Figure 13 The semiconductor device is a transistor as an example. Figure 13 As shown, in some embodiments, optionally, the first end of the conductive unit 23 can be electrically connected to the gate 24 or the source 21, the second end of the conductive unit 23 can be electrically connected to the target potential end M, and the conductive unit 23 can be used as a resistor R.

[0126] like Figure 13 As shown, in some embodiments, optionally, the conductive unit 23 can form a PN junction, the first end of the conductive unit 23 can be electrically connected to the source 21, the second end of the conductive unit 23 can be electrically connected to the drain 22, and the conductive unit 23 can be used as a diode D.

[0127] like Figure 13 As shown, in some embodiments, optionally, one of the conductive units 23 can be electrically connected to the gate 24, and the other conductive unit 23 can be electrically connected to the source 21 or the drain 22. The two conductive units 23 can be used as a capacitor C and can be two plates of the capacitor C respectively.

[0128] According to some embodiments of the present application, the conductive units 23 may be made of the same material or different materials. For example, some conductive units 23 may be made of a material with a higher resistivity to form a resistor with a higher resistance.

[0129] like Figure 3 As shown, according to some embodiments of the present application, optionally, the semiconductor device 20 may be a transistor, such as a HEMT. The transistor may be an enhancement mode transistor or a depletion mode transistor, which is not limited in the present application.

[0130] Based on the same technical concept as the semiconductor device 20 provided in the first aspect, in a second aspect, the embodiment of the present application further provides a semiconductor device 30 , which differs from the semiconductor device 20 provided in the first aspect in that the gate of the semiconductor device 30 is separately provided, while multiple conductive units are intermittently provided in the same groove.

[0131] Figure 14 A schematic cross-sectional view of a semiconductor device provided in an embodiment of the present application. Figure 15 Another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 16 Another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 17 Another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0132] like Figures 14 to 17 As shown, the semiconductor device 30 may include a III-N structure layer 00, a source 21, a drain 22, a plurality of conductive units 23, a gate 24, a first dielectric layer 05, and a second dielectric layer 06. In some embodiments, the semiconductor device 30 may be a transistor, such as a high electron mobility transistor (HEMT), and the gate 24 may be used to control the on and off states of the transistor. The III-N structure layer may include at least two film layers of different III-N materials. A heterojunction may be formed in the III-N structure layer, acting as a channel of the semiconductor device (see Figure 14 (shown by the dotted line), such as a two-dimensional electron gas (2DEG) channel, so that the semiconductor device 20 can be used as a high electron mobility transistor (HEMT). The materials of the source 21, the drain 22, the conductive unit 23, and the gate 24 can all be conductive materials. The material of the conductive unit 23 and the material of the gate 24 can be the same or different, and this application is not limited to this. The first dielectric layer 05 can be a single insulating material or a multi-layer composite insulating material. The second dielectric layer 06 can be a single insulating material or a multi-layer composite insulating material. Insulating materials include but are not limited to silicon nitride or silicon dioxide.

[0133] Along the thickness direction Z of the semiconductor device, the first dielectric layer 05 having a thickness of 1000 Å may be located between the III-N structure layer 00 and the second dielectric layer 06. The source 21 and the drain 22 may both be in electrical contact with the 2DEG of the heterojunction, such as an ohmic contact.

[0134] like Figures 14 to 17 As shown, in some embodiments, the gate 24 may be covered by the first dielectric layer 05, or the gate 24 may be located in a first groove C1 defined in the first dielectric layer 05 and covered by the second dielectric layer 06. The first dielectric layer 05 or the second dielectric layer 06 may further define a second groove C2, wherein the second groove C2 has a first sidewall B1 close to the source 21 and a second sidewall B2 close to the drain 22.

[0135] A plurality of conductive units 23 are intermittently arranged at the bottom of the second groove C2 and / or on at least one side wall of the first side wall B1 and the second side wall B2, and are discontinuous in the second groove C2. Among them, at least part of the conductive units 23 are used as field plates for adjusting the electric field distribution. That is, only part of the conductive units 23 can be used as field plates, or all of the conductive units 23 can be used as field plates. It should be noted that the number, position and width of the plurality of conductive units 23 can be flexibly adjusted according to actual conditions, and this application does not limit this. In addition, the spacing between any two adjacent conductive units 23 can be equal spacing or unequal spacing, and this application does not limit this.

[0136] In the semiconductor device 30 provided in the embodiment of the present application, on the one hand, at least part of the conductive units can be used as field plates, which is beneficial to reducing the peak electric field of the semiconductor device and increasing the breakdown voltage of the semiconductor device, thereby achieving a higher voltage withstand specification of the semiconductor device; on the other hand, multiple conductive units arranged at intervals replace the original single large-area metal covering, which is beneficial to reducing the overlapping area between the conductive units and other conductive elements (such as electrodes or electrode interconnections), thereby facilitating the reduction of parasitic capacitance between the conductive units and other conductive elements (such as electrodes or electrode interconnections), and further facilitating the improvement of the switching speed of the semiconductor device, shortening the response time of the semiconductor device, and reducing power consumption; on the other hand, as the area of ​​the conductive units decreases, it is beneficial to reduce the risk of short circuits caused by the introduction of particles or dust into the conductive units during the production process, thereby improving the yield of the semiconductor device; on the other hand, the number, position and width of the multiple conductive units can be flexibly adjusted according to actual conditions, which is beneficial to flexible adjustment of parasitic capacitance.

[0137] like Figure 14 As shown, according to some embodiments of the present application, the gate 24 may optionally include a sub-gate 24a. Alternatively, as shown in FIG. Figure 15As shown, the gate 24 may also include multiple sub-gates 24a. When the gate 24 includes multiple sub-gates 24a, the multiple sub-gates 24a are intermittently disposed on the surface of the III-N structure layer 00 near the first dielectric layer 05 or intermittently disposed in the first groove C1. It should be noted that along the thickness direction Z of the semiconductor device, when there is another film layer between the III-N structure layer 00 and the first dielectric layer 05, such as an insulator layer 07, the multiple sub-gates 24a can be intermittently disposed on the surface of the insulator layer 07 near the first dielectric layer 05.

[0138] In this way, the gate 24 is divided into a plurality of sub-gates 24a arranged at intervals, which can reduce the parallel resistance of the gate, reduce switching delay, increase switching speed, reduce conduction loss, and improve device efficiency.

[0139] In some specific embodiments, both the first sidewall B1 and the second sidewall B2 have no steps, and the plurality of conductive units 23 are intermittently disposed at the bottom of the second groove C2 and / or on at least one of the first sidewall B1 and the second sidewall B2 that is inclined relative to a horizontal reference plane P, where the horizontal reference plane P is perpendicular to the thickness direction Z of the semiconductor device. That is, the plurality of conductive units 23 can be intermittently disposed at the bottom of the second groove C2 or on at least one of the first sidewall B1 and the second sidewall B2. Alternatively, a portion of the conductive units 23 can be intermittently disposed at the bottom of the second groove C2, while another portion of the conductive units 23 can be intermittently disposed on at least one of the first sidewall B1 and the second sidewall B2, although this application is not limited thereto.

[0140] like Figure 16 or Figure 17 As shown, in other specific embodiments, at least one of the first sidewall B1 and the second sidewall B2 includes n steps T, where n ≥ 1 and is an integer. The value of n can be flexibly adjusted according to actual conditions and is not limited in this application. At least a portion of the conductive unit 23 is intermittently provided on the steps T of at least one of the first sidewall B1 and the second sidewall B2, and is discontinuous on the steps T of at least one sidewall.

[0141] like Figures 14 to 17 As shown, for example, among the plurality of conductive units 23, a first portion of the conductive units 23 may be disposed at the bottom of the second groove C2, a second portion of the conductive units 23 may be disposed on the first sidewall B1, and a third portion of the conductive units 23 may be disposed on the second sidewall B2. Each portion of the conductive units 23 may include one or more conductive units 23.

[0142] Similar to the semiconductor device 20 provided in the first aspect, Figures 14 to 17As shown, in the semiconductor device 30, at least a portion of the conductive unit 23 may be a slanted field plate x1 that is inclined relative to a horizontal reference plane P, and the horizontal reference plane P is perpendicular to the thickness direction Z of the semiconductor device. Alternatively, at least a portion of the conductive unit 23 may be a planar field plate x2 that is parallel to the horizontal reference plane P. Alternatively, at least a portion of the conductive unit 23 may include an inclined portion that is inclined relative to the horizontal reference plane P and a planar portion that is parallel to the horizontal reference plane P, with the inclined portion serving as the slanted field plate x1 and the planar portion serving as the planar field plate x2.

[0143] It should be noted that other structures and functions of the semiconductor device 30 are the same as or similar to those of the semiconductor device 20 , and are not described again for the sake of brevity.

[0144] Based on the same technical concept as the semiconductor device 20 provided in the first aspect, the present application also provides a method for manufacturing a semiconductor device. This method can be used to manufacture the semiconductor device 20 provided in the above embodiment. Please see the following embodiment.

[0145] Figure 18 A schematic flow chart of a method for preparing a semiconductor device according to an embodiment of the present application. Figure 18 As shown, the method for preparing a semiconductor device provided in an embodiment of the present application may include the following steps S181 to S185.

[0146] S181: Provide or form a semiconductor bottom structure.

[0147] like Figure 2 and Figure 3 As shown, the semiconductor bottom structure may include at least a III-N structure layer 00, a source electrode 21, and a drain electrode 22. The III-N structure layer may include at least two film layers of different III-N materials, and a heterojunction may be formed in the III-N structure layer to serve as a channel of the semiconductor device (see Figure 3 The source 21 and the drain 22 can both be in electrical contact with the 2DEG of the heterojunction, such as an ohmic contact.

[0148] S182: forming a first dielectric layer on the III-N structure layer.

[0149] like Figure 3 As shown, a first dielectric layer 05 may be formed on the III-N structure layer 00. The first dielectric layer 05 may be a single insulating material or a multi-layer composite insulating material.

[0150] S183: forming a groove on the first dielectric layer, wherein the groove has a first sidewall close to the source and a second sidewall close to the drain.

[0151] like Figure 3As shown, a groove C can be formed in the first dielectric layer 05. The groove C may or may not penetrate the first dielectric layer 05, and this application does not limit this. The groove C has a first sidewall B1 close to the source 21 and a second sidewall B2 close to the drain 22. The first sidewall B1 and the second sidewall B2 may have a step or no step, and this application does not limit this.

[0152] S184: forming a discontinuously arranged gate and at least one conductive unit in the groove.

[0153] like Figure 3 As shown, a discontinuous gate 24 and at least one conductive unit 23 can be formed in the groove C. The gate 24 at least partially covers the bottom of the groove C, and the at least one conductive unit 23 can be provided on at least one of the first sidewall B1 and the second sidewall B2. The gate 24 and the at least one conductive unit 23 are discontinuous. At least some of the conductive units are used as field plates to adjust the electric field distribution.

[0154] S185: forming a second dielectric layer on a side of the first dielectric layer away from the III-N structure layer.

[0155] like Figure 3 As shown, a second dielectric layer 06 may be formed on a side of the first dielectric layer 05 away from the III-N structure layer 00 . The second dielectric layer 06 may at least cover the groove C, the gate 24 and the at least one conductive unit 23 .

[0156] In the semiconductor device obtained by the method for preparing a semiconductor device provided in the embodiment of the present application, on the one hand, at least part of the conductive units can be used as field plates, which is beneficial to reducing the peak electric field of the semiconductor device and increasing the breakdown voltage of the semiconductor device, thereby achieving a higher voltage withstand specification of the semiconductor device; on the other hand, the gates and at least one conductive unit arranged at intervals replace the original single large-area metal covering, which is beneficial to reducing the overlapping area between the conductive unit and other conductive elements (such as electrodes or electrode interconnections), thereby facilitating the reduction of the parasitic capacitance between the conductive unit and other conductive elements (such as electrodes or electrode interconnections), and further facilitating the improvement of the switching speed of the semiconductor device, shortening the response time of the semiconductor device, and reducing power consumption; on the other hand, as the area of ​​the conductive unit is reduced, it is beneficial to reduce the risk of short circuit caused by the introduction of particles or dust into the conductive unit during the production process, thereby improving the yield of the semiconductor device; on the other hand, the number, position and width of the multiple conductive units can be flexibly adjusted according to actual conditions, which is beneficial to flexible adjustment of the parasitic capacitance.

[0157] Figure 19 This is a schematic diagram of a process of S184 in the method for preparing a semiconductor device according to an embodiment of the present application. Figure 19As shown, according to some embodiments of the present application, optionally, S184: forming a discontinuously arranged gate and at least one conductive unit in the groove may include the following steps:

[0158] A conductive layer is deposited on the bottom and at least one sidewall of the groove, and the conductive layer is etched into discontinuously arranged gates and at least one conductive unit.

[0159] like Figure 19 As shown, for example, a covering conductive layer 160 may be first deposited in the groove C. Then, the conductive layer 160 is etched by an etching process to form discontinuously arranged gates 24 and at least one conductive unit 23 .

[0160] and Figure 19 Different from the illustrated embodiment, according to other embodiments of the present application, optionally, S184: forming a discontinuously arranged gate and at least one conductive unit in the groove may include the following steps:

[0161] A mask is used to cover a part of the groove, and discontinuously arranged gates and at least one conductive unit are deposited on the bottom of the groove and on the area of ​​at least one sidewall not covered by the mask.

[0162] Specifically, in some embodiments, before depositing the conductive unit, a mask can be used to block part of the area in the groove (such as the gap area between the gate and at least one conductive unit), and then the intermittently set gate and at least one conductive unit are deposited in the area of ​​the groove that is not blocked by the mask.

[0163] like Figure 4 、 Figure 5 or Figure 6 As shown, according to some embodiments of the present application, optionally, the semiconductor bottom structure may further include an insulator layer 07. Along the thickness direction Z of the semiconductor device, the insulator layer 07 may be located on the side of the barrier layer 04 away from the channel layer 03, that is, the insulator layer 07 may be located between the barrier layer 04 and the first dielectric layer 05.

[0164] Accordingly, S182: forming a first dielectric layer on the III-N structure layer may include the following steps:

[0165] forming an insulator layer on the III-N structure layer;

[0166] A first dielectric layer is formed on a side of the insulator layer away from the III-N structure layer.

[0167] It should be noted that Figure 18 The manufacturing method of the semiconductor device shown has the same or corresponding technical features as the semiconductor device 20 of the above embodiment, and both can achieve the same technical effects. For the sake of brevity, they will not be described here in detail.

[0168] Based on the same technical concept as the semiconductor device 30 provided in the second aspect, the present application also provides a method for preparing a semiconductor device. The preparation method can be used to prepare Figure 14 and Figure 15 The above embodiment provides a semiconductor device 30. Please refer to the following embodiments.

[0169] Figure 20 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. Figure 21 A schematic diagram of a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 20 As shown, the method for preparing a semiconductor device provided in an embodiment of the present application may include the following steps S201 to S204.

[0170] S201: providing or forming a semiconductor bottom structure.

[0171] like Figure 14 、 Figure 15 and Figure 21 As shown, the semiconductor bottom structure may include at least a III-N structure layer 00, a source electrode 21, and a drain electrode 22. The III-N structure layer may include at least two film layers of different III-N materials, and a heterojunction may be formed in the III-N structure layer to serve as a channel of the semiconductor device (see Figure 3 The source 21 and the drain 22 can both be in electrical contact with the 2DEG of the heterojunction, such as an ohmic contact.

[0172] S202 : forming a gate and a first dielectric layer on the III-N structure layer in sequence, wherein the first dielectric layer covers the gate.

[0173] like Figure 14 、 Figure 15 and Figure 21 As shown, a gate 24 may be first formed on the III-N structure layer 00, and then a first dielectric layer 05 may be formed on the III-N structure layer 00. The first dielectric layer 05 may cover the gate 24. It should be noted that when other film layers, such as an insulator layer 07, are included between the III-N structure layer 00 and the first dielectric layer 05, the insulator layer 07 may be first formed on the III-N structure layer 00, and then the gate 24 may be formed on the insulator layer 07. Finally, the first dielectric layer 05 may be formed on the insulator layer 07. The first dielectric layer 05 may cover the gate 24.

[0174] S203 : Opening a second groove on the first dielectric layer, the second groove having a first sidewall close to the source and a second sidewall close to the drain.

[0175] like Figure 14、 Figure 15 and Figure 21 As shown, a second groove C2 can be opened on the first dielectric layer 05, and the second groove C2 has a first sidewall B1 close to the source 21 and a second sidewall B2 close to the drain 22. The first sidewall B1 and the second sidewall B2 may have steps or no steps, which is not limited in this application.

[0176] S204: forming a plurality of discontinuously arranged conductive units on the bottom and / or at least one sidewall of the second groove, wherein the plurality of conductive units are discontinuous in the second groove, and at least some of the conductive units are used as field plates for adjusting electric field distribution.

[0177] like Figure 14 、 Figure 15 and Figure 21 As shown, a plurality of conductive units 23 can be formed discontinuously on the bottom and / or at least one sidewall of the second groove C2. The plurality of conductive units 23 are discontinuous in the second groove C2, and at least some of the conductive units 23 can be used as field plates to adjust the electric field distribution. The process of S204 is similar to that of S184 and will not be repeated here for the sake of brevity.

[0178] It should be noted that Figure 20 The manufacturing method of the semiconductor device shown has the same or corresponding technical features as the semiconductor device 30 of the above embodiment, and both can achieve the same technical effects. For the sake of brevity, they will not be described here in detail.

[0179] Based on the same technical concept as the semiconductor device 30 provided in the second aspect, the present application also provides a method for preparing a semiconductor device. The preparation method can be used for Figure 16 and Figure 17 The semiconductor device 30 provided in the above embodiment is prepared as shown in the following embodiment.

[0180] Figure 22 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. Figure 23 A schematic diagram of a process of manufacturing a semiconductor device according to an embodiment of the present application. Figure 22 As shown, the method for preparing a semiconductor device provided in an embodiment of the present application may include the following steps S221 to S225.

[0181] S221: Provide or form a semiconductor bottom structure.

[0182] like Figure 16 、 Figure 17 and Figure 23As shown, the semiconductor bottom structure may include at least a III-N structure layer 00, a source electrode 21, and a drain electrode 22. The III-N structure layer may include at least two film layers of different III-N materials, and a heterojunction may be formed in the III-N structure layer to serve as a channel of the semiconductor device (see Figure 3 The source 21 and the drain 22 can both be in electrical contact with the 2DEG of the heterojunction, such as an ohmic contact.

[0183] S222: forming a gate and a first dielectric layer on the III-N structure layer in sequence, wherein the first dielectric layer covers the gate; or forming a first dielectric layer on the III-N structure layer, opening a first groove in the first dielectric layer, and forming a gate in the first groove.

[0184] like Figure 16 、 Figure 17 and Figure 23 As shown, a gate 24 may be first formed on the III-N structure layer 00, and then a first dielectric layer 05 may be formed on the III-N structure layer 00. The first dielectric layer 05 may cover the gate 24. It should be noted that when other film layers, such as an insulator layer 07, are included between the III-N structure layer 00 and the first dielectric layer 05, the insulator layer 07 may be first formed on the III-N structure layer 00, and then the gate 24 may be formed on the insulator layer 07. Then, the first dielectric layer 05 may be formed on the insulator layer 07. The first dielectric layer 05 may cover the gate 24.

[0185] Alternatively, a first dielectric layer 05 is formed on the III-N structure layer 00 or the insulator layer 07 , a first groove C1 is opened in the first dielectric layer 05 , and the gate 24 is formed in the first groove C1 .

[0186] S223 : forming a second dielectric layer on a side of the first dielectric layer away from the III-N structure layer.

[0187] like Figure 16 、 Figure 17 and Figure 23 As shown, a second dielectric layer 06 may be formed on a side of the first dielectric layer 05 away from the III-N structure layer 00 .

[0188] S224: Opening a second groove in the second dielectric layer, the second groove having a first sidewall close to the source and a second sidewall close to the drain.

[0189] like Figure 16 、 Figure 17 and Figure 23As shown, a second groove C2 can be opened in the second dielectric layer 06, and the second groove C2 has a first sidewall B1 close to the source 21 and a second sidewall B2 close to the drain 22. The first sidewall B1 and the second sidewall B2 may have steps or no steps, which is not limited in this application.

[0190] S225: forming a plurality of discontinuously arranged conductive units on the bottom and / or at least one sidewall of the second groove, wherein the plurality of conductive units are discontinuous in the second groove, and at least some of the conductive units are used as field plates for adjusting electric field distribution.

[0191] like Figure 16 、 Figure 17 and Figure 23 As shown, a plurality of conductive units 23 can be formed discontinuously on the bottom and / or at least one sidewall of the second groove C2. The plurality of conductive units 23 are discontinuous in the second groove C2, and at least some of the conductive units 23 can be used as field plates to adjust the electric field distribution. The process of S225 is similar to that of S184 and is not repeated here for the sake of brevity.

[0192] It should be noted that Figure 20 The manufacturing method of the semiconductor device shown has the same or corresponding technical features as the semiconductor device 30 of the above embodiment, and both can achieve the same technical effects. For the sake of brevity, they will not be described here in detail.

[0193] It should be understood that the cross-sectional structures and top-view structures of the semiconductor devices provided in the drawings of the embodiments of the present application are merely examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application may be combined with each other unless there is any contradiction.

[0194] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments described above in accordance with the present application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

[0195] Those skilled in the art should understand that the above embodiments are illustrative rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to identify names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The fact that certain technical features appear in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A semiconductor device comprising a III-N structure layer, a source electrode, a drain electrode, a gate electrode, at least one conductive unit, a first dielectric layer, and a second dielectric layer; Along the thickness direction of the semiconductor device, a first dielectric layer having a thickness is located between the III-N structure layer and the second dielectric layer; The first dielectric layer is provided with a groove, wherein the groove has a first sidewall close to the source electrode and a second sidewall close to the drain electrode; The gate and the at least one conductive unit are intermittently arranged in the groove, the gate at least partially covers the bottom of the groove, the at least one conductive unit is arranged on at least one sidewall of the first sidewall and the second sidewall, and the gate and the at least one conductive unit are discontinuous, wherein at least part of the conductive unit is used to serve as a field plate for adjusting the electric field distribution; The second dielectric layer at least covers the groove, the gate and the at least one conductive unit.

2. The semiconductor device according to claim 1, wherein The first sidewall and the second sidewall have no steps, and the at least one conductive unit is arranged on at least one of the first sidewall and the second sidewall inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to the thickness direction of the semiconductor device.

3. The semiconductor device according to claim 1, wherein At least one of the first sidewall and the second sidewall comprises n steps, where n is an integer and is greater than or equal to 1; The semiconductor device includes a plurality of conductive units, which are intermittently arranged on the step of the at least one sidewall and are discontinuous on the step of the at least one sidewall.

4. The semiconductor device according to claim 3, wherein The first side wall includes n1 steps, the second side wall includes n2 steps or has no steps, n1≥1, n2≥1, and n1 and n2 are both integers; The plurality of conductive units are discontinuously arranged on n1 steps of the first sidewall, and / or the plurality of conductive units are discontinuously arranged on n2 steps of the second sidewall.

5. The semiconductor device according to claim 3, wherein The number of steps of the first side wall is the same as or different from the number of steps of the second side wall. The semiconductor device according to claim 1 , wherein: The III-N structure layer includes at least a channel layer and a barrier layer, wherein a heterojunction is formed between the channel layer and the barrier layer to serve as a channel of the device; Along the thickness direction of the semiconductor device, the source electrode and the drain electrode are located between the channel layer and the first dielectric layer, and both the source electrode and the drain electrode form an ohmic electrical contact with the heterojunction.

7. The semiconductor device according to claim 6, wherein The semiconductor device further includes a substrate, and the III-N structure layer further includes a buffer layer. Along the thickness direction of the semiconductor device, the buffer layer is located on a side of the channel layer away from the barrier layer, and the substrate is located on a side of the buffer layer away from the channel layer. The buffer layer, the channel layer, and the barrier layer are formed by the composition difference between the III-N structure layers. A heterojunction is formed at the interface between the channel layer and the barrier layer, and a 2DEG channel is formed in the heterojunction.

8. The semiconductor device according to claim 1, wherein The groove penetrates the first dielectric layer, and the gate covers at least the bottom of the groove and extends at least to the step between the first sidewall and the second sidewall.

9. The semiconductor device according to claim 1, wherein At least part of the conductive unit is a slanted field plate inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to the thickness direction of the semiconductor device; Alternatively, at least part of the conductive units are planar field plates parallel to the horizontal reference plane; Alternatively, at least part of the conductive unit includes an inclined portion inclined to the horizontal reference plane and a planar portion parallel to the horizontal reference plane, the inclined portion is used as a slanted field plate, and the planar portion is used as a planar field plate.

10. The semiconductor device according to claim 9, wherein When the conductive unit is a slanted field plate, the angle between the conductive unit and the horizontal reference plane is greater than 0° and less than 90°, or greater than 90° and less than 180°.

11. The semiconductor device according to claim 3, wherein The conductive unit is located on at least one step and covers the slope surface between two adjacent steps.

12. The semiconductor device according to claim 11, wherein The conductive unit located on the i-th step of the first sidewall and / or the second sidewall further extends to the surface of the i+1-th step, where i≤n-1 and is a positive integer; Along the thickness direction of the semiconductor device, the step closest to the second dielectric layer is the nth step; the conductive unit located on the nth step of the first sidewall and / or the second sidewall also extends to the surface of the first dielectric layer close to the second dielectric layer.

13. The semiconductor device according to claim 1, wherein The source electrode and the drain electrode are arranged along a first direction, and the source electrode and the drain electrode extend along a second direction, the first direction intersects the second direction, and the first direction and the second direction are both perpendicular to the thickness direction of the semiconductor device; The semiconductor device includes a plurality of conductive units, and the plurality of conductive units are arranged at intervals along the first direction, or at least some of the conductive units are arranged in an array along the first direction and the second direction.

14. The semiconductor device according to claim 13, wherein The multiple conductive units of the semiconductor device are all connected to the same potential.

15. The semiconductor device according to claim 14, wherein The plurality of conductive units are at least partially electrically connected to any one of the gate, the source, or other target potential terminals.

16. The semiconductor device according to claim 15, wherein The semiconductor device also includes at least one connecting unit, the at least one connecting unit extends along a first direction, the multiple conductive units extend along a second direction, the at least one connecting unit and the multiple conductive units are located in the same conductive layer, and the at least one connecting unit is used to electrically connect the multiple conductive units to the gate.

17. The semiconductor device according to claim 1, wherein At least one end of the conductive unit is open, and the open end is connected to a potential at any position; or At least part of the conductive unit has open interfaces at both ends, one end of at least part of the conductive unit is electrically connected to one end of a functional element inside or outside the semiconductor device, and the other end of at least part of the conductive unit and / or the other end of the functional element is connected to a potential at any position.

18. The semiconductor device according to claim 1, wherein At least two conductive units of the semiconductor device are connected to different potentials.

19. The semiconductor device according to claim 18, wherein A portion of the conductive units is electrically connected to the gate, and another portion of the conductive units is electrically connected to the source.

20. The semiconductor device according to claim 1, wherein At least part of the conductive units are used as functional elements inside the semiconductor device.

21. The semiconductor device according to claim 20, wherein A first end of the conductive unit is electrically connected to the gate or the source, a second end of the conductive unit is electrically connected to a target potential end, and the conductive unit is used as a resistor; And / or, the conductive unit forms a PN junction, a first end of the conductive unit is electrically connected to the source, a second end of the conductive unit is electrically connected to the drain, and the conductive unit is used to serve as a diode; And / or, one of the conductive units is electrically connected to the gate, and the other conductive unit is electrically connected to the source or the drain, and the two conductive units are used as capacitors.

22. A semiconductor device comprising a III-N structure layer, a source electrode, a drain electrode, a gate electrode, a plurality of conductive units, a first dielectric layer, and a second dielectric layer; Along the thickness direction of the semiconductor device, a first dielectric layer having a thickness is located between the III-N structure layer and the second dielectric layer; The gate is covered by the first dielectric layer, or the gate is located in a first groove defined in the first dielectric layer and is covered by the second dielectric layer; The first dielectric layer or the second dielectric layer further defines a second groove, wherein the second groove has a first sidewall close to the source electrode and a second sidewall close to the drain electrode; The plurality of conductive units are intermittently arranged on the bottom and / or at least one sidewall of the second groove and are discontinuous in the second groove, wherein: At least part of the conductive unit is used as a field plate for adjusting the electric field distribution.

23. The semiconductor device according to claim 22, wherein The gate includes one sub-gate or multiple sub-gates; When the gate includes a plurality of sub-gates, the plurality of sub-gates are discontinuously arranged on a surface of the III-N structure layer close to the first dielectric layer or discontinuously arranged in the first groove.

24. The semiconductor device according to claim 22, wherein Both the first side wall and the second side wall have no steps, and the multiple conductive units are discontinuously arranged at the bottom of the second groove and / or on at least one side wall of the first side wall and the second side wall inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to the thickness direction of the semiconductor device.

25. The semiconductor device according to claim 22, wherein At least one of the first sidewall and the second sidewall comprises n steps, where n is an integer and is greater than or equal to 1; At least part of the conductive unit is discontinuously disposed on the step of the at least one side wall and is discontinuous on the step of the at least one side wall.

26. The semiconductor device according to claim 22, wherein Among the plurality of conductive units, a first portion of the conductive units is disposed at the bottom of the second groove, a second portion of the conductive units is disposed on the first sidewall, and a third portion of the conductive units is disposed on the second sidewall.

27. The semiconductor device according to claim 22, wherein At least part of the conductive unit is a slanted field plate inclined to a horizontal reference plane, and the horizontal reference plane is perpendicular to the thickness direction of the semiconductor device; Alternatively, at least part of the conductive units are planar field plates parallel to the horizontal reference plane; Alternatively, at least part of the conductive unit includes an inclined portion inclined to the horizontal reference plane and a planar portion parallel to the horizontal reference plane, the inclined portion is used as a slanted field plate, and the planar portion is used as a planar field plate.

28. A method for preparing a semiconductor device, comprising: Providing or forming a semiconductor bottom structure, wherein the semiconductor bottom structure comprises at least a III-N structure layer, a source electrode, and a drain electrode; forming a first dielectric layer on the III-N structure layer; A groove is formed in the first dielectric layer, wherein the groove has a first sidewall close to the source electrode and a second sidewall close to the drain electrode; A gate and at least one conductive unit are formed in the groove, wherein the gate at least partially covers the bottom of the groove, the at least one conductive unit is arranged on at least one of the first sidewall and the second sidewall, and the gate and the at least one conductive unit are discontinuous, and at least part of the conductive unit is used to serve as a field plate for adjusting the electric field distribution; A second dielectric layer is formed on a side of the first dielectric layer away from the III-N structure layer.

29. The preparation method according to claim 28, wherein A gate and at least one conductive unit are formed intermittently in the groove, comprising: A conductive layer is deposited on the bottom and at least one side wall of the groove, and the conductive layer is etched into intermittently arranged gates and at least one conductive unit; or, a mask is used to block part of the groove, and intermittently arranged gates and at least one conductive unit are deposited on the bottom and at least one side wall of the groove in areas not blocked by the mask.

30. The preparation method according to claim 28, wherein The semiconductor bottom structure further includes an insulator layer, and along the thickness direction of the semiconductor device, the insulator layer is located between the III-N structure layer and the first dielectric layer; forming a first dielectric layer on the III-N structure layer, comprising: forming an insulator layer on the III-N structure layer; A first dielectric layer is formed on a side of the insulator layer away from the III-N structure layer, wherein the first dielectric layer covers the source electrode, the drain electrode and the insulator layer.

31. A method for preparing a semiconductor device, comprising: Providing or forming a semiconductor bottom structure, wherein the semiconductor bottom structure comprises at least a III-N structure layer, a source electrode, and a drain electrode; forming a gate and a first dielectric layer on the III-N structure layer in sequence, wherein the first dielectric layer covers the gate; A second groove is formed in the first dielectric layer, wherein the second groove has a first sidewall close to the source electrode and a second sidewall close to the drain electrode; A plurality of discontinuously arranged conductive units are formed on the bottom and / or at least one sidewall of the second groove, wherein the plurality of conductive units are discontinuous in the second groove, and at least some of the conductive units are used as field plates for adjusting electric field distribution.

32. A method for preparing a semiconductor device, comprising: Providing or forming a semiconductor bottom structure, wherein the semiconductor bottom structure comprises at least a III-N structure layer, a source electrode, and a drain electrode; forming a gate and a first dielectric layer on the III-N structure layer in sequence, wherein the first dielectric layer covers the gate; or forming a first dielectric layer on the III-N structure layer, defining a first groove in the first dielectric layer, and forming the gate in the first groove; forming a second dielectric layer on a side of the first dielectric layer away from the III-N structure layer; A second groove is formed in the second dielectric layer, wherein the second groove has a first sidewall close to the source electrode and a second sidewall close to the drain electrode; A plurality of discontinuously arranged conductive units are formed on the bottom and / or at least one sidewall of the second groove, wherein the plurality of conductive units are discontinuous in the second groove, and wherein at least some of the conductive units are used as field plates for adjusting electric field distribution.

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