Composite gate dielectric layer for MISHEMT device, depletion mode MISHEMT device and preparation method of depletion mode MISHEMT device

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a composite gate dielectric layer for an MISHEMT device, a depletion mode MISHEMT device and a preparation method of the depletion mode MISHEMT device. The composite gate dielectric is prepared at normal temperature through an electron cyclotron resonance physical vapor deposition coating technology, and the composite gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer which are adjacent to each other; the first gate dielectric layer is made of Si3N4, and the second gate dielectric layer is made of Ta2O5. According to the method, electron cyclotron resonance (ECR) coating equipment is used, the ECR effect and the high energy density of ECR plasma are utilized, reaction gas is fully ionized and uniformly deposited, the uniform, compact and defect-free Si3N4 film is formed at the normal temperature, and the problem of Ga atom diffusion in high-temperature deposition is avoided; the second layer is made of a Ta2O5 material, the dielectric constant is high, the thickness of an equivalent oxide layer can be effectively reduced, the gate capacitance density is improved, and the driving capacity of the device is enhanced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to a composite gate dielectric layer for a MISHEMT device, a depletion-type MISHEMT device and a preparation method thereof. Background Art

[0002] As a third-generation semiconductor, gallium nitride (GaN) high-electron-mobility-transistor (HEMT) has been widely studied due to its advantages such as high breakdown voltage, high electron mobility, and high electron saturation velocity.

[0003] However, GaN-based HEMT devices face the challenge of lacking a good heterojunction substrate during the growth process, which easily leads to the formation of a certain concentration of body traps in the buffer layer and barrier layer, as well as the formation of surface traps on the surface of the barrier layer. This causes GaN-based HEMT devices to have large gate leakage current, threshold hysteresis and other reliability issues. To solve this problem, an insulating dielectric material is usually inserted between the gate and the barrier layer to produce an AlGaN / GaN metal-insulator-semiconductor high-electron-mobility-transistor (MISHEMT) device. Therefore, for MISHEMT, the quality of the gate dielectric layer, the dielectric material and the interface quality with the GaN contact layer are particularly important for device reliability.

[0004] Currently, there are many types of AlGaN / GaN MISHEMT gate dielectrics, such as SiN, SiO2, Al2O3, and TaN. When selecting a gate dielectric material, it's important to consider not only the material's inherent properties, such as a large bandgap, a large conduction band step, a high dielectric constant, and a high-quality MIS interface, but also the stability and maturity of the material's preparation process.

[0005] Gate dielectrics are typically grown using chemical vapor deposition (CVD) methods, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), and ionized plasma chemical vapor deposition (ICPCVD). LPCVD is currently the most common method for growing Si3N4. However, compared to traditional PECVD-grown dielectric layers, LPCVD-grown Si3N4 insulating materials offer superior film quality due to their mature process, high growth temperature (780°C), low impurity levels, and lack of ion bombardment damage. This makes them a relatively advantageous choice for use as gate dielectrics in HEMT devices. However, during high-temperature Si3N4 growth, Ga atoms in the GaN layer diffuse outward, resulting in Ga vacancies and dangling bonds on the GaN surface, creating leakage paths. Therefore, developing a novel gate dielectric fabrication method to avoid Ga atom diffusion during high-temperature deposition has become a critical challenge in the semiconductor industry. Summary of the Invention

[0006] Technical issues

[0007] To solve the above problems, the present invention provides a Ta2O5 / Si3N4 composite gate dielectric layer prepared at room temperature using electron cyclotron resonance physical vapor deposition coating technology. This preparation method avoids the diffusion of Ga atoms during high-temperature deposition.

[0008] Technical Solution

[0009] A first aspect of the present invention provides a composite gate dielectric layer for a MISHEMT device, wherein the composite gate dielectric is prepared at room temperature by electron cyclotron resonance physical vapor deposition (ECR-PVD) technology, wherein the composite gate dielectric layer includes an adjacent first gate dielectric layer and a second gate dielectric layer; the material of the first gate dielectric layer is Si3N4, and the material of the second gate dielectric layer is Ta2O5.

[0010] In some embodiments, in an electron cyclotron resonance physical vapor deposition coating system, the process conditions for depositing Si3N4 are: RF source power is 300-700W, microwave power is 300-700W, preferably 400W; Ar flow rate is 20-60sccm, preferably 30sccm; N2 flow rate is 7-12sccm, preferably 9sccm.

[0011] In some embodiments, in an electron cyclotron resonance physical vapor deposition coating system, the process conditions for depositing Ta2O5 are: RF source power is 400-700W, microwave power is 300-600W, preferably 550W; Ar flow rate is 30-50sccm, preferably 40sccm; O2 flow rate is 5-10sccm, preferably 7sccm.

[0012] A second aspect of the present invention provides a depletion-mode MISHEMT device, comprising: a substrate; a buffer layer formed on the substrate; a channel layer formed on the buffer layer; a barrier layer formed on the channel layer; a cap layer formed on the barrier layer; a drain and a source formed on the barrier layer; a composite gate dielectric layer as described in any one of the above, the composite gate dielectric layer being formed on the cap layer; and a gate formed on the composite gate dielectric layer.

[0013] In some embodiments, the thickness of the substrate is 0.1-10 mm; the total thickness of the channel layer and the barrier layer formed on the channel layer is 0.1-10 μm; the thickness of the cap layer is 0.1-1 μm; and the total thickness of the composite gate dielectric layer is 15-30 nm.

[0014] In some embodiments, the material of the buffer layer is high-resistance GaN; the material of the channel layer is one or more of AlN, GaN or GaAs; the material of the barrier layer is one or more of AlGaN, AlInN, GaAs or AlN; and the cap layer is a p-type semiconductor whose material is GaN or AlGaN.

[0015] A third aspect of the present invention provides a method for preparing a depletion-mode MISHEMT device as described in any of the above items, comprising the following steps: S1, substrate preparation; S2, epitaxial structure growth; S3, composite gate dielectric layer preparation; S4, mesa etching and source and drain ohmic contact electrode preparation; S5, gate electrode preparation.

[0016] In some embodiments, in step S2, the specific steps of growing the epitaxial structure are: sequentially growing a buffer layer, a channel layer, a barrier layer, and a cap layer on the substrate by metal organic chemical vapor deposition.

[0017] In some embodiments, in step S4, the specific steps of mesa etching and preparation of ohmic contact electrodes in the source and drain regions are: isolating the device active area by fluorine ion implantation, defining the source and drain electrode regions by using a semiconductor photolithography process, and then using an etching opening process to remove the composite gate dielectric layer, cap layer and part of the barrier layer in the source and drain regions, wherein the etching opening is divided into two steps: SF6 etching the composite gate dielectric layer; BCl3 etching the cap layer and part of the barrier layer; then depositing the source and drain region metal of the device by electron beam evaporation, and finally stripping the metal in the non-electrode region and alloying the metal by high-temperature rapid thermal annealing to form an ohmic contact electrode.

[0018] In some embodiments, in step S5, the specific steps of preparing the gate electrode are: using a semiconductor photolithography process to define the gate electrode area, depositing the gate electrode metal by a metal deposition method, and stripping the metal in the non-electrode area to form the gate electrode.

[0019] In some embodiments, the substrate is made of one or more materials selected from silicon, sapphire, silicon carbide, and gallium nitride.

[0020] In some embodiments, before forming the composite gate dielectric layer, the epitaxial structure wafer is cleaned in a dilute HCl solution for 3 minutes to remove unstable oxides on the surface.

[0021] In some embodiments, the metal deposited in the source and drain regions is Ti / Al / Ni / Au.

[0022] In some embodiments, the thickness of the removed portion of the barrier layer is 6 nm.

[0023] In some embodiments, the deposited gate electrode metal is Ni / Au.

[0024] Technical Effects

[0025] 1) Through the electron cyclotron resonance physical vapor deposition (ECR-PVD) technology, combined with the room temperature coating process to form a dense passivation layer, a breakthrough was constructed for the construction of a Si3N4 / Ta2O5 composite gate dielectric system;

[0026] 2) Si3N4 gate dielectric deposition is carried out at room temperature, especially using electron cyclotron resonance physical vapor deposition coating technology. Utilizing atomic-level surface growth technology, an atomic-level flat interface can be formed without the need for high temperature. Room temperature inhibits Ga diffusion, thus avoiding the impact of high-temperature environments on the GaN or AlGaN contact interface.

[0027] 3) The Si3N4 deposited by ECR-PVD technology has good flatness, and the reaction gas can be fully ionized and evenly deposited on the substrate. The formed Si3N4 film is uniform, dense, defect-free, and has high interface quality. Ta2O5 has a high dielectric constant (about 25), which can effectively reduce the equivalent oxide layer thickness, increase the gate capacitance density, and enhance the driving capability of the device.

[0028] 4) The high-k structure of Ta2O5 / Si3N4 stacked structure can improve interface characteristics and suppress leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The epitaxial structure of the MISHEMT device is proposed for the technical solution of the present invention;

[0030] Figure 2 The technical solution of the present invention proposes a structure of a MISHEMT device after depositing a dielectric layer;

[0031] Figure 3 The technical solution of the present invention proposes a source and drain metal electrode structure of a MISHEMT device;

[0032] Figure 4 The complete structure of a GaN-based MISHEMT device is proposed for the technical solution of the present invention. DETAILED DESCRIPTION

[0033] To facilitate the implementation of the technical solution of the application, the following first provides a general description and definition of the terms and expressions involved in the present invention.

[0034] The terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0035] The "normal temperature" in the present invention refers to 20°C-25°C.

[0036] In each set of comparative experiments provided by the present invention, unless otherwise specified, other experimental conditions, materials, etc., except for the differences indicated in each group, are kept consistent to ensure comparability.

[0037] Unless otherwise specified, the reagents and instruments used in the embodiments of the present invention can be purchased from the market.

[0038] The following further describes a composite gate dielectric layer for a MISHEMT device, a depletion-mode MISHEMT device, and a preparation method thereof provided by the present invention.

[0039] Example 1 Preparation of Depletion-Mode MISHEMT Device

[0040] The specific preparation steps of the depletion-mode MISHEMT device are as follows:

[0041] 1) Using metal organic chemical vapor deposition (MOCVD) equipment to grow AlGaN / GaN material epitaxial structure on Si substrate (such as Figure 1 The epitaxial wafer is shown in Figure 1, consisting of a 3.6μm high-resistance GaN buffer layer, a 200nm GaN channel layer, an 18nm AlGaN barrier layer, and a 2nm GaN cap layer. Before the gate dielectric layer growth process, the wafer with the epitaxial structure is cleaned in a dilute HCl solution for 3 minutes to remove unstable surface oxides.

[0042] 2) Place the cleaned wafer into a solid source ECR coating machine for pre-coating. Close the coating shield during pre-coating, turn on the RF source on the Si target with an RF power of 400 W and a microwave power of 400 W, and introduce 30 sccm Ar and 2 sccm N2 gases. Pre-react for 5 minutes, then open the coating shield and coat the Si3N4 thin film with 30 sccm Ar and 9 sccm N2 gases. The insulating Si3N4 dielectric layer is deposited to a thickness of 5 nm at a coating rate of 2 nm / min. After Si3N4 coating, the RF source on the Si target is turned off, and the RF source on the Ta target is turned on. The RF power is 550W, the microwave power is 550W, and 40sccmAr and 7sccm O2 gases are introduced. After a pre-reaction of 5 minutes, the coating plate is turned on and Ta2O5 thin film coating is carried out. The process parameters for Ta2O5 coating are consistent with the pre-reaction parameters. The RF power is 550W, the microwave power is 550W, and 40sccmAr and 7sccm O2 gases are introduced. The thickness of the insulating Ta2O5 dielectric layer is 15nm, and the coating rate is 4nm / min. The structure after the gate dielectric layer is deposited is as follows Figure 2 shown.

[0043] 3) After the gate dielectric is deposited, fluorine ion implantation is used to isolate the active area of ​​the device. For the isolated device, the ohmic contact area on the wafer is first etched. During the pore opening process, the reactive ion etching method using SF6 as the etching gas is used to remove the dielectric layer in the source and drain areas. Then, the cap layer and the 6nm thick AlGaN barrier layer are etched away using inductively coupled plasma (ICP) with BCl3 as the etching gas. After that, Ti / Al / Ni / Au (titanium, aluminum, nickel, gold) is deposited as the source and drain metal electrodes using electron beam evaporation equipment, and annealed at high temperature to form ohmic contacts. The source and drain metal electrode structures are as follows: Figure 3 shown.

[0044] 4) Using electron beam evaporation, the gate electrode region is determined by depositing Ni / Au using photolithography technology and then stripping to form the gate electrode. The complete structure of the GaN-based MISHEMT device provided by the present invention is as follows: Figure 4 shown.

[0045] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. A composite gate dielectric layer for a MISHEMT device, characterized in that: The composite gate dielectric is prepared at room temperature by electron cyclotron resonance physical vapor deposition coating technology, wherein the composite gate dielectric layer includes an adjacent first gate dielectric layer and a second gate dielectric layer; the material of the first gate dielectric layer is Si3N4, and the material of the second gate dielectric layer is Ta2O5.

2. The composite gate dielectric layer for a MISHEMT device according to claim 1, wherein: In the electron cyclotron resonance physical vapor deposition coating system, the process conditions for depositing Si3N4 are: RF source power is 300-700W, microwave power is 300-700W; Ar flow rate is 20-60sccm, and N2 flow rate is 7-12sccm.

3. The composite gate dielectric layer for a MISHEMT device according to claim 1, wherein: In the electron cyclotron resonance physical vapor deposition coating system, the process conditions for depositing Ta2O5 are: RF source power of 400-700W, microwave power of 300-600W; Ar flow rate of 30-50sccm, O2 flow rate of 5-10sccm.

4. A depletion-mode MISHEMT device, characterized in that: include: substrate; a buffer layer formed on a substrate; a channel layer formed on the buffer layer; a barrier layer formed on the channel layer; a cap layer formed on the barrier layer; a drain and a source formed on the barrier layer; The composite gate dielectric layer according to any one of claims 1 to 3, wherein the composite gate dielectric layer is formed on the cap layer; a gate formed on the composite gate dielectric layer; The channel layer and the barrier layer constitute the heterojunction of the MISHEMT device.

5. The depletion-mode MISHEMT device according to claim 4, characterized in that: The thickness of the substrate is 0.1-10 mm; the total thickness of the channel layer and the barrier layer formed on the channel layer is 0.1-10 μm; the thickness of the cap layer is 0.1-1 μm; and the total thickness of the composite gate dielectric layer is 15-30 nm.

6. The depletion-mode MISHEMT device according to claim 5, characterized in that: The material of the buffer layer is high-resistance GaN; the material of the channel layer is one or more of AlN, GaN or GaAs; the material of the barrier layer is one or more of AlGaN, AlInN, GaAs or AlN; the cap layer is a p-type semiconductor made of GaN or AlGaN.

7. A method for preparing a depletion-mode MISHEMT device according to any one of claims 4 to 6, characterized in that: The steps include: S1, substrate preparation; S2, epitaxial structure growth; S3, preparing a composite gate dielectric layer; S4, mesa etching and preparation of ohmic contact electrodes in the source and drain regions; S5. Preparation of gate electrode.

8. The method according to claim 7, characterized in that In step S2, the specific steps of growing the epitaxial structure are: sequentially growing a buffer layer, a channel layer, a barrier layer and a cap layer on the substrate by metal organic compound chemical vapor deposition.

9. The method according to claim 7, characterized in that In step S4, the specific steps of mesa etching and preparation of ohmic contact electrodes in the source and drain regions are: isolating the device active region by fluorine ion implantation, defining the source and drain electrode regions by using a semiconductor photolithography process, and then removing the composite gate dielectric layer, cap layer and part of the barrier layer in the source and drain regions by an etching opening process, wherein the etching opening is divided into two steps: SF6 etching the composite gate dielectric layer; BCl3 etching the cap layer and part of the barrier layer; then depositing the device source and drain region metal by an electron beam evaporation method, and finally stripping the metal in the non-electrode region and alloying the metal by high-temperature rapid thermal annealing to form the ohmic contact electrode.

10. The method according to claim 7, characterized in that In step S5, the specific steps of preparing the gate electrode are: using a semiconductor photolithography process to define the gate electrode area, depositing the gate electrode metal by a metal deposition method, and stripping the metal in the non-electrode area to form the gate electrode.

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