Semiconductor device

Abstract

The invention provides a semiconductor device with high reliability. A semiconductor device in which a plurality of semiconductor elements are electrically connected, a bonding contact portion for bonding and electrically connecting the semiconductor elements to each other and a dummy bonding contact portion for bonding and non-conductively connecting the semiconductor elements to each other are disposed, and the dummy bonding contact portion is continuously provided along an outer periphery of a bonding region of the semiconductor elements. In the semiconductor element, the bonding contact portions are bonded to each other and the dummy bonding contact portions are bonded to each other in a state in which the bonding regions of each other face each other.

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected, and more particularly to a semiconductor device in which semiconductor elements having bonding contacts for electrically connecting the semiconductor elements to each other and dummy bonding contacts for not electrically connecting the semiconductor elements to each other are bonded. Background Art

[0002] Currently, various methods have been proposed for connecting semiconductor elements, or between a semiconductor element and a substrate, such as wafer-on-wafer, chip-on-wafer, or chip-on-chip. Hybrid bonding is also used to connect semiconductor elements, or between a semiconductor element and a substrate.

[0003] For example, Patent Documents 1 and 2 describe a hybrid-bonded semiconductor device. The semiconductor device of Patent Document 1 includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between a first bonding layer and a second bonding layer. The first semiconductor structure includes a first interconnect layer including a first interconnect and a first bonding layer including a first bonding contact. At least one first interconnect is a first virtual interconnect. Each first interconnect is in contact with its own first bonding contact. The second semiconductor structure includes a second interconnect layer including a second interconnect and a second bonding layer including a second bonding contact. At least one second interconnect is a second virtual interconnect. Each second interconnect is in contact with its own second bonding contact. Each first bonding contact is in contact with its own second bonding contact at the bonding interface.

[0004] Furthermore, the semiconductor device of Patent Document 2 includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first bonding layer and the second bonding layer. In the first semiconductor structure, each first interconnection contacts its own first bonding contact. In the second semiconductor structure, at least one second bonding contact contacts its own second interconnection. At least one other second bonding contact is separated from the second interconnection. Each first bonding contact contacts contacts one of the second bonding contacts at the bonding interface.

[0005] Previous technical literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-511451

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2022-509249 Summary of the Invention

[0009] Technical issues to be solved by the invention

[0010] Because chip-stacked wafers and chip-stacked chips are difficult to clean after singulation, they are less likely to reduce foreign matter, such as particles measuring several nanometers in size, that cause bonding defects compared to wafer-stacked wafers. This increases the likelihood that particles and other foreign matter will hinder bonding at the bonding interface of semiconductor devices, and also increases the likelihood of oxygen and moisture infiltration through the bonding interface. Consequently, ensuring the reliability of semiconductor devices is difficult.

[0011] Patent Documents 1 and 2 include the bonding interface between the first bonding layer and the second bonding layer, that is, the bonding surface. Therefore, as described above, even in the semiconductor devices of Patent Documents 1 and 2, it is difficult to ensure reliability due to foreign matter such as particles.

[0012] An object of the present invention is to provide a semiconductor device with high reliability.

[0013] Means for solving technical problems

[0014] In order to achieve the above-mentioned object, the invention [1] is a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected, wherein the semiconductor elements have: a bonding region, a bonding contact portion configured to bond the semiconductor elements to each other and electrically connect the semiconductor elements to each other, and a virtual bonding contact portion configured to bond the semiconductor elements to each other and connect the semiconductor elements to each other in a non-conductive manner, the virtual bonding contact portion being continuously arranged along the periphery of the bonding region of the semiconductor element, and in the semiconductor element, when the bonding regions are opposed to each other, the bonding contact portions are bonded to each other, and the virtual bonding contact portions are bonded to each other.

[0015] Invention [2] is the semiconductor device according to Invention [1], wherein:

[0016] In the plurality of semiconductor elements, the bonding contacts are directly bonded to one another with their bonding regions facing each other, and the dummy bonding contacts are directly bonded to one another.

[0017] Invention [3] is the semiconductor device according to Invention [1], wherein:

[0018] An anisotropic conductive member having conductivity in the stacking direction of the semiconductor elements is arranged between the bonding regions of the plurality of semiconductor elements, thereby electrically connecting the bonding contacts to each other and electrically connecting the dummy bonding contacts to each other.

[0019] Invention [4] is the semiconductor device according to Invention [3], wherein:

[0020] The anisotropic conductive member includes an insulating base material having electrical insulation properties and a plurality of conductive paths penetrating the insulating base material in a thickness direction and provided in a state of being electrically insulated from each other.

[0021] Invention [5] is the semiconductor device according to any one of Inventions [1] to [4], wherein:

[0022] The Vickers hardness of the virtual bond contact portion is 1 / 10 or less of the Vickers hardness of the region other than the bond and the virtual bond contact portion within the joint region.

[0023] Invention [6] is the semiconductor device according to any one of Inventions [1] to [5], wherein:

[0024] The dummy bonding contact is made of aluminum or copper, or an alloy containing aluminum or copper.

[0025] Effects of the Invention

[0026] According to the present invention, a highly reliable semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic perspective view showing an example of a semiconductor element used in a semiconductor device according to an embodiment of the present invention.

[0028] Figure 2 This is a schematic cross-sectional view showing a first example of a semiconductor device according to an embodiment of the present invention.

[0029] Figure 3 This is a schematic cross-sectional view showing an example of a method for manufacturing a first example of a semiconductor device according to an embodiment of the present invention.

[0030] Figure 4 This is a schematic cross-sectional view showing a second example of a semiconductor device according to an embodiment of the present invention.

[0031] Figure 5 This is a schematic cross-sectional view showing an example of a method for manufacturing a second example of a semiconductor device according to an embodiment of the present invention.

[0032] Figure 6 This is a schematic cross-sectional view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention.

[0033] Figure 7 This is a schematic plan view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] Hereinafter, a semiconductor device of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

[0035] In addition, the drawings described below are exemplary drawings for explaining the present invention, and the present invention is not limited to the drawings shown below.

[0036] In addition, the following "to" indicating a numerical range includes the values ​​described on both sides. For example, "ε is a value εα to a value εβ" means that the range of ε is a range including the values ​​εα and εβ, and in mathematical notation, it is εα≤ε≤εβ.

[0037] Regarding “parallel”, unless otherwise specified, it includes the error range generally allowed in the relevant technical field.

[0038] Regarding “same”, unless otherwise specified, it includes the error range generally allowed in the relevant technical field.

[0039] [First example of a semiconductor device]

[0040] Figure 1 This is a schematic perspective view showing an example of a semiconductor element used in a semiconductor device according to an embodiment of the present invention. Figure 2 1 is a schematic cross-sectional view showing a first example of a semiconductor device according to an embodiment of the present invention. Figure 1 , two semiconductor elements 12 are shown, but one of the two semiconductor elements 12 is a dummy. Figure 2 In, with Figure 1 The same components of the semiconductor element 12 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0041] Figure 1 The semiconductor element 12 shown constitutes a semiconductor device in which a plurality of semiconductor elements are stacked and electrically connected. Figure 1 Two semiconductor elements 12 are shown.

[0042] The semiconductor element 12 has a quadrilateral outer shape when viewed from above, for example, and has a flat surface 12 a . The flat surface 12 a also has a quadrilateral outer shape when viewed from above.

[0043] The semiconductor element 12 includes a bonding region Aj on the plane 12a. The bonding region Aj has a rectangular shape, for example, when viewed from above. The shape of the bonding region Aj is similar to the shape of the plane 12a. The bonding region Aj includes a bonding contact portion 20 that bonds and electrically connects the semiconductor elements 12 to each other, and a dummy bonding contact portion 22 that bonds and non-conductively connects the semiconductor elements 12 to each other. In the semiconductor elements 12 before bonding, the surfaces of the bonding contact portion 20 and the dummy bonding contact portion 22 do not protrude from the plane 12a and are flush with the plane 12a.

[0044] The dummy bonding contact portion 22 is continuously provided along the periphery of the bonding area Aj of the semiconductor element 12. More specifically, the dummy bonding contact portion 22 is strip-shaped when viewed from above, and is continuously provided in a ring shape along the periphery. For example, the outer and inner shapes of the dummy bonding contact portion 22 are quadrilaterals when viewed from above. The outer and inner shapes of the dummy bonding contact portion 22 are similar.

[0045] The bonding contact portion 20 is arranged in a region Ad surrounded by the dummy bonding contact portion 22. The region Ad is a region having a quadrilateral outer shape in a plan view.

[0046] The bonding contact portion 20 is conductive and electrically connects the semiconductor element 12. Electrical signals can be transmitted and received between the semiconductor elements 12 via the bonding contact portion 20. The bonding contact portion 20 corresponds to an electrode or terminal. While the bonding contact portion 20 may be circular in plan view, this is not limited to this and may also be a quadrilateral.

[0047] The dummy bonding contacts 22 are, for example, conductive and connect the semiconductor elements 12 to each other in a non-conductive manner. In other words, the dummy bonding contacts 22 bond the semiconductor elements 12 to each other but do not electrically connect them. The dummy bonding contacts 22 do not participate in the transmission and reception of electrical signals between the semiconductor elements 12.

[0048] The dummy bonding contacts 22 seal the periphery of the bonding contacts 20 of the semiconductor device 10 by bonding the dummy bonding contacts 22 to each other, shielding and protecting the bonding contacts 20 from the outside world. The dummy bonding contacts 22 prevent oxygen, moisture, and the like from penetrating into the bonding contacts 20, thereby enhancing the reliability of the semiconductor device 10. Furthermore, the dummy bonding contacts 22 increase the bonding surface, thereby maintaining the bonding strength of the semiconductor device 10.

[0049] As described above, the bonding contact portion 20 and the dummy bonding contact portion 22 are arranged in the joint region Aj.

[0050] When the semiconductor device 10 is composed of two semiconductor elements 12, the bonding contacts 20 of the two semiconductor elements 12 are bonded to each other, and the dummy bonding contacts 22 are bonded to each other, with the two semiconductor elements 12 facing each other with their planes 12a facing each other and their bonding regions Aj facing each other. This makes it possible to obtain a highly reliable semiconductor device.

[0051] Furthermore, as long as the size and shape of the bonding region Aj are the same, even if the semiconductor elements 12 have different sizes of the flat surfaces 12 a , the semiconductor elements 12 can be bonded to each other, thereby obtaining a semiconductor device.

[0052] The semiconductor device 10 will be described in more detail.

[0053] Figure 2 The semiconductor device 10 shown is composed of two semiconductor elements. For example, the semiconductor device 10 is a device in which a first semiconductor element 13 and a second semiconductor element 14 are stacked and bonded in a stacking direction Ds, thereby electrically connecting them. For example, the first semiconductor element 13 and the second semiconductor element 14 have different sizes when viewed from above, with the first semiconductor element 13 being larger than the second semiconductor element 14.

[0054] and Figure 1 Similar to the semiconductor element 12 shown, the first semiconductor element 13 has, for example, a quadrilateral outer shape in a plan view, has a flat surface 13 a , and includes a bonding region (not shown) on the flat surface 13 a .

[0055] The plane 13a and the joint region both have a quadrilateral shape in plan view.

[0056] A bonding contact 20 and a dummy bonding contact 22 are arranged in the bonding region.

[0057] The first semiconductor element 13 includes a first insulating layer 23 . A surface 23 a of the first insulating layer 23 serves as a plane 13 a of the first semiconductor element 13 .

[0058] The bonding contact portion 20 and the dummy bonding contact portion 22 are provided on the first insulating layer 23. The surfaces of the bonding contact portion 20 and the dummy bonding contact portion 22 do not protrude from the surface 23a of the first insulating layer 23 and are flush with the surface 23a of the first insulating layer 23.

[0059] Figure 2 In the embodiment, a second insulating layer 24 is provided as a bottom layer on the side of the first insulating layer 23 opposite the plane 13a of the first semiconductor element 13. A conductive connection portion 25 is provided on the second insulating layer 24 so as to contact the lower surface 20b of the bonding contact portion 20. The connection portion 25 is electrically connected to the bonding contact portion 20.

[0060] In addition, the connection portion 25 is not provided in the dummy bonding contact portion 22 .

[0061] A third insulating layer 26 is provided as a base layer on the side of the second insulating layer 24 opposite the plane 13a of the first semiconductor element 13. A wiring layer 27 is provided in the third insulating layer 26. The wiring layer 27 is composed of a plurality of wirings 27a. Among the wirings 27a, the wirings 27a arranged below the connecting portion 25 are electrically connected to the connecting portion 25.

[0062] A fourth insulating layer 28 is provided as a base layer on the side of the third insulating layer 26 opposite the plane 13a of the first semiconductor element 13. A through-electrode 29 is provided in the fourth insulating layer 28. The through-electrode 29 is provided so as to contact the wiring 27a electrically connected to the bonding contact portion 20. The through-electrode 29 is electrically connected to the wiring 27a.

[0063] The first insulating layer 23 , the second insulating layer 24 , the third insulating layer 26 and the fourth insulating layer 28 all have electrical insulating properties and are made of, for example, silicon, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric or any combination thereof.

[0064] and Figure 1 Similar to the semiconductor element 12 shown, the second semiconductor element 14 has, for example, a quadrilateral outer shape in a plan view, has a flat surface 14 a , and includes a bonding region (not shown) on the flat surface 14 a .

[0065] The plane 14a and the joint region both have a quadrilateral shape in a plan view.

[0066] A bonding contact 20 and a dummy bonding contact 22 are arranged in the bonding region.

[0067] The second semiconductor element 14 includes a first insulating layer 30 . A surface 30 a of the first insulating layer 30 serves as the plane 14 a of the second semiconductor element 14 .

[0068] The bonding contact 20 and the dummy bonding contact 22 are provided in the first insulating layer 30. The surfaces of the bonding contact 20 and the dummy bonding contact 22 do not protrude from the surface of the first insulating layer 30 and are flush with the surface 30a of the first insulating layer 30.

[0069] Figure 2 In the embodiment, a second insulating layer 31 is provided as an upper layer on the opposite side of the first insulating layer 30 from the plane 14a of the second semiconductor element 14. A conductive connection portion 32 is provided on the second insulating layer 31 so as to contact the lower surface 20b of the bonding contact portion 20. The connection portion 32 is electrically connected to the bonding contact portion 20.

[0070] In addition, the connection portion 32 is not provided in the dummy bonding contact portion 22 .

[0071] A third insulating layer 33 is provided as an upper layer on the side of the second insulating layer 31 opposite the plane 14a of the second semiconductor element 14. A wiring layer 34 is provided in the third insulating layer 33. The wiring layer 34 is composed of a plurality of wirings 34a. Among the wirings 34a, the wirings 34a disposed on the connecting portion 32 are electrically connected to the connecting portion 32.

[0072] A fourth insulating layer 35 is provided as an upper layer on the opposite side of the third insulating layer 33 from the plane 14a of the second semiconductor element 14. A through-electrode 36 is provided in the fourth insulating layer 35. The through-electrode 36 is provided so as to contact the wiring 34a electrically connected to the bonding contact portion 20. The through-electrode 36 is electrically connected to the wiring 34a.

[0073] A fifth insulating layer 37 is provided as an upper layer on the opposite side of the fourth insulating layer 35 from the plane 14a of the second semiconductor element 14. A wiring layer 38 is provided in the fifth insulating layer 37. The wiring layer 38 is composed of a plurality of wirings 38a. Among the wirings 38a, the wirings 38a disposed on the through-electrodes 36 are electrically connected to the through-electrodes 36.

[0074] A sixth insulating layer 39 is provided as an upper layer on the opposite side of the fifth insulating layer 37 from the plane 14a of the second semiconductor element 14. A conductive connection portion 40 is provided on the sixth insulating layer 39 so as to contact the upper surface 38b of the wiring 38a electrically connected to the through-electrode 36. The connection portion 40 is electrically connected to the wiring 38a.

[0075] A seventh insulating layer 41 is provided as an upper layer on the opposite side of the sixth insulating layer 39 from the plane 14a of the second semiconductor element 14. The aforementioned bonding contact portion 20 and dummy bonding contact portion 22 are provided in the seventh insulating layer 41. The bonding contact portion 20 is provided so as to contact the upper surface 40a of the connecting portion 40. The bonding contact portion 20 and the connecting portion 40 are electrically connected.

[0076] In addition, the connection portion 40 is not provided in the dummy bonding contact portion 22 .

[0077] The above-mentioned first insulating layer 30, second insulating layer 31, third insulating layer 33, fourth insulating layer 35, fifth insulating layer 37, sixth insulating layer 39 and seventh insulating layer 41 all have electrical insulating properties, for example, are composed of silicon, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectrics or any combination thereof.

[0078] The fourth insulating layer 28 provided with the through electrode 29 and the fourth insulating layer 35 provided with the through electrode 36 both have a structure such as a TSV (Through Silicon Via) and can be made of silicon.

[0079] In the first semiconductor element 13 and the second semiconductor element 14, the bonding contact portion 20, dummy bonding contact portion 22, connecting portions 25, 32, 40, wiring layers 27, 34, 38, and through-electrodes 29 and 36 are all conductive and made of, for example, tungsten, cobalt, copper, aluminum, silicide, or a combination thereof. Alternatively, materials used for terminals or electrode pads in the semiconductor element field can be appropriately utilized.

[0080] Among these, the dummy bonding contact portion 22 is preferably made of a metal or alloy that is more easily deformed during bonding than a semiconductor, oxide, or nitride, and more preferably made of aluminum, copper, or an alloy containing aluminum or copper.

[0081] In the semiconductor device 10, the bonding contacts 20 of the first semiconductor element 13 and the second semiconductor element 14 are directly bonded and electrically connected to each other. As a result, the bonding contacts 20, connecting portion 40, wiring layer 38, through-electrode 36, wiring layer 34, and connecting portion 32 of the second semiconductor element 14 are electrically connected to the bonding contacts 20, connecting portion 25, wiring layer 27, and through-electrode 29 of the first semiconductor element 13, enabling transmission and reception of electrical signals between the first semiconductor element 13 and the second semiconductor element 14.

[0082] In the semiconductor device, the semiconductor element 12 (refer to Figure 1 ) is preferably a Vickers hardness of the virtual bonding contact portion 22 of the bonding area Aj (reference Figure 1 ) except the bonding contact portion 20 (reference Figure 1 ) and the virtual bonding contact portion 22 (reference Figure 1 ) outside the area As (reference Figure 1 ) is less than 1 / 10 of the Vickers hardness of the semiconductor device 10. In this case, the dummy bonding contact portion 22 is softer than the region As, so even if foreign matter such as particles is present, it can be seamlessly sandwiched between the dummy bonding contact portions 22 and bonded. Thus, even if foreign matter such as particles is present, the periphery of the bonding contact portion 20 of the semiconductor device 10 can be reliably sealed, and any obstruction of bonding at the bonding surface Bc of the semiconductor device 10 can be suppressed. This further improves the reliability of the semiconductor device 10.

[0083] The region As corresponds to the plane 14 a of the first semiconductor element 13 , ie, the surface 23 a of the first insulating layer 23 , and also corresponds to the plane 14 a of the second semiconductor element 14 , ie, the surface 30 a of the first insulating layer 30 .

[0084] Regarding Vickers hardness, Si single crystal is 10.6 GPa, SiO2 is 9.7 GPa, Cu (copper) is 0.80 GPa, and Al (aluminum) is 0.50 GPa.

[0085] In addition, the Vickers hardness was measured in accordance with JIS (Japanese Industrial Standards) Z 2255:2003.

[0086] In the semiconductor device 10 , the interface between the plane 13 a of the first semiconductor element 13 and the plane 14 a of the second semiconductor element 14 is a bonding surface Bc. At the bonding surface Bc, the bonding contacts 20 are directly bonded to each other, and the dummy bonding contacts 22 are directly bonded to each other.

[0087] As described above, the dummy bonding contacts 22 are arranged to surround the bonding contacts 20. Therefore, the dummy bonding contacts 22 prevent oxygen, moisture, and the like from penetrating into the bonding contacts 20. Thus, a highly reliable semiconductor device 10 can be obtained.

[0088] Here, direct bonding refers to bonding without using an intermediate layer such as solder or adhesive, for example.

[0089] The semiconductor device 10 has a structure in which two semiconductor elements, namely the first semiconductor element 13 and the second semiconductor element 14, are stacked. However, the number of semiconductor elements may be plural and is not limited to two.

[0090] Furthermore, in the semiconductor device 10, a semiconductor element (not shown) having the aforementioned bonding contacts 20 and dummy bonding contacts 22 may be further stacked on the surface 41a of the seventh insulating layer 41 opposite to the plane 14a of the second semiconductor element 14. In this case, the number of stacked semiconductor elements is not particularly limited.

[0091] Figure 2 The layer structure of the second semiconductor element 14 shown is symmetrical with the fourth insulating layer 35 in the stacking direction Ds. The second semiconductor element 14 has the aforementioned bonding contacts 20 and dummy bonding contacts 22 arranged on the plane 14a and the surface 41a of the seventh insulating layer 41. Therefore, multiple second semiconductor elements 14 can be stacked in the stacking direction, with the bonding contacts 20 and the dummy bonding contacts 22 electrically connected to each other. In this case, if the second semiconductor element 14 is a memory, a memory stack is formed. The number of stacked second semiconductor elements 14 is not particularly limited.

[0092] In addition, both the first semiconductor element 13 and the second semiconductor element 14 can be manufactured by a known manufacturing method for manufacturing semiconductor elements.

[0093] [First Example of Manufacturing Method of Semiconductor Device]

[0094] Figure 3 1 is a schematic cross-sectional view showing an example of a method for manufacturing a first example of a semiconductor device according to an embodiment of the present invention. Figure 3 In, with Figure 2 The same components of the first semiconductor element 13 and the second semiconductor element 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0095] For example, Figure 3As shown, the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 are positioned opposite each other, so that their bonding regions face each other. In this case, the first semiconductor element 13 and the second semiconductor element 14 are aligned so that the bonding contacts 20 and the dummy bonding contacts 22 of the first semiconductor element 13 face each other and the bonding contacts 20 and the dummy bonding contacts 22 of the second semiconductor element 14. In this state, the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 are brought into contact with each other, directly bonding the bonding contacts 20 and directly bonding the dummy bonding contacts 22.

[0096] The method for bonding semiconductor elements to each other is not particularly limited, and for example, a bonding method used in hybrid bonding can be used.

[0097] Furthermore, as a bonding method, for example, DBI (Direct Bond Interconnect) or SAB (Surface Activated Bond) can be used.

[0098] DBI is a technique that involves laminating a silicon oxide film on a semiconductor element, performing chemical mechanical polishing, and then activating the silicon oxide film interface through plasma treatment to bring the semiconductor elements into contact and thereby bond them together.

[0099] SAB is a technique that activates the bonding surfaces of semiconductor elements by surface treatment in a vacuum. In this state, the semiconductor elements are brought into contact with each other at room temperature to bond them together. The surface treatment utilizes ion irradiation with an inert gas such as argon or irradiation with a neutral atom beam.

[0100] Alternatively, a conductive intermediate material such as solder may be provided between the bonding contacts 20 and dummy bonding contacts 22 of the first semiconductor element 13 and the bonding contacts 20 and dummy bonding contacts 22 of the second semiconductor element 14 to join the first semiconductor element 13 and the second semiconductor element 14 to form a semiconductor device.

[0101] [Second example of semiconductor device]

[0102] Figure 4 1 is a schematic cross-sectional view showing a second example of a semiconductor device according to an embodiment of the present invention. Figure 4 In, with Figure 2 The same components of the first semiconductor element 13 and the second semiconductor element 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0103] Figure 4 The semiconductor device 10a shown is Figure 2 Compared to the semiconductor device 10 shown in FIG. 1 , the difference is that an anisotropic conductive component 16 having conductivity in the stacking direction Ds of the semiconductor elements is arranged between the bonding regions of the plurality of semiconductor elements. Furthermore, the bonding surface Bc of the semiconductor device 10a is the interface between the flat surface 13a of the first semiconductor element 13 and the back surface 16b of the anisotropic conductive component 16, and is also the interface between the flat surface 14a of the second semiconductor element 14 and the front surface 16a of the anisotropic conductive component 16. The other structures are the same as those of FIG. Figure 2 The semiconductor devices 10 shown are identical.

[0104] exist Figure 4 In the illustrated semiconductor device 10a, the flat surface 13a of the first semiconductor element 13 is positioned opposite the back surface 16b of the anisotropically conductive component 16, and the flat surface 14a of the second semiconductor element 14 is positioned opposite the front surface 16a of the anisotropically conductive component 16. In the semiconductor device 10a, the bonding contacts 20 are electrically connected to each other, and the dummy bonding contacts 22 are electrically connected to each other, via the anisotropically conductive component 16. Thus, in the semiconductor device 10a, the bonding contacts 20 and the dummy bonding contacts 22 are not directly bonded to each other.

[0105] In the semiconductor device 10a, the first semiconductor element 13 and the second semiconductor element 14 are bonded and electrically connected to each other via the anisotropic conductive member 16 and the bonding contact portion 20. This electrically connects the bonding contact portion 20, the connecting portion 40, the wiring layer 38, the through-electrode 36, the wiring layer 34, and the connecting portion 32 of the second semiconductor element 14 to the bonding contact portion 20, the connecting portion 25, the wiring layer 27, and the through-electrode 29 of the first semiconductor element 13, enabling transmission and reception of electrical signals between the first semiconductor element 13 and the second semiconductor element 14.

[0106] and Figure 2 Similarly to the semiconductor device 10 shown, in the semiconductor device 10a, the dummy bonding contacts 22 are also arranged to surround the bonding contacts 20. Therefore, oxygen, moisture, etc. are prevented from penetrating into the bonding contacts 20. Thus, a highly reliable semiconductor device 10a can be obtained.

[0107] and Figure 2 Similarly to the semiconductor device 10 shown, in the semiconductor device 10a, a structure is set to be formed by stacking two semiconductor elements, namely a first semiconductor element 13 and a second semiconductor element 14. However, the number of semiconductor elements may be plural and is not limited to two.

[0108] And, with Figure 2Similar to the semiconductor device 10 shown, in the semiconductor device 10a, a semiconductor element (not shown) having the aforementioned bonding contacts 20 and dummy bonding contacts 22 may be further stacked on the surface 41a of the seventh insulating layer 41 of the second semiconductor element 14 via the anisotropic conductive member 16. In this case, the number of stacked layers is not particularly limited. Furthermore, when bonding the semiconductor element to the surface 41a of the seventh insulating layer 41 of the second semiconductor element 14, the second semiconductor element 14 and the semiconductor element may be bonded linearly without providing the anisotropic conductive member 16.

[0109] Furthermore, in the semiconductor device 10a, multiple second semiconductor elements 14 can be stacked in the stacking direction via the anisotropic conductive member 16, electrically connecting the bonding contacts 20 and the dummy bonding contacts 22. In this case, if the second semiconductor element 14 is a memory, a memory stack is formed. The number of stacked second semiconductor elements 14 is not particularly limited.

[0110] In both the semiconductor devices 10 and 10a, the bonding contacts 20 and the dummy bonding contacts 22 are arranged on the same layer. This allows the dummy bonding contacts 22 to be formed using the same process as the bonding contacts 20, thereby minimizing the complexity of the semiconductor device manufacturing process. When the bonding contacts 20 and the dummy bonding contacts 22 are arranged on the same layer, they are formed using the same process. Therefore, for example, the bonding contacts 20 and the dummy bonding contacts 22 may be made of the same metal or alloy.

[0111] Furthermore, formation through the same process means formation through a single film-forming step such as a plating step, a sputtering step, and a CVD (Chemical Vapor Deposition) step, for example.

[0112] [Method for Manufacturing the Second Example of a Semiconductor Device]

[0113] Figure 5 1 is a schematic cross-sectional view showing an example of a method for manufacturing a second example of a semiconductor device according to an embodiment of the present invention. Figure 5 In, with Figure 4 The same components of the first semiconductor element 13 , the second semiconductor element 14 , and the anisotropic conductive member 16 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0114] For example, Figure 5As shown, the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14 are placed opposite each other, so that their bonding regions are placed opposite each other. In this case, the first semiconductor element 13 and the second semiconductor element 14 are aligned so that the bonding contact portion 20 and the dummy bonding contact portion 22 of the first semiconductor element 13 are placed opposite the bonding contact portion 20 and the dummy bonding contact portion 22 of the second semiconductor element 14.

[0115] The anisotropic conductive member 16 is then arranged between the flat surface 13a of the first semiconductor element 13 and the flat surface 14a of the second semiconductor element 14, with the back surface 16b of the anisotropic conductive member 16 facing the flat surface 13a of the first semiconductor element 13 and the front surface 16a of the anisotropic conductive member 16 facing the flat surface 14a of the second semiconductor element 14. In this state, the flat surface 13a of the first semiconductor element 13 is in contact with the back surface 16b of the anisotropic conductive member 16, and the flat surface 14a of the second semiconductor element 14 is in contact with the front surface 16a of the anisotropic conductive member 16. As a result, the bonding contacts 20 are bonded together via the anisotropic conductive member 16, and the dummy bonding contacts 22 are bonded together.

[0116] The method for bonding semiconductor elements to each other is not particularly limited, and for example, a bonding method used in hybrid bonding can be used. In addition, the above-mentioned DBI or SAB can be used as a bonding method.

[0117] In addition, solder can be set between the bonding contact portion 20 and the dummy bonding contact portion 22 of the first semiconductor element 13 and the back surface 16b of the anisotropic conductive component 16, and solder can be set between the bonding contact portion 20 and the dummy bonding contact portion 22 of the second semiconductor element 14 and the surface 16a of the anisotropic conductive component 16 to join the first semiconductor element 13, the anisotropic conductive component 16 and the second semiconductor element 14 to form a semiconductor device.

[0118] (Anisotropic conductive component)

[0119] Figure 6 This is a schematic cross-sectional view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention. Figure 7 This is a schematic plan view showing an example of an anisotropic conductive member of a second example of a semiconductor device according to an embodiment of the present invention. Figure 7 It is from Figure 6 The top view of the anodized film as viewed from the surface side shows a state without the resin layer 54 .

[0120] Figure 6 The anisotropic conductive member 16 shown is arranged in the stacking direction Ds (refer to FIG. Figure 2 ) is conductive.

[0121] The anisotropic conductive member 16 includes an insulating base material 50 having electrical insulating properties, a plurality of conductive paths 52 extending through the insulating base material 50 in a thickness direction Dt and electrically insulated from one another, and a resin layer 54 covering at least one surface of the insulating base material 50. The anisotropic conductive member 16 is disposed between the first semiconductor element 13 and the second semiconductor element 14 such that the thickness direction Dt is parallel to the stacking direction Ds.

[0122] Multiple conductive pathways 52 are provided on an insulating substrate 50 in a state electrically insulated from one another. In this case, for example, the insulating substrate 50 has multiple pores 51 extending through the insulating substrate 50 in the thickness direction Dt. The conductive pathways 52 are provided in the pores 51. The conductive pathways 52 protrude from the front surface 50a of the insulating substrate 50. Furthermore, the conductive pathways 52 protrude from the back surface 50b of the insulating substrate 50.

[0123] The conductive path 52 is preferably configured to protrude from one surface of the insulating substrate 50 in the thickness direction Dt. In this case, a resin layer 54 is provided on the surface of the insulating substrate 50 where the conductive path 52 protrudes. The resin layer 54 covers the protruding portion 52a of the conductive path 52, and the protruding portion 52a is embedded in the resin layer 54. Furthermore, the resin layer 54 covers the protruding portion 52b of the conductive path 52, and the protruding portion 52b is embedded in the resin layer 54.

[0124] The insulating base material 50 is formed of, for example, an anodic oxide film. The front surface 50 a of the insulating base material 50 and the back surface 50 b of the insulating base material 50 are surfaces facing each other in the thickness direction Dt of the insulating base material 50 .

[0125] The anisotropic conductive member 16 has anisotropic conductivity and is conductive in the thickness direction Dt, but has very low conductivity in a direction parallel to the surface 50 a of the insulating base material 50 .

[0126] like Figure 7 As shown, the outer shape of the anisotropic conductive member 16 is, for example, a quadrilateral. The outer shape and size of the anisotropic conductive member 16 are appropriately determined according to the outer shape and size of the bonding region of the semiconductor element.

[0127] For example, the anisotropic conductive member 16 is bonded in a state where there is no resin layer 54 or even if there is a resin layer 54 , the surface 54 a thereof is left bare.

[0128] The structure of the anisotropic conductive member will be described in more detail below. The anisotropic conductive member has the same structure as that described in, for example, International Publication No. 2022 / 163260 and can be manufactured by the same method as that of the aforementioned structure.

[0129] <Insulating Base Material>

[0130] The insulating substrate 50 provides a plurality of conductive paths 52 formed of a conductor in an electrically insulated state. The insulating substrate 50 has electrical insulating properties. Furthermore, the insulating substrate 50 has a plurality of pores 51 that form the conductive paths 52. The composition of the insulating substrate 50 will be described later.

[0131] The length of the insulating substrate 50 in the thickness direction Dt, i.e., the thickness ht of the insulating substrate 50, is preferably in the range of 1 to 1000 μm, more preferably in the range of 5 to 500 μm, and even more preferably in the range of 10 to 300 μm. When the thickness ht of the insulating substrate 50 is within this range, the handling of the insulating substrate 50 is improved.

[0132] From the viewpoint of easy winding, the thickness ht of the insulating base material 50 is preferably 30 μm or less, and more preferably 5 to 20 μm.

[0133] In addition, the thickness of the insulating substrate is a value calculated as follows: using a focused ion beam (FIB), the insulating substrate is cut along the thickness direction Dt, and its cross-section is photographed using a scanning electron microscope (SEM) (magnification 50,000 times), and the surface is calculated as the average value obtained by measuring 10 points.

[0134] <Average Pore Diameter>

[0135] The average diameter of pores 51 is preferably 1 μm or less, more preferably 5 to 500 nm, even more preferably 20 to 400 nm, even more preferably 40 to 200 nm, and most preferably 50 to 100 nm. When the average diameter d of pores 51 is 1 μm or less and is within this range, conductive paths 52 having the above average diameter can be obtained.

[0136] The average diameter of the pores 51 is calculated as follows: a scanning electron microscope (SEM) is used to photograph the surface of the insulating substrate 50 from directly above at a magnification of 100 to 10,000 times to obtain a photographic image. At least 20 pores connected in a ring shape are extracted from the photographic image, and their diameters are measured to define the opening diameter. The average of these opening diameters is then calculated as the average pore diameter.

[0137] Furthermore, the magnification can be appropriately selected within the above range to obtain a photographic image capable of capturing 20 or more pores. Furthermore, the opening diameter is measured as the maximum distance between the ends of the pores. That is, the shape of the pore opening is not limited to being roughly circular. Therefore, when the opening is non-circular, the maximum distance between the ends of the pores is used as the opening diameter. Therefore, for example, even in the case of a pore shape where two or more pores are integrated, these are considered a single pore, and the maximum distance between the ends of the pores is used as the opening diameter.

[0138] <Conductive Path>

[0139] As described above, the plurality of conductive paths 52 are provided on the insulating base material 50 , such as the anodic oxide film, in a state of being electrically insulated from one another.

[0140] The plurality of conductive paths 52 are electrically conductive. The conductive paths are formed from a conductive material. The conductive material is not particularly limited, and metals may be mentioned. Specific examples of metals include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), and cobalt (Co). From the perspective of electrical conductivity, copper, gold, aluminum, nickel, and cobalt are preferred, copper and gold are more preferred, and copper is most preferred.

[0141] Metals are superior in ductility and other properties compared to oxide conductors and are easily deformed. They are also easily deformed even by compression during joining. Therefore, it is preferable that the conductive path be made of metal.

[0142] The height of the conductive path 52 in the thickness direction Dt is preferably 10 to 300 μm, more preferably 20 to 30 μm.

[0143] The Shape of Conductive Paths

[0144] The average diameter d of the conductive paths 52 is preferably 1 μm or less, more preferably 5 to 500 nm, further preferably 20 to 400 nm, further preferably 40 to 200 nm, and most preferably 50 to 100 nm.

[0145] The density of the conductive paths 52 is preferably 20,000 / mm 2 More than 2 million / mm 2 More than 10 million pieces / mm 2 More than 50 million / mm 2 More than 100 million / mm is most preferred 2 above.

[0146] Furthermore, the center-to-center distance p between adjacent conductive paths 52 is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and even more preferably 50 nm to 140 nm.

[0147] The average diameter of the conductive paths is calculated as follows: a scanning electron microscope is used to photograph the surface of the insulating substrate from directly above at a magnification of 100 to 10,000 times to obtain a photographic image. From the photographic image, at least 20 conductive paths connected in a circular pattern are extracted, and their diameters are measured and defined as the opening diameter. The average of these opening diameters is then calculated as the average diameter of the conductive paths.

[0148] Furthermore, the magnification can be appropriately selected within the above range to obtain a photographic image capable of extracting 20 or more conductive pathways. Furthermore, when the opening is non-circular, the maximum distance between the ends of the conductive pathway is used as the opening diameter. Therefore, even in the case of a conductive pathway with a shape such as two or more conductive pathways being integrated, these pathways are considered a single conductive pathway, and the maximum distance between the ends of the conductive pathways is used as the opening diameter. The average diameter d of the conductive pathway 52 is the same as the average diameter of the protrusion.

[0149] The center distance p between adjacent conductive pathways 52 is further determined by the center positions of the conductive pathways identified in the photographic image of the insulating substrate 50 obtained above (not shown). The distance between the center positions of adjacent conductive pathways is calculated at 10 points. The average value of these distances is used as the center distance p between adjacent conductive pathways 52. The center position is the center position of the region corresponding to the conductive pathway 52 in the photographic image. In the photographic image, known image analysis methods can be used to calculate the center position of the region.

[0150] The Bulge

[0151] The protrusion is a part of the conductive path and is columnar. From the viewpoint of increasing the contact area with the object to be joined, the protrusion is preferably columnar.

[0152] The average protrusion length ha of the protrusions 52a and the average length hb of the protrusions 52b are preferably 10 nm to 1000 nm, more preferably 50 nm to 500 nm. When the average protrusion length ha and the average length hb are 10 nm to 1000 nm, the adhesion between the resin layer 54 and the insulating base material 50 is improved.

[0153] As described above, the average protrusion length ha of the protrusion 52a and the average length hb of the protrusion 52b are obtained by obtaining a cross-sectional image of the protrusion using a scanning electron microscope, measuring the height of the protrusion at 10 points based on the cross-sectional image, and determining the average value.

[0154] The distance between conductive pathway 52 and adjacent protrusions is preferably 20 nm to 200 nm, more preferably 40 nm to 100 nm. When the distance between adjacent protrusions is within this range, the distance between conductive pathway 52 and adjacent protrusions can be maintained on the surface 50a or back surface 50b of insulating substrate 50. This prevents short circuits in conductive pathway 52 during semiconductor device bonding, further improving bonding reliability.

[0155] Resin Layer

[0156] As described above, the resin layer covers at least one of the front and back surfaces of the insulating substrate and protects the insulating substrate and the conductive path. For example, if the conductive path has a protruding portion, the resin layer embeds the protruding portion. In other words, the resin layer covers the end of the conductive path protruding from the insulating substrate and protects the protruding portion.

[0157] To achieve the above functions, the resin layer preferably exhibits fluidity in a temperature range of 50° C. to 200° C. and cures at a temperature of 200° C. or higher. The resin layer is, for example, a thermoplastic layer composed of a thermoplastic resin, and the resin layer will be described in detail later.

[0158] The average thickness hm of the resin layer 54 is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 1 μm or less. When the average thickness hm of the resin layer 54 is 10 μm or less, the protruding portion of the conductive path 52 can be fully protected and the surrounding area of ​​the electrode can be filled during bonding of the semiconductor device.

[0159] The average thickness hm of the resin layer 54 is the average distance from the surface 50a of the insulating substrate 50 or the average distance from the back surface 50b of the insulating substrate 50. The average thickness hm of the resin layer 54 is obtained by cutting the resin layer along the thickness direction Dt of the anisotropic conductive member 16 and observing the cut section using a scanning electron microscope. The average value of the distances from the surface 50a of the insulating substrate 50 at 10 locations corresponding to the resin layer is obtained. Furthermore, the average value of the distances from the back surface 50b of the insulating substrate 50 at 10 locations corresponding to the resin layer is obtained.

[0160] The resin layer can also have the following composition. The composition of the resin layer is described below. For example, the resin layer contains a polymer material and may also contain an antioxidant material.

[0161] Specific examples of the resin material constituting the resin layer include thermoplastic resins such as ethylene copolymers, polyamide resins, polyester resins, polyurethane resins, polyolefin resins, acrylic resins, acrylonitrile resins, and cellulose resins. Polyacrylonitrile can also be used as the resin material constituting the resin layer 54.

[0162] In addition to the above, as the resin layer, for example, a main composition containing an acrylic polymer, an acrylic monomer, and a maleimide compound described in International Publication No. 2022 / 163260 can be used.

[0163] [An example of a semiconductor device]

[0164] In semiconductor devices, the functions of the semiconductor device are distinguished by the operation of the semiconductor device. Examples of semiconductor functions include calculations performed by CPUs (Central Processing Units) and GPUs (Graphics Processing Units), storage performed by memories, conversion performed by converters, filtering, and sensing. When these functions are integrated into a single chip or unit, the functions are defined in that integrated state. If the defined functions are different, the semiconductor device is considered a different one.

[0165] The semiconductor element is not particularly limited as long as it has the above-mentioned bonding contact portion 20 and the dummy bonding contact portion 22. More specifically, as semiconductor elements, for example, logic LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), ASSP (Application Specific Standard Product), etc.), microprocessors (for example, CPU, GPU, etc.), memories (for example,DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), HMC (Hybrid Memory Cube), MRAM (Magnetic RAM), PCM (Phase-Change Memory), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM), Flash memory, etc.), LED (Light Emitting Diode), Power devices, Analog IC (Integrated Circuit), such as DC (Direct Current)-DC converters, Insulated Gate Bipolar Transistors (IGBTs), MEMS (Micro Electro Mechanical Systems), such as accelerometers, pressure sensors, vibrators, and gyroscope sensors, such as GPS (Global Positioning System), FM (Frequency Modulation), NFC (Near Field Communication), RFEM (RF Expansion) Module: RF expansion module), MMIC (Monolithic Microwave Integrated Circuit: monolithic microwave integrated circuit), WLAN (Wireless Local Area Network: wireless local area network), discrete components, BSI (Back Side Illumination: back-illuminated sensor), CIS (Contact Image Sensor: contact image sensor), camera module, passive devices, SAW (Surface Acoustic Wave: surface acoustic wave) filter, RF (Radio Frequency: radio frequency) filter, RFIPD (Radio Frequency Integrated Passive Devices: radio frequency integrated passive devices), and BB (Broadband: broadband), etc.

[0166] The composition of the semiconductor constituting the semiconductor element is not particularly limited. Examples of the semiconductor composition include diamond, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide, and silicon-on-insulator (SOI).

[0167] 〔Semiconductor devices〕

[0168] As mentioned above, a semiconductor device is made up of multiple semiconductor elements stacked and electrically connected. A semiconductor device can integrate multiple semiconductor elements to perform a specific function, but it may also simply transmit electrical signals.

[0169] The semiconductor device may be, for example, a logic device with a two-dimensional (2D), two and a half-dimensional (2.5D), or three-dimensional (3D) architecture. Furthermore, the semiconductor device may be, for example, a DRAM stack formed by stacking multiple DRAMs, or a structure formed by stacking a DRAM stack and a logic LSI.

[0170] Furthermore, the semiconductor device may have a structure including a printed wiring board and a heat sink.

[0171] In addition to the aforementioned semiconductor elements, a semiconductor device may also include digital, analog, or mixed-signal peripheral circuits. More specifically, a semiconductor device may include a peripheral device layer including one or more of a page buffer, a row decoder, a column decoder, a sense amplifier, a driver, a charge pump, a transistor, a diode, a resistor, or a capacitor.

[0172] Furthermore, the semiconductor device may also have a structure having an element region in addition to the above-mentioned semiconductor elements. The element region is a region where various elements constituting circuits for functioning as electronic elements are formed. The element region is, for example, a region where memory circuits such as flash memory are formed, logic circuits such as microprocessors and FPGAs (field-programmable gate arrays), and regions where communication modules such as wireless tags and wiring are formed. In addition, MEMS may also be formed in the element region. Examples of MEMS include sensors, actuators, and antennas. Examples of sensors include various sensors such as acceleration, sound, and light.

[0173] The present invention is basically constituted by the above-mentioned structure. Although the semiconductor device of the present invention has been described in detail above, the present invention is not limited to the above-mentioned embodiment, and various improvements and modifications can be made without departing from the scope of the present invention.

[0174] Explanation of symbols

[0175] 10, 10a - semiconductor device, 12 - semiconductor element, 12a, 13a, 14a - plane, 13 - first semiconductor element, 14 - second semiconductor element, 16 - anisotropic conductive component, 16a, 23a, 30a, 41a, 50a, 54a - surface, 16b, 50b - back surface, 20 - bonding contact portion, 20b - lower surface, 22 - virtual bonding contact portion, 23, 30 - first insulating layer, 24, 31 - second insulating layer, 25, 32, 40 - connection portion, 26, 33 - third insulating layer, 27, 34, 38 -Wiring layer, 27a, 34a, 38a-wiring, 28, 35-4th insulating layer, 29, 36-through electrode, 37-5th insulating layer, 38b, 40a-upper surface, 39-6th insulating layer, 41-7th insulating layer, 50-insulating substrate, 51-pore, 52-conductive path, 52a, 52b-protrusion, 54-resin layer, Ad-area, Aj-joining area, As-area, Bc-joining surface, Ds-stacking direction, Dt-thickness direction, d-average diameter, hm-average thickness, ht-thickness, p-center-to-center distance.

Claims

1. A semiconductor device comprising a plurality of semiconductor elements stacked and electrically connected, wherein: Semiconductor components have: a bonding region configured with bonding contacts for bonding the semiconductor elements to each other and electrically connecting the semiconductor elements to each other and dummy bonding contacts for bonding the semiconductor elements to each other and connecting the semiconductor elements to each other in a non-conductive manner; The dummy bonding contact portion is continuously provided along the periphery of the bonding region of the semiconductor element, In the semiconductor element, the bonding contacts are bonded to each other, and the dummy bonding contacts are bonded to each other, with the bonding regions facing each other.

2. The semiconductor device according to claim 1, wherein In the plurality of semiconductor elements, the bonding contacts are directly bonded to one another, and the dummy bonding contacts are directly bonded to one another, with the bonding regions facing one another.

3. The semiconductor device according to claim 1, wherein An anisotropic conductive member having conductivity in a stacking direction of the semiconductor elements is arranged between the bonding regions of the plurality of semiconductor elements, whereby the bonding contacts are electrically connected to each other and the dummy bonding contacts are electrically connected to each other.

4. The semiconductor device according to claim 3, wherein The anisotropic conductive member includes an insulating base material having electrical insulation properties and a plurality of conductive paths penetrating the insulating base material in a thickness direction and provided in a state of being electrically insulated from each other.

5. The semiconductor device according to any one of claims 1 to 4, wherein The Vickers hardness of the virtual bond contact portion is 1 / 10 or less of the Vickers hardness of a region other than the bond and the virtual bond contact portion within the joint region.

6. The semiconductor device according to any one of claims 1 to 4, wherein The dummy bonding contact is made of aluminum or copper, or an alloy containing aluminum or copper.

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