Semiconductor material having a cdte epitaxial layer grown on a gaas substrate and method of making the same

Abstract

The application provides a semiconductor material with a CdTe epitaxial layer grown on a GaAs substrate and a preparation method thereof, and belongs to the technical field of semiconductor materials. The semiconductor material with the CdTe epitaxial layer grown on the GaAs substrate comprises a GaAs substrate, a hetero buffer layer and a CdTe epitaxial layer which are sequentially stacked; the hetero buffer layer comprises a first metal-rich layer, a ZnSeTe layer, a second metal-rich layer, a ZnTe layer, a third metal-rich layer and a CdZnTe layer, and the first metal-rich layer, the ZnSeTe layer, the second metal-rich layer, the ZnTe layer, the third metal-rich layer and the CdZnTe layer are sequentially and layer by layer located between the GaAs substrate and the CdTe epitaxial layer; the thickness of the hetero buffer layer is 500-1000 nm, the Cd component ratio of the CdZnTe layer gradually increases from the side close to the GaAs substrate to the side far from the GaAs substrate, and the Zn component ratio gradually decreases from the side close to the GaAs substrate to the side far from the GaAs substrate. The semiconductor material has a relatively thin thickness, and the hetero buffer layer can effectively release stress and reduce the defect density of the CdTe epitaxial layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor materials, and in particular to a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate and a preparation method thereof. Background Art

[0002] Cadmium telluride (CdTe) is a direct bandgap semiconductor with a cubic structure. Its high average atomic number and strong radiation resistance make it suitable for the manufacture of light-emitting devices, multi-junction solar cells, and X-ray and gamma-ray detectors.

[0003] These devices are obtained by epitaxially growing CdTe on a substrate. However, homogeneous CdTe substrates are expensive and the process is not mature enough, resulting in high production costs.

[0004] Among related technologies, gallium arsenide (GaAs) substrates have a more mature process, are less expensive, and require simpler substrate pre-processing. However, the lattice mismatch between CdTe and GaAs is as high as 14%, making it difficult to obtain high-quality epitaxial layers when growing CdTe on GaAs substrates. It is even possible to grow CdTe epitaxial layers with a different crystal orientation than the GaAs substrate, which in turn affects the performance of CdTe devices.

[0005] Therefore, it is necessary to find a way to produce a CdTe epitaxial layer with better quality at a lower cost. Summary of the Invention

[0006] In view of this, in order to at least partially solve the above-mentioned technical problems, the present invention provides a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate and a preparation method thereof.

[0007] According to an embodiment of one aspect of the present invention, a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate is provided, comprising a GaAs substrate, a heterogeneous buffer layer, and a CdTe epitaxial layer stacked in sequence; the heterogeneous buffer layer comprising a first metal-rich layer, a ZnSeTe layer, a second metal-rich layer, a ZnTe layer, a third metal-rich layer, and a CdZnTe layer, wherein the first metal-rich layer, the ZnSeTe layer, the second metal-rich layer, the ZnTe layer, the third metal-rich layer, and the CdZnTe layer are sequentially positioned layer by layer between the GaAs substrate and the CdTe epitaxial layer; the thickness of the heterogeneous buffer layer is 500-1000 nm, the Cd component ratio of the CdZnTe layer gradually increases from a side close to the GaAs substrate to a side away from the GaAs substrate, and the Zn component ratio gradually decreases from a side close to the GaAs substrate to a side away from the GaAs substrate.

[0008] According to an embodiment of another aspect of the present invention, a method for preparing a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate is provided, characterized in that it includes: growing a heterogeneous buffer layer on the GaAs substrate, the heterogeneous buffer layer including a first metal-rich layer, a ZnSeTe layer, a second metal-rich layer, a ZnTe layer, a third metal-rich layer and a CdZnTe layer, the first metal-rich layer, the ZnSeTe layer, the second metal-rich layer, the ZnTe layer, the third metal-rich layer and the CdZnTe layer being grown layer by layer in sequence on the surface of the GaAs substrate; and growing a CdTe epitaxial layer on the heterogeneous buffer layer to obtain a semiconductor material.

[0009] According to an embodiment of the present invention, a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate is used. The present invention forms a ZnSeTe layer, a ZnTe layer, and a CdZnTe layer within a heterogeneous buffer layer. The stress in the initially formed buffer layer (e.g., the ZnSeTe layer and the ZnTe layer) is relatively high, promoting interatomic sliding, dislocation movement, and greater stress release. The stress in the subsequently formed CdZnTe layer is relatively low, making it easier to filter penetrating dislocations and prevent dislocations from entering the CdTe epitaxial layer. Because a metal-rich layer is first formed between the aforementioned ZnSeTe layer, ZnTe layer, and CdZnTe layer in the heterogeneous buffer layer, defects are generated at the interface, releasing stress generated by lattice mismatch and reducing the possibility of dislocations and other defects penetrating upward, which facilitates better stress release and, in turn, reduces the thickness of the heterogeneous buffer layer, saving costs while growing a high-quality CdTe epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0011] Figure 1 A schematic structural diagram of a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate according to the present invention is shown;

[0012] Figure 2 The figure shows a flow chart of a method for preparing a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate according to the present invention.

[0013] In the accompanying drawings, the meanings of the reference numerals are as follows:

[0014] 1-GaAs substrate;

[0015] 2-heterogeneous buffer layer;

[0016] 21-first metal-rich layer;

[0017] 22-ZnSeTe layer;

[0018] 23- second metal-rich layer;

[0019] 24-ZnTe layer;

[0020] 25-third metal-rich layer;

[0021] 26-CdZnTe layer;

[0022] 3-CdTe epitaxial layer;

[0023] 4-GaAs homogeneous buffer layer;

[0024] 5-metal-rich CdTe layer;

[0025] 6-CdTe homogeneous buffer layer. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0027] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The term "comprising" used herein indicates the existence of features, steps, operations, but does not exclude the existence or addition of one or more other features.

[0028] When expressions such as “at least one of A, B, and C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, and C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). When expressions such as “at least one of A, B, or C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, or C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.).

[0029] In the present invention, the term "step-like" refers to a semiconductor material that undergoes a sudden change at the interface between two layers (e.g., a ZnSeTe layer and a ZnTe layer), instantly jumping from one state to another, with a clear boundary between the two states and no intermediate transition region.

[0030] In the present invention, the term "gradual transition" means that the semiconductor material transitions continuously and smoothly from one state to another within a layer (eg, within a CdZnTe layer), with a transition region in between.

[0031] When attempting to obtain higher-quality CdTe epitaxial layers, related technologies often use homogeneous CdTe substrates. However, the high cost of CdTe substrates limits the preparation of CdTe epitaxial layers, which in turn limits the promotion of CdTe devices.

[0032] The lattice constant of GaAs is approximately 5.653Å, while that of CdTe is approximately 6.481Å, resulting in a lattice mismatch of nearly 14%. This significant mismatch makes it nearly impossible to grow high-quality CdTe directly on GaAs, resulting in a high density of dislocations and other defects, leading to extremely poor material performance.

[0033] In the process of realizing the concept of the present invention, it was found that when trying to grow a very thick CdTe epitaxial layer on a GaAs substrate, the defects can be allowed to gradually react with each other starting from the interface and annihilate each other. Alternatively, a ZnTe buffer layer with a lattice constant between the two is grown between the GaAs substrate and the CdTe epitaxial layer. The above two methods or a combination of the two can improve the quality of the CdTe epitaxial layer to a certain extent. However, the above situation usually requires the growth of a CdTe or ZnTe buffer layer with a thickness of several microns to obtain a CdTe epitaxial layer with a low defect density, resulting in an increase in time cost and raw material cost, and it is still likely that some unreacted defects will remain and enter the CdTe epitaxial layer.

[0034] To address these issues, the present invention employs an alternating structure of a metal-rich layer and a buffer layer within the heterogeneous buffer layer. This structure effectively releases stress through interatomic sliding, reducing the defect density of the CdTe epitaxial layer. Furthermore, by forming a layered structure with a gradient composition within the CdZnTe layer, the present invention minimizes stress and further prevents stress from entering the CdTe epitaxial layer. The inserted metal-rich layer also helps release stress generated by lattice mismatch at the interface, reducing the overall thickness of the heterogeneous buffer layer.

[0035] Specifically, according to an embodiment of one aspect of the present invention, a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate is provided. Figure 1 The structure diagram of the semiconductor material with a CdTe epitaxial layer grown on a GaAs substrate of the present invention is shown in FIG. Figure 1 As shown, the semiconductor material includes a GaAs substrate 1, a heterogeneous buffer layer 2 and a CdTe epitaxial layer 3 which are stacked in sequence.

[0036] The heterogeneous buffer layer 2 includes a first metal-rich layer 21, a ZnSeTe layer 22, a second metal-rich layer 23, a ZnTe layer 24, a third metal-rich layer 25 and a CdZnTe layer 26. The first metal-rich layer 21, the ZnSeTe layer 22, the second metal-rich layer 23, the ZnTe layer 24, the third metal-rich layer 25 and the CdZnTe layer 26 are successively located between the GaAs substrate 1 and the CdTe epitaxial layer 3.

[0037] It can be understood that the presence of the heterogeneous buffer layer 2 is to gradually transition the relatively large lattice constant difference between the aforementioned GaAs substrate 1 and the CdTe epitaxial layer 3. The aforementioned first metal-rich layer 21, second metal-rich layer 23, and third metal-rich layer 25 generate defects at the interface between the ZnSeTe layer 22, ZnTe layer 24, and CdZnTe layer 26, thereby releasing the stress generated by the lattice mismatch, which is conducive to better stress release, thereby reducing the possibility of defects such as dislocations penetrating into the CdTe epitaxial layer 3, and thus helping to reduce the thickness of the heterogeneous buffer layer 2. The thickness of the heterogeneous buffer layer 2 is 500~1000nm. Thinning the thickness of the heterogeneous buffer layer 2 helps to thin the overall thickness of the semiconductor material, which can save the growth time of each layer structure and the corresponding source materials, saving costs.

[0038] The lattice constant of the ZnSeTe layer 22 lies between that of the GaAs substrate 1 and the ZnTe layer 24, acting as a preliminary buffer. By adjusting the Se / Te ratio, the lattice constant of the ZnSeTe layer 22 can be varied between ZnSe (5.668 Å) and ZnTe (6.101 Å). The lattice constant can be designed to be closer to that of ZnTe (i.e., by increasing the Te content to a greater proportion of the total Se and Te content, for example, between 0.55 and 0.7).

[0039] The lattice constant of the ZnTe layer 24 is 6.101 Å, which is between the GaAs substrate 1 (5.653 Å) and the CdTe epitaxial layer 3 (6.481 Å), further achieving a transition and buffering of the lattice constant.

[0040] Furthermore, the Cd component ratio of the CdZnTe layer 26 gradually increases from the side close to the GaAs substrate 1 to the side away from the GaAs substrate 1, while the Zn component ratio gradually decreases from the side close to the GaAs substrate 1 to the side away from the GaAs substrate 1. It can be understood that the CdZnTe layer 26 exhibits a gradual change. By controlling the Cd component to gradually increase from the side close to the GaAs substrate 1 to the side away from the GaAs substrate 1 (which can be understood as the Zn component gradually decreasing), a continuous and gradual change in the lattice constant (for example, a linear gradient) is achieved. In other words, the lattice constant on the side close to the GaAs substrate 1 is relatively small, while the lattice constant on the side close to the CdTe epitaxial layer 3 is larger. This gradual setting can effectively prevent dislocation lines from extending upward from the interface between the GaAs substrate 1 and the heterogeneous buffer layer 2 to the CdTe epitaxial layer 3. Dislocations tend to bend, merge, or annihilate in the CdZnTe layer 26, reducing the possibility of vertical penetration and significantly reducing the threading dislocation density in the CdTe epitaxial layer 3.

[0041] According to an embodiment of the present invention, the insertion of multiple metal-rich layers prevents interdoping between III-V elements (e.g., GaAs substrate 1) and II-VI elements (e.g., ZnSeTe layer 22) or abnormal bonding between III-VI elements. The atomic interactions within the metal-rich layers are weaker, resulting in weaker bonding. This releases more stress through interatomic sliding. Within the heterogeneous buffer layer 2, the rate of change in the lattice constants of the ZnSeTe layer 22 and ZnTe layer 24 of the same thickness gradually decreases. This results in greater stress in the portion of the heterogeneous buffer layer 2 (ZnSeTe layer 22) where growth begins, promoting dislocation movement, interaction, and annihilation. The subsequently grown portion of the heterogeneous buffer layer 2 (ZnTe layer 24) experiences relatively less stress, making it easier to filter threading dislocations and prevent them from entering the CdTe epitaxial layer 3. The present invention adopts a heterogeneous buffer layer 2 structure with a stepped lower layer (i.e., ZnSeTe layer 22 and ZnTe layer 24) and a gradient upper layer (i.e., CdZnTe layer 26), which is conducive to growing a CdTe epitaxial layer 3 with high quality, low dislocation density and good surface morphology.

[0042] It should be noted that the ZnTe layer 24 spontaneously exhibits p-type when not intentionally doped, and the CdTe epitaxial layer 3 spontaneously exhibits n-type when not intentionally doped, and the ternary alloy CdZnTe forms self-compensation and has a lower intrinsic carrier concentration. At the same time, compared with ZnCdSe and CdTeSe, which have lattice constants between the GaAs substrate 1 and the CdTe epitaxial layer 3, the ZnSeTe layer 22 and CdZnTe layer 26 used in the present invention have a larger band gap and a lower intrinsic carrier concentration. Therefore, the insulating properties of the heterogeneous buffer layer 2 grown in this way are better, which is more beneficial to the preparation of devices formed by the upper CdTe epitaxial layer 3.

[0043] In some embodiments, at the same unit thickness, the absolute value of the difference in lattice constant between the ZnSeTe layer 22 and the ZnTe layer 24 is greater than the absolute value of the difference in lattice constant between the side close to the GaAs substrate 1 and the side away from the GaAs substrate 1 in the CdZnTe layer 26. It can be understood that at the same unit thickness, the abrupt lattice change of the ZnSeTe layer 22 and the ZnTe layer 24 forms a stepped interlayer structure, which has a greater degree of span than the lattice constant change in the CdZnTe layer 26, and will cause a high density of misfit dislocations to be generated at the interface between the ZnSeTe layer 22 and the ZnTe layer 24, which can cause dislocations to move, interact, bend, or even annihilate near this interface, thereby preventing dislocations from propagating upward. This arrangement allows the initial quality of the subsequent growth of the CdZnTe layer 26, that is, the dislocation density, to be greatly improved compared to direct growth on the GaAs substrate 1. The CdZnTe layer 26 forms a graded layer structure. This arrangement causes dislocations to bend and extend laterally, further reducing the likelihood of dislocations penetrating vertically upward. This arrangement, by synergizing the lower-layer step structure with the upper-layer graded structure, helps to ensure the high quality and low stress state of the CdTe epitaxial layer 3 to a large extent.

[0044] In some embodiments, the first metal-rich layer 21 is a metal-rich GaZnSeTe layer with a metal:non-metal ratio greater than 1:1. This metal:non-metal ratio greater than 1:1 can be understood as meaning that the first metal-rich layer 21 is rich in metal atoms such as Zn and Ga. The surface of the GaAs substrate 1 has a large number of As dangling bonds (an As-rich surface) and is chemically highly active. Consequently, excess metal atoms preferentially bond with the As dangling bonds on the surface of the GaAs substrate 1. The first metal-rich layer 21 prevents the formation of abnormal bonding interfaces between III-VI elements. The bonds formed between Zn and Ga atoms are weak, allowing for easy atomic sliding under stress, thereby relieving stress. The second metal-rich layer 23 is a metal-rich ZnTe layer with a metal:non-metal ratio greater than 1:1; and the third metal-rich layer 25 is a metal-rich ZnTe layer with a metal:non-metal ratio greater than 1:1. The presence of the second and third metal-rich layers 23, 25 facilitates the generation of defects at the interface of the interlayer structure, further precisely relieving stress caused by lattice mismatch. Furthermore, the insertion of the three metal-rich layers helps to maintain a clear heterogeneous interface, isolates As from diffusing into the CdTe epitaxial layer 3 , and further improves the quality of the CdTe epitaxial layer 3 .

[0045] In some embodiments, the thickness of the ZnSeTe layer 22 is 100-200 nm. This configuration forms a preliminary filter for misfit dislocations, promotes the initial merging or annihilation of dislocations, and reduces the density of dislocations propagating upward. The thickness of the ZnTe layer 24 is 100-200 nm. This configuration further filters dislocations and provides a growth surface with a lower defect density for the subsequent growth of the CdZnTe layer 26. If the thickness is too thick, the cost increases. If the thickness is too thin, the dislocation filtering is insufficient, resulting in poor initial quality of the CdZnTe layer 26. The thickness of the CdZnTe layer 26 is 300-600 nm. This configuration achieves a linear transition of the lattice constant through continuous composition changes (Cd / Zn ratio changes). Such a thickness provides sufficient thickness for dislocation turning and mutual reaction, ensuring that dislocations are eliminated before reaching the CdTe epitaxial layer 3. If the thickness is too small, the dislocation reaction is insufficient, affecting the crystal quality of the CdTe epitaxial layer 3; if the thickness is too large, the space for reducing the dislocation density is relatively limited, and the time cost and material cost are increased, and the risk of stress accumulation within the layer increases.

[0046] Optionally, the thickness of the ZnSeTe layer 22 may be 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, or 200 nm.

[0047] Optionally, the thickness of the ZnTe layer 24 may be 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, or 200 nm.

[0048] Alternatively, the thickness of the CdZnTe layer 26 may be 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, or 600 nm.

[0049] In some embodiments, a GaAs homogeneous buffer layer 4 is further included between the GaAs substrate 1 and the heterogeneous buffer layer 2. It is understandable that during the processes of cutting and polishing, the surface of the GaAs substrate 1 will inevitably be damaged and have a certain degree of roughness. The in-situ epitaxial formation of the GaAs homogeneous buffer layer 4 can repair possible damage on the surface of the GaAs substrate 1, reduce the surface roughness, and during the formation process, it is beneficial to remove contaminants on the surface of the GaAs substrate 1. The thickness of the GaAs homogeneous buffer layer 4 is 50~250nm. Such an arrangement can provide a relatively pure and smooth growth surface for the heterogeneous buffer layer 2. If the thickness is too small, it is difficult to completely cover the surface damage; if the thickness is too large, continuing to grow after the surface damage has been fully covered is not conducive to reducing time and source material costs.

[0050] Optionally, the thickness of the GaAs homogeneous buffer layer 4 may be 50 nm, 100 nm, 150 nm, 200 nm, or 250 nm.

[0051] In some embodiments, a metal-rich CdTe layer 5 and a CdTe homogeneous buffer layer 6 are disposed between the heterogeneous buffer layer 2 and the CdTe epitaxial layer 3, each having a metal:nonmetal ratio greater than 1:1. The excess Cd atoms in the metal-rich CdTe layer 5 facilitate the release of lattice mismatch stress. The CdTe homogeneous buffer layer 6 can eliminate the mismatch stress caused by residual dislocations in the heterogeneous buffer layer 2, absorb the differences in thermal expansion coefficients between the layers in the heterogeneous buffer layer 2, and help reduce surface roughness, providing a relatively smooth surface for the subsequent growth of the CdTe epitaxial layer 3.

[0052] In some embodiments, the thickness of the CdTe homogeneous buffer layer 6 is 100-200 nm. If the thickness is too low, it is difficult to effectively reduce the roughness; if the thickness is too high, it may lead to further increase in cost.

[0053] Optionally, the thickness of the CdTe homogeneous buffer layer 6 may be 100 nm, 120 nm, 140 nm, 160 nm, 180 nm or 200 nm, etc.

[0054] According to another embodiment of the present invention, a method for preparing a semiconductor material having a CdTe epitaxial layer 3 grown on a GaAs substrate is provided. Figure 2 The figure shows a flow chart of a method for preparing a semiconductor material having a CdTe epitaxial layer 3 grown on a GaAs substrate according to the present invention. Figure 2 As shown, the preparation method includes operations S201 to S202.

[0055] In operation S201, a heterogeneous buffer layer 2 is grown on a GaAs substrate 1. The heterogeneous buffer layer 2 includes a first metal-rich layer 21, a ZnSeTe layer 22, a second metal-rich layer 23, a ZnTe layer 24, a third metal-rich layer 25 and a CdZnTe layer 26. The first metal-rich layer 21, the ZnSeTe layer 22, the second metal-rich layer 23, the ZnTe layer 24, the third metal-rich layer 25 and the CdZnTe layer 26 are grown layer by layer in sequence on the surface of the GaAs substrate 1.

[0056] It is understood that the heterogeneous buffer layer 2 can be grown by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD), and the present invention is not particularly limited thereto. Furthermore, migration-enhanced epitaxy (MEE) can be used at the interface between the first metal-rich layer 21 and the ZnSeTe layer 22 to significantly reduce the interface roughness.

[0057] In operation S202 , a CdTe epitaxial layer 3 is grown on the heterogeneous buffer layer 2 to obtain a semiconductor material.

[0058] It is understood that the CdTe epitaxial layer 3 can also be grown by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD), and the present invention is not particularly limited thereto. The present invention can grow the CdTe epitaxial layer 3 of the aforementioned thickness and / or doping according to the requirements of subsequent processes.

[0059] According to embodiments of the present invention, as previously described, the heterogeneous buffer layer 2 (e.g., ZnSeTe layer 22 and ZnTe layer 24) grown in this manner facilitates dislocation movement and stress relief. The CdZnTe layer 26 grown has relatively low stress, making it easier to filter threading dislocations. Furthermore, the resulting metal-rich layer helps relieve stress caused by lattice mismatch, reducing the depth of defects such as dislocations, and thus facilitating thinning of the heterogeneous buffer layer 2.

[0060] In some embodiments, growing the first metal-rich layer 21 includes sequentially depositing Ga and Zn to a thickness of 1 to 3 atomic layers, and then depositing Se and Te on a GaAs substrate 1 at a temperature of 330 to 370°C, to obtain the first metal-rich layer 21. The first deposited Ga atoms can prevent Zn from forming dangling bonds with As in the GaAs substrate 1 or prevent Ga atoms from forming bonds with Te, and can help form the interface of the first metal-rich layer 21 rich in Ga and Zn. Thus, a very thin first metal-rich layer 21 that deviates from the stoichiometric ratio and lacks significant III-V / II-VI main group interface intermixing is formed on the surface of the GaAs substrate 1. The connection between the two layers of atoms in the first metal-rich layer 21 is weak, and the stress introduced when the lattice-mismatched buffer layer is subsequently grown thereon is more likely to generate defects in the first metal-rich layer 21, thereby more effectively releasing the stress and preventing the defects from extending too deeply upward.

[0061] It can be understood that the time for depositing Se and Te can be 2-5 seconds, which is helpful to form the first metal-rich layer 21 rich in Ga and Zn.

[0062] In one embodiment, the process of growing the first metal-rich layer 21 can be as follows: Open the Ga baffle and form a very thin Ga layer on the surface of the GaAs substrate 1 to avoid the generation of Zn-As compounds at the interface. The thickness of the Ga layer is 1-3 atomic layers, and the Ga baffle is closed. Open the Zn baffle and form a very thin Zn layer on the GaAs substrate 1 to avoid the generation of Zn-As and / or Ga-Te compounds at the interface. The thickness of the Zn layer is 1 to 5 atomic layers, and the Zn baffle is closed. At the same time, open the Se and Te baffles for 2 to 5 seconds to cover the GaAs substrate 1 with Se and Te. The beam current of Se and Te is the same as the beam current used in the next step of growing the ZnSeTe layer 22.

[0063] In some embodiments, growing the second metal-rich layer 23 includes first depositing Te on the ZnSeTe layer 22 at 310-340°C, followed by depositing Zn to a thickness of 1-5 atomic layers, to form the second metal-rich layer 23. Depositing Te first provides a Te-rich environment, protecting the surface of the ZnSeTe layer 22 and thereby forming a thin, flat second metal-rich layer 23. This results in a very thin, deviating second metal-rich layer 23 on the surface of the ZnSeTe layer 22, facilitating stress relief during the subsequent growth of the lattice-mismatched buffer layer.

[0064] In one embodiment, the process for growing the second metal-rich layer 23 can be as follows: Open the Te baffle and lower the temperature of the GaAs substrate 1 to 310-340°C, which is the optimal growth temperature for the ZnTe layer 24. Simultaneously, adjust the temperature of the Zn source furnace to the temperature corresponding to the Zn beam current required in the next step. Open the Zn baffle to form a Zn layer 1-5 atomic layers thick on the GaAs substrate 1. Simultaneously, adjust the temperature of the Te source furnace to the temperature corresponding to the Te beam current required in the next step.

[0065] In some embodiments, growing the third metal-rich layer 25 includes first depositing Te on the ZnTe layer 24 at 300-320°C, followed by depositing Zn to a thickness of 1-5 atomic layers, to form the third metal-rich layer 25. Depositing Te before depositing Zn primarily protects the surface of the ZnTe layer 24, preventing excessive desorption from the ZnTe layer 24 during cooling, which could result in a rough surface. This results in a very thin, destoichiometric third metal-rich layer 25 formed on the surface of the ZnTe layer 24, facilitating stress relief during the subsequent growth of the lattice-mismatched buffer layer.

[0066] In one embodiment, the process for growing the third metal-rich layer 25 can be as follows: Open the Te shutter and lower the temperature of the GaAs substrate 1 to 300-320°C. This is the optimal growth temperature for the CdZnTe layer 26. Simultaneously, adjust the temperature of the Zn source furnace to the desired Zn beam current for the next step. Maintaining the Zn shutter open, form a Zn layer 1-5 atomic layers thick on the ZnTe layer 24.

[0067] In some embodiments, the ZnSeTe layer 22 is grown under the following conditions: a growth temperature of 330-370°C, a Te content of 55-70%, and a (Se+Te) / Zn beam ratio of 6-12. This configuration facilitates the growth of a stoichiometric ZnSeTe layer 22. It should be noted that the thickness of the ZnSeTe layer 22 is at least twice the critical thickness for misfit dislocations, i.e., the aforementioned 100-200 nm (1000-2000 Å).

[0068] In some embodiments, the ZnTe layer 24 is grown at a temperature of 310-340°C and a Te / Zn beam ratio of 3-7. This configuration facilitates the growth of a relatively flat buffer layer that facilitates dislocation interaction. Consistent with the above, the thickness of the ZnTe layer 24 is at least twice the critical thickness for misfit dislocations, i.e., 100-200 nm (1000-2000 Å).

[0069] In some embodiments, the growth conditions for the CdZnTe layer 26 are as follows: Using a GaAs substrate 1 temperature of 300-320°C as the growth temperature, the temperature of the Cd source furnace is gradually increased, while the temperature of the Zn source furnace is gradually decreased during the growth process. It is understood that the specific ramp rates can be calculated based on the growth time and the temperatures corresponding to the components at the start and end of growth, and are not particularly limited in the present invention. Growth is performed such that the CdZnTe layer 26 near the GaAs substrate 1 has a Cd content of 10-30%; the CdZnTe layer 26 away from the GaAs substrate 1 has a Cd content of 80-90%, and the Te / (Zn+Cd) beam ratio is 7-12. This configuration facilitates a gradual compositional change in the CdZnTe layer 26, further achieving a transition in lattice constant and elimination of dislocations. Consistent with the above, the thickness of the CdZnTe layer 26 should be at least twice the critical thickness for misfit dislocations. This is the aforementioned 300~600nm (3000~6000Å).

[0070] In some embodiments, before growing the heterogeneous buffer layer 2, a GaAs homogeneous buffer layer 4 is also grown on the GaAs substrate 1. The GaAs homogeneous buffer layer 4 is suitable for covering defects on the surface of the GaAs substrate 1. As previously described, the thickness of the GaAs homogeneous buffer layer 4 is 50-250 nm (500-2500 Å).

[0071] In some embodiments, the conditions for growing the GaAs homogeneous buffer layer 4 are: a growth temperature of 580-600° C., and an As / Ga beam ratio of 15-40, preferably 25-35.

[0072] In some embodiments, before growing the CdTe epitaxial layer 3 , a metal-rich CdTe layer 5 and a CdTe homogeneous buffer layer 6 are sequentially grown on the heterogeneous buffer layer 2 .

[0073] In some embodiments, the metal-rich CdTe layer 5 is grown under the following conditions: Te is first deposited on the CdZnTe layer 26 at 300-320°C, followed by a 2-4 atomic layer thickness of Cd to obtain the metal-rich CdTe layer 5. Thus, the thinner metal-rich CdTe layer 5, which deviates from the stoichiometric ratio, can better relieve stress during the subsequent growth of the lattice-mismatched layered structure.

[0074] In some embodiments, the CdTe homogeneous buffer layer 6 is grown at a temperature of 300-320° C. and a Te / Cd beam ratio of 9-13. This helps to obtain a relatively flat surface.

[0075] In a specific embodiment, the process of growing a high-quality CdTe epitaxial layer 3 on a GaAs substrate 1 can be as follows:

[0076] The GaAs homogeneous buffer layer 4 is grown at a temperature of 580-600° C. and an As / Ga beam ratio of 15-40.

[0077] The GaAs substrate 1 is cooled. When cooling begins, the As baffle and valve are kept open. The As beam current can be appropriately reduced, preferably to 1 / 2-2 / 3 of the As beam current during the growth of the GaAs homogeneous buffer layer 4 .

[0078] When the temperature drops to a point where As no longer desorbs significantly from the surface, close the As valve and baffle at 400-500°C to evacuate as much As as possible from the chamber to prevent residual As from acting as a dopant source in the subsequently grown II-VI compounds or introducing non-ideal interfaces. Simultaneously, continue cooling to the target temperature, which is the growth temperature for the ZnSeTe layer 22 in the next step, preferably 330-370°C.

[0079] Open the Ga baffle to form a Ga layer with a thickness of 1 to 3 atomic layers on the surface of the GaAs homogeneous buffer layer 4 to avoid the formation of Zn-As compounds at the interface. Close the Ga baffle, open the Zn baffle, form a Zn layer with a thickness of 1 to 5 atomic layers on the surface of the Ga layer to avoid the formation of Ga-Zn and / or Ga-Te compounds at the interface, and close the Zn baffle. At the same time, open the Se and Te baffles to cover the surface of the Zn layer with Se and Te. The Se and Te beam currents are the same as those used in the next step to grow the ZnSeTe layer 22, and the opening time is 2 to 5 seconds, thus forming the first metal-rich layer 21.

[0080] Keeping the Se and Te baffles open, the Zn baffle was opened to begin growing a stoichiometric ZnSeTe layer 22 with a Te composition of 0.55-0.7. The (Se+Te) / Zn beam ratio was 6-12, forming the ZnSeTe layer 22.

[0081] Open the Te shutter and lower the substrate temperature to 310-340°C. This is the optimal growth temperature for the ZnTe layer 24. Simultaneously, adjust the Zn source furnace temperature to the desired Zn beam current for the next step. Open the Zn shutter to form a Zn layer 1-5 atomic layers thick on the surface of the ZnSeTe layer 22. Simultaneously, adjust the Te source furnace temperature to the desired Te beam current for the next step. This forms the second metal-rich layer 23.

[0082] The Te baffle is opened, the Te / Zn beam ratio is 3-7, and the ZnTe layer 24 is grown.

[0083] Open the Te baffle and lower the temperature of the GaAs substrate 1 to 300-320°C, the optimal growth temperature for the CdZnTe layer 26. Simultaneously, adjust the temperature of the Zn source furnace to the temperature corresponding to the Zn beam current required in the next step. Keep the Zn baffle open to form a Zn layer 1-5 atomic layers thick on the surface of the ZnTe layer 24. Simultaneously, adjust the temperature of the Te source furnace to the temperature corresponding to the Te beam current required in the next step. At this point, a third metal-rich layer 25 is formed on the surface of the ZnTe layer 24.

[0084] The Te baffle is opened, and the Zn and Cd baffles are opened to grow a CdZnTe layer 26. During the growth process, the temperature of the Cd source furnace gradually increases, while the temperature of the Zn source furnace gradually decreases, forming a CdZnTe layer 26 with a gradually increasing Cd composition. The starting Cd composition is 0.1-0.3, and the ending Cd composition is 0.8-0.9. The Te / (Zn+Cd) beam ratio is 7-12.

[0085] The Te baffle is opened, and the temperature of the Cd source furnace is adjusted to the temperature corresponding to the Cd beam current required in the next step. The Cd baffle is opened, and a Cd layer 1 to 5 atomic layers thick is formed on the surface of the CdZnTe layer 26. Simultaneously, the temperature of the Te source furnace is adjusted to the temperature corresponding to the Te beam current required in the next step, and the Te baffle is opened. At this point, a metal-rich CdTe layer 5 is formed on the surface of the CdZnTe layer 26.

[0086] The Te / Cd beam ratio is set to 9-13, the Cd baffle is closed, and the Te baffle is kept open for 3-10 seconds to obtain a flat surface. The Cd baffle is then opened to grow a CdTe homogeneous buffer layer 6.

[0087] According to the requirements of subsequent processes, a CdTe epitaxial layer 3 with a required thickness and doping is grown.

[0088] The present invention is further illustrated below by way of examples and their results. In the detailed description that follows, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, it is apparent that one or more embodiments may be implemented without these specific details. Furthermore, the details in the following embodiments may be arbitrarily combined into other feasible embodiments, unless conflicting.

[0089] It should be noted that the following specific examples are for illustration only and the scope of protection of the present invention is not limited thereto. The raw materials used in the following examples were either commercially available or prepared in-house using generally accepted processing methods.

[0090] Example 1:

[0091] A 1000Å thick GaAs homogeneous buffer layer was grown on a GaAs substrate at a growth temperature of 580°C and an As / Ga beam ratio of 30. The GaAs substrate was cooled, with the As baffle and valve kept open at the beginning of the cooling process. The As beam current was reduced to half the As beam current used for GaAs growth. When the temperature dropped by 450°C, the As valve and baffle were closed, and the temperature continued to drop to 350°C until the vacuum gauge reading was an order of magnitude lower than when the As valve and baffle were closed.

[0092] The Ga baffle is opened, and three Ga atomic layers are deposited on the surface of the GaAs homogeneous buffer layer. The Ga baffle is then closed. The Zn baffle is opened, and three Zn atomic layers are deposited on the surface of the Ga atomic layer. The Zn baffle is then closed. Simultaneously, the Se and Te baffles are opened for 4 seconds, using the same Se and Te beam currents as those used to grow the ZnSeTe layer in the next step. This completes the formation of the first metal-rich thin layer on the GaAs homogeneous buffer layer.

[0093] Keep the Se and Te shutters open, open the Zn shutter, and start growing a stoichiometric ZnSeTe layer with a Te composition of 0.6, a (Se+Te) / Zn beam ratio of 9, and a ZnSeTe layer thickness of 1500Å.

[0094] With only the Te shutter open, the substrate temperature was lowered to 325°C, while the Zn source furnace was adjusted to the temperature corresponding to the Zn beam current required for the next step. With only the Zn shutter open, three Zn atomic layers were deposited on the ZnSeTe layer, while the Te source furnace was adjusted to the temperature corresponding to the Te beam current required for the next step. This formed a second metal-rich layer on the ZnSeTe layer. With the Te shutter open, the ZnTe layer was grown with a Te / Zn beam ratio of 5 and a thickness of 1500 Å.

[0095] With only the Te shutter open, the substrate temperature is lowered to 310°C. Meanwhile, the Zn source furnace is adjusted to the temperature corresponding to the Zn beam current required for the next step. With only the Zn shutter open, three Zn atomic layers are deposited on the ZnTe layer while the Te source furnace is adjusted to the temperature corresponding to the Te beam current required for the next step. This forms a third metal-rich layer on the ZnTe layer.

[0096] The Te baffle, Zn baffle, and Cd baffles were opened to grow a CdZnTe layer. During the growth process, the temperature of the Cd source furnace gradually increased while the temperature of the Zn source furnace gradually decreased, forming a CdZnTe layer with a gradually increasing Cd composition. The starting Cd composition was 0.2 and the ending Cd composition was 0.9. The Te / (Zn + Cd) beam ratio was 9-11, and the thickness was 5000 Å.

[0097] Only the Te source shutter is opened, and the Cd source furnace is adjusted to the temperature corresponding to the Cd beam current required in the next step. With only the Cd shutter open, three Cd atomic layers are deposited on the epitaxial layer surface. Simultaneously, the Te source furnace temperature is adjusted to the Te beam current required in the next step, and the Te shutter is opened. This forms a metal-rich CdTe layer on the CdZnTe layer.

[0098] The Te / Cd beam ratio was optimized to 11, as this helped to achieve higher crystal quality. The Cd shutter was closed, the Te shutter was kept open for 5 seconds, and then the Cd shutter was opened to grow a 1500Å thick CdTe homogeneous buffer layer.

[0099] According to the requirements of subsequent processes, a CdTe epitaxial layer of required thickness and doping is grown.

[0100] In the semiconductor material with CdTe epitaxial layer grown on the obtained GaAs substrate, the dislocation density can be controlled to 5E6 / cm by growing a heterogeneous buffer layer. 2 Below, the half-width of the 0.5μm CdTe epitaxial layer is controlled below 800arcsec. The reason is that the use of a stepped heterogeneous buffer layer structure with a larger span between components on the side close to the GaAs substrate is conducive to promoting the movement, reaction and annihilation of mismatch dislocations and reducing residual stress; the use of a gradient heterogeneous buffer layer with a slower lattice constant change on the side away from the GaAs substrate is conducive to reducing the density of threading dislocations, thereby reducing the impact of dislocations generated in the heterogeneous buffer layer on the crystal quality of the CdTe epitaxial layer. In addition, the formation of multiple metal-rich layers is conducive to the generation of defects at the interface, releasing the stress generated by the lattice mismatch, reducing the possibility of defects such as dislocations penetrating upward, thereby reducing the thickness of the heterogeneous buffer layer and growing a CdTe epitaxial layer with better quality.

[0101] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate, characterized in that: It includes a GaAs substrate, a heterogeneous buffer layer and a CdTe epitaxial layer stacked in sequence; The heterogeneous buffer layer includes a first metal-rich layer, a ZnSeTe layer, a second metal-rich layer, a ZnTe layer, a third metal-rich layer and a CdZnTe layer, wherein the first metal-rich layer, the ZnSeTe layer, the second metal-rich layer, the ZnTe layer, the third metal-rich layer and the CdZnTe layer are sequentially arranged between the GaAs substrate and the CdTe epitaxial layer; The thickness of the heterogeneous buffer layer is 500-1000 nm, wherein the Cd component ratio of the CdZnTe layer gradually increases from the side close to the GaAs substrate to the side away from the GaAs substrate, and the Zn component ratio gradually decreases from the side close to the GaAs substrate to the side away from the GaAs substrate; The first metal-rich layer is a metal-rich GaZnSeTe layer with a metal content: non-metal content greater than 1:1; the second metal-rich layer is a metal-rich ZnTe layer with a metal content: non-metal content greater than 1:1; and the third metal-rich layer is a metal-rich ZnTe layer with a metal content: non-metal content greater than 1:

1.

2. The semiconductor material according to claim 1, characterized in that At the same unit thickness, the absolute value of the difference in lattice constant between the ZnSeTe layer and the ZnTe layer is greater than the absolute value of the difference in lattice constant between the side close to the GaAs substrate and the side away from the GaAs substrate in the CdZnTe layer.

3. The semiconductor material according to claim 1 or 2, characterized in that The thickness of the ZnSeTe layer is 100-200 nm; the thickness of the ZnTe layer is 100-200 nm; and the thickness of the CdZnTe layer is 300-600 nm.

4. The semiconductor material according to claim 1, characterized in that A GaAs homogeneous buffer layer is included between the GaAs substrate and the heterogeneous buffer layer, and the thickness of the GaAs homogeneous buffer layer is 50 to 250 nm; and / or, Between the heterogeneous buffer layer and the CdTe epitaxial layer, there are also a metal-rich CdTe layer with a metal content: non-metal content greater than 1:1 and a CdTe homogeneous buffer layer, and the thickness of the CdTe homogeneous buffer layer is 100~200nm.

5. A method for preparing a semiconductor material having a CdTe epitaxial layer grown on a GaAs substrate, characterized in that: include: Growing a heterogeneous buffer layer on a GaAs substrate, the heterogeneous buffer layer comprising a first metal-rich layer, a ZnSeTe layer, a second metal-rich layer, a ZnTe layer, a third metal-rich layer and a CdZnTe layer, wherein the first metal-rich layer, the ZnSeTe layer, the second metal-rich layer, the ZnTe layer, the third metal-rich layer and the CdZnTe layer are grown layer by layer on the surface of the GaAs substrate; Growing a CdTe epitaxial layer on the heterogeneous buffer layer to obtain a semiconductor material; Growing the first metal-rich layer comprises: first depositing Ga with a thickness of 1 to 3 atomic layers and Zn with a thickness of 1 to 5 atomic layers on a GaAs substrate, and then depositing Se and Te at a temperature of 330 to 370° C., to obtain the first metal-rich layer; Growing the second metal-rich layer comprises: first depositing Te on the ZnSeTe layer and then depositing Zn with a thickness of 1 to 5 atomic layers at a temperature of 310 to 340° C. to obtain the second metal-rich layer; Growing the third metal-rich layer includes: first depositing Te on the ZnTe layer under the condition of 300-320° C., and then depositing Zn with a thickness of 1-5 atomic layers to obtain the third metal-rich layer.

6. The preparation method according to claim 5, characterized in that The growth conditions of the ZnSeTe layer are: growth temperature of 330-370°C, Te content of 55-70%, and (Se+Te) / Zn beam ratio of 6-12. The growth conditions of the ZnTe layer are: growth temperature of 310-340°C and Te / Zn beam ratio of 3-7.

7. The preparation method according to claim 5, characterized in that The growth conditions of the CdZnTe layer are: With the growth temperature at 300~320℃, the temperature of the Cd source furnace is gradually increased, and the temperature of the Zn source furnace is gradually decreased, so that the Cd content of the CdZnTe layer close to the GaAs substrate is 10~30%; the Cd content of the CdZnTe layer away from the GaAs substrate is 80~90%, and the beam ratio of Te / (Zn+Cd) is 7~12.

8. The preparation method according to claim 5, characterized in that Before growing the heterogeneous buffer layer, a GaAs homogeneous buffer layer is also grown on the GaAs substrate, and the conditions for growing the GaAs homogeneous buffer layer are: a growth temperature of 580-600° C. and an As / Ga beam ratio of 15-40; and / or, Before growing the CdTe epitaxial layer, a metal-rich CdTe layer and a CdTe homogeneous buffer layer are grown on the heterogeneous buffer layer; Among them, growing a metal-rich CdTe layer includes: first depositing Te on a CdZnTe layer at 300-320°C, and then depositing Cd with a thickness of 2-4 atomic layers to obtain a metal-rich CdTe layer; the conditions for growing a CdTe homogeneous buffer layer are: a growth temperature of 300-320°C and a Te / Cd beam ratio of 9-13.

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