Current sampling circuit, PCB and chip

Abstract

The invention relates to the technical field of electronics, and discloses a current sampling circuit, a PCB and a chip, the current sampling circuit comprises an operational amplification unit, a sampling unit and an offset elimination unit; the sampling unit is electrically connected with the operational amplification unit, and the offset elimination unit is electrically connected with the operational amplification unit; the sampling unit can obtain a voltage signal reflecting a measured current, the operational amplification unit amplifies the voltage signal transmitted by the sampling unit, and the offset elimination unit provides a compensation current for the operational amplification unit, so that the negative influence of the offset voltage of the operational amplification unit is effectively counteracted, and the operational amplification unit is ensured to stably and accurately amplify the signal. The three parts are tightly matched to finally output a high-precision sampling result, and accurate current data are provided for the system.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a current sampling circuit, a PCB board, and a chip. Background Art

[0002] In the field of electronic circuits, current sampling is a crucial step in the operation of many electrical devices and systems. Its sampling accuracy directly affects the performance, stability, and reliability of the system. Traditional current sampling circuits generally suffer from insufficient sampling accuracy.

[0003] Specifically, in the existing current sampling technology, the operational amplifier unit inside the sampling circuit is a key part for amplifying the voltage signal obtained by the sampling unit. Due to reasons such as the manufacturing process, an offset voltage inevitably exists. This offset voltage will be amplified as the signal is amplified, causing the operational amplifier unit to accumulate errors caused by the offset voltage during the signal amplification process, thereby causing deviations in the final sampling results, which seriously affects the accuracy of current sampling and cannot accurately reflect the true situation of the measured current. Summary of the Invention

[0004] The present invention aims to improve at least one technical problem in the background technology.

[0005] A first aspect of the present invention provides a current sampling circuit, comprising: an operational amplifier unit, a sampling unit, and an offset cancellation unit; the sampling unit is electrically connected to the operational amplifier unit, and the offset cancellation unit is electrically connected to the operational amplifier unit; the sampling unit is used to obtain a voltage signal of a measured current; the operational amplifier unit is used to amplify the voltage signal obtained by the sampling unit; and the offset cancellation unit is used to provide a compensation current to the operational amplifier unit to eliminate the offset voltage of the operational amplifier unit.

[0006] In the first embodiment of the present invention, the sampling unit is responsible for acquiring the voltage signal of the measured current, providing raw data for the entire sampling process; the operational amplifier unit amplifies the voltage signal transmitted by the sampling unit for subsequent circuit processing and analysis; and the offset cancellation unit closely cooperates with the operational amplifier unit to monitor the offset of the operational amplifier unit in real time. When the operational amplifier unit experiences an offset voltage, the offset cancellation unit responds quickly and accurately provides a compensation current to it, effectively offsetting the negative impact of the offset voltage of the operational amplifier unit and ensuring that the operational amplifier unit stably and accurately amplifies the signal. The three closely cooperate to ultimately output a high-precision sampling result, providing accurate current data for the system.

[0007] As some sub-solutions of the above technical solution, the operational amplifier unit includes a first bias unit, an input unit, an amplifying unit and an output unit; the input unit is connected to the amplifying unit, and the amplifying unit is connected to the output unit; the first bias unit is connected to the input unit and the output unit; the first bias unit is used to provide a bias voltage and a bias current for the input unit and the output unit; the input unit is used to receive the voltage signal output by the sampling unit and perform signal conversion on the voltage signal; the amplifying unit is used to amplify the signal transmitted from the input unit; and the output unit is used to output the amplified signal to a subsequent circuit.

[0008] As some sub-solutions of the above technical solution, the input unit includes a positive input terminal VIN, a negative input terminal VIP, a first field effect transistor M1 and a second field effect transistor M2; the gate of the first field effect transistor M1 is connected to the positive input terminal VIN, the gate of the second field effect transistor M2 is connected to the negative input terminal VIP, the drain of the first field effect transistor M1 is connected to the source of the second field effect transistor M2 and the first bias unit; the source of the first field effect transistor M1 is connected to the amplification unit, and the drain of the second field effect transistor M2 is connected to the amplification unit.

[0009] As some sub-solutions of the above technical solution, the amplifying unit includes a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11 and a power supply voltage terminal; the source of the eighth field effect transistor M8 is connected to the source of the ninth field effect transistor M9 and the power supply voltage terminal; the gate of the eighth field effect transistor M8 is connected to the gate of the ninth field effect transistor M9, the drain of the tenth field effect transistor M10 and the output unit; the drain of the eighth field effect transistor M8 is connected to the source of the tenth field effect transistor M10; the drain of the ninth field effect transistor M9 is connected to the drain of the eleventh field effect transistor M11; the gate of the tenth field effect transistor M10 is connected The gate is connected to the gate of the eleventh field effect transistor M11; the source of the eleventh field effect transistor M11 is connected to the output unit; the drain of the sixth field effect transistor M6 is connected to the output unit, the gate of the fourth field effect transistor M4 and the gate of the fifth field effect transistor M5; the gate of the sixth field effect transistor M6 is connected to the gate of the seventh field effect transistor M7; the source of the sixth field effect transistor M6 is connected to the source of the first field effect transistor M1 and the drain of the fourth field effect transistor M4; the source of the fourth field effect transistor M4 is grounded; the drain of the seventh field effect transistor M7 is connected to the output unit, the source of the seventh field effect transistor M7 is connected to the drain of the second field effect transistor M2 and the drain of the fifth field effect transistor M5; the source of the fifth field effect transistor M5 is grounded.

[0010] As some sub-solutions of the above technical solution, the output unit includes an offset adjustment terminal VC, an output terminal VOUT, a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a twenty-second field effect transistor M22 and a twenty-third field effect transistor M23; the source of the twelfth field effect transistor M12 is connected to the drain of the tenth field effect transistor M10 and the drain of the thirteenth field effect transistor M13, the gate of the twelfth field effect transistor M12 is connected to the gate of the fourteenth field effect transistor M14 and the first bias unit, the drain of the twelfth field effect transistor M12 is connected to the source of the thirteenth field effect transistor M13 and the drain of the sixth field effect transistor M6; the gate of the thirteenth field effect transistor M13 is connected to the fifteenth field effect transistor The gate of the 14th field-effect transistor M14 is connected to the source of the 11th field-effect transistor M11, the drain of the 15th field-effect transistor M15, and the gate of the 22nd field-effect transistor M22; the drain of the 14th field-effect transistor M14 is connected to the source of the 15th field-effect transistor M15, the drain of the 7th field-effect transistor M7, the gate of the 23rd field-effect transistor M23, and the offset adjustment terminal VC; the offset adjustment terminal VC is connected to the offset cancellation unit; the source of the 22nd field-effect transistor M22 is connected to the power supply voltage terminal, the drain of the 22nd field-effect transistor M22 is connected to the drain of the 23rd field-effect transistor M23 and the output terminal VOUT; the source of the 23rd field-effect transistor M23 is grounded.

[0011] As some sub-solutions of the above technical solution, the offset cancellation unit includes a second bias unit and a branch combination unit; the second bias unit is connected to the branch combination unit, and the branch combination unit is connected to the offset adjustment terminal VC; the second bias unit is used to provide a bias current and a bias voltage for the branch combination unit; the branch combination unit injects or extracts current into or from the operational amplifier unit by controlling the conduction and cutoff of each current branch within it.

[0012] As some sub-solutions of the above technical solution, the branch combination unit includes a forty-eighth field-effect transistor M48, a forty-ninth field-effect transistor M49 and at least one current branch; the source of the forty-eighth field-effect transistor M48 is connected to the power supply voltage end, the gate of the forty-eighth field-effect transistor M48 is connected to the second bias unit, the drain of the forty-eighth field-effect transistor M48 is connected to the drain of the forty-ninth field-effect transistor M49, the gate of the forty-ninth field-effect transistor M49 is connected to the second bias unit, and the source of the forty-ninth field-effect transistor M49 is connected to the offset adjustment end VC and the input end of the current branch; the control end of the current branch is connected to the second bias unit.

[0013] As some sub-solutions of the above technical solution, the sampling unit 1 includes a transistor IGBT, a sampling resistor RS, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; one end of the sampling resistor RS is connected to the emitter of the transistor IGBT and one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth resistor and the positive input terminal VIN of the operational amplifier unit 2; the other end of the sampling resistor RS is connected to one end of the first resistor R1 and ground; the other end of the first resistor R1 is connected to the negative input terminal VIP of the operational amplifier unit 2 and one end of the second resistor R2; and the other end of the second resistor R2 is connected to the output terminal VOUT of the operational amplifier unit 2.

[0014] A second aspect of the present invention provides a PCB board, on which any of the above-described current sampling circuits is printed.

[0015] The PCB board according to the embodiment of the second aspect of the present invention also has corresponding beneficial effects because it includes the current sampling circuit of the above technical solution.

[0016] A third aspect of the present invention provides a chip, which uses any of the above-mentioned current sampling circuits to achieve operation control.

[0017] The chip according to the embodiment of the third aspect of the present invention also has corresponding beneficial effects because it includes the current sampling circuit of the above technical solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which:

[0019] Figure 1 A circuit block diagram of the current sampling circuit provided by the present invention;

[0020] Figure 2 An application circuit diagram of the current sampling circuit provided by the present invention;

[0021] Figure 3 An application circuit diagram of the operational amplifier unit 2 provided by the present invention;

[0022] Figure 4 This is an application circuit diagram of the offset cancellation unit 3 provided by the present invention.

[0023] In the accompanying drawings: 1-sampling unit; 2-operational amplifier unit; 3-offset cancellation unit. DETAILED DESCRIPTION

[0024] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0025] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0026] In the description of the present invention, "several" means an indefinite quantity, "multiple" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, and "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" is solely for the purpose of distinguishing technical features and should not be understood to indicate or imply relative importance, or to implicitly indicate the number or order of the technical features indicated. "And / or" throughout the text represents three parallel solutions. For example, "A and / or B" means a solution where A satisfies, a solution where B satisfies, or a solution where both A and B satisfy.

[0027] In the description of the present invention, if there is a short sentence containing multiple parallel features, the attributive defines the closest feature. For example, "B, C, and E are arranged on A, and are connected to D" means that B is arranged on A and E is connected to D, and does not constitute a limitation on C. However, attributives that express the relationship between features, such as "spaced arrangement" or "circular arrangement", do not fall into this category. If the word "all" is preceded by an attributive, it means that all features in the short sentence are limited. For example, "B, C, and D are all arranged on A" means that B, C, and D are all arranged on A. In a sentence with an omitted subject, the omitted subject is the subject of the previous sentence, that is, "B is arranged on A, including C" means that B is arranged on A and A includes C.

[0028] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0029] The following combination Figures 1 to 4 Embodiments of the present invention are described.

[0030] A current sampling circuit in this embodiment includes: an operational amplifier unit 2, a sampling unit 1, and an offset cancellation unit 3; the sampling unit 1 is electrically connected to the operational amplifier unit 2, and the offset cancellation unit 3 is electrically connected to the operational amplifier unit 2; the sampling unit 1 is used to obtain a voltage signal of a measured current; the operational amplifier unit 2 is used to amplify the voltage signal obtained by the sampling unit 1; and the offset cancellation unit 3 is used to provide a compensation current to the operational amplifier unit 2 to eliminate the offset voltage of the operational amplifier unit 2.

[0031] In the first embodiment of the present invention, sampling unit 1 is responsible for acquiring the voltage signal of the measured current, providing raw data for the entire sampling process; operational amplifier unit 2 amplifies the voltage signal transmitted by sampling unit 1 for subsequent circuit processing and analysis; and offset cancellation unit 3 works closely with operational amplifier unit 2 to monitor the offset of operational amplifier unit 2 in real time. When an offset voltage appears in operational amplifier unit 2, offset cancellation unit 3 responds quickly and accurately provides a compensation current to it, effectively offsetting the negative impact of the offset voltage in operational amplifier unit 2 and ensuring that operational amplifier unit 2 stably and accurately amplifies the signal. The three units work closely together to ultimately output a high-precision sampling result, providing accurate current data for the system.

[0032] Specifically, the operational amplifier unit 2 includes a first bias unit, an input unit, an amplifying unit and an output unit; the input unit is connected to the amplifying unit, and the amplifying unit is connected to the output unit; the first bias unit is connected to the input unit and the output unit; the first bias unit is used to provide a bias voltage and a bias current for the input unit and the output unit; the input unit is used to receive the voltage signal output by the sampling unit 1 and perform signal conversion on the voltage signal, the amplifying unit is used to amplify the signal transmitted from the input unit, and the output unit is used to output the amplified signal to a subsequent circuit.

[0033] In this embodiment, the first bias unit provides appropriate bias voltage and bias current for the input unit, the amplification unit, and the output unit, determines the static operating point of active devices such as transistors in each unit, so that these devices can operate in a suitable linear region; the input unit serves as the first processing stage of the operational amplifier unit 2, converting the received signal into a signal form suitable for processing by the amplification unit; the amplification unit then amplifies the signal transmitted from the input unit, amplifies the weak input signal, and increases the amplitude of the signal so that it can be effectively detected and processed in the subsequent circuit; the output unit is responsible for outputting the amplified signal to the subsequent circuit.

[0034] Specifically, see Figure 3The input unit includes a positive input terminal VIN, a negative input terminal VIP, a first field effect transistor M1, and a second field effect transistor M2; the gate of the first field effect transistor M1 is connected to the positive input terminal VIN, the gate of the second field effect transistor M2 is connected to the negative input terminal VIP, the drain of the first field effect transistor M1 is connected to the source of the second field effect transistor M2 and the first bias unit; the source of the first field effect transistor M1 is connected to the amplification unit, and the drain of the second field effect transistor M2 is connected to the amplification unit.

[0035] In this embodiment, the positive input terminal VIN and the negative input terminal VIP respectively receive voltage signals from the sampling unit 1; the first field-effect transistor M1 and the second field-effect transistor M2 form a differential pair structure. The gate of the first field-effect transistor M1 is connected to the positive input terminal VIN, and the gate of the second field-effect transistor M2 is connected to the negative input terminal VIP. When there is a voltage difference between the positive input terminal VIN and the negative input terminal VIP, the conduction state of the first field-effect transistor M1 and the second field-effect transistor M2 changes. This differential input method can effectively suppress common-mode signals and only amplify differential-mode signals, thereby improving the circuit's anti-interference ability and signal processing accuracy. The source of the first field-effect transistor M1 is connected to the amplification unit, and the drain of the second field-effect transistor M2 is also connected to the amplification unit, thereby transmitting the result of the differential processing of the input signal to the amplification unit for further amplification.

[0036] Specifically, see Figure 3The amplifying unit includes a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11 and a power supply voltage terminal; the source of the eighth field effect transistor M8 is connected to the source of the ninth field effect transistor M9 and the power supply voltage terminal; the gate of the eighth field effect transistor M8 is connected to the gate of the ninth field effect transistor M9, the drain of the tenth field effect transistor M10 and the output unit; the drain of the eighth field effect transistor M8 is connected to the source of the tenth field effect transistor M10; the drain of the ninth field effect transistor M9 is connected to the drain of the eleventh field effect transistor M11; the gate of the tenth field effect transistor M10 is connected to the gate of the tenth field effect transistor M11; The gate of the field effect transistor M11 is connected; the source of the eleventh field effect transistor M11 is connected to the output unit; the drain of the sixth field effect transistor M6 is connected to the output unit, the gate of the fourth field effect transistor M4 and the gate of the fifth field effect transistor M5; the gate of the sixth field effect transistor M6 is connected to the gate of the seventh field effect transistor M7; the source of the sixth field effect transistor M6 is connected to the source of the first field effect transistor M1 and the drain of the fourth field effect transistor M4; the source of the fourth field effect transistor M4 is grounded; the drain of the seventh field effect transistor M7 is connected to the output unit, and the source of the seventh field effect transistor M7 is connected to the drain of the second field effect transistor M2 and the drain of the fifth field effect transistor M5; the source of the fifth field effect transistor M5 is grounded.

[0037] In this embodiment, the fourth field-effect transistor M4, the fifth field-effect transistor M5, the sixth field-effect transistor M6, and the seventh field-effect transistor M7 form a low-voltage current mirror structure. The eighth field-effect transistor M8, the ninth field-effect transistor M9, the tenth field-effect transistor M10, and the eleventh field-effect transistor M11 also form a low-voltage current mirror structure, which serve as a common-source and common-gate active load. The common-source and common-gate structure combination increases the equivalent impedance of the output end. In the amplifier circuit, the higher the output impedance, the greater the change in output voltage for the same input signal change, thereby increasing the voltage gain. The input unit transmits the processed signal to the fourth field-effect transistor M4 and the fifth field-effect transistor M5, causing their current to change. The low-voltage current mirror structure composed of the fourth field-effect transistor M4, the fifth field-effect transistor M5, the sixth field-effect transistor M6 and the seventh field-effect transistor M7 replicates and transmits this current change, and at the same time uses the high output impedance characteristics of the common-source common-gate structure to achieve preliminary signal amplification; the low-voltage current mirror structure composed of the eighth field-effect transistor M8, the ninth field-effect transistor M9, the tenth field-effect transistor M10 and the eleventh field-effect transistor M11 further enhances this amplification effect and transmits the amplified signal to the output unit.

[0038] Specifically, see Figure 3The output unit includes an offset adjustment terminal VC, an output terminal VOUT, a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a twenty-second field effect transistor M22, and a twenty-third field effect transistor M23; the source of the twelfth field effect transistor M12 is connected to the drain of the tenth field effect transistor M10 and the drain of the thirteenth field effect transistor M13, the gate of the twelfth field effect transistor M12 is connected to the gate of the fourteenth field effect transistor M14 and the first bias unit, the drain of the twelfth field effect transistor M12 is connected to the source of the thirteenth field effect transistor M13 and the drain of the sixth field effect transistor M6; the gate of the thirteenth field effect transistor M13 is connected to the gate of the fifteenth field effect transistor M15 and the gate of the first bias unit. The first bias unit is connected; the source of the fourteenth field-effect transistor M14 is connected to the source of the eleventh field-effect transistor M11, the drain of the fifteenth field-effect transistor M15 and the gate of the twenty-second field-effect transistor M22; the drain of the fourteenth field-effect transistor M14 is connected to the source of the fifteenth field-effect transistor M15, the drain of the seventh field-effect transistor M7, the gate of the twenty-third field-effect transistor M23 and the offset adjustment terminal VC; the offset adjustment terminal VC is connected to the offset cancellation unit 3; the source of the twenty-second field-effect transistor M22 is connected to the power supply voltage terminal, the drain of the twenty-second field-effect transistor M22 is connected to the drain of the twenty-third field-effect transistor M23 and the output terminal VOUT; the source of the twenty-third field-effect transistor M23 is grounded.

[0039] In this embodiment, the twelfth field-effect transistor M12 and the thirteenth field-effect transistor M13 act as floating current sources to provide a quiescent current that is insensitive to the power supply voltage to the twenty-second field-effect transistor M22 and the twenty-third field-effect transistor M23. When the power supply voltage fluctuates, the twelfth field-effect transistor M12 and the thirteenth field-effect transistor M13 can automatically adjust their own currents to maintain a stable quiescent current of the output transistor, thereby ensuring the stability of the output stage operation.

[0040] The fourteenth field effect transistor M14 and the fifteenth field effect transistor M15 serve as floating Class AB bias transistors to provide appropriate bias for the twenty-second field effect transistor M22 and the twenty-third field effect transistor M23, so that the difference in gate voltage between the twenty-second field effect transistor M22 and the twenty-third field effect transistor M23 remains constant;

[0041] The offset adjustment terminal VC is connected to the offset cancellation unit 3. When an offset is detected in the operational amplifier, the offset cancellation unit 3 changes the current injected into or extracted from the twenty-third field-effect transistor M23 through the offset adjustment terminal VC, thereby optimizing the operating point of the output transistor, compensating for the influence of the offset voltage, and ensuring the accuracy of the output signal.

[0042] The twenty-second field-effect transistor M22 and the twenty-third field-effect transistor M23 form a push-pull output structure, wherein the source of the twenty-second field-effect transistor M22 is connected to the power supply voltage terminal, and the source of the twenty-third field-effect transistor M23 is grounded. When the input signal causes the gate voltage of the twenty-second field-effect transistor M22 to decrease, the twenty-second field-effect transistor M22 turns on, transmitting the power supply voltage terminal signal to the output terminal VOUT. When the input signal causes the gate voltage of the twenty-third field-effect transistor M23 to increase, the twenty-third field-effect transistor M23 turns on, transmitting the ground signal to the output terminal VOUT. This push-pull output structure can significantly improve the driving capability of the output unit, quickly providing or absorbing current for the load, ensuring that the output signal can effectively drive subsequent circuits and meet the requirements of different loads.

[0043] The signal processed by the amplification unit is first transmitted to the bias and signal transmission network consisting of the twelfth field-effect transistor M12, the thirteenth field-effect transistor M13, the fourteenth field-effect transistor M14, and the fifteenth field-effect transistor M15. The twelfth field-effect transistor M12 and the thirteenth field-effect transistor M13 act as floating current sources to stabilize the quiescent current of the output transistor, and the fourteenth field-effect transistor M14 and the fifteenth field-effect transistor M15 act as floating Class AB bias transistors to optimize the output transistor bias. At the same time, the offset cancellation unit 3 compensates for the offset voltage through the offset adjustment terminal VC. Finally, the twenty-second field-effect transistor M22 and the twenty-third field-effect transistor M23 output the amplified signal through a push-pull output structure based on the adjusted bias state, providing a stable, accurate signal with sufficient driving capability for subsequent circuits.

[0044] Specifically, the output unit further includes a fifth resistor R5, a sixth resistor R6, a first capacitor C1, and a second capacitor C2; one end of the fifth resistor R5 is connected to the gate of the twenty-second field effect transistor M22, and the other end thereof is connected to one end of the first capacitor C1; the other end of the first capacitor is connected to the drain of the twenty-second field effect transistor M22; one end of the sixth resistor R6 is connected to the gate of the twenty-third field effect transistor M23, and the other end thereof is connected to one end of the first capacitor C2; the other end of the first capacitor is connected to the drain of the twenty-second field effect transistor M22; the fifth resistor R5 and the first capacitor C1, the sixth resistor R6 are connected to the gate of the twenty-third field effect transistor M23, and the other end thereof is connected to one end of the first capacitor C2; the other end of the first capacitor is connected to the drain of the twenty-second field effect transistor M22; Resistor R6 and the second capacitor C2 act as Miller compensation to ensure the stability of the circuit; taking the fifth resistor R5 and the first capacitor C1 as an example, when the signal frequency is low, the first capacitor C1 presents high impedance and has little impact on the signal. The circuit mainly operates according to normal amplification characteristics. As the signal frequency increases, the impedance of the first capacitor C1 gradually decreases, introducing an additional pole and zero point. The pole will accelerate the rate of gain decrease of the circuit, while the zero point can partially offset the phase lag caused by the pole, thereby improving the phase margin of the circuit; the fifth resistor R5 can adjust the position of the pole and zero point to further optimize the frequency response.

[0045] Specifically, the first bias unit includes a third field effect transistor M3, a sixteenth field effect transistor M16, a seventeenth field effect transistor M17, a twentieth field effect transistor M20, and a twenty-first field effect transistor M21; the source of the third field effect transistor M3 is connected to the power supply voltage terminal, and the drain of the third field effect transistor M3 is connected to the drain of the first field effect transistor M1 and the source of the second field effect transistor M2; the bias current of the third field effect transistor M3 provides a suitable operating point for the first field effect transistor M1 and the second field effect transistor M2, ensuring that they are in a good linear region when amplifying the signal, and obtaining a common mode voltage range of the ground potential, so that the operational amplifier unit 2 can process input signals close to the ground potential, meeting the working requirement that the input common mode range is close to the ground potential when the IGBT is turned on; the source of the sixteenth field effect transistor M16 is connected to the power supply voltage terminal. The first and second field-effect transistors M16 and M17 are connected to a voltage terminal, with their gate connected to their drain and the source of the seventeenth field-effect transistor M17; the gate connected to the seventeenth field-effect transistor M17 and its drain and the gate of the fourteenth field-effect transistor M14; the gate connected to the twentieth field-effect transistor M20 and its drain and the gate of the fifteenth field-effect transistor M15; the source of the twentieth field-effect transistor M20 is connected to the drain of the twenty-first field-effect transistor M21 and the gate of the twenty-first field-effect transistor M21, and the source of the twenty-first field-effect transistor M21 is grounded; the sixteenth field-effect transistor M16 and the seventeenth field-effect transistor M17, the twentieth field-effect transistor M20 and the twenty-first field-effect transistor M21 respectively form two current mirror structures to provide bias voltages for the twelfth field-effect transistor M12, the thirteenth field-effect transistor M13, the fourteenth field-effect transistor M14 and the fifteenth field-effect transistor M15.

[0046] Specifically, the offset cancellation unit 3 includes a second bias unit and a branch combination unit; the second bias unit is connected to the branch combination unit, and the branch combination unit is connected to the offset adjustment terminal VC; the second bias unit is used to provide a bias current and a bias voltage for the branch combination unit; the branch combination unit injects or extracts current into or from the operational amplifier unit 2 by controlling the conduction and cutoff of each current branch within it.

[0047] In this embodiment, the second bias unit continuously provides a stable bias current and voltage to the branch combination unit. When the operational amplifier unit 2 has an offset, the external control circuit generates a control signal to control the conduction and cutoff of each current branch in the branch combination unit. The branch combination unit injects or extracts current into or out of the operational amplifier unit 2 through the offset adjustment terminal VC according to the control signal, continuously adjusts the working state of the operational amplifier unit 2, and gradually eliminates the influence of the offset voltage, so that the operational amplifier unit 2 can amplify the signal more accurately, thereby improving the accuracy of the current sampling circuit.

[0048] Specifically, see Figure 4The branch combination unit includes a forty-eighth field-effect transistor M48, a forty-ninth field-effect transistor M49, and at least one current branch; the source of the forty-eighth field-effect transistor M48 is connected to the power supply voltage terminal, the gate of the forty-eighth field-effect transistor M48 is connected to the second bias unit, the drain of the forty-eighth field-effect transistor M48 is connected to the drain of the forty-ninth field-effect transistor M49, the gate of the forty-ninth field-effect transistor M49 is connected to the second bias unit, the source of the forty-ninth field-effect transistor M49 is connected to the offset adjustment terminal VC and the input terminal of the current branch; and the control terminal of the current branch is connected to the second bias unit.

[0049] Specifically, see Figure 4 The second bias unit includes a 50th field effect transistor M50, a 50th field effect transistor M51, a 52nd field effect transistor M52, a 53rd field effect transistor M53, a 54th field effect transistor M54 and a 55th field effect transistor M55; the source of the 55th field effect transistor M55 is connected to the power supply voltage terminal, the drain of the 55th field effect transistor M55 is connected to the gate of the 55th field effect transistor M55 and the source of the 54th field effect transistor M54; the drain of the 54th field effect transistor M54 is connected to the gate of the 54th field effect transistor M54 and the drain of the 53rd field effect transistor M53; the 53rd field effect transistor M55 is connected to the gate of the 54th field effect transistor M54 and the drain of the 53rd field effect transistor M53; the 55th ... The source of the field effect transistor M53 is connected to the drain of the fifty-second field effect transistor M52, and the gate of the fifty-third field effect transistor M53 is connected to the drain of the fiftieth field effect transistor M50; the gate of the fiftieth field effect transistor M50 is connected to the power supply voltage terminal; the source of the fifty-third field effect transistor M53 is connected to the drain of the fifty-second field effect transistor M52; the source of the fiftieth field effect transistor M50 is connected to the drain of the fifty-first field effect transistor M51, the gate of the fifty-first field effect transistor M51 and the gate of the fifty-second field effect transistor M52, and the source of the fifty-first field effect transistor M51 and the source of the fifty-second field effect transistor M52 are grounded.

[0050] Specifically, see Figure 4The current branch includes a first current branch consisting of the twenty-seventh field-effect transistor M27, the thirty-fourth field-effect transistor M34, and the forty-first field-effect transistor M41; a second current branch consisting of the twenty-eighth field-effect transistor M28, the thirty-fifth field-effect transistor M35, and the forty-second field-effect transistor M42; a third current branch consisting of the twenty-ninth field-effect transistor M29, the thirty-sixth field-effect transistor M36, and the forty-third field-effect transistor M43; a fourth current branch consisting of the thirtieth field-effect transistor M30, the thirty-seventh field-effect transistor M37, and the forty-fourth field-effect transistor M44; a fifth current branch consisting of the thirty-first field-effect transistor M31, the thirty-eighth field-effect transistor M38, and the forty-fifth field-effect transistor M45; a sixth current branch consisting of the thirty-second field-effect transistor M32, the thirty-ninth field-effect transistor M39, and the forty-sixth field-effect transistor M46; and a seventh current branch consisting of the thirty-third field-effect transistor M33, the fortieth field-effect transistor M40, and the forty-seventh field-effect transistor M47.

[0051] Taking the first current branch as an example, the drain of the forty-first field-effect transistor M41 is connected to the offset adjustment terminal VC and the source of the forty-ninth field-effect transistor M49, the gate of the forty-first field-effect transistor M41 is connected to the external control signal, the source of the forty-first field-effect transistor M41 is connected to the drain of the thirty-fourth field-effect transistor M34, the gate of the thirty-fourth field-effect transistor M34 is connected to the gate of the fiftieth field-effect transistor M50, the source of the thirty-fourth field-effect transistor M34 is connected to the drain of the twenty-seventh field-effect transistor M27, the gate G1 of the field-effect transistor is connected to the gate of the fifty-first field-effect transistor M51, and the source of the twenty-seventh field-effect transistor M27 is grounded.

[0052] In this embodiment, the working logic of the offset cancellation unit 3 is as follows:

[0053] The fiftieth field effect transistor M50, the fifty-first field effect transistor M51, the fifty-second field effect transistor M52, the fifty-third field effect transistor M53, the fifty-fourth field effect transistor M54 and the fifty-fifth field effect transistor M55 provide cascode bias for the branch combination unit;

[0054] The source of the forty-eighth field-effect transistor M48 is connected to the power supply voltage terminal, the gate of the forty-fifth field-effect transistor M55 is connected to obtain the bias voltage Vb3, and the drain of the forty-ninth field-effect transistor M49 is connected. The gate of the forty-ninth field-effect transistor M49 is connected to the fifty-fourth field-effect transistor M54 to obtain the bias voltage Vb4, and the source of the forty-ninth field-effect transistor M49 is connected to the offset adjustment terminal VC and all current branches. Under the action of the bias voltage, the forty-eighth field-effect transistor M48 and the forty-ninth field-effect transistor M49 are in a suitable conduction state, providing a path for current conduction between the current branches and the offset adjustment terminal VC.

[0055] The seven current branches have the same structure. Taking the first current branch as an example, the 41st field-effect transistor M41 serves as a switch transistor, and its gate is connected to an external control signal to control the conduction and cutoff of the branch. When the corresponding bit of the control signal is at a high level, the 41st field-effect transistor M41 is turned on, and current can flow through the 48th field-effect transistor M48 and the 49th field-effect transistor M49 through the current branch. When the corresponding bit of the control signal is at a low level, the 41st field-effect transistor M41 is turned off, and no current flows through the current branch. The gate of the 34th field-effect transistor M34 is connected to the drain of the 50th field-effect transistor M50 to obtain the bias voltage Vb2, and the gate of the 27th field-effect transistor M27 is connected to the drain of the 50th field-effect transistor M51 to obtain the bias voltage Vb1, ensuring that the field-effect transistors in the current branch operate in the appropriate state and generate stable current.

[0056] The 7-bit binary control signal D<7:0> is used to precisely control the on / off combination of the seven current branches, thereby injecting or extracting currents of different magnitudes into or from the operational amplifier unit 2 to eliminate the offset voltage; <0> Control the first current branch, D <1> Control the second current branch, and so on, D <6> Controlling the seventh current branch; each current branch has a different current weight, with I as the reference current. The weighted current of the first current branch is I, the weighted current of the second current branch is 2I, the weighted current of the third current branch is 4I, the weighted current of the fourth current branch is 8I, the weighted current of the fifth current branch is 16I, the weighted current of the sixth current branch is 32I, and the weighted current of the seventh current branch is 64I. This design enables the branch combination unit to output currents of different magnitudes through different combinations of control signals;

[0057] When operational amplifier unit 2 has an offset voltage, a corresponding 7-bit binary control signal D<7:0> is output to the current branch unit based on the deviation. When control signal D<7:0> is equal to 1000000, no current is injected or extracted from operational amplifier unit 2, and operational amplifier unit 2 is in a balanced state. When D<7:0> is greater than 1000000, the current extracted from operational amplifier unit 2 is greater than the input current, and the operating state of operational amplifier unit 2 is adjusted by extracting current from operational amplifier unit 2. When D<7:0> is less than 1000000, the current injected into the operational amplifier unit 2 is greater than the current drawn, and the offset voltage of the operational amplifier unit 2 is compensated by the injected current. For example, assuming that a compensation current of 13I is required to be injected into the operational amplifier unit 2, the control signal D<7:0> is 0001101, that is, the first, third, and fourth current branches are turned on, and the other branches are turned off. These turned-on current branches jointly generate a current of 13I, which is injected into the offset adjustment terminal VC. The current is then injected into the operational amplifier unit 2 through the offset adjustment terminal VC to adjust the operational amplifier unit 2 until the offset voltage is eliminated.

[0058] In summary, the offset cancellation unit 3 provides a stable bias through the second bias unit, and the branch combination unit flexibly controls the conduction and cutoff of the current branch according to the 7-bit binary control signal, thereby effectively eliminating the offset voltage of the operational amplifier unit 2 and ensuring the high-precision operation of the circuit.

[0059] Specifically, the sampling unit 1 includes a transistor IGBT, a sampling resistor RS, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; one end of the sampling resistor RS is connected to the emitter of the transistor IGBT and one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth resistor and the positive input terminal VIN of the operational amplifier unit 2; the other end of the sampling resistor RS is connected to one end of the first resistor R1 and ground; the other end of the first resistor R1 is connected to the negative input terminal VIP of the operational amplifier unit 2 and one end of the second resistor R2; the other end of the second resistor R2 is connected to the output terminal VOUT of the operational amplifier unit 2.

[0060] In this embodiment, the sampling resistor RS is connected to the emitter of the transistor IGBT under test to convert the current signal of the transistor IGBT into a voltage signal. The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the operational amplifier unit 2 together constitute a differential detection circuit, which suppresses the common-mode signal at both ends of the sampling resistor RS and only extracts the differential-mode voltage, effectively eliminating common-mode signal interference and improving detection accuracy.

[0061] A second aspect of the present invention provides a PCB board, on which any of the above-described current sampling circuits is printed.

[0062] A third aspect of the present invention provides a chip, which uses any of the above-mentioned current sampling circuits to achieve operation control.

[0063] The above specifically describes the preferred embodiments of the present invention, but the present disclosure is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.

Claims

1. A current sampling circuit, characterized in that: include: An operational amplifier unit, a sampling unit and an offset cancellation unit; the sampling unit is electrically connected to the operational amplifier unit, and the offset cancellation unit is electrically connected to the operational amplifier unit; the sampling unit is used to obtain a voltage signal of a measured current; the operational amplifier unit is used to amplify the voltage signal obtained by the sampling unit; the offset cancellation unit is used to provide a compensation current for the operational amplifier unit to eliminate the offset voltage of the operational amplifier unit.

2. The current sampling circuit according to claim 1, wherein: The operational amplifier unit includes a first bias unit, an input unit, an amplifying unit, and an output unit; the input unit is connected to the amplifying unit, and the amplifying unit is connected to the output unit; the first bias unit is connected to the input unit and the output unit; The first bias unit is used to provide bias voltage and bias current for the input unit and the output unit; the input unit is used to receive the voltage signal output by the sampling unit and perform signal conversion on the voltage signal; the amplification unit is used to amplify the signal transmitted from the input unit; and the output unit is used to output the amplified signal to a subsequent circuit.

3. The current sampling circuit according to claim 2, wherein: The input unit includes a positive input terminal VIN, a negative input terminal VIP, a first field effect transistor M1, and a second field effect transistor M2; the gate of the first field effect transistor M1 is connected to the positive input terminal VIN, the gate of the second field effect transistor M2 is connected to the negative input terminal VIP, the drain of the first field effect transistor M1 is connected to the source of the second field effect transistor M2 and the first bias unit; the source of the first field effect transistor M1 is connected to the amplification unit, and the drain of the second field effect transistor M2 is connected to the amplification unit.

4. The current sampling circuit according to claim 3, wherein: The amplifying unit includes a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11 and a power supply voltage terminal; The source of the eighth field effect transistor M8 is connected to the source of the ninth field effect transistor M9 and the power supply voltage terminal; the gate of the eighth field effect transistor M8 is connected to the gate of the ninth field effect transistor M9, the drain of the tenth field effect transistor M10 and the output unit; the drain of the eighth field effect transistor M8 is connected to the source of the tenth field effect transistor M10; the drain of the ninth field effect transistor M9 is connected to the drain of the eleventh field effect transistor M11; the gate of the tenth field effect transistor M10 is connected to the gate of the eleventh field effect transistor M11; the source of the eleventh field effect transistor M11 is connected to the output unit; the sixth field effect transistor M8 is connected to the gate of the ninth field effect transistor M9, the drain of the tenth field effect transistor M10 and ... source of the eleventh field effect transistor M11 is connected to the output unit; the sixth field effect transistor M8 is connected to the gate of the ninth field effect transistor M9. The drain of the field effect transistor M6 is connected to the output unit, the gate of the fourth field effect transistor M4, and the gate of the fifth field effect transistor M5; the gate of the sixth field effect transistor M6 is connected to the gate of the seventh field effect transistor M7; the source of the sixth field effect transistor M6 is connected to the source of the first field effect transistor M1 and the drain of the fourth field effect transistor M4; the source of the fourth field effect transistor M4 is grounded; the drain of the seventh field effect transistor M7 is connected to the output unit, and the source of the seventh field effect transistor M7 is connected to the drain of the second field effect transistor M2 and the drain of the fifth field effect transistor M5; the source of the fifth field effect transistor M5 is grounded.

5. The current sampling circuit according to claim 4, wherein: The output unit includes an offset adjustment terminal VC, an output terminal VOUT, a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a twenty-second field effect transistor M22, and a twenty-third field effect transistor M23; the source of the twelfth field effect transistor M12 is connected to the drain of the tenth field effect transistor M10 and the drain of the thirteenth field effect transistor M13, the gate of the twelfth field effect transistor M12 is connected to the gate of the fourteenth field effect transistor M14 and the first bias unit, the drain of the twelfth field effect transistor M12 is connected to the source of the thirteenth field effect transistor M13 and the drain of the sixth field effect transistor M6; the gate of the thirteenth field effect transistor M13 is connected to the fifteenth field effect transistor M10. The gate of the MOSFET M15 is connected to the first bias unit; the source of the fourteenth MOSFET M14 is connected to the source of the eleventh MOSFET M11, the drain of the fifteenth MOSFET M15, and the gate of the twenty-second MOSFET M22; the drain of the fourteenth MOSFET M14 is connected to the source of the fifteenth MOSFET M15, the drain of the seventh MOSFET M7, the gate of the twenty-third MOSFET M23, and the offset adjustment terminal VC; the offset adjustment terminal VC is connected to the offset cancellation unit; the source of the twenty-second MOSFET M22 is connected to the power supply voltage terminal, and the drain of the twenty-second MOSFET M22 is connected to the drain of the twenty-third MOSFET M23 and the output terminal VOUT; The source of the twenty-third field effect transistor M23 is grounded.

6. The current sampling circuit according to claim 5, characterized in that: The offset cancellation unit includes a second bias unit and a branch combination unit; the second bias unit is connected to the branch combination unit, and the branch combination unit is connected to the offset adjustment terminal VC; the second bias unit is used to provide a bias current and a bias voltage for the branch combination unit; the branch combination unit injects or extracts current into or from the operational amplifier unit by controlling the conduction and cutoff of each current branch within it.

7. The current sampling circuit according to claim 6, wherein: The branch combination unit includes a forty-eighth field effect transistor M48, a forty-ninth field effect transistor M49 and at least one current branch; The source of the forty-eighth field-effect transistor M48 is connected to the power supply voltage terminal, the gate of the forty-eighth field-effect transistor M48 is connected to the second bias unit, the drain of the forty-eighth field-effect transistor M48 is connected to the drain of the forty-ninth field-effect transistor M49, the gate of the forty-ninth field-effect transistor M49 is connected to the second bias unit, the source of the forty-ninth field-effect transistor M49 is connected to the offset adjustment terminal VC and the input terminal of the current branch; and the control terminal of the current branch is connected to the second bias unit.

8. The current sampling circuit according to claim 4, wherein: The sampling unit includes a transistor IGBT, a sampling resistor RS, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; one end of the sampling resistor RS is connected to the emitter of the transistor IGBT and one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth resistor and the positive input terminal VIN of the operational amplifier unit; the other end of the sampling resistor RS is connected to one end of the first resistor R1 and ground; the other end of the first resistor R1 is connected to the negative input terminal VIP of the operational amplifier unit and one end of the second resistor R2; and the other end of the second resistor R2 is connected to the output terminal VOUT of the operational amplifier unit.

9. A PCB board, characterized in that: The PCB board is printed with the current sampling circuit according to any one of claims 1 to 8.

10. A chip, characterized in that: The chip uses the current sampling circuit described in any one of claims 1 to 8 to achieve operation control.

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