Chip detection device and method

Abstract

The invention discloses a chip detection device and method, relates to the field of detection, and is used for solving the problem of low chip detection efficiency in the prior art. The device comprises a detection chip with a control module and a connector, the connector is used for being connected with a first end of a to-be-detected chip, a first sub-loop is formed through the connector and the detection chip, and the control module is used for sending a control signal to the to-be-detected chip through the connector and sending the control signal to the to-be-detected chip. The control signal is used for triggering the chip to be detected to perform signal transmission detection of the first sub-loop, and the control module is also used for receiving a signal detection result of the first sub-loop through the connector. Through the scheme, the chip detection efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of detection, and in particular to a chip detection device and method. Background Art

[0002] With the continuous development of high-speed data transmission systems, retimer cards have become critical devices for improving high-speed signal transmission quality in servers, data centers, high-performance computers, and other fields. Retimer cards typically require functional testing after production to ensure their integrity. However, current functional testing of retimer cards suffers from low efficiency.

[0003] Therefore, how to improve the detection efficiency of the chip to be tested (such as a retimer card) is a problem that needs to be solved urgently. Summary of the Invention

[0004] The present invention provides a chip detection device and method for improving the detection efficiency of a chip to be tested.

[0005] In a first aspect, the present invention provides a chip detection device, comprising a detection chip having a control module and a connector, the connector being used to connect to a first end of a chip to be tested, forming a first sub-loop through the connector and the detection chip, the control module being used to send a control signal to the chip to be tested through the connector, the control signal being used to trigger the chip to be tested to perform signal transmission detection of the first sub-loop, and the control module being further used to receive a signal detection result of the first sub-loop through the connector.

[0006] The above solution uses a test chip instead of the existing server, simplifying the test environment while also enabling comprehensive testing of the chip under test through a loopback design (the first sub-loop). The test chip sends a control signal to the chip under test via the control module, causing the chip under test to perform signal transmission testing based on the control signal. The signal detection results are then sent to the control module, allowing the test chip to determine whether the chip under test is functioning properly.

[0007] In addition, when the present invention detects the chip to be tested, after the test of one chip to be tested is completed, the next chip to be tested can be directly replaced for testing, eliminating the lengthy process of the server needing to repeatedly power off-power on-wait in the prior art, saving test time and improving test efficiency.

[0008] Optionally, a connecting chip is further included, which is connected to the second end of the chip to be tested to form a second sub-loop. The control signal is specifically used to trigger the chip to be tested to perform signal transmission detection of the first sub-loop and the second sub-loop. The control module is specifically used to receive the signal detection results of the first sub-loop and the second sub-loop.

[0009] Through the above scheme, by setting up a dual-loop structure (the first sub-loop and the second sub-loop), simultaneous detection of signals at both ends of the chip to be tested is achieved, making the detection more comprehensive. In addition, the control module can simultaneously receive the detection results of the two loops, which is conducive to comprehensive analysis of the overall performance of the chip and improves the accuracy and efficiency of detection.

[0010] Optionally, the first sub-loop and the second sub-loop form a test loop to perform signal transmission detection.

[0011] The above solution combines two sub-loops into a complete test loop, verifying the entire signal link of the test signal from one end of the chip under test to the other. This test loop structure allows the test signal to completely pass through the transmit and receive channels of the chip under test, effectively verifying the integrity of the signal transmission within the chip under test and, in turn, the connectivity of the chip under test. Furthermore, combining the two sub-loops into a large test loop is more efficient than testing the two sub-loops separately, avoiding repeated testing and saving test time.

[0012] Optionally, the detection chip is used to connect the first sending channel and the first receiving channel of the chip to be tested at the first end.

[0013] Through the above solution, by directly connecting the sending channel and receiving channel of the chip under test to form a loop, the detection signal starts from the sending channel, passes through the connector and the detection chip, and returns to the receiving channel, thus achieving a complete test of the signal transmission path. It can verify the entire process from signal sending to receiving, and facilitate accurate positioning of problems that may occur during the signal transmission process.

[0014] Optionally, the connectivity chip is configured to connect the second transmit channel and the second receive channel at the second end of the chip under test. Any transmit channel at the first end and any receive channel at the second end constitute a transmit channel within the chip under test, and any receive channel at the first end and any transmit channel at the second end constitute a receive channel within the chip under test. With this solution, the connectivity chip can independently complete loopback testing at the second end.

[0015] Optionally, the control module is further configured to send a clock signal and a reset signal to the chip under test through the connector to put the chip under test into a working state.

[0016] Through the above solution, the control module directly provides clock and reset signals, ensuring that the chip under test can enter the working state normally and that the chip can start stably. By directly providing these basic signals through the control module, the present invention simplifies the test environment, eliminates the need to rely on the server system to provide these signals, and improves the independence and efficiency of the test.

[0017] Optionally, the detection chip also includes an external interface, which is used to connect to the processor. The detection chip is also used to receive test instructions sent by the processor and send signal detection results to the processor, wherein the test instructions are used to trigger the detection chip to generate a control signal.

[0018] Through the above scheme, the communication connection between the detection chip and the processor is realized through the external interface, so that the test process can be controlled and monitored by the processor, which improves the degree of automation of the test. In addition, the processor can send test instructions and receive test results, realizing the human-computer interaction function, which is convenient for operators to control the test process and view the test results.

[0019] Optionally, the chip under test performs signal transmission detection through a pseudo-random binary sequence (PRBS).

[0020] The above scheme uses a pseudo-random binary sequence for testing, simulating various possible data transmission scenarios, improving the comprehensiveness and reliability of the test. Furthermore, due to the determinism of pseudo-random binary sequences, the receiver can predict the correct sequence. By comparing the received sequence with the locally generated sequence, the bit error rate can be accurately calculated, effectively evaluating the quality of the communication link.

[0021] In a second aspect, the present invention provides a chip detection method, comprising: connecting a chip to be tested to the chip detection device as described above, triggering the chip to be tested to perform loopback signal transmission detection through a control signal of the chip detection device and obtaining a signal detection result.

[0022] The present invention directly triggers and controls the loopback test through the chip detection device, which greatly simplifies the construction of the test environment compared to the traditional solution that relies on the server system. During the chip testing process, there is no need to equip a complete server system and complex equipment such as PCIe standard cards, which reduces the testing cost and reduces the requirements for the test environment. In addition, since the present invention adopts a loopback test method, the test results directly reflect the performance status of the chip to be tested, avoiding the interference caused by complex links and improving the accuracy of the test. At the same time, the testing process of the present invention is simple and direct, and there is no need to wait for the server to start and perform power-off and restart operations, which significantly improves the testing efficiency.

[0023] Optionally, the chip to be tested is a Retimer card, and the method further includes connecting the chip to be tested to a PCIE card and testing the PCIE card after the signal detection result indicates that the chip to be tested has passed the test.

[0024] The above solution first performs basic functional testing on the retimer card, effectively preventing problems with the retimer card itself from affecting the accuracy of PCIe card test results. This solution quickly identifies problematic retimer cards and prevents them from being used in subsequent PCIe card tests, improving overall test efficiency.

[0025] The technical effects that can be achieved from the first aspect to the second aspect can be referred to the description of the beneficial effects in the first aspect, and will not be repeated here one by one.

[0026] These implementations or other implementations of the present application will be more concise and understandable in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 A schematic diagram of a system architecture for retimer card detection provided by the prior art;

[0029] Figure 2 A schematic structural diagram of a chip detection device provided by an embodiment of the present invention;

[0030] Figure 3 A schematic structural diagram of another chip detection device provided by an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of a signal circuit for a test loop provided by an embodiment of the present invention;

[0032] Figure 5 A schematic structural diagram of another chip detection device provided by an embodiment of the present invention;

[0033] Figure 6 A schematic structural diagram of another chip detection device provided by an embodiment of the present invention;

[0034] Figure 7 A schematic diagram of a control signal provided by an embodiment of the present invention;

[0035] Figure 8 A schematic diagram of a test log provided by an embodiment of the present invention;

[0036] Figure 9 A schematic flow chart of a chip detection method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and beneficial effects of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0038] The following is an explanation of some of the terms used in this application. It should be noted that these explanations are for the purpose of facilitating understanding by those skilled in the art and do not limit the scope of protection claimed in this application.

[0039] 1. Retimer card.

[0040] A retimer card is an electronic device used to improve the quality of high-speed signal transmission. It is primarily used in servers, data centers, and high-performance computers, where high-speed data transmission is required. It realigns and enhances signals, ensuring they remain high quality over long distances. Retimer cards are typically installed on the Peripheral Component Interconnect Express (PCIe) interface to optimize data transmission performance.

[0041] 2. PCIe.

[0042] PCIe is a high-speed serial computer expansion bus standard, serving as a crucial interface for connecting computer motherboards to various hardware devices. The PCIe interface is widely used to connect hardware such as graphics cards, network cards, and storage devices. It supports various bandwidth specifications (e.g., x1, x4, x8, x16, etc.), boasts high speed and low latency, and is one of the most important internal communication standards in modern computer systems. A PCIe standard card is a device with a PCIe interface that complies with the PCIe protocol. Common examples include network cards and GPU cards. PCIe standard cards can connect and exchange data with devices such as server motherboards and PCIe expansion boards via the PCIe interface.

[0043] 3. Field-programmable gate array (FPGA).

[0044] An FPGA is a programmable integrated circuit that combines the high performance of a dedicated chip with the flexibility of software.

[0045] 4. Inter-integrated circuit (I2C).

[0046] I2C is a commonly used serial communication bus protocol that allows a master device to communicate with multiple slave devices. It is widely used in electronic devices due to its simplicity, reliability and low cost.

[0047] 5. PRBS.

[0048] PRBS is a binary sequence that appears random but is actually generated by a specific algorithm. It can be used for bit error rate testing. The transmitter sends a PRBS sequence, and the receiver compares the received sequence with the same PRBS sequence generated locally. The receiver calculates the bit error rate by counting the number of bit errors, thereby evaluating the quality of the communication link.

[0049] In the related art, the functional test of the retimer card requires the use of a complete server system, such as Figure 1 The system architecture diagram of a retimer card detection provided by the prior art is shown as follows. The server system 100 includes a server 110, a connection device 120, a retimer card 130, a PCIe expansion board 140 and a PCIe standard card 150 connected in sequence.

[0050] When performing a retimer card function test, the server 110 initiates a data request and sends a signal to the retimer card 130 through the connection device 120. The signal is transmitted to the PCIe standard card 150 via the PCIe expansion board 140, and then returns along the original route, that is, from the PCIe standard card 150 through the PCIe expansion board 140, to the retimer card 130, and finally returns to the server 110 through the connection device 120.

[0051] However, the testing methods of the prior art have the following disadvantages:

[0052] First, testing efficiency is low. After each test, the system must power down, replace the retimer card under test, and then power back on and wait for the server to enter operational status before the next test can begin. Due to the complexity of server systems, the startup process requires a series of steps, including motherboard self-test, CPU and memory initialization, and operating system loading. This waiting process consumes a significant amount of time. Only after the server is fully operational can the next retimer card test begin. This repeated power-down-power-up-wait-test cycle severely impacts retimer card testing efficiency.

[0053] Second, fault location is difficult. Due to the complexity and length of the overall link, it's difficult to pinpoint the cause and location of any issues that arise during testing. Specifically, because signals must travel back and forth through multiple components (server, connection device, retimer card, PCIe expansion card, and standard PCIe card), if a test signal fails, it's difficult to pinpoint the specific component in the link that's causing the problem.

[0054] Based on this, the present invention provides a chip detection device, which can improve detection efficiency and accurately locate faults by detecting the chip to be tested through a detection chip.

[0055] The present invention will be described in detail below with reference to the accompanying drawings.

[0056] See also Figure 2 , shows a structural schematic diagram of a chip detection device, which includes a detection chip 200 having a control module 210 and a connector 300. The connector 300 is used to connect to the first end 510 of the chip to be tested 500, and a first sub-loop is formed by the connector 300 and the detection chip 200.

[0057] Based on the above connection method, the control module 210 sends a control signal to the chip under test 500 through the connector 300, wherein the control signal is used to trigger the chip under test 500 to perform signal transmission detection of the first sub-loop. After receiving the control signal, the chip under test 500 sends a detection signal to the detection chip 200 through the connector 300. The detection signal forms a first sub-loop in the connector 300 and the detection chip 200, and then returns to the chip under test 500.

[0058] Here, the first sub-loop is as follows: the chip under test 500 sends a detection signal to the connector 300 , the detection signal is sent to the detection chip 200 through the connector 300 , passes through the detection chip 200 and then returns to the connector 300 , and finally returns to the chip under test 500 .

[0059] The control module 210 is further configured to receive the signal detection result of the first sub-loop through the connector 300. That is, the chip under test 500 determines whether the chip under test 500 is abnormal based on the sent detection signal and the received detection signal, and sends the signal detection result to the control module 210.

[0060] The detection result here may be whether the signal transmission of the chip under test 500 is normal, whether there is a link failure at both ends of the chip under test 500, or specifically whether a signal pin of the chip under test 500 is abnormal, etc., and the present invention does not limit this.

[0061] The above solution uses a detection chip instead of the existing server, which not only simplifies the test environment but also enables comprehensive detection of the chip's signals through a loopback design (the first sub-loop). The detection chip sends a control signal to the chip under test through the control module, causing the chip under test to perform signal transmission detection based on the control signal. The signal detection results are then sent to the control module, allowing the detection chip to determine whether the chip under test is functioning properly.

[0062] In addition, when the present invention detects the chip to be tested, after the test of one chip to be tested is completed, the next chip to be tested can be directly replaced for testing, eliminating the lengthy process of the server needing to repeatedly power off-power on-wait in the prior art, saving test time and improving test efficiency.

[0063] Optional, see Figure 3 , shows a schematic diagram of the structure of another chip testing device. The chip testing device also includes a communication chip 400, which is connected to the second end 520 of the chip under test 500 to form a second sub-loop. Based on this connection relationship, a control signal is used to trigger the chip under test 500 to perform signal transmission detection on the first sub-loop and the second sub-loop. The control module 210 is used to receive the signal detection results of the first and second sub-loops.

[0064] That is, after receiving the control signal, the chip under test 500 sends a first detection signal to the connector 300 at the first end 510. The first detection signal passes through the connector 300 and the detection chip 200, then returns from the detection chip 200 to the connector 300, and finally returns to the chip under test 500, forming a first sub-loop. At the second end 520, the chip under test 500 sends a second detection signal to the connectivity chip 400. The second detection signal passes through the connectivity chip 400 and returns to the chip under test 500, forming a second sub-loop. The control module 210 then receives the detection results of the first and second sub-loops.

[0065] Through the above scheme, by setting up a dual-loop structure (the first sub-loop and the second sub-loop), simultaneous detection of signals at both ends of the chip to be tested is achieved, making the detection more comprehensive. In addition, the control module can simultaneously receive the detection results of the two loops, which is conducive to comprehensive analysis of the overall performance of the chip and improves the accuracy and efficiency of detection.

[0066] The detection structure of the present invention is simple and clear. The signal at the first end of the detection chip forms a loop through the connector and the detection chip, and the signal at the second end forms a loop through the connecting chip. The two loops are independent of each other, which makes it easy to judge the signal quality at both ends of the chip to be tested separately.

[0067] Optional, please continue to Figure 3The connector 300 and the detection chip 200 are used to connect the first transmitting channel 511 of the chip under test 500 at the first end 510 to the first receiving channel 512. This connection can be achieved via a cable. Thus, the detection signal from the first transmitting channel 511 of the chip under test 500 passes through the connector 300 and the detection chip 200 and returns to the chip under test 500 at the first receiving channel 512.

[0068] Furthermore, optionally, the connector 300 is used to connect the first transmitting channel 511 of the chip under test 500 and the third receiving channel 232 of the detection chip 200, and to connect the first receiving channel 512 of the chip under test 500 and the third transmitting channel 231 of the detection chip 200. Inside the detection chip 200, the third receiving channel 232 and the third transmitting channel 231 are connected via a cable.

[0069] Through the above solution, by directly connecting the sending channel and receiving channel of the chip under test to form a loop, the detection signal starts from the sending channel, passes through the connector and the detection chip, and returns to the receiving channel, thus achieving a complete test of the signal transmission path. It can verify the entire process from signal sending to receiving, and facilitate accurate positioning of problems that may occur during the signal transmission process.

[0070] Optional, please continue to Figure 3 The connectivity chip 400 is used to connect the second transmitting channel 521 and the second receiving channel 522 of the chip under test 500 at the second end 520. This connection can be achieved via a cable. Thus, the test signal from the second transmitting channel 521 of the chip under test 500 passes through the connectivity chip 400 and returns to the chip under test 500 at the second receiving channel 522. Through this solution, the connectivity chip can independently complete the loopback test at the second end.

[0071] Optionally, the first sub-loop and the second sub-loop form a test loop to perform signal transmission detection. Figure 4 A schematic diagram of a signal circuit for a test loop is shown. The circuit for the test loop is specifically as follows:

[0072] (1) The chip under test 500 sends a test signal to the connected chip 400;

[0073] (2) The test signal passes through the connected chip 400 and then returns to the chip to be tested 500;

[0074] (3) The test signal passes through the chip under test 500 from the inside;

[0075] (4) The chip under test 500 sends a test signal to the detection chip 200 through the connector 300;

[0076] (5) The test signal passes through the detection chip 200 and the connector 300 and then returns to the chip under test 500.

[0077] Based on the above test loop circuit, any transmitting channel of the first end 510 of the chip under test 500 and any receiving channel of the second end 520 constitute a transmitting channel inside the chip under test 500; any receiving channel of the first end 510 and any transmitting channel of the second end 520 constitute a receiving channel inside the chip under test 500.

[0078] The above solution combines two sub-loops into a complete test loop, verifying the entire signal link of the test signal from one end of the chip under test to the other. This test loop structure allows the test signal to completely pass through the transmit and receive channels of the chip under test, effectively verifying the integrity of the signal transmission within the chip under test and, in turn, the connectivity of the chip under test. Furthermore, combining the two sub-loops into a large test loop is more efficient than testing the two sub-loops separately, avoiding repeated testing and saving test time.

[0079] Optionally, the control module 210 is further configured to send a clock signal and a reset signal to the chip under test 500 through the connector 300 to put the chip under test 500 into a working state.

[0080] Here, the control module 210 may be any processing unit capable of sending a clock signal and a reset signal. For example, in a specific example, the control module 210 may be an FPGA.

[0081] With this solution, the control module directly provides clock and reset signals, ensuring that the chip under test can enter the normal working state and that the chip can start stably. Furthermore, the control module directly provides these basic signals, simplifying the test environment and eliminating the need to rely on the server system to provide these signals, thereby improving the independence and efficiency of the test.

[0082] Optional, see Figure 5 A structural schematic diagram of another chip detection device is shown. The detection chip 200 can also include an external interface 220, which is used to connect to the processor 600. The detection chip 200 is also used to receive test instructions sent by the processor 600, and the test instructions are used to trigger the detection chip to generate a control signal; when the control module 210 receives the signal detection result, the control module 210 sends the signal detection result to the processor 600 through the external interface 220.

[0083] That is, the processor 600 can receive test instructions and send them to the detection chip 200 through the external interface 220. After receiving the test instructions, the detection chip 200 generates a control signal and sends it to the chip under test 500. In this way, the detection chip can automatically generate control signals according to the test instructions of the processor, making the entire testing process more standardized and regularized, and reducing errors caused by human operation.

[0084] Through the above scheme, the communication connection between the detection chip and the processor is realized through the external interface, so that the test process can be controlled and monitored by the processor, which improves the degree of automation of the test. In addition, the processor can send test instructions and receive test results, realizing the human-computer interaction function, which is convenient for operators to control the test process and view the test results.

[0085] Optionally, the chip under test 500 performs signal transmission detection through a pseudo-random binary sequence.

[0086] The above scheme uses a pseudo-random binary sequence for testing, simulating various possible data transmission scenarios, improving the comprehensiveness and reliability of the test. Furthermore, due to the determinism of pseudo-random binary sequences, the receiver can predict the correct sequence. By comparing the received sequence with the locally generated sequence, the bit error rate can be accurately calculated, effectively evaluating the quality of the communication link.

[0087] Furthermore, optionally, the processor 600 can display the test log. That is, after the chip under test 500 sends the signal detection result to the detection chip 200, the detection chip 200 sends the signal detection result to the processor 600 through the external interface 220, and the processor 600 displays the test log according to the signal detection result.

[0088] Through the above scheme, the test results can be intuitively displayed by the processor, which is convenient for quickly judging the performance status of the chip under test and improving the test efficiency.

[0089] The above describes the chip detection device. The following is a further introduction to the chip detection device using a specific example. Figure 6 , shows a structural schematic diagram of another chip detection device, which includes a detection chip 200, a connector 300, a communication chip 400 and a processor 600.

[0090] Among them, the detection chip 200 includes a control module 210 and an external interface 220, the processor 600 is connected to the detection chip 200 through the external interface 220, the detection chip 200 is connected to the connector 300, the connector 300 is connected to the first end 510 of the chip to be tested 500, and the connecting chip 400 is connected to the second end 520 of the chip to be tested 500.

[0091] Optionally, the detection chip 200 further includes an indicator light to indicate to the user that chip detection can be initiated and that chip detection is complete. Specifically, after the chip detection device is initialized, the indicator light illuminates to indicate that the user can begin chip detection. After the control module 210 receives the signal detection result, the indicator light illuminates again to indicate to the user that chip detection is complete.

[0092] Based on the above chip detection device, the chip detection process is as follows:

[0093] Step a: the processor 600 receives a test instruction.

[0094] Here, when starting the test, the staff can input a test instruction on the processor 600 , and the test instruction is used to trigger the detection chip 200 to generate a control signal.

[0095] Step b: the processor 600 sends the test instruction to the detection chip 200 through the external interface 220 .

[0096] Optionally, the external interface 220 may be a network port, a TAPE-C port, a USB port, a JTAG port, etc., which is not limited here.

[0097] In step c, the detection chip 200 receives the test instruction, the control module 210 generates a control signal according to the test instruction, and sends the control signal to the chip under test 500 through the connector 300 .

[0098] Optionally, the control signal includes a clock signal and a reset signal, that is, the control module 210 provides a clock signal and a reset signal to the chip under test 500 to keep the chip under test 500 in a working state. Figure 7 A schematic diagram showing a control signal sent by the control module 210 is shown. Figure 7 In the figure, the control module 210 also provides 1.8v and 0.9v power signals to the chip under test 500, which are the top signals in the figure, the middle signal is the reset signal, and the bottom signal is the clock signal. Figure 7 The power signal, clock signal, and reset signal satisfy the following relationship in terms of timing:

[0099] (1) The high-level start time of the power signal and the high-level start time of the reset signal are greater than or equal to 100ms;

[0100] (2) The first high-level start time of the clock signal and the high-level start time of the reset signal are greater than or equal to 100us.

[0101] It is understandable that the control module 210 may be any processing unit capable of sending the above control signal, for example, an FPGA, a microcontroller or other application-specific integrated circuit.

[0102] In step d, after receiving the control signal, the chip under test 500 sends a first detection signal to the connector 300 at the first end 510 and sends a second detection signal to the connectivity chip 400 at the second end 520; the first detection signal forms a first sub-loop in the connector 300 and the connectivity chip 200, and the second detection signal forms a second sub-loop in the connectivity chip 400.

[0103] Optionally, the detection signal is a high-speed differential signal. When the chip under test 500 is a retimer card, the chip under test 500 sends 16 pairs of high-speed differential signals to both ends, that is, 32 loopback signals are formed at the first end 510 and the second end 520 respectively.

[0104] Optionally, the first sub-loop and the second sub-loop constitute a test loop. Here, after receiving the control signal, the chip under test 500 sends a detection signal to the communication chip 400. The detection signal forms a second sub-loop in the communication chip 400 and then returns to the chip under test 500. The chip under test 500 sends the detection signal received from the communication chip 400 to the detection chip 200 through the communication device 300. The detection signal forms a first sub-loop in the detection chip 200 and then returns to the chip under test 500 again through the connector 300. The specific test loop circuit can be referred to above. Figure 4 .

[0105] It is understandable that the above content is described with one test loop signal as an example. In practice, there may be many test loop signals, for example, Figure 6 In the example shown in FIG, the chip under test 500 has 16 pairs of differential signals at the first end and the second end, respectively, that is, there are 32 test loops.

[0106] In step e, after performing multiple loopback tests, the chip under test 500 sends the signal test results to the detection chip 200 through the connector 300 .

[0107] Optionally, the chip under test 500 communicates with the control module 210 via I2C, and the chip under test 500 sends the signal test result to the control module 210 via I2C.

[0108] Optionally, the chip under test 500 performs signal transmission detection using PRBS and sends the PRBS detection results to the detection chip 200. Here, after multiple loopback tests, the chip under test 500 can perform PRBS detection based on the multiple loopback test results. Based on the PRBS detection results and the working status of the chip under test 500, the detection chip 200 can evaluate the chip under test 500 from the following aspects:

[0109] 1. Signal transmission and reception quality: Check whether the chip 500 can send and receive data signals normally;

[0110] 2. Link loss: Detect the attenuation of the signal during transmission to ensure that the loss is within an acceptable range;

[0111] 3. Front-end and rear-end series resistance status: Check whether the series impedance of each port of chip 500 is normal to verify the conductivity of the signal path.

[0112] In step f, the detection chip 200 sends the signal test result to the processing machine 600 through the external interface 220 .

[0113] In step g, the processor 600 displays the test log according to the signal test result.

[0114] Figure 8 A schematic diagram of a test log is shown. It can be seen from the figure that the left side of the test log is the loopback line, and the right side is the test result corresponding to the loopback line. It can be understood that Figure 8 The test log is only an example and does not limit the present invention.

[0115] This invention fundamentally changes the traditional retimer card testing scheme through loopback testing. By implementing loopback testing with a detection chip and a connectivity chip, it enables comprehensive detection of signals at both ends of the retimer card. This invention not only simplifies the testing environment but also provides clock and reset signals through a control module, combined with PRBS for loopback testing. This allows for comprehensive evaluation of transmit and receive signal quality, link loss, and string resistance. More importantly, when a signal link problem is detected, this invention can precisely locate the specific fault location.

[0116] In practice, the testing process of the present invention is simple and intuitive. Simply connect the chip detection device to a power source, wait for the device to initialize, and then insert the retimer card to be tested to begin testing. After the test is complete, the next retimer card can be directly replaced without powering off, significantly improving testing efficiency. Furthermore, the test results can be intuitively displayed through the processor's human-computer interface, facilitating quick judgment by the operator.

[0117] Based on the chip detection device described above, the present invention also proposes a chip detection method, such as Figure 9 As shown, the chip detection method specifically includes the following steps:

[0118] Step 910: Connect the chip to be tested to the chip detection device.

[0119] Optionally, before connecting the chip to be tested to the chip detection device, it is necessary to connect the chip detection device to a power source and wait for the chip detection device to be initialized. After the initialization is completed, the indicator light on the detection chip 200 lights up to prompt the user to start testing.

[0120] Based on the chip detection device provided by the present invention, the time from the chip detection device being connected to the power supply to the completion of initialization is very short and almost negligible. Compared with the prior art server, which takes a long time from powering on to initialization completion, the present invention greatly reduces the chip detection time and improves the chip detection efficiency.

[0121] Step 920: triggering the chip under test to perform loopback signal transmission detection through the control signal of the chip detection device and obtaining a signal test result.

[0122] Here, after the control module 210 of the detection chip 200 detects the test instruction, it sends a control signal to the chip under test 500 through the connector 300, so that the chip under test 500 performs a loopback signal transmission test, and then the chip under test 500 sends the signal detection result to the control module 210 through the connector 300.

[0123] Optionally, the control module 210 sends the signal detection result to the processor 600 through the external interface 220, and the processor 600 displays the test log according to the signal detection result.

[0124] Optionally, after a chip under test is tested, the indicator light of the chip testing device lights up to inform the user that the test is complete. There is no need to turn off the power afterwards, and the chip under test can be directly replaced and the next round of testing can be carried out.

[0125] The present invention directly triggers and controls the loopback test through the chip detection device, which greatly simplifies the construction of the test environment compared to the traditional solution that relies on the server system. During the chip testing process, there is no need to equip a complete server system and complex equipment such as PCIe standard cards, which reduces the testing cost and reduces the requirements for the test environment. In addition, since the present invention adopts a loopback test method, the test results directly reflect the performance status of the chip to be tested, avoiding the interference caused by complex links and improving the accuracy of the test. At the same time, the testing process of the present invention is simple and direct, and there is no need to wait for the server to start and perform power-off and restart operations, which significantly improves the testing efficiency.

[0126] Optionally, if the chip to be tested is a retimer card, since the retimer card is usually used in conjunction with a PCIe card, after completing the basic function test of the retimer card, it is necessary to further verify the function of the PCIe card. Therefore, after the retimer card test is completed, the following step 930 may also be included.

[0127] Step 930: After the signal test result indicates that the chip under test has passed the test, connect it to the PCIe card and test the PCIe card.

[0128] The above solution first performs basic functional testing on the retimer card, effectively preventing problems with the retimer card itself from affecting the accuracy of PCIe card test results. This solution quickly identifies problematic retimer cards and prevents them from being used in subsequent PCIe card tests, improving overall test efficiency.

[0129] A chip detection device and method are introduced above. The chip detection method is further introduced below using a specific example to provide a complete chip detection step.

[0130] The first step is to connect the chip detection device to the power supply.

[0131] In the second step, after the chip detection device is initialized, the indicator light on the detection chip 200 lights up to prompt the user to start testing.

[0132] The third step is to insert the retimer card to be tested.

[0133] In the fourth step, the control module 210 receives the test instruction, and the chip detection device starts to test the retimer card.

[0134] Step 5: After the test is completed, the indicator light on the detection chip 200 lights up again to remind the user that the test is completed, and the processor 600 displays the test log.

[0135] Step 6: Replace the next retimer card to be tested without powering off the power supply and repeat steps 1 to 5.

[0136] In some scenarios, after the retimer card test is completed, the PCIe card test is also required to ensure the functional integrity of the entire system (retimer card and PCIe card).

[0137] All other embodiments derived by persons of ordinary skill in the art based on the exemplary embodiments described herein without inventive effort are within the scope of protection of the claims appended hereto. Furthermore, although the disclosure herein is presented based on one or more exemplary embodiments, it should be understood that each aspect of the disclosure may constitute a complete embodiment on its own.

[0138] It should be noted that the brief descriptions of terms in this application are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0139] In the specification and claims of this application, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar or similar objects or entities and are not necessarily intended to limit a particular order or precedence, unless otherwise noted. It should be understood that such terms are interchangeable where appropriate, e.g., embodiments of this application can be implemented in an order other than that shown or described in the drawings or descriptions.

[0140] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0141] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A chip detection device, characterized in that: It includes a detection chip with a control module and a connector; The connector is used to connect to the first end of the chip to be tested, and a first sub-loop is formed by the connector and the detection chip; The control module is configured to send a control signal to the chip under test through the connector, wherein the control signal is configured to trigger the chip under test to perform signal transmission detection on the first sub-loop; The control module is further configured to receive a signal detection result of the first sub-loop through the connector.

2. The device according to claim 1, wherein Also includes connectivity chips; The connecting chip is connected to the second end of the chip to be tested to form a second sub-loop; The control signal is specifically used to trigger the chip under test to perform signal transmission detection of the first sub-loop and the second sub-loop; The control module is specifically configured to receive signal detection results of the first sub-loop and the second sub-loop.

3. The device according to claim 2, wherein The first sub-loop and the second sub-loop form a test loop to perform signal transmission detection.

4. The device according to any one of claims 1 to 3, characterized in that The connector and the detection chip are used together to connect the first transmitting channel and the first receiving channel of the chip to be tested at the first end.

5. The device according to claim 4, characterized in that The connecting chip is used to connect the second transmitting channel and the second receiving channel of the chip under test at the second end; Any transmitting channel of the first end and any receiving channel of the second end constitute a transmitting channel inside the chip under test; Any receiving channel at the first end and any sending channel at the second end constitute a receiving channel inside the chip under test.

6. The device according to claim 4, characterized in that The control module is further configured to send a clock signal and a reset signal to the chip under test through the connector to put the chip under test into an operating state.

7. The device according to claim 4, wherein The detection chip further includes an external interface, and the external interface is used to connect to a processor; The detection chip is further configured to receive a test instruction sent by the processor and send the signal detection result to the processor; the test instruction is configured to trigger the detection chip to generate the control signal.

8. The device according to claim 4, wherein The chip to be tested performs signal transmission detection through a pseudo-random binary sequence.

9. A chip detection method, characterized in that: include: Connecting the chip to be tested to the chip detection device according to any one of claims 1 to 8; The chip under test is triggered by the control signal of the chip detection device to perform loopback signal transmission detection and obtain a signal detection result.

10. The method according to claim 9, wherein The chip to be tested is a retimer card; and the method further comprises: after the signal detection result indicates that the chip to be tested has passed the test, connecting the chip to the PCIe card and testing the PCIe card.

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