A high-speed data acquisition and storage method, system, device and medium

Abstract

The application relates to a high-speed data acquisition and storage method, system, device and medium, and belongs to the technical field of signal acquisition and data storage. The method comprises the following steps: acquiring at least one high-voltage probe pulse signal and 24 switch probe signals in real time; attenuating the high-voltage probe pulse signal to the input threshold range of an optical coupling device, and performing signal conversion and electrical isolation to generate a TTL level signal; performing micro-capacitance charging and discharging detection on the switch probe signal to obtain switch probe timestamp data; encapsulating the TTL level signal, the switch probe timestamp data and 64-bit time reference data into a data frame, and transmitting the data frame through a main-backup dual-fiber channel in parallel; performing integrity check on the data frame at a receiving end, and dynamically allocating a storage physical address; responding to a host computer instruction to execute a storage data export or specified block erasing operation, and exporting a device digital signature and the storage physical address. The application can improve the data acquisition accuracy and storage security in transient events.

Description

Technical Field

[0001] This application relates to the field of signal acquisition and data storage technology, and in particular to a high-speed data acquisition and storage method, system, device and medium. Background Technology

[0002] Signal acquisition and data storage technologies play a crucial role in many fields, including modern industry, military, aerospace, medicine, and scientific research, especially in applications requiring high precision and reliability. These technologies have wide-ranging applications, including but not limited to aerospace, military equipment, industrial automation, laboratory data acquisition, and environmental monitoring. With the continuous development of modern technology, an increasing number of high-speed, high-precision data acquisition systems have emerged. These systems often need to be able to process and store data from multi-channel, multi-source signals to support functions such as real-time monitoring, fault diagnosis, early warning systems, and data analysis.

[0003] Currently, in some critical fields, such as military equipment or aerospace applications, signal acquisition devices typically need to operate reliably in environments with explosions, high acceleration, or severe vibrations. These devices usually require the rapid acquisition of large amounts of data, and the data storage and transmission processes must be completed within a short timeframe to ensure high accuracy and no data loss. Especially in the high-impact environments of military equipment and explosions, acquisition devices often need to withstand extremely large vibrations and accelerations. In such situations, common hard disk drive (HDD) storage, due to the vulnerability of its moving parts to impacts that can lead to data loss or hardware damage, can no longer meet the high reliability requirements.

[0004] Therefore, how to achieve high-precision real-time acquisition and transmission of data in instantaneous events (such as explosions or impacts) and improve the security and reliability of data storage is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] To improve the accuracy of data acquisition and the security of data storage, this application provides a high-speed data acquisition and storage method, system, device and medium.

[0006] Firstly, this application provides a high-speed data acquisition and storage method, employing the following technical solution:

[0007] A high-speed data acquisition and storage method, the method comprising:

[0008] Real-time acquisition of at least one high-voltage probe pulse signal and 24 switch probe signals;

[0009] The high-voltage probe pulse signal is attenuated to the input threshold range of the optocoupler through a resistor divider network, and signal conversion and electrical isolation are performed using an optocoupler isolation circuit to generate a TTL level signal corresponding to the original high-voltage pulse.

[0010] The switch probe signal is subjected to microcapacitor charge and discharge detection. The level status of each switch probe channel is polled by the FPGA, and the precise timestamp of the level transition of each switch probe channel is recorded to obtain the switch probe timestamp data.

[0011] The TTL level signal, the switch probe timestamp data, and the 64-bit time base data generated by the FPGA global clock are encapsulated into a data frame.

[0012] The data frames are transmitted in parallel via primary and backup dual fiber optic channels.

[0013] The receiving end performs integrity verification on the data frame, writes the verified data into the parallel Flash storage array page by page, and uses a wear leveling algorithm to dynamically allocate storage physical addresses.

[0014] Responding to commands issued by the host computer via serial port, it performs data export or specified block erasure operations, and attaches a device digital signature and storage physical address to the exported data.

[0015] By employing the above technical solution, precise synchronous acquisition, timing control, and signal isolation of high-voltage and switching signals can be achieved, ensuring accurate capture and processing of complex high-voltage signals. Simultaneously, through redundant fiber optic channels, data verification, and wear leveling, high reliability of data transmission and persistent storage are guaranteed in the face of instantaneous events (such as explosions or impacts). The technical solution of this application is particularly suitable for application scenarios with extremely high requirements for data acquisition accuracy and transmission stability, such as high-voltage power equipment monitoring and real-time acquisition of explosion data.

[0016] Optionally, the resistor voltage divider network includes a first precision resistor and a second precision resistor connected in series, with a voltage division ratio configured as 1:100.

[0017] Optionally, the steps of performing microcapacitor charge / discharge detection on the switch probe signal, polling the level state of each switch probe channel through the FPGA, and recording the precise timestamp of the level transition of each switch probe channel to obtain the switch probe timestamp data include:

[0018] Each switch probe channel is configured with a parallel microcapacitor, and a constant current source is set to charge and discharge the microcapacitor.

[0019] The capacitor voltage of each switch probe channel is continuously acquired by an analog-to-digital converter, and the instantaneous slope of the capacitor voltage of each switch probe channel is calculated by an FPGA.

[0020] When the instantaneous slope of the capacitor voltage of any switch probe channel exceeds a preset threshold, the edge-jumping logic is triggered.

[0021] The global timer value at the trigger moment is recorded as a timestamp, and the timestamp deviation is corrected according to the preset trace delay parameters to obtain the switch probe timestamp data.

[0022] By employing the above technical solution, real-time acquisition, time stamping, and transmission of high-precision switch probe signals are achieved. Through micro-capacitor charging and discharging detection, combined with FPGA's high-precision calculations and timestamp correction mechanism, the system can accurately and in real-time record the signal change moments of each switch probe channel and transmit this data to the storage module via a high-efficiency fiber optic transmission system. In this way, the system not only ensures high precision and reliability in signal detection but also guarantees the efficiency and accuracy of data transmission and storage, making it suitable for applications requiring real-time response and high-precision data recording.

[0023] Optionally, the step of transmitting the data frame in parallel via primary and backup dual fiber optic channels includes:

[0024] Configure the operating parameters of the primary and backup optical fiber channels in the primary and backup dual optical fiber channels; wherein, the primary channel uses an 850 nm wavelength optical module and the backup channel uses a 1310 nm wavelength optical module;

[0025] A globally incrementing sequence number field is appended to each data frame, and the data frames are sent in parallel through primary and backup dual channels.

[0026] By adopting the above technical solution, the main channel and backup channel achieve effective redundancy and flexible fault switching. In practical applications, even if the transmission of a certain wavelength fails, the system can seamlessly switch to the backup wavelength to achieve highly reliable data transmission; furthermore, even in the case of multi-channel parallel transmission, the data frames can be transmitted and processed correctly, avoiding data loss or disordered order due to switching operations or packet loss, thereby enhancing data reliability.

[0027] Optionally, after the step of transmitting the data frame in parallel via primary and backup dual fiber optic channels, the method further includes:

[0028] At the receiving end, count the number of erroneous frames in the main channel and the backup channel respectively, and calculate the bit error rate;

[0029] When the main channel bit error rate exceeds the preset threshold, a channel switching command is triggered;

[0030] Activate the backup channel transmission queue and retransmit a preset number of historical data frames;

[0031] Update the channel status register, mark the original primary channel as a backup channel, and reset the bit error rate statistics.

[0032] By adopting the above technical solution, efficient management of dual-channel parallel transmission is achieved. Through precise bit error rate monitoring and historical data retransmission mechanisms, the stability and integrity of data transmission are guaranteed. When the primary channel fails, the system can quickly switch to the backup channel and retransmit lost data frames, greatly improving the system's fault tolerance and reliability. Through globally incrementing sequence numbers and real-time bit error rate monitoring, this solution ensures data orderliness, reliability, and efficiency, making it suitable for fiber optic communication systems requiring high redundancy and reliability, and particularly valuable in real-time data transmission and critical communication scenarios.

[0033] Optionally, the steps of performing integrity verification on the data frame at the receiving end, writing the verified data to the parallel Flash storage array page by page, and dynamically allocating storage physical addresses using a wear leveling algorithm include:

[0034] The receiving end receives the transmitted data frames and extracts the payload and check field from the data frames.

[0035] Perform an integrity check on the payload and generate a check result;

[0036] Upon successful verification, the payload is encrypted to generate an encrypted data block.

[0037] The encrypted data block is split into multiple sub-data segments and written in parallel to different physical pages of the Flash storage array;

[0038] Write addresses are dynamically allocated based on the historical write count of each physical page, and the mapping table between logical addresses and physical addresses is updated.

[0039] If the write fails, perform a preset number of retries and mark the abnormal physical page.

[0040] By adopting the above technical solution, based on an intelligent wear leveling algorithm, the system can optimize the write process of Flash storage, extend the lifespan of the storage device, and effectively retries and mark abnormal storage areas in the event of a write failure, thus preventing data loss. The overall solution provides an efficient, secure, and reliable data storage solution, particularly suitable for storage systems with high write frequencies and high reliability requirements.

[0041] Secondly, this application provides a high-speed data acquisition and storage system, which adopts the following technical solution:

[0042] A high-speed data acquisition and storage system, the system comprising:

[0043] The signal acquisition module includes a high-voltage probe interface unit and a switch probe interface unit. The high-voltage probe interface unit is configured to acquire at least one high-voltage pulse signal in real time, and the switch probe interface unit is configured to acquire 24 switch probe signals simultaneously.

[0044] The signal processing module includes a resistor divider network and an optocoupler isolation circuit; wherein, the resistor divider network is used to attenuate the high-voltage probe pulse signal to the input threshold range of the optocoupler device, and the optocoupler isolation circuit is used to perform signal conversion and electrical isolation on the attenuated signal to generate a TTL level signal corresponding to the original high-voltage pulse;

[0045] The FPGA control module includes a microcapacitor charge / discharge detection unit and a timestamp recording unit; wherein, the microcapacitor charge / discharge detection unit is used to poll the level status of each switch probe channel, and the timestamp recording unit is used to record the precise timestamp of the level transition of each switch probe channel to obtain switch probe timestamp data;

[0046] The data frame encapsulation module is used to encapsulate the TTL level signal, the switch probe timestamp data, and the 64-bit time base data generated by the FPGA global clock into a data frame.

[0047] The fiber optic communication module includes primary and backup dual fiber optic channels for transmitting the data frames in parallel.

[0048] The storage controller module includes a verification unit, a parallel Flash writing unit, and a wear leveling management unit. The verification unit is used to perform integrity verification on the data frame at the receiving end. The parallel Flash writing unit is used to write the verified data to the parallel Flash storage array page by page. The wear leveling management unit is used to dynamically allocate storage physical addresses using a wear leveling algorithm.

[0049] The instruction response module is used to respond to instructions issued by the host computer via the serial port, perform data export or specified block erasure operations, and attach device digital signature and storage physical address to the exported data.

[0050] Thirdly, this application provides a computer device, which adopts the following technical solution:

[0051] A computer device includes a memory, a processor, and a computer program stored in the memory, the processor executing the computer program to perform the steps of the method as described in the first aspect.

[0052] Fourthly, this application provides a computer-readable storage medium, which adopts the following technical solution:

[0053] A computer-readable storage medium storing a computer program that can be loaded by a processor and executed as in any of the methods in the first aspect.

[0054] In summary, this application includes at least one of the following beneficial technical effects: It achieves safe and accurate acquisition of high-voltage signals through a resistor divider network and optocoupler isolation technology; combined with FPGA-controlled microcapacitor charging and discharging detection and nanosecond-level timestamp synchronization technology, it significantly improves the time accuracy of 24-channel switch probe signal acquisition; it effectively enhances the reliability of data transmission in complex electromagnetic environments by employing a primary and backup dual-fiber channel parallel transmission mechanism; and combined with a parallel Flash storage array and dynamic wear leveling algorithm, it extends the lifespan of the storage medium while ensuring storage speed; through a data encapsulation method that binds device identifiers and physical addresses with digital signatures, and an anti-interference fiber optic communication architecture, it forms a secure protection system covering the entire data acquisition, transmission, and storage chain, ultimately achieving high-speed, high-precision, and anti-interference data acquisition and storage capabilities in extreme environments, meeting the stringent requirements of aerospace, military equipment, and other scenarios. Attached Figure Description

[0055] Figure 1 This is a first flowchart illustrating a high-speed data acquisition and storage method according to one embodiment of this application.

[0056] Figure 2 This is a second flowchart illustrating a high-speed data acquisition and storage method according to one embodiment of this application.

[0057] Figure 3 This is a schematic diagram of the third process of a high-speed data acquisition and storage method according to one embodiment of this application.

[0058] Figure 4 This is a schematic diagram of the fourth process of a high-speed data acquisition and storage method according to one embodiment of this application.

[0059] Figure 5 This is a schematic diagram of the fifth process of a high-speed data acquisition and storage method according to one embodiment of this application. Detailed Implementation

[0060] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figure 1-5 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.

[0061] This application discloses a high-speed data acquisition and storage method.

[0062] Reference Figure 1 A high-speed data acquisition and storage method, the method comprising:

[0063] Step S101: Real-time acquisition of at least one high-voltage probe pulse signal and 24 switch probe signals;

[0064] The high-voltage probe pulse signal input voltage range is 0-200V, and the acquisition time deviation between each channel of the switch probe signal does not exceed 5ns.

[0065] It is important to note that the acquisition system has extremely strict timing requirements for both high-voltage and switching signals. High-voltage signals are typically pulse signals with a voltage range of 0 to 200V, while switching probe signals are usually used to detect changes in the switching state of circuits. The timing deviation of these signals needs to be strictly controlled within 5ns. This 5ns timing error limit is very stringent, meaning that the accuracy requirement for each signal sampling point is extremely high. Excessive timing deviation will cause errors in the acquired signals during subsequent data processing, thus affecting signal analysis and system control decisions.

[0066] Step S102: The high-voltage probe pulse signal is attenuated to the input threshold range of the optocoupler through a resistor divider network, and the signal is converted and electrically isolated by an optocoupler isolation circuit to generate a TTL level signal corresponding to the original high-voltage pulse.

[0067] The resistor divider network attenuates high-voltage signals to a suitable low-voltage range for processing. For example, when the input high-voltage signal is 200V, the divider network attenuates it to 2V, ensuring the signal does not exceed the input voltage range of the optocoupler. The optocoupler's role here is electrical isolation, separating the input voltage signal from the output signal to prevent high-voltage signals from interfering with or damaging subsequent circuits. Through the optocoupler's signal conversion, the signal's pulse characteristics are preserved, and the output is a TTL (Transistor-Transistor Logic) level signal. TTL level signals conform to digital circuit standards and are suitable for further digital processing.

[0068] Understandably, this signal conversion and isolation method not only protects downstream circuits from high-voltage electrical surges but also ensures that the signal conversion process is free from electrical interference. Optocoupler isolation provides an effective electrical isolation solution, guaranteeing the reliability of the entire data acquisition system. Between high-voltage equipment and low-voltage control systems, the use of optocouplers effectively avoids the impact of noise and interference on the signal, improving system stability.

[0069] Step S103: Perform microcapacitor charging and discharging detection on the switch probe signal. Poll the level status of each switch probe channel through the FPGA, record the precise timestamp of the level transition of each switch probe channel, and obtain the switch probe timestamp data.

[0070] The detection method for the switch probe signal is based on the principle of microcapacitor charging and discharging. When the switch state changes, the capacitor of the switch probe charges and discharges, and the voltage change of the capacitor during this process can be monitored. To detect this voltage change with high precision, the FPGA chip continuously checks the level state of each switch probe channel through polling technology. When the voltage slope of the capacitor changes, the FPGA records the time of the change, generating a precise timestamp. These timestamps reflect the moment of signal state transition and are the basis for subsequent analysis of key information such as switch behavior and signal transmission delay.

[0071] Understandably, this micro-capacitor charge / discharge detection method ensures high-precision recording of signal transition moments. For high-speed switching signals, the timestamp provides accurate timing information, aiding in the analysis of factors such as switching response time and signal transmission delay. This mechanism is of great significance for scenarios such as high-speed data acquisition, real-time monitoring systems, and precision measurement.

[0072] Step S104: Encapsulate the TTL level signal, the switch probe timestamp data, and the 64-bit time base data generated by the FPGA global clock into a data frame;

[0073] The data frame contains a synchronization header field, a channel number field, and a checksum field. As the basic unit of information transmission, the data frame includes various information fields, such as TTL level signals (representing the state of the digital signal), switch probe timestamps (marking the time of each transition), and global clock time base data generated by the FPGA (ensuring global synchronization). Using 64-bit time base data provides high-precision timestamps, ensuring that data from all channels is time-aligned and avoiding signal confusion caused by time synchronization issues.

[0074] Step S105: Data frames are sent in parallel through the primary and backup dual fiber optic channels;

[0075] The main channel uses an 850 nm wavelength SFP optical module; the backup channel uses a 1310 nm wavelength SFP optical module; the bit error rate of the two channels is monitored in real time, and the backup channel is automatically switched when the bit error rate of the main channel exceeds the preset threshold.

[0076] Specifically, to ensure high reliability and efficiency in data transmission, a primary and backup dual-fiber channel is used for parallel data transmission. The primary and backup channels use optical modules of different wavelengths, allowing for seamless switching to the backup channel even if the primary channel fails. Data transmission on both channels is performed in parallel, and data frames carry the same sequence number. The receiving end can verify data integrity by checking the continuity of the sequence number.

[0077] Step S106: At the receiving end, the integrity of the data frame is checked, and the data that passes the check is written to the parallel Flash storage array page by page. The wear leveling algorithm is used to dynamically allocate the storage physical address.

[0078] The data receiving end first performs data verification to ensure that the data has not been corrupted during transmission. After verification, the data is written to the storage array page by page. To improve the lifespan of the storage media, the system uses a wear leveling algorithm to dynamically allocate data to different physical storage areas, avoiding excessive wear caused by frequent writes to the same storage block. The wear leveling algorithm selects the target storage area based on the number of erases and writes in each storage area, ensuring balanced use of the storage blocks.

[0079] Understandably, data verification ensures the accuracy of transmitted data, while wear leveling algorithms extend the lifespan of storage devices and optimize the use of storage resources. This is especially important for high-frequency data storage applications, such as monitoring systems and data acquisition systems, as it effectively prevents storage devices from failing due to overuse of certain areas.

[0080] Step S107: In response to the instruction sent by the host computer via the serial port, perform the storage data export or specified block erasure operation, and attach the device digital signature and storage physical address to the exported data.

[0081] The system receives instructions from the host computer via a serial port to perform specific data operations, such as exporting stored data or erasing specified storage blocks. The exported data includes the device's digital signature and storage physical address information. The digital signature ensures data integrity and source credibility, while the storage physical address helps trace the data's origin later, ensuring data verifiability.

[0082] In the above embodiments, precise synchronous acquisition, timing control, and signal isolation of high-voltage signals and switching signals ensure accurate capture and processing of complex high-voltage signals. Simultaneously, through redundant fiber optic channels, data verification, and wear leveling, high reliability of data transmission and persistent storage are guaranteed in the face of instantaneous events (such as explosions or impacts). The technical solution of this application is particularly suitable for application scenarios with extremely high requirements for data acquisition accuracy and transmission stability, such as high-voltage power equipment monitoring and real-time acquisition of explosion data.

[0083] As one implementation of a resistor voltage divider network, the resistor voltage divider network includes a first precision resistor and a second precision resistor connected in series, with a voltage division ratio configured as 1:100.

[0084] In this embodiment, the resistor voltage divider network is configured based on the series voltage divider principle. A precise 1:100 voltage divider ratio is formed by connecting a first precision resistor with a high resistance of 1MΩ and a second precision resistor with a low resistance of 10kΩ in series, which linearly attenuates the input high voltage pulse signal to the safe input range of the optocoupler (typically within 2V).

[0085] Among them, the high-resistance resistor bears the main voltage drop to reduce power consumption, while the low-resistance resistor provides a stable voltage divider node. The two work together to achieve high voltage isolation while accurately transmitting signal waveform characteristics. The low-voltage signal after voltage division is converted by optocoupler to generate a TTL level signal with the same phase as the original high-voltage pulse. This ensures electrical isolation between the high-voltage side and the low-voltage side, and also ensures the real-time performance and accuracy of signal acquisition.

[0086] Reference Figure 2 As one implementation of step S103, the steps of detecting the charge and discharge of the switch probe signal using microcapacitors, polling the level state of each switch probe channel through the FPGA, and recording the precise timestamp of the level transition of each switch probe channel to obtain the switch probe timestamp data include:

[0087] Step S201: Configure parallel microcapacitors for each switch probe channel and set a constant current source to charge and discharge the microcapacitors.

[0088] Microcapacitor charge-discharge detection is a method that identifies signal state changes based on capacitor voltage variations. The purpose of configuring parallel microcapacitors for each switch probe channel is to store charge and continuously charge and discharge them using a constant current source. This capacitor charge-discharge method provides a stable voltage rise or fall process, thus providing sufficient basic data for subsequent voltage slope calculations. Providing a constant current through the constant current source ensures that the charging and discharging process is unaffected by external power fluctuations, thereby improving the stability and accuracy of signal detection.

[0089] Understandably, by configuring parallel microcapacitors and constant current sources, the charging and discharging characteristics of each channel can be ensured to be stable and reliable, avoiding signal errors caused by power supply fluctuations. This mechanism ensures the uniformity and repeatability of the charging and discharging process, which helps to provide an accurate input signal for voltage slope calculation, thereby enhancing the accuracy of signal detection.

[0090] Step S202: Continuously acquire the capacitor voltage of each switch probe channel through an analog-to-digital converter, and calculate the instantaneous slope of the capacitor voltage of each switch probe channel through an FPGA.

[0091] Specifically, the analog-to-digital converter (ADC) is used to convert analog voltage signals into digital signals for FPGA processing. The capacitor voltage of each switch probe channel is continuously sampled, and the ADC converts the analog signal into a digital quantity for FPGA processing. The slope calculation logic within the FPGA monitors the rate of change of the voltage by calculating the rate of change of the capacitor voltage over time, i.e., the instantaneous slope. By continuously sampling the voltage, the FPGA can calculate the voltage slope in each sampling period and compare it with a preset threshold.

[0092] By leveraging the high sampling rate of the analog-to-digital converter and the computing power of the FPGA, the system can monitor changes in capacitor voltage in real time and perform high-precision calculations of the instantaneous slope. The FPGA can analyze the dynamic characteristics of voltage changes through efficient computational logic, enabling the system to monitor changes in the switch probe signal in real time and provide accurate data for subsequent transition determination and timestamp recording.

[0093] Step S203: When the instantaneous slope of the capacitor voltage of any switch probe channel exceeds a preset threshold, the edge-jumping determination logic is triggered.

[0094] Specifically, the instantaneous slope calculation is used to detect signal changes. When the instantaneous slope of the capacitor voltage of a certain switch probe channel exceeds a preset threshold, it indicates that the signal of that channel has undergone a significant change (e.g., a rising edge from low to high or a falling edge from high to low). At this time, the FPGA will trigger the edge-jumping logic to mark a valid edge-jumping event for that channel.

[0095] The threshold value can be adjusted according to actual application requirements to avoid triggering erroneous transition judgments due to minor noise or meaningless fluctuations. This judgment logic can accurately identify significant voltage changes, avoid false triggering by noise or interference signals, and the system can effectively distinguish between normal signal transitions and invalid fluctuations, thereby improving the reliability and accuracy of detection.

[0096] Step S204: Record the global timer value at the trigger moment as a timestamp, and correct the timestamp deviation according to the preset trace delay parameters to obtain the switch probe timestamp data.

[0097] When a transition edge is detected as a timing condition, the system records the trigger time using a global timer (typically a 64-bit clock within the FPGA). The global timer is typically very accurate, providing precise timestamps within each clock cycle. Due to potential trace delays during signal transmission, the FPGA corrects the timestamp based on pre-measured delays (Δt) for each channel. This correction ensures the accuracy of the timestamp recording, taking into account the physical delays of each signal path within the circuit.

[0098] Understandably, this mechanism effectively calibrates timestamps, ensuring consistency and accuracy in signal timing across different channels. By correcting for trace delays, the system can more accurately reflect the actual moments of signal change, thereby improving the precision of subsequent data analysis and signal processing. This method is particularly suitable for complex signal acquisition and processing systems where time synchronization is crucial.

[0099] The above implementation achieves real-time acquisition, time stamping, and transmission of high-precision switch probe signals. By using a micro-capacitor charging and discharging detection method, combined with the high-precision calculation and timestamp correction mechanism of the FPGA, the system can accurately and in real-time record the signal change moments of each switch probe channel and transmit this data to the storage module via a high-efficiency fiber optic transmission system. In this way, the system not only ensures high precision and reliability in signal detection but also guarantees the efficiency and accuracy of data transmission and storage, making it suitable for applications requiring real-time response and high-precision data recording.

[0100] Reference Figure 3 As one implementation of step S105, the step of transmitting data frames in parallel through primary and backup dual fiber optic channels includes:

[0101] Step S301: Configure the operating parameters of the primary and backup optical fiber channels in the primary and backup dual optical fiber channels; wherein, the primary channel uses an 850 nm wavelength optical module and the backup channel uses a 1310 nm wavelength optical module.

[0102] In this embodiment, the configuration of primary and backup dual fiber optic channels is based on the principle of physical layer differential redundancy design. The primary channel uses 850 nm short-wavelength optical signals to optimize its transmission performance over shorter distances; while the backup channel uses 1310 nm wavelength optical modules, commonly used for longer-distance transmission. This configuration of two optical modules ensures channel compatibility and multi-path redundancy, effectively preventing system downtime due to primary channel failure.

[0103] Step S302: Attach a globally incrementing sequence number field to each data frame and send the data frames in parallel through the primary and backup dual channels.

[0104] The inclusion of a globally incrementing sequence number field in each data frame is primarily to ensure data order and integrity. When data frames are transmitted in parallel via primary and backup channels, the sequence number field allows the receiver to distinguish between the individual frames and ensure the correct frame order. This design effectively avoids data out-of-order issues caused by channel switching or erroneous retransmissions.

[0105] For example, if the 1000th frame of data on the primary channel is transmitted successfully, but the 1000th frame of data on the backup channel is out of order at the receiving end, the sequence number field will help the receiving end to reorder the data to ensure data consistency.

[0106] In the above embodiments, the main channel and the backup channel achieve effective redundancy and flexible fault switching. In practical applications, even if the transmission of a certain wavelength fails, the system can seamlessly switch to the backup wavelength to achieve highly reliable data transmission; furthermore, even in the case of multi-channel parallel transmission, the order of data frames can be transmitted and processed correctly, avoiding data loss or disordered order due to switching operations or packet loss, thereby enhancing data reliability.

[0107] Reference Figure 4 As a further implementation of the high-speed data acquisition and storage method, the step of transmitting data frames in parallel via primary and backup dual fiber optic channels also includes:

[0108] Step S401: At the receiving end, count the number of erroneous frames in the main channel and the backup channel respectively, and calculate the bit error rate;

[0109] The receiving end needs to perform bit error detection on the data received from the main channel and the backup channel, typically using techniques such as CRC (Cyclic Redundancy Check) to check data integrity. Counting the number of erroneous frames and calculating the bit error rate helps in real-time monitoring of the transmission quality of each channel. The bit error rate is calculated by dividing the number of erroneous frames by the total number of transmitted frames.

[0110] For example, if 2 out of every 100 data frames have bit errors, the bit error rate is 2%. If the bit error rate exceeds a set threshold, a channel switch is required.

[0111] Step S402: When the main channel bit error rate exceeds a preset threshold, a channel switching command is triggered;

[0112] Once the bit error rate (BER) of the primary channel exceeds a preset threshold, the system will trigger a channel switching command based on the BER. This threshold can be adjusted according to the actual application scenario, typically between 0.0001% and 1%. When the BER exceeds the threshold, it indicates that the transmission quality of the primary channel has deteriorated to an unacceptable level, and the system will switch to the backup channel.

[0113] For example, in a communication system, the bit error rate of the main channel was found to exceed 1×10⁻ after measurement. 6 When this happens, the system will automatically switch to the backup channel to continue transmission, avoiding impact on the overall system performance due to poor transmission quality.

[0114] Step S403: Activate the backup channel transmission queue and retransmit a preset number of historical data frames;

[0115] Specifically, when the bit error rate of the primary channel exceeds a threshold, the system needs to activate the transmission queue of the backup channel and retransmit a certain number of historical data frames through the backup channel. These data frames are the data that was not transmitted in time when the primary channel encountered problems. In this way, the backup channel not only replaces the primary channel in continuing to transmit current data, but also retransmits the data lost by the primary channel.

[0116] For example, in a real-time data acquisition system, if the main channel loses the first 5 data frames due to signal interference, the backup channel will retransmit these 5 data frames by activating the transmission queue to ensure that no data is lost.

[0117] Step S404: Update the channel status register, mark the original primary channel as a backup channel, and reset the bit error rate statistics.

[0118] After the channel switch is completed, the system updates the channel status register, marking the original primary channel as the backup channel and the backup channel as the primary channel. Furthermore, the bit error rate (BER) statistics are reset to reassess the transmission quality of the new primary channel. Resetting the BER statistics ensures the system can re-evaluate the quality of the new primary channel.

[0119] The above implementation achieves efficient management of dual-channel parallel transmission and ensures the stability and integrity of data transmission through precise bit error rate monitoring and historical data retransmission mechanisms. When the primary channel fails, the system can quickly switch to the backup channel and retransmit lost data frames, greatly improving the system's fault tolerance and reliability. By using globally incrementing sequence numbers and real-time bit error rate monitoring, this scheme ensures data orderliness, reliability, and efficiency, making it suitable for fiber optic communication systems requiring high redundancy and reliability, and particularly valuable in real-time data transmission and critical communication scenarios.

[0120] Reference Figure 5 As one implementation of step S106, the steps of performing integrity verification on the data frame at the receiving end, writing the verified data to the parallel Flash storage array page by page, and dynamically allocating storage physical addresses using a wear leveling algorithm include:

[0121] Step S501: Receive the transmitted data frame at the receiving end and extract the payload and check field from the data frame;

[0122] In data transmission, data frames are sent to the receiving end via transmission media such as optical fiber. A data frame typically contains multiple fields, including a payload (the actual data) and a checksum field (such as CRC or other checksums). The receiving end first extracts the payload and checksum field from the data frame for subsequent verification, encryption, and storage operations. The payload is the core data that needs to be processed and stored, while the checksum field ensures data integrity.

[0123] For example, the receiving end receives a data frame containing file data (payload) and a CRC32 checksum (check field). The receiving end extracts the file data and verifies the integrity of the file data using the check field.

[0124] Step S502: Perform an integrity check on the payload and generate the check result;

[0125] Integrity verification is a crucial step in ensuring that received data has not been damaged or tampered with during transmission. Common integrity verification methods include CRC (Cyclic Redundancy Check) and hash functions. In this step, the receiving end performs a CRC32 check on the payload, calculates the check value, and compares it with the check field in the data frame. If the two check values ​​match, the data passes the verification; otherwise, the data is considered to contain errors.

[0126] For example, a received data frame contains file data. The receiving end calculates the CRC32 checksum of this data and compares it with the CRC field in the data frame. If the two values ​​are the same, it means the data is not corrupted; otherwise, the frame needs to be discarded and a retransmission requested.

[0127] Step S503: In response to the successful verification result, the payload is encrypted to generate an encrypted data block;

[0128] Once the data passes integrity verification, the receiving end encrypts the payload to ensure confidentiality and security. AES (Advanced Encryption Standard) is typically used for encryption. For example, AES-128 can be used with a 128-bit key to encrypt the data, converting the payload into encrypted data blocks. The encryption key is stored in a protected Flash memory area to prevent leakage.

[0129] Step S504: The encrypted data block is split into multiple sub-data segments and written in parallel to different physical pages of the Flash storage array;

[0130] The encrypted data block needs to be stored. Before storage, the data block is split into multiple sub-segments and distributed across multiple physical pages. This improves storage efficiency and reduces the write pressure on a single physical page. Furthermore, parallel writing to different physical pages of the Flash storage array accelerates the write process and increases storage throughput. For example, the encrypted data block is split into four sub-segments, each written to a different physical page. Each physical page can perform write operations independently, thereby reducing the erase / write frequency of a single physical page.

[0131] Step S505: Dynamically allocate write addresses based on the historical erase / write counts of each physical page, and update the mapping table between logical addresses and physical addresses;

[0132] Flash memory chips have a limited number of physical pages that can be erased and written a few times. To extend the lifespan of the storage device, wear leveling algorithms are used to dynamically allocate write addresses. By recording the historical erase and write counts of each physical page, the system can prioritize writing new data to physical pages with fewer erase and write counts. Updating the mapping table between logical and physical addresses ensures accurate data location during writes and reliable data storage. For example, the system counts the erase and write counts of each physical page and selects physical pages with fewer erase and write counts (e.g., those with less than 80% of the average remaining erase and write counts) to store new data based on the statistical results.

[0133] Understandably, through wear leveling algorithms, the system can effectively allocate write addresses, avoiding premature damage to certain physical pages due to frequent erases and writes. This helps extend the overall lifespan of Flash storage and ensures the reliability of data storage.

[0134] Step S506: Response to writing failure result, perform a preset number of retry operations and mark the abnormal physical page.

[0135] If a write operation fails during data writing, the system will execute a pre-defined retry procedure, retrying a maximum of several times. If multiple retries still fail, the system will mark the physical page as an abnormal physical page and record it in the bad block mapping table. The address of the abnormal physical page will be replaced with an address in the redundant storage area to ensure that data is not lost. For example, if a physical page cannot be written to due to a hardware failure, the system will retry writing to that page three times. If it still fails, the physical page will be marked as a bad block, and the data will be written to the redundant storage area.

[0136] In the above embodiments, based on an intelligent wear leveling algorithm, the system can optimize the write process of Flash storage, extend the lifespan of the storage device, and effectively retries and marks abnormal storage areas when write failures occur, thus preventing data loss. The overall solution provides an efficient, secure, and reliable data storage solution, particularly suitable for storage systems with high write frequencies and high reliability requirements.

[0137] This application also discloses a high-speed data acquisition and storage system.

[0138] A high-speed data acquisition and storage system, specifically comprising:

[0139] The signal acquisition module includes a high-voltage probe interface unit and a switch probe interface unit. The high-voltage probe interface unit is configured to acquire at least one high-voltage pulse signal in real time, and the switch probe interface unit is configured to acquire 24 switch probe signals simultaneously.

[0140] The signal processing module includes a resistor divider network and an optocoupler isolation circuit. The resistor divider network is used to attenuate the high-voltage probe pulse signal to the input threshold range of the optocoupler device, and the optocoupler isolation circuit is used to convert and electrically isolate the attenuated signal to generate a TTL level signal corresponding to the original high-voltage pulse.

[0141] The FPGA control module includes a microcapacitor charge / discharge detection unit and a timestamp recording unit. The microcapacitor charge / discharge detection unit is used to poll the level status of each switch probe channel, and the timestamp recording unit is used to record the precise timestamp of the level transition of each switch probe channel to obtain switch probe timestamp data.

[0142] The data frame encapsulation module is used to encapsulate TTL level signals, switch probe timestamp data, and 64-bit time base data generated by the FPGA global clock into data frames.

[0143] The fiber optic communication module includes primary and backup dual fiber optic channels for parallel transmission of data frames.

[0144] The storage controller module includes a verification unit, a parallel Flash writing unit, and a wear leveling management unit. The verification unit is used to perform integrity verification on the data frame at the receiving end. The parallel Flash writing unit is used to write the verified data to the parallel Flash storage array page by page. The wear leveling management unit is used to dynamically allocate storage physical addresses using a wear leveling algorithm.

[0145] The instruction response module is used to respond to instructions issued by the host computer via the serial port, perform data export or specified block erasure operations, and attach device digital signature and storage physical address to the exported data.

[0146] The high-speed data acquisition and storage system of this application embodiment can implement any of the above acquisition and storage methods, and the specific working process of each module in the acquisition and storage system can be referred to the corresponding process in the above method embodiment.

[0147] In the several embodiments provided in this application, it should be understood that the provided methods and systems can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for example, the division of a certain module is merely a logical functional division, and in actual implementation there may be other division methods, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed.

[0148] This application also discloses a computer device.

[0149] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a high-speed data acquisition and storage method as described above.

[0150] This application also discloses a computer-readable storage medium.

[0151] A computer-readable storage medium storing a computer program that can be loaded by a processor and executed as described above in any of the high-speed data acquisition and storage methods.

[0152] The computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device; the program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0153] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0154] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.

Claims

1. A high-speed data acquisition and storage method, characterized in that, The method includes: Real-time acquisition of at least one high-voltage probe pulse signal and 24 switch probe signals; The high-voltage probe pulse signal is attenuated to the input threshold range of the optocoupler through a resistor divider network, and signal conversion and electrical isolation are performed using an optocoupler isolation circuit to generate a TTL level signal corresponding to the original high-voltage pulse. The switch probe signal is subjected to microcapacitor charge and discharge detection. The level status of each switch probe channel is polled by the FPGA, and the precise timestamp of the level transition of each switch probe channel is recorded to obtain the switch probe timestamp data. The TTL level signal, the switch probe timestamp data, and the 64-bit time base data generated by the FPGA global clock are encapsulated into a data frame. The data frames are transmitted in parallel via primary and backup dual fiber optic channels. The receiving end performs integrity verification on the data frame, writes the verified data into the parallel Flash storage array page by page, and uses a wear leveling algorithm to dynamically allocate storage physical addresses. Responding to commands issued by the host computer via serial port, it performs data export or specified block erasure operations, and attaches a device digital signature and storage physical address to the exported data.

2. The high-speed data acquisition and storage method according to claim 1, characterized in that, The resistor voltage divider network includes a first precision resistor and a second precision resistor connected in series, with a voltage division ratio of 1:

100.

3. The high-speed data acquisition and storage method according to claim 1, characterized in that... The steps for detecting the charge and discharge of the switch probe signals using microcapacitors, polling the level status of each switch probe channel via FPGA, and recording the precise timestamps of level transitions in each switch probe channel to obtain switch probe timestamp data include: Each switch probe channel is configured with a parallel microcapacitor, and a constant current source is set to charge and discharge the microcapacitor. The capacitor voltage of each switch probe channel is continuously acquired by an analog-to-digital converter, and the instantaneous slope of the capacitor voltage of each switch probe channel is calculated by an FPGA. When the instantaneous slope of the capacitor voltage of any switch probe channel exceeds a preset threshold, the edge-jumping logic is triggered. The global timer value at the trigger moment is recorded as a timestamp, and the timestamp deviation is corrected according to the preset trace delay parameters to obtain the switch probe timestamp data.

4. The high-speed data acquisition and storage method according to claim 1, characterized in that... The steps of transmitting the data frame in parallel via primary and backup dual fiber optic channels include: Configure the operating parameters of the primary and backup optical fiber channels in the primary and backup dual optical fiber channels; wherein, the primary channel uses an 850 nm wavelength optical module and the backup channel uses a 1310 nm wavelength optical module; A globally incrementing sequence number field is appended to each data frame, and the data frames are sent in parallel through primary and backup dual channels.

5. A high-speed data acquisition and storage method according to claim 4, characterized in that... After the step of transmitting the data frame in parallel via primary and backup dual fiber optic channels, the method further includes: At the receiving end, count the number of erroneous frames in the main channel and the backup channel respectively, and calculate the bit error rate; When the main channel bit error rate exceeds the preset threshold, a channel switching command is triggered; Activate the backup channel transmission queue and retransmit a preset number of historical data frames; Update the channel status register, mark the original primary channel as a backup channel, and reset the bit error rate statistics.

6. A high-speed data acquisition and storage method according to any one of claims 1 to 5, characterized in that... The steps of performing integrity verification on data frames at the receiving end, writing the verified data to the parallel Flash storage array page by page, and dynamically allocating storage physical addresses using a wear leveling algorithm include: The receiving end receives the transmitted data frames and extracts the payload and check field from the data frames. Perform an integrity check on the payload and generate a check result; Upon successful verification, the payload is encrypted to generate an encrypted data block. The encrypted data block is split into multiple sub-data segments and written in parallel to different physical pages of the Flash storage array; Write addresses are dynamically allocated based on the historical write count of each physical page, and the mapping table between logical addresses and physical addresses is updated. If the write fails, perform a preset number of retries and mark the abnormal physical page.

7. A high-speed data acquisition and storage system, characterized in that, The system includes: The signal acquisition module includes a high-voltage probe interface unit and a switch probe interface unit. The high-voltage probe interface unit is configured to acquire at least one high-voltage pulse signal in real time, and the switch probe interface unit is configured to acquire 24 switch probe signals simultaneously. The signal processing module includes a resistor divider network and an optocoupler isolation circuit; wherein, the resistor divider network is used to attenuate the high-voltage probe pulse signal to the input threshold range of the optocoupler device, and the optocoupler isolation circuit is used to perform signal conversion and electrical isolation on the attenuated signal to generate a TTL level signal corresponding to the original high-voltage pulse; The FPGA control module includes a microcapacitor charge / discharge detection unit and a timestamp recording unit; wherein, the microcapacitor charge / discharge detection unit is used to poll the level status of each switch probe channel, and the timestamp recording unit is used to record the precise timestamp of the level transition of each switch probe channel to obtain switch probe timestamp data; The data frame encapsulation module is used to encapsulate the TTL level signal, the switch probe timestamp data, and the 64-bit time base data generated by the FPGA global clock into a data frame. The fiber optic communication module includes primary and backup dual fiber optic channels for transmitting the data frames in parallel. The storage controller module includes a verification unit, a parallel Flash writing unit, and a wear leveling management unit. The verification unit is used to perform integrity verification on the data frame at the receiving end. The parallel Flash writing unit is used to write the verified data to the parallel Flash storage array page by page. The wear leveling management unit is used to dynamically allocate storage physical addresses using a wear leveling algorithm. The instruction response module is used to respond to instructions issued by the host computer via the serial port, perform data export or specified block erasure operations, and attach device digital signature and storage physical address to the exported data.

8. A computer device, characterized in that: It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as claimed in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 6.

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