Adapter device and mainboard detection method

Abstract

The present application provides an adapter device and a motherboard detection method, which can be applied to the field of adapter card technology. The adapter device includes: a control module for adjusting the in-place signal of the control module to a signal adapted to the target interface of the motherboard to be tested in response to a level control signal; a slot module for transmitting the adjusted in-place signal to the target interface so that the motherboard to be tested detects the in-place state of the adapter device; the control module is further configured to send a pulse signal to the target interface when the adapter device is in place; read the level of a first target pin in the target interface; transmit the level of the first target pin to an external test system so that the external test system detects the fault state of the first target pin; and, if there is no fault in the pin of the motherboard to be tested, obtain the target bus signal of the target interface, and transmit a response signal of the target bus signal to the target interface so that the motherboard to be tested detects the path state of the link used to transmit the target bus signal.

Description

Technical Field

[0001] The present application relates to the field of adapter cards, and in particular to an adapter device and a mainboard detection method. Background Art

[0002] In the entire server structure, motherboards (PCBs) serve as the bridge between the CPU (Central Processing Unit) and various components, playing a key role. The quality of PCBs is crucial to the overall performance and stability of the server. Therefore, as a key link in server production, ensuring the quality of PCBs is of paramount importance.

[0003] Conventional technology typically uses general-purpose equipment to test boards with a single power-on, but this doesn't cover all signals. To achieve more comprehensive test coverage, multiple devices are used for testing to ensure that every interface signal is fully verified. However, the frequent device changes and reboots significantly increase testing time and complicate device management and operation. Summary of the Invention

[0004] In view of the above problems, the present application provides a switching device and a mainboard detection method.

[0005] According to the first aspect of the present application, a switching device is provided, comprising: a control module electrically connected to a slot module, for adjusting the in-place signal of the control module to a signal adapted to a target interface of a motherboard to be tested in response to a level control signal from an external test system, and sending the adjusted in-place signal to the slot module; the slot module electrically connected to the target interface, for transmitting the received adjusted in-place signal to the target interface, so that the motherboard to be tested detects the in-place state of the switching device based on the adjusted in-place signal; the control module is further configured to send a fault detection signal to the target interface in response to a fault detection signal from the external test system when the switching device is in place. pulse signal; reading the level of the first target pin in the above-mentioned target interface; transmitting the level of the above-mentioned first target pin to the above-mentioned external test system, so that the above-mentioned external test system detects the fault state of the first target pin on the above-mentioned motherboard to be tested based on the level of the above-mentioned first target pin, and sends a target bus detection signal to the above-mentioned control module when it is determined that there is no fault in the pin of the above-mentioned motherboard to be tested; in response to the target bus detection signal from the above-mentioned external test system, obtaining the target bus signal of the above-mentioned target interface, and transmitting a response signal for the above-mentioned target bus signal to the above-mentioned target interface, so that the above-mentioned motherboard to be tested detects the path state of the link used to transmit the above-mentioned target bus signal based on the above-mentioned response signal.

[0006] The second aspect of the present application provides a motherboard detection method, comprising: utilizing a control module, in response to a level control signal from an external test system, adjusting the in-place signal of the control module to a signal adapted to a target interface of the motherboard to be tested, and sending the adjusted in-place signal to the slot module; utilizing the slot module, transmitting the received adjusted in-place signal to the target interface, so that the motherboard to be tested detects the in-place state of the adapter device based on the adjusted in-place signal; utilizing the control module, in the case where the adapter device is in place, in response to a fault detection signal from the external test system, sending a pulse signal to the target interface; reading the target interface; the level of the first target pin in the interface; transmitting the level of the above-mentioned first target pin to the above-mentioned external test system, so that the above-mentioned external test system detects the fault state of the first target pin on the above-mentioned mainboard to be tested based on the level of the above-mentioned first target pin, and sends a target bus detection signal to the above-mentioned control module when it is determined that there is no fault in the pin of the above-mentioned mainboard to be tested; in response to the target bus detection signal from the above-mentioned external test system, obtain the target bus signal of the above-mentioned target interface, and transmit the response signal for the above-mentioned target bus signal to the above-mentioned target interface, so that the above-mentioned mainboard to be tested detects the path state of the link used to transmit the above-mentioned target bus signal based on the above-mentioned response signal.

[0007] According to the adapter device and motherboard detection method provided by the present application, based on the adapter device, when the motherboard to be tested is powered on once, it is possible to detect multiple signals such as the in-place signal, the fault status of the pins and the target bus signal on the motherboard to be tested, thereby avoiding problems such as complex changes and a significant extension of the test cycle caused by multiple equipment replacements. In addition, the adapter device can also dynamically adjust the in-place signal of the adapter device based on the different requirements of the interface of the motherboard to be tested to adapt to the requirements of different motherboards to be tested. At the same time, when it is determined that the adapter device is in place, the adapter device actively sends a pulse signal to the pin in the target interface of the motherboard to be tested, so as to determine whether the first target pin is in a fault state by reading the level of the first target pin associated with the pin in the target interface, and then determine the fault state of all pins on the motherboard to be tested, so as to ensure that the pins on the motherboard to be tested are well soldered. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings.

[0009] Figure 1 A schematic diagram of a switching device according to an embodiment of the present application is shown.

[0010] Figure 2 A schematic diagram of a plug-in module in a switching device according to an embodiment of the present application is shown.

[0011] Figure 3 A schematic diagram of the connection between the MCIO adapter and the motherboard to be tested according to an embodiment of the present application is shown.

[0012] Figure 4 A schematic diagram of the connection between the adapter device for PCIeX16 and the motherboard to be tested according to an embodiment of the present application is shown.

[0013] Figure 5 A schematic diagram of a link for transmitting a target bus signal according to an embodiment of the present application is shown.

[0014] Figure 6 A schematic diagram of a serial port in a switching device according to an embodiment of the present application is shown.

[0015] Figure 7 A flow chart of detecting a target bus signal according to an embodiment of the present application is shown.

[0016] Figure 8 A schematic diagram of a sensing unit in a switching device according to an embodiment of the present application is shown.

[0017] Figure 9 A flow chart of a motherboard detection method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0019] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0020] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0021] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0022] In the process of implementing this application, it was found that the current production quality inspection of boards and cards mainly consists of two parts of tests, namely ICT (In-Circuit Test) and FCT (Functional Circuit Test). Among them, FCT simulates the real working environment to test the performance of the board and card in actual application, verifying the reliability of its interface and signal, and has this irreplaceable role.

[0023] Related testing solutions include using universal equipment for a single power-on test. This approach typically uses universal equipment to test the board in a single power-on, covering as many major interface connection signals as possible. This single power-on test reduces the time and testing process required for repeated power-ups, achieving the desired test results in the shortest possible time. Furthermore, universal, standardized equipment can cover the vast majority of board signals and meet the testing requirements for most common signals.

[0024] While testing solutions based on general-purpose equipment offer significant advantages in cost control and efficiency, they cannot cover all signals, especially complex and specially defined signals (such as clock signals and reset lights), increasing the risk of missed tests. Furthermore, signals not covered by general-purpose equipment are critical to device performance and stability, potentially leading to system instability or failures during use.

[0025] Specifically, in some highly complex designs, multiple signals may interact or depend on each other, such as timing relationships and signal synchronization issues. General-purpose equipment often cannot effectively capture these complex signal interactions, making it easy to overlook potential issues. These interaction issues may not become apparent until after the product is released to the market, leading to repairs or customer complaints, increasing after-sales costs and brand risk. Because missed signals are recorded and marked as risky shipments, potential uncertainty exists before the product leaves the factory. This makes it difficult to verify and track missed signals, complicating later problem location and repair, impacting product quality control and customer satisfaction. Furthermore, since missed signals cannot be effectively verified during the production process, end users may experience performance degradation or system instability. Once a problem is discovered, repair or replacement work is arduous, and due to insufficient testing, the root cause is difficult to quickly locate, increasing the burden and cost of after-sales service. High-end customized products, due to the unique interfaces, often have additional specialized signal definitions that are difficult to cover with standard test cards. These specially defined pins are critical to the functionality and performance of the entire product, making testing with general-purpose equipment extremely risky.

[0026] Based on the above, while general-purpose testing solutions are suitable for most common hardware designs, they may not fully meet the quality testing needs of some demanding, high-end products. Therefore, further improvements are needed in detecting high-risk signals to ensure high product reliability and stability.

[0027] Related art testing solutions also include replacing multiple devices for multiple tests. To achieve more comprehensive test coverage, multiple devices can be replaced for testing to ensure that each interface signal can be fully verified. The core of this solution is to increase the type and number of devices, using dedicated equipment for testing different signals to ensure comprehensive signal coverage. However, due to the need to frequently replace devices and perform multiple restarts, testing time will increase significantly, and the complexity of device management and operation will also increase accordingly.

[0028] Specifically, because testing requires the use of multiple different devices, each device must be replaced after each test. This is especially time-consuming when testing different interfaces or signals, as the device switching process, including device connection and interface configuration, can reduce testing efficiency. This significantly extends the production cycle when testing batch products, impacting overall production efficiency. Furthermore, after replacing each device, each device must be initialized, configured, and restarted, which is not only time-consuming but can also lead to technical issues or operational errors. Device failures and configuration errors can directly impact testing progress and increase maintenance and repair time.

[0029] Furthermore, as the number and variety of devices increase, operators need to master the use and switching procedures of multiple devices. A slight oversight during the testing process can lead to incorrect device connections, configuration errors, or signal measurement errors, increasing operational complexity. This requires more training to familiarize staff with the functions, configurations, and operating procedures of each device, increasing training costs and potentially making training more difficult due to staff turnover.

[0030] Furthermore, to ensure that every signal is effectively tested, multiple specialized test equipment must be purchased. Each piece of equipment not only has an initial purchase cost but also requires regular maintenance and calibration, increasing the company's equipment investment and long-term operational costs. As the number and variety of equipment increases, the difficulty of storing, managing, and maintaining the equipment increases. Furthermore, compatibility issues can arise between different devices, especially when there are differences in vendor, hardware configuration, and interface protocols, making analysis and resolution difficult. Frequent equipment changes for testing generate a large amount of test data, often with significant redundancy, making the aggregation, organization, and analysis of overall test results challenging. The design of diagnostic programs for the board itself is complex, the logic control is challenging, and version switching and control are cumbersome, making them unsuitable for factory production. Changes to interface protocols or signals require new test fixtures to accommodate them, forcing the factory to re-evaluate, apply for, and build a new test environment. This solution lacks flexibility for design changes, especially during the development phase.

[0031] Based on the above, comprehensive testing by replacing multiple devices can ensure coverage of all interface signals and is particularly suitable for products requiring high-precision testing and high quality. However, increasing the number and type of equipment significantly increases testing time, management difficulty and costs, and the complexity of the test procedures, while also reducing test flexibility. Therefore, due to the high complexity of this solution, the large number of devices involved, the long testing time, and the huge investment in manpower and time, factories often do not adopt this solution.

[0032] To this end, an embodiment of the present application provides a switching device to implement testing and response to multiple signals on the motherboard, thereby enhancing the compatibility, reliability, and stability of the system.

[0033] Figure 1 A schematic diagram of a switching device according to an embodiment of the present application is shown.

[0034] like Figure 1 As shown, the adapter 100 includes a control module 110 and a slot module 120. The control module 110 is electrically connected to the slot module 120, the control module 110 is electrically connected to the external test system 130, and the slot module 120 is electrically connected to the target interface of the motherboard to be tested 140.

[0035] Based on the above content, it can be known that during the process of testing the motherboard 140 to be tested, the adapter 100 is electrically connected to the target interface of the motherboard 140 to be tested via the slot module 120 .

[0036] In one embodiment, although the adapter device 100 is electrically connected to the target interface of the motherboard to be tested 140, the slot module 120 of the adapter device 100 may still have problems such as poor contact with the target interface of the motherboard to be tested 140. In order to ensure that the adapter device 100 is indeed connected to the target interface of the motherboard to be tested 140 and the contact is stable, it is necessary to detect the in-place signal.

[0037] According to an embodiment of the present application, when the adapter 100 is electrically connected to the motherboard under test 140, the external test system 130 can send a level control signal to the control module 110. In response to the level control signal, the control module 110 can adjust the in-position signal of the control module 110 to a signal adapted to the target interface of the motherboard under test 140.

[0038] The presence signal of the control module 110 is the presence signal of the adapter 100 .

[0039] According to an embodiment of the present application, when the motherboard to be tested 140 is turned on, the motherboard to be tested 140 will read the presence signal of the adapter device 100 to detect the presence status of the adapter device based on the presence signal of the adapter device 100, thereby determining whether the adapter device 100 has been installed to the target interface of the motherboard to be tested 140.

[0040] The in-place status of the adapter device can indicate whether the adapter device is successfully connected to the mainboard to be tested.

[0041] In one embodiment, the motherboard under test 140 reads the presence signal of the adapter device 100. Specifically, the control module 110 sends the adjusted presence signal to the slot module 120, and the slot module 120 transmits the adjusted presence signal to the target interface of the motherboard under test 140, so that the motherboard under test 140 can read the presence signal of the adapter device 100.

[0042] According to an embodiment of the present application, based on the types of different interfaces on the motherboard under test, the interfaces on the motherboard under test may use different presence signals to detect whether the device is correctly connected to the motherboard under test. That is, different interfaces on the motherboard under test may need to detect different presence signals to determine whether the device is correctly connected to the motherboard under test. Therefore, during the process of the adapter device connecting to the target interface of the motherboard under test, the external test system can send a level control signal corresponding to the presence signal requirement of the target interface of the motherboard under test to the control module, so that the control module can adjust the presence signal of the control module to the presence signal of the target interface of the motherboard under test based on the level control signal.

[0043] Based on the above content, it can be seen that since the adapter 100 can adjust its own presence signal, the adapter 100 can adapt to the requirements of different motherboards to be tested, thereby enabling detection of different motherboards to be tested.

[0044] According to an embodiment of the present application, the motherboard under test 140 can detect the presence status of the adapter device based on the presence signal of the adapter device 100. The external test system 130 can obtain the detection result of the motherboard under test 140 on the presence status of the adapter device, and when it is determined that the adapter device is in place, send a fault detection signal to the control module 110 to instruct the adapter device 100 to detect the fault status of the pin of the target interface of the motherboard under test 140.

[0045] The determination that the adapter is in place indicates that the adapter is successfully connected to the target interface of the mainboard to be tested, and the contact between the adapter and the mainboard to be tested is stable.

[0046] In one embodiment, when the motherboard to be tested determines that the adapter device is not in place, that is, there is a problem such as poor contact between the adapter device and the target interface of the motherboard to be tested, the fault status of the pins in the motherboard to be tested cannot be detected. It is necessary to ensure that the adapter device is in place before detecting the fault status of the pins in the motherboard to be tested, so as to avoid problems such as signal interruption during the detection of the motherboard to be tested, which makes it impossible to continue to detect the motherboard to be tested.

[0047] The fault detection signal may represent a signal used by the control adapter to detect the fault status of a pin on the mainboard to be tested.

[0048] According to an embodiment of the present application, when the control module 110 receives a fault detection signal from the external test system 130 , the control module 110 may send a pulse signal to a target interface of the motherboard under test 140 in response to the fault detection signal.

[0049] In one embodiment, the control module 110 sends a pulse signal to the slot module 120 , and the slot module 120 then transmits the pulse signal to the target interface of the motherboard under test 140 , that is, the control module 110 sends the pulse signal to the target interface through the slot module 120 .

[0050] The pulse signal may be a low-voltage, low-current pulse signal to prevent the motherboard under test from being damaged by excessively high voltage due to insufficient high-voltage tolerance of the motherboard under test.

[0051] According to an embodiment of the present application, based on the design and soldering conditions of the motherboard under test 140, when the control module 110 sends a pulse signal to the target interface of the motherboard under test 140, the pins in the target interface may be affected by the pulse signal. Therefore, the control module 110 can determine whether the pins are affected by the pulse signal by reading the voltage level of the pins in the target interface, thereby determining whether the pins are faulty.

[0052] The first target pin may represent a pin associated with a pin in the target interface that receives the pulse signal.

[0053] Specifically, the control module 110 may transmit the read level of the first target pin to the external test system 130. The external test system 130 may detect the fault state of the first target pin on the motherboard under test 140 according to the level of the first target pin.

[0054] Specifically, the external test system 130 may compare the level of the first target pin with an expected level, and determine the fault state of the first target pin based on the comparison result, wherein the expected level is determined according to the pulse signal.

[0055] In one embodiment, a pulse signal can be sent to the slot module 120 through a pin in the control module 110, and the slot module 120 can send the pulse signal to a pin in the target interface of the motherboard to be tested 140 that is electrically connected to the pin that sends the pulse signal in the control module 110.

[0056] Based on the above content, by sending a pulse signal to the target interface of the motherboard to be tested, the fault status of all pins in the target interface can be detected, and based on the detection of all target interfaces on the motherboard to be tested, the fault status of all pins in all target interfaces on the motherboard to be tested can be detected.

[0057] According to an embodiment of the present application, when the external test system determines that there are no faults in all pins in all target interfaces on the motherboard to be tested, a target bus detection signal can be sent to the control module to instruct the adapter to detect the target bus signal of the target interface of the motherboard to be tested.

[0058] In one embodiment, when the external test system determines that there is a pin fault on the motherboard to be tested, the target bus signal of the target interface of the motherboard to be tested cannot be detected. It is necessary to detect the target bus signal of the target interface of the motherboard to be tested only after determining that there is no pin fault on the motherboard to be tested.

[0059] Therefore, when it is determined that a pin on the motherboard to be tested is faulty, further testing of the motherboard to be tested is stopped, and the faulty pin on the motherboard to be tested is repaired until the pin on the motherboard to be tested is no longer faulty.

[0060] In one embodiment, a motherboard under test typically requires an attached device for testing. While the motherboard under test supports signal transmission and data exchange based on a target bus, the attached device may not support the target bus. Consequently, the attached device cannot detect the target bus signals on the motherboard under test. To detect the target bus signals on the motherboard under test, the attached device must be replaced, which can increase the test cycle and lead to other issues.

[0061] Based on this, the adapter device of the present application supports the target bus, avoiding the need to replace the device, and can also detect the target bus signal of the motherboard to be tested.

[0062] Specifically, upon receiving the target bus detection signal, the control module can obtain the target bus signal of the target interface and transmit a response signal of the target bus signal to the target interface. Thus, the motherboard under test can detect the path status of the link used to transmit the target bus signal based on the response signal.

[0063] In one embodiment, the control module 110 may be a microcontroller unit (MCU), and the external test system 130 may be a functional circuit test (FCT) system.

[0064] According to the embodiments of the present application, based on the adapter, when the motherboard to be tested is powered on once, it is possible to detect multiple signals including the in-place signal, the fault status of the pins and the target bus signal on the motherboard to be tested, thereby avoiding problems such as complex changes and a significant extension of the test cycle caused by multiple equipment replacements. In addition, the adapter can also dynamically adjust the in-place signal of the adapter based on the different requirements of the interface of the motherboard to be tested to adapt to the requirements of different motherboards to be tested. At the same time, when it is determined that the adapter is in place, the adapter actively sends a pulse signal to the pin in the target interface of the motherboard to be tested, so as to determine whether the first target pin is in a fault state by reading the level of the first target pin associated with the pin in the target interface, and then determine the fault state of all pins on the motherboard to be tested, so as to ensure that the pins on the motherboard to be tested are well soldered.

[0065] According to an embodiment of the present application, the fault detection signal may include a pin disconnection detection signal and a pin short circuit detection signal. The pin disconnection detection signal may indicate that the control adapter detects the disconnection state of the pin of the motherboard under test. The fault state may include a disconnection state. The pulse signal may include a first pulse signal.

[0066] The following is a test to see if there is a short circuit on the pins of the target interface on the motherboard to be tested.

[0067] According to an embodiment of the present application, the control module can also be used to respond to a pin circuit break detection signal, and send a first pulse signal to a pin electrically connected to the second target pin in the target interface through the second target pin on the control module at a preset frequency; read the level of the first target pin, and transmit the level of the first target pin to an external test system, so that the external test system determines the circuit break state of the first target pin on the motherboard to be tested based on the level of the first target pin, and sends a pin short circuit detection signal to the control module when it is determined that there is no circuit breakage on the pin of the motherboard to be tested.

[0068] The pin in the target interface electrically connected to the second target pin and the first target pin are electrically connected to each other on the mainboard to be tested.

[0069] According to an embodiment of the present application, for a plurality of pins in a target interface that are connected on a motherboard to be tested, a pin in the control module that is electrically connected to any of the plurality of pins is used as a second target pin. The control module 110 can transmit a first pulse signal at a preset frequency to a pin in the target interface that is electrically connected to the second target pin via the second target pin.

[0070] The preset frequency is set as needed to verify whether the pin can continuously respond to a pulse signal of a fixed preset frequency, thereby determining whether the pin has a short circuit.

[0071] On this basis, other pins on the control module 110 can read the level of the pins electrically connected to them on the target interface. For example, the control module 110 can read the level of the first target pin electrically connected to it in the target interface through the pin.

[0072] According to an embodiment of the present application, the control module 110 may transmit the read level of the first target pin to an external test system, and the external test system may determine the disconnection state of the first target pin based on the level of the first target pin.

[0073] In one embodiment, the external test system may compare the level of the first target pin with the expected level. If the comparison is consistent, it may be determined that there is no short circuit on the first target pin; if the comparison is inconsistent, it may be determined that there is a short circuit on the second target pin.

[0074] For example, the target interface of the motherboard under test has three ground-related pins, such as Pin 1, Pin 2, and Pin 3. The control module can send a first pulse signal to Pin 1 via a pin electrically connected to Pin 1. Since Pins 1, 2, and 3 are interconnected on the motherboard under test, the control module can read the electrical levels of Pins 1, 2, and 3 via the pins electrically connected to those pins, respectively. If the control module reads the electrical levels of Pins 1 and 2 but not Pin 3, it can be determined that Pin 3 of the target interface of the motherboard under test is open circuit.

[0075] Based on the above content, the adapter device can perform the above operation on multiple connected pins in the target interface of the motherboard to be tested, so as to detect the open circuit status of all pins in the target interface.

[0076] According to an embodiment of the present application, when the external test system determines that there is no short circuit on the pins of the motherboard to be tested, a pin short circuit detection signal can be sent to the control module to instruct the adapter to detect the short circuit status of the pins in the target interface on the motherboard to be tested.

[0077] In one embodiment, when the external test system determines that there is a short circuit on the pins of the motherboard to be tested, the short-circuit status of the pins in the target interface of the motherboard to be tested cannot be detected. It is necessary to detect the short-circuit status of the pins in the target interface after determining that there is no short circuit on the pins of the motherboard to be tested, so as to avoid affecting the short-circuit detection of the pins on the motherboard to be tested due to the short circuit of the pins.

[0078] Therefore, when it is determined that there is a pin break on the mainboard to be tested, the mainboard to be tested is stopped from being tested, and the pin break on the mainboard to be tested is repaired until there is no pin break on the mainboard to be tested.

[0079] According to an embodiment of the present application, in order to detect whether there is a short circuit on the pins on the motherboard to be tested, a first pulse signal can be sent to the pins in the target interface of the motherboard to be tested, and the level of the first target pin on the motherboard to be tested that is connected to the pin of the first pulse signal sent to the target interface is read, so that the external test system can judge the short circuit state of the first target pin based on the level of the first target pin, and thereby realize the detection of the short circuit state of all pins in the target interface.

[0080] The following is a test to determine whether there is a short circuit between any adjacent pins in the target interface on the motherboard to be tested.

[0081] According to an embodiment of the present application, the fault detection signal may further include a pin break detection signal, which may indicate that the control adapter has detected a pin short circuit condition on the motherboard under test. A fault condition may also include a short circuit condition. The pulse signal may further include a second pulse signal, wherein the first pulse signal and the second pulse signal may be the same or different.

[0082] According to an embodiment of the present application, the control module can also be used to send a second pulse signal to the third target pin in the target interface in response to a pin short circuit detection signal; read the level of the first target pin; transmit the level of the first target pin to an external test system, so that the external test system determines the short circuit state between the first target pin and the third target pin based on the level of the first target pin, and sends a functional detection signal to the control module when it is determined that there is no short circuit between any two adjacent pins on the motherboard to be tested.

[0083] The third target pin and the first target pin are any two adjacent pins in the target interface.

[0084] According to an embodiment of the present application, for any two adjacent pins in the target interface on the motherboard to be tested: a first target pin and a third target pin, the control module can send a second pulse signal to the third target pin.

[0085] In one embodiment, the control module may send the second pulse signal to a third target pin on the target interface through the slot module.

[0086] According to an embodiment of the present application, the control module can also read the level of the first target pin, thereby determining the short circuit status between the third target pin and the first target pin based on the level of the first target pin. The short circuit status can indicate whether a short circuit exists between the third target pin and the first target pin on the motherboard under test.

[0087] In one embodiment, if a short circuit occurs between the third target pin and the first target pin on the motherboard to be tested, after the control module sends a second pulse signal to the third target pin, the level of the first target pin will change due to the second pulse signal, so the level of the first target pin read by the control module will change.

[0088] According to an embodiment of the present application, when the level of the first target pin changes, it can be determined that there is a short circuit between the third target pin and the first target pin; when the level of the first target pin does not change, it can be determined that there is no short circuit between the first pin to be tested and the first target pin, that is, the third target pin and the first target pin are well welded.

[0089] According to an embodiment of the present application, the control module may transmit the read level of the first target pin to an external test system, and the external test system may determine a short circuit state between the first target pin and the third target pin based on the level of the first target pin.

[0090] In one embodiment, the external test system may compare the level of the first target pin with the expected level. If the comparison characteristics are consistent, the level of the first target pin changes with the second pulse signal received by the third target pin, and it can be determined that there is a short circuit between the first target pin and the third target pin; if the comparison characteristics are inconsistent, it can be determined that there is no short circuit between the first target pin and the third target pin.

[0091] According to an embodiment of the present application, the control module can send a second pulse signal to the pins on the motherboard to be tested at a preset fixed frequency to detect the short-circuit status of all adjacent pins in the target interface on the motherboard to be tested.

[0092] According to the embodiment of the present application, on the basis of determining whether there are welding abnormalities between adjacent pins on the motherboard to be tested, it is necessary to further combine the design of the motherboard to be tested itself, that is, what needs to be detected are the pins on the motherboard to be tested that have welding problems during the welding process.

[0093] In one embodiment, if a short circuit exists between pins A and B in the design of the motherboard under test, then after a second pulse signal is sent to pin A, the read voltage level of pin B changes, which can also determine that there is no abnormality in the soldering between pins A and B. If a short circuit does not exist between pins A and B in the design of the motherboard under test, then after a second pulse signal is sent to pin A, the read voltage level of pin B changes, which can determine that there is an abnormality in the soldering between pins A and B.

[0094] According to an embodiment of the present application, when the external test system determines that there is no short circuit between any two adjacent pins on the motherboard to be tested, a function detection signal can be sent to the control module to instruct the adapter to perform other function tests on the motherboard to be tested.

[0095] In one embodiment, when the external testing system determines that there is a short circuit on the pins of the motherboard to be tested, the motherboard to be tested cannot be tested any further. It is necessary to test the target interface after determining that there is no short circuit on the pins of the motherboard to be tested, so as to avoid affecting the detection of the motherboard to be tested due to the short circuit of the pins.

[0096] Therefore, when it is determined that two adjacent pins on the motherboard to be tested are short-circuited, the motherboard to be tested is stopped from being tested, and the two short-circuited pins on the motherboard to be tested are repaired until no two adjacent pins on the motherboard to be tested are short-circuited.

[0097] According to an embodiment of the present application, by sending a second pulse signal to one of any two adjacent pins of the target interface on the motherboard to be tested and then reading the level of the other pin, the short-circuit state of the two adjacent pins can be determined based on whether the level of the other pin changes with the second pulse signal, thereby realizing the detection of the welding condition of the pins in the target interface on the motherboard to be tested.

[0098] According to an embodiment of the present application, the control module includes input and output pins, and the second target pin is an input and output pin; the control module can also be used to set the mode of the input and output pin to input mode or output mode in response to a mode control signal for the input and output pin from an external test system.

[0099] According to an embodiment of the present application, the control module may include input and output pins. The mode control signal may represent the mode of the input and output pins in the control module, and the mode may represent the input and output mode of the pins, including input mode and output mode.

[0100] In one embodiment, the input / output pins may be GPIO (General Purpose Input / Output).

[0101] According to an embodiment of the present application, the input and output pins in the control module support flexible configuration and can be controlled by an external test system to set the input and output modes of specified pins in the control module.

[0102] In one embodiment, the external test system may send a mode control signal to the control module. Based on the mode control signal, the control module may determine the input / output pins that require input / output mode adjustment and then set the input / output mode of the pins to the input mode or output mode corresponding to the mode control signal.

[0103] Specifically, when the mode control signal indicates that the pin is set to the input mode, the control module sets the pin to the input mode in response to the mode control signal.

[0104] When the pin is in input mode, the pin is used to receive signals; when the pin is in output mode, the pin is used to output signals.

[0105] In one embodiment, the control module may be configured with 48 input and output pins.

[0106] For example, before the control module sends the first pulse signal through the second target pin, the control module can respond to the mode control signal of the external test system for the second target pin and set the second target pin to output mode so that the second target pin can output the first pulse signal; when the control module needs to receive a signal from the mainboard to be tested through the second target pin, the control module can respond to the mode control signal of the external test system for the second target pin and set the second target pin to input mode so that the second target pin can read the signal of the mainboard to be tested.

[0107] According to the embodiments of the present application, since each input and output pin in the control module can be independently configured as an input mode or an output mode, it can adapt to different application needs to further implement testing of different aspects of the motherboard to be tested.

[0108] Figure 2 A schematic diagram of a plug-in module in a switching device according to an embodiment of the present application is shown.

[0109] like Figure 2 As shown, the adapter 100 may further include a plug-in module 210. The plug-in module 210 may be electrically connected to the control module 110 and the external device 220. The pins of the control module 110 may include a first bus pin and a second bus pin.

[0110] exist Figure 2 In the embodiment, the first bus pin of the control module 110 can be electrically connected to the slot module 120 , and the second bus pin of the control module 110 can be electrically connected to the plug-in module 210 .

[0111] The function detection signal may include a target bus detection signal.

[0112] According to an embodiment of the present application, the control module 110 can also be used to respond to a target bus detection signal from an external test system and determine whether the external device supports target bus communication by scanning the external device 220; if the external device 220 supports target bus communication, the address of the first bus pin can be set to the target bus address of the external device.

[0113] According to an embodiment of the present application, when the external device 220 does not support target bus communication, the address of the first bus pin still uses the default address.

[0114] The first bus pin and the second bus pin can be used to transmit bus signals.

[0115] According to an embodiment of the present application, whether the external device supports target bus communication, that is, whether the external device can receive signals transmitted by the bus.

[0116] According to the embodiments of the present application, neither the motherboard under test nor the external device can sense the presence of the adapter. If the external device supports target bus communication, the address of the first bus pin is set to the target bus address of the external device. The control module can then transparently transmit the signals transmitted by the first bus pin and the second bus pin to the external device without affecting the external device.

[0117] Specifically, the address of the first bus pin is set as the target bus address of the external device so as to make the mainboard under test transparent to the adapter device, and the mainboard under test believes that it is directly connected to the external device.

[0118] Based on the above Figure 2 The external device 220 can be a PCIe (PCI Express) card or an MCIO (Multi-Channel Input / Output) cable. Depending on the type of external device, the adapter device of this application may include an adapter device for PCIeX16 and an adapter device for MCIO. PCI stands for Peripheral Component Interconnect.

[0119] On this basis, the slot module in the adapter for PCIeX16 can be a PCIe gold finger, and the plug-in module can be a PCIe female head; the slot module in the adapter for MCIO can be an MCIO gold finger, and the plug-in module can be an MCIO female head.

[0120] Figure 3 A schematic diagram of the connection between the MCIO adapter and the motherboard to be tested according to an embodiment of the present application is shown.

[0121] like Figure 3 As shown, the slot module 120 in the adapter 100 for MCIO is electrically connected to the target interface of the motherboard to be tested 140 through a cable.

[0122] Figure 4 A schematic diagram of the connection between the adapter device for PCIeX16 and the motherboard to be tested according to an embodiment of the present application is shown.

[0123] like Figure 4 As shown, the slot module 120 in the adapter 100 for PCIeX16 can be directly inserted into the target interface of the motherboard to be tested 140 to achieve electrical connection between the adapter and the motherboard to be tested.

[0124] In one embodiment, the difference between a PCIe X16 adapter and an MCIO adapter lies in the use of a plug-in module and a slot module. The PCIe X16 adapter can be directly plugged into the motherboard under test via the slot module, while the MCIO adapter can be connected to the motherboard under test via a cable.

[0125] Specifically, for the PCIe interface on the motherboard to be tested, a switching device for PCIeX16 can be used; for the MCIO interface on the motherboard to be tested, a switching device for MCIO can be used.

[0126] According to an embodiment of the present application, there are four sets of sideband signals inside the adapter. Depending on the project design, the sideband signals can be used for in-place signals, PowerGood (power good signal), etc.

[0127] The present application provides an adapter device that can perform signal coverage and testing between the PCIe port or MCIO port of the motherboard under test and a standard PCIe card. The sideband signal is detected through the adapter device provided by the present application. The input and output pins derived from the control module inside the adapter device can have their functions set by an external test system, enabling simulated signal input and output, and adaptation to multiple multiplexed sideband signals in MCIO.

[0128] The MCIO adapter connects to an external MCIO cable and detects and configures low-speed signals within the MCIO port. By integrating with an external test system, the adapter accurately detects and configures sideband signals within the MCIO interface, ensuring the integrity of each signal path.

[0129] In one embodiment, the control module in the MCIO adapter is the same as that in the PCIe X16 adapter, reducing development complexity and enabling configuration to adapt to MCIO port testing requirements. For example, by modifying the configuration file to set the levels of the MCIO port's first set of sideband signals, A0-A3, to [low, low, high, high] in sequence, the BIOS (Basic Input / Output System) recognizes the MCIO port as two X4 signals to accommodate the hard drive.

[0130] Figure 5 A schematic diagram of a link for transmitting a target bus signal according to an embodiment of the present application is shown.

[0131] like Figure 5As shown, the first bus pin is used to receive the target bus signal from the target interface of the motherboard under test 140; the control module 110 is also used to forward the target bus signal to the second bus pin when the external device supports target bus communication; the second bus pin is used to transmit the target bus signal to the external device 220, and transmit the response signal from the external device to the motherboard under test through the first bus pin, so that the motherboard under test can detect the path status of the link used to transmit the target bus signal based on the response signal from the external device.

[0132] According to an embodiment of the present application, the target bus signal may represent an I2C (Inter-Integrated Circuit) bus signal, and the first bus pin and the second bus pin may represent pins for transmitting the I2C bus signal.

[0133] According to an embodiment of the present application, a bus pin is also provided on the target interface of the motherboard under test, and a target bus signal can be transmitted to a first bus pin of the control module via the bus pin. If the external device supports target bus communication, the control module can forward the target bus signal to a second bus pin, so that the second bus pin transmits the target bus signal to the external device.

[0134] According to an embodiment of the present application, the external device can respond to the target bus signal and generate a response signal. The external device can transmit the generated response signal to the second bus pin, and the second bus pin can forward the response signal to the first bus pin, which then transmits the response signal to the motherboard under test.

[0135] In one embodiment, when the second bus pin forwards the response signal to the first bus pin, the external test system can send a mode control signal to the control module to adjust the input and output mode of the first bus pin from input mode to output mode, so that the response signal can be transmitted to the motherboard under test by the first bus pin.

[0136] On this basis, the mainboard under test can determine the path status of the target bus signal in the link between the mainboard under test, the control module and the external device based on the response signal.

[0137] The access status of the link can indicate whether the link for transmitting the target bus signal between the mainboard to be tested, the control module and the external device can communicate normally.

[0138] In one embodiment, the motherboard under test may determine whether the link of the target bus signal between the motherboard under test and the external device is connected based on whether a response signal from the external device to the target bus signal is received.

[0139] According to an embodiment of the present application, based on the transmission of the target bus signal between the first bus pin and the second bus pin, the target bus signal on the motherboard to be tested is tested, that is, the link of the target bus is detected when the motherboard to be tested is produced, so as to detect whether the link of the target bus between the motherboard to be tested, the control module and the external device is connected, thereby ensuring that the target bus signal on the motherboard to be tested can be transmitted to the device.

[0140] like Figure 5 As shown, the control module 110 is also used to: when the external device 220 does not support target bus communication, transmit the response signal to the target bus signal to the mainboard under test 140 through the first bus pin, so that the mainboard under test 140 detects the path status of the link used to transmit the target bus signal based on the response signal to the target bus signal.

[0141] According to an embodiment of the present application, when the external device supports target bus communication, the control module can transmit the target bus signal to the external device; when the external device does not support target bus communication, the control module cannot transmit the target bus signal to the external device.

[0142] Therefore, when the external device does not support target bus communication, the control module can respond to the target bus signal upon receiving the target bus signal, and transmit the response signal to the target bus signal to the motherboard under test through the first bus pin.

[0143] On this basis, the mainboard under test can determine the path status of the target bus signal in the link between the mainboard under test, the control module and the external device based on the response signal.

[0144] In one embodiment, the mainboard under test may determine whether the link of the target bus signal between the mainboard under test and the control module is open based on whether a response signal from the control module to the target bus signal is received.

[0145] According to an embodiment of the present application, based on the transmission of the target bus signal between the mainboard to be tested and the control module through the first bus pin, the target bus signal on the mainboard to be tested can be tested, that is, the link of the target bus can be detected when the mainboard to be tested is produced, so as to detect whether the link of the target bus between the mainboard to be tested and the control module is connected, thereby ensuring that the target bus signal on the mainboard to be tested can be transmitted to the device.

[0146] According to an embodiment of the present application, when the mainboard under test receives a response signal, the mainboard under test can determine that the link of the target bus signal on the mainboard under test is connected; when the mainboard under test does not receive a response signal, the mainboard under test can determine that the link of the target bus signal on the mainboard under test is disconnected.

[0147] Based on the above content, when the external device supports target bus communication, the target bus signal can be transmitted to the external device; when the external device does not support target bus communication, the control module can directly respond to the target bus signal to ensure the transmission of the signal, thereby achieving the test of all pins of the motherboard interface to be tested during a single power-on test.

[0148] In one embodiment, the external test system can be set on the motherboard to be tested, thereby, the external test system can generate a report reflecting the path status of the link of the target bus signal based on the path status of the link of the target bus signal on the motherboard to be tested, so as to intuitively display the path status of the link of the target bus signal.

[0149] Furthermore, based on the above, when testing I2C, there are cases where the external device does not support I2C communication, but the motherboard under test does. If the motherboard under test is tested using an external device, the I2C signal of the motherboard under test cannot be detected. To detect the I2C signal of the motherboard under test, the external device must be replaced. However, the adapter device of the present application supports I2C communication and can still detect the I2C signal of the motherboard under test even if the external device does not support I2C, thus avoiding the need to replace the external device.

[0150] Figure 6 A schematic diagram of a serial port in a switching device according to an embodiment of the present application is shown.

[0151] like Figure 6 As shown, the adapter 100 may further include a serial port 610 , a first end of the serial port 610 is electrically connected to the control module 110 , and a second end of the serial port 610 is electrically connected to the external test system 130 .

[0152] exist Figure 6 In the embodiment, the control module 110 is electrically connected to the external test system 130 via the serial port 610. Thus, the external test system 130 can transmit signals to the control module 110 via the serial port 610, and the control module 110 can also transmit signals to the external test system 130 via the serial port 610.

[0153] In one embodiment, the serial port 610 may be used to transmit a mode control signal, a level control signal, a fault detection signal, and a function detection signal from an external test system to the control module 110 .

[0154] The level control signal may be used to adjust a designated pin in the control module 110 to a required level.

[0155] According to an embodiment of the present application, the control module in the adapter is electrically connected to the external test system via a serial port, enabling bidirectional transmission between the control module and the external test system. Furthermore, the use of the serial port simplifies system wiring. Thus, communication between the control module and the external test system via the serial port provides improved stability, reliability, and anti-interference capabilities.

[0156] According to an embodiment of the present application, the input and output pins of the control module include an in-place signal pin; the control module is used to adjust the level of the in-place signal pin to a predetermined level according to a level control signal when the in-place signal pin is in output mode, and send the generated adjusted in-place signal to the slot module.

[0157] According to an embodiment of the present application, the test to be performed on the motherboard to be tested may also include the detection of a presence signal. The presence signal can be used to indicate whether the device is successfully installed on the motherboard to be tested, so as to ensure that the device is correctly identified and can work normally.

[0158] In one embodiment, the input and output pins of the control module may include a presence signal pin, the presence signal pin in the control module is used to be electrically connected to the presence signal pin on the motherboard to be tested, and the presence signal pin is used to transmit the presence signal.

[0159] According to an embodiment of the present application, when testing the in-place signal of the mainboard to be tested, the external test system can send a mode control signal for the in-place signal pin to the control module through the serial port. The control module responds to the mode control signal and sets the input and output mode of the in-place signal pin on the control module to the output mode, so that the in-place signal pin on the control module can output a signal.

[0160] According to an embodiment of the present application, the external test system may also transmit a level control signal to the control module through the serial port, and the control module may set the level of the in-position signal pin to a predetermined level according to the level control signal.

[0161] The level control signal is set according to the motherboard to be tested, and the level control signal is used to indicate that the level of the in-position signal pin is set to a predetermined level.

[0162] Therefore, the serial port has the function of modifying the level of the in-position signal pin of the control module.

[0163] According to an embodiment of the present application, when the level of the in-position signal pin is set to a predetermined level, the control module can generate an in-position signal and send it to the slot module, wherein the in-position signal can represent the level of the in-position signal pin in the control module.

[0164] According to an embodiment of the present application, the slot module can send a presence signal to the motherboard under test. The motherboard under test can determine the presence status of the adapter based on the presence signal. The presence status of the adapter can indicate whether the adapter is installed on the motherboard under test, that is, whether the presence signal pin on the adapter can communicate normally with the presence signal pin on the motherboard under test.

[0165] Therefore, the in-place status of the adapter device can be used to determine whether the in-place signal pins on the mainboard to be tested have been correctly soldered.

[0166] According to an embodiment of the present application, different motherboards under test need to identify different presence signals, that is, different motherboards under test need to identify different presence signals to confirm that a device is in place.

[0167] In one embodiment, the mainboard to be tested may identify the presence signal through the BIOS (Basic Input / Output System) and the BMC (Baseboard Management Controller) to determine the presence status of the adapter.

[0168] In one embodiment, when there are four in-place signal pins and the in-place signal that the motherboard to be tested needs to recognize is "1100", the levels of the four in-place signal pins need to be high level, high level, low level and low level respectively. A level control signal is set based on the in-place signal that the motherboard to be tested needs to recognize, so that the control module sets the levels of the in-place signal pins to predetermined levels, that is, high level, high level, low level and low level respectively according to the level control signal. When the in-place signal received by the motherboard to be tested is "1100", it is determined that the adapter device has been installed on the motherboard to be tested; when the in-place signal received by the motherboard to be tested is not "1100", it is determined that the adapter device is not installed on the motherboard to be tested.

[0169] In the process of detecting the presence signal of other mainboards to be tested, the presence signal that other mainboards to be tested need to identify may be "0011".

[0170] According to an embodiment of the present application, the control module can set the level of the in-position signal pin according to the level control signal to simulate the in-position signal for different motherboards under test. The motherboard under test can identify and determine the in-position state of the adapter device based on the received in-position signal, thereby realizing the detection of the in-position signal of the motherboard under test, that is, realizing the detection of the soldering quality of the in-position signal pin on the motherboard under test during the production process of the motherboard under test.

[0171] Based on the above content, the control module supports input and output pin setting functions, including input and output mode settings and pin level settings, which can simulate and replace in-position signals and other related signals to make up for the functions that standard cards cannot provide.

[0172] Figure 7 A flow chart of detecting a target bus signal according to an embodiment of the present application is shown.

[0173] like Figure 7 As shown, this embodiment includes operations S710 to S780.

[0174] In operation S710 , external devices are scanned to determine whether the external devices support target bus communication.

[0175] According to an embodiment of the present application, if the external device supports target bus communication, operation S720 is performed; if the external device does not support target bus communication, operation S770 is performed.

[0176] In operation S720, the address of the first bus pin is set as a target bus address of the external device.

[0177] The control module performs operation S720.

[0178] In operation S730 , the target interface of the mainboard to be tested sends a target bus signal to the first bus pin.

[0179] In operation S740 , the control module transmits the target bus signal to the external device through the second bus pin.

[0180] In operation S750 , the external device transmits a response signal to the target bus signal to the control module.

[0181] In operation S760, the control module transmits the response signal to the mainboard under test through the first bus pin.

[0182] In operation S770 , the target interface of the mainboard to be tested sends a target bus signal to the first bus pin.

[0183] In operation S780, the control module responds to the target bus signal and transmits the response signal to the mainboard under test through the first bus pin.

[0184] Based on the above content, it can be seen that the control module has powerful hardware functions, especially in GPIO control and I2C communication, and is suitable for high-precision signal testing and response.

[0185] In output mode, each GPIO pin can be independently configured as high or low, thereby simulating or responding to various signals from the motherboard. This allows the control module to precisely control the level of each pin according to different requirements, meeting the testing requirements of different signals.

[0186] Furthermore, the control module configuration management system supports flexible setting updates through configuration files. Users can change the input and output status of GPIO pins simply by updating the configuration file without having to re-upgrade the firmware, greatly improving the maintainability and flexibility of the system.

[0187] The control module features two independent built-in I2C interfaces, supporting high-speed data communication with external devices such as sensors, other MCUs, and peripheral modules. Each I2C interface has independent address and bus configuration, enabling simultaneous connection and data transmission between multiple I2C devices. This enables the MCU to provide efficient control and data processing capabilities in applications where multiple test signals require real-time interaction.

[0188] Figure 8 A schematic diagram of a sensing unit in a switching device according to an embodiment of the present application is shown.

[0189] like Figure 8 As shown, the adapter 100 may further include a sensing unit 810 .

[0190] exist Figure 8 In the embodiment, the input end of the sensing unit 810 is electrically connected to the mainboard to be tested 140 , and the output end of the sensing unit 810 is electrically connected to the control module 110 .

[0191] Specifically, the sensing unit 810 may be electrically connected to the mainboard to be tested 140 through the socket module 120 .

[0192] The sensing unit 810 may be a sensor; and the functional test signal includes a power supply detection signal.

[0193] In one embodiment, if Figure 8 The slot module 120 , the control module 110 , the serial port 610 , the sensing unit 810 , and the plug-in module 210 in the switching device 100 shown can be integrated onto one circuit board.

[0194] According to an embodiment of the present application, the test to be performed on the motherboard to be tested may further include detection of a power supply signal, which may represent the voltage and current of a target interface on the motherboard to be tested.

[0195] Specifically, the input end of the sensing unit 810 may be electrically connected to the power supply pin and the ground pin of the target interface on the motherboard to be tested 140 through the slot module 120 .

[0196] According to an embodiment of the present application, the sensing unit can be used to detect the power supply signal of the target interface on the mainboard to be tested, and send the detected power supply information to the control module; the control module is also used to respond to the power supply detection signal from the external test system, and send the power supply information to the external test system, so that the external test system detects the power supply signal of the target interface of the mainboard to be tested based on the power supply information, and sends a power supply signal abnormality instruction to the control module when it is determined that the power supply signal of the target interface is abnormal; in response to the power supply signal abnormality instruction, an alarm message is issued.

[0197] The power supply information includes the detected voltage and current of the target interface on the mainboard to be tested.

[0198] According to an embodiment of the present application, the control module can send power supply information to an external test system, so that the external test system can determine whether the power supply signal of the target interface is abnormal based on the power supply information. If the external test system determines that the power supply signal is abnormal, it can send a power supply signal abnormality instruction to the control module via the serial port, so that the control module can respond to the power supply signal abnormality instruction and issue an alarm.

[0199] The power supply signal abnormality instruction represents an instruction for controlling the control module to issue an alarm message.

[0200] In one embodiment, the abnormal power supply signal may indicate abnormal changes in voltage and current of the motherboard to be tested.

[0201] Specifically, the alarm information may indicate that an alarm LED (Light Emitting Diode) on the adapter is lit. The control module may control the LED to light up to indicate that the power supply signal on the motherboard under test is abnormal.

[0202] In one embodiment, a sensing unit can detect the power supply signals of four pins within a target interface of a motherboard under test that are associated with power signals. Based on the power supply information of these four pins, an external detection system can determine whether the power supply signals of the pins are abnormal. Specifically, if the supply voltage of three pins is 12V and the supply voltage of one pin is 0V, the external testing system can determine that the power supply signal of the pin with a supply voltage of 0V is abnormal.

[0203] On this basis, if it is determined that the power supply signal is abnormal, it is necessary to repair the power supply signal of the target interface in the motherboard under test until the power supply signal is normal, and then continue other tests on the motherboard under test.

[0204] According to an embodiment of the present application, the sensing unit can detect the power supply signal of the motherboard under test in real time, that is, detect changes in the voltage and current of the motherboard under test in real time. In the event of an abnormal power supply signal, the control module can issue an alarm to indicate the abnormal power supply signal, thereby ensuring the safety of the test environment. Furthermore, detecting the power supply signal of the motherboard under test can ensure the stability of the motherboard's power supply and promptly identify potential problems.

[0205] According to an embodiment of the present application, the control module is further configured to update the firmware of the control module in response to a firmware update signal from an external test system.

[0206] According to an embodiment of the present application, when the serial port receives a firmware update signal from an external test system, the serial port can transmit the firmware update signal to the control module. The control module can update its firmware in response to the firmware update signal.

[0207] According to the embodiments of the present application, the firmware of the control module can be updated via a serial interface to ensure flexible functional expansion and repair during application. Moreover, the functions of the control module can be upgraded and adjusted by updating the firmware without requiring hardware modification.

[0208] According to an embodiment of the present application, the control module is also used to read the level of the enable status pin in the target interface in response to an enable status detection signal from an external test system; and transmit the level of the enable status pin to the external test system so that the external test system detects the enable status of the enable status pin based on the level of the enable status pin.

[0209] The function detection signal also includes an enable state detection signal.

[0210] According to an embodiment of the present application, the control module can also, under the instruction of the external test system, use a designated pin to read the level of the enable state pin of the target interface on the motherboard under test, and transmit the read level of the enable state pin to the external test system, so that the external test system can detect the enable state of the enable state pin based on the level of the enable state pin. The enable state can represent the operating state of the target interface on the motherboard under test, and the operating state of the target interface on the motherboard under test includes high-level enable and low-level enable.

[0211] In one embodiment, when the level of the enable status pin of the motherboard to be tested is read as a high level, it can be determined that the enable status of the enable status pin is high level enable; when the level of the enable status pin of the motherboard to be tested is read as a low level, it can be determined that the enable status of the enable status pin is low level enable.

[0212] According to an embodiment of the present application, the control module reads the level of the enable status pin on the motherboard to be tested and detects the enable status of the enable status pin to achieve enable detection of the motherboard to be tested.

[0213] According to an embodiment of the present application, the control unit is also used to obtain the power management signal of the target interface in response to the power management detection signal from the external test system; transmit the power management signal to the external device; and transmit the response signal from the external device to the power management signal to the mainboard under test, so that the mainboard under test can detect the path status of the link used to transmit the power management signal based on the response signal to the power management signal.

[0214] The function detection signal also includes a power management detection signal.

[0215] According to an embodiment of the present application, the test to be performed on the motherboard to be tested may also include detection of power management signals. The power management signals may include PowerGood (power good signal), PowerEnable (power enable signal), Reset (reset signal) and other signals.

[0216] The power management signal may represent a control signal of a target interface on the motherboard to be tested to an external device.

[0217] For each signal in the power management signal, the target interface on the motherboard to be tested has a pin for outputting each signal.

[0218] According to an embodiment of the present application, the control module can also be used to obtain a power management signal from a target interface on the motherboard under test and transmit the power management signal to an external device. The external device will respond to the power management signal and transmit the generated response signal to the control module. The control module can transmit the response signal of the external device to the power management signal to the motherboard under test, so that the motherboard under test can detect the path status of the link used to transmit the power management signal based on the response signal to the power management signal.

[0219] The access status of the link can indicate whether the link for transmitting the power management signal between the mainboard to be tested and the external device can communicate normally.

[0220] In one embodiment, whether the power management signal link between the motherboard under test and the adapter is open can be determined based on whether the control module receives the power management signal. If the control module receives the power management signal, it can be determined that the power management signal link between the motherboard under test and the adapter is open.

[0221] On this basis, the motherboard under test can also determine whether the power management signal is responded to by the control module or the external device according to the response signal, and determine whether the power management signal link between the motherboard under test, the adapter and the external device is open.

[0222] On this basis, if it is determined that the power management signal link is blocked, it is necessary to repair the link between the motherboard under test, the adapter and the external device until the path status of the power management signal link is connected, and then continue other tests on the motherboard under test.

[0223] According to the embodiment of the present application, the control module can ensure that the power management signal is accurately transmitted, avoid signal loss or timing errors, and ensure that the external device starts and runs at the correct timing.

[0224] Based on the above content, the adapter device of the present application can realize simulation testing and response testing of multiple test signals such as power supply signals, target bus signals, and in-place signals on the motherboard to be tested.

[0225] According to an embodiment of the present application, the function detection signal may further include a clock detection signal. The control module may further respond to the clock detection signal from the external test system by obtaining a clock signal from the motherboard under test and transmitting the clock signal to an external device, so that the external device also operates according to the clock signal, thereby ensuring that the motherboard under test and the external device are synchronized.

[0226] In one embodiment, the control module may further monitor the accuracy of the clock signal and detect the frequency deviation of the clock signal to determine whether the clock signal has changed during transmission, thereby performing fault diagnosis.

[0227] Furthermore, whether the control module can obtain the clock signal can also be used to determine whether there is a soldering problem with the pins transmitting the clock signal on the motherboard to be tested.

[0228] In one embodiment, the external test system may send various detection signals included in the function detection signal to the control module in any order.

[0229] According to an embodiment of the present application, the adapter device can also integrate a self-diagnosis function, which can automatically perform a series of signal verifications when connected to the motherboard to be tested, such as detecting whether the voltage, current, clock and other signals are normal, and feedback to the external test system through the serial interface.

[0230] Therefore, the self-diagnosis function of the adapter can ensure that the adapter and the external device are in normal working condition before testing, avoiding inaccurate test results due to hardware failure.

[0231] According to an embodiment of the present application, the control module of the adapter can also support programming and configuration, allowing users to customize and load program configurations, control signals through the adapter, and automatically execute test tasks. This function supports the automatic generation of test reports, improving test efficiency and accuracy.

[0232] Based on the above content, it can be seen that the adapter device of the present application performs outstandingly in the full coverage test of the interface signals of the motherboard to be tested. Through a power-on test, all interface signals can be completely tested, which makes up for the deficiency that the traditional standard test card cannot cover some signals. Compared with the traditional method, the present application does not need to switch multiple external devices or restart the machine multiple times, which significantly reduces the time cost and manpower input of production testing. By integrating multiple test functions into one, the number of devices and the complexity of program logic are reduced, making the entire full-signal testing process more efficient and simple. This not only improves the test efficiency, but also enables the full-signal test to be smoothly applied to the board production process of the factory, ensuring product quality while greatly improving the automation level of the production line.

[0233] Figure 9 A flow chart of a motherboard detection method according to an embodiment of the present application is shown.

[0234] like Figure 9 As shown, the method 900 includes operations S910 to S930.

[0235] According to an embodiment of the present application, the method 900 can be applied to Figures 1 to 6 and Figure 8 In the adapter shown.

[0236] In operation S910, the control module adjusts the presence signal of the control module to a signal adapted to the target interface of the motherboard under test in response to a level control signal from an external test system, and sends the adjusted presence signal to the slot module.

[0237] In operation S920, the slot module is used to transmit the received adjusted presence signal to the target interface, so that the mainboard to be tested detects the presence status of the adapter device based on the adjusted presence signal.

[0238] In operation S930, using the control module, when the adapter is in place, in response to the fault detection signal from the external test system, a pulse signal is sent to the target interface; the level of the first target pin in the target interface is read; the level of the first target pin is transmitted to the external test system, so that the external test system detects the fault state of the first target pin on the mainboard to be tested based on the level of the first target pin, and sends a target bus detection signal to the control module when it is determined that there is no fault on the pin of the mainboard to be tested; in response to the target bus detection signal from the external test system, the target bus signal of the target interface is obtained, and a response signal for the target bus signal is transmitted to the target interface, so that the mainboard to be tested detects the path state of the link used to transmit the target bus signal based on the response signal.

[0239] According to the embodiments of the present application, based on the adapter, when the motherboard to be tested is powered on once, it is possible to detect multiple signals including the in-place signal, the fault status of the pins and the target bus signal on the motherboard to be tested, thereby avoiding problems such as complex changes and a significant extension of the test cycle caused by multiple equipment replacements. In addition, the adapter can also dynamically adjust the in-place signal of the adapter based on the different requirements of the interface of the motherboard to be tested to adapt to the requirements of different motherboards to be tested. At the same time, when it is determined that the adapter is in place, the adapter actively sends a pulse signal to the pin in the target interface of the motherboard to be tested, so as to determine whether the first target pin is in a fault state by reading the level of the first target pin associated with the pin in the target interface, and then determine the fault state of all pins on the motherboard to be tested, so as to ensure that the pins on the motherboard to be tested are well soldered.

[0240] According to an embodiment of the present application, multiple target interfaces on the mainboard to be tested are electrically connected to respective adapter devices.

[0241] In one embodiment, the target interface on the motherboard to be tested may include a PCIe port and an MCIO port. For the PCIe interface, a switching device for PCIeX16 may be used; for the MCIO interface, a switching device for MCIO may be used.

[0242] Therefore, before testing the mainboard to be tested, all target interfaces on the mainboard to be tested are connected to the adapter device.

[0243] According to an embodiment of the present application, the mainboard to be tested includes multiple target interfaces. During the detection of the mainboard to be tested, the adapter device of the present application can be electrically connected to the corresponding target interface on the mainboard to be tested, so that all interface signals can be fully tested through a single power-on test.

[0244] Based on the above, it can be seen that the motherboard detection method using the adapter device of this application can be performed efficiently and stably during the factory board production process. The entire process simplifies the testing process, avoids the tediousness of multiple device switching or machine restarts, and reduces the number of equipment and labor input in factory production. At the same time, the adapter device achieves comprehensive coverage testing of the motherboard interface signals, ensuring the high quality of the signal link, providing higher test accuracy and reliability for the product, so that it can be implemented in actual production.

[0245] This application also achieves full coverage testing of the motherboard interface signals to be tested, ensuring that every signal of the board is accurately detected and adjusted during the production process. This not only improves test accuracy, but also reduces the production of defective products, ensuring the high quality and reliability of the product.

[0246] Another notable feature of this application is its reduced reliance on standard PCIe equipment. By using customized adapters and universal equipment, all signal testing requirements can be met without relying on dedicated PCIe test equipment. This innovation not only reduces the need for high-cost, specialized hardware, but also increases the versatility and flexibility of test equipment, allowing production lines to complete comprehensive signal testing without adding additional equipment. This approach not only reduces equipment procurement and maintenance costs, but also simplifies the production testing process, providing factories with greater economic benefits and operational convenience.

[0247] Compared with the traditional method of multiple equipment replacement, this application significantly reduces the complexity of the test procedure and reduces the operation links, thereby effectively reducing the probability of error. At the same time, the use of general equipment for full signal testing reduces the dependence on dedicated test equipment, significantly reduces equipment investment and costs, and also reduces the maintenance pressure of equipment inventory. In addition, this application simplifies the test process, reduces the technical requirements for testers, improves the convenience and efficiency of operation, and provides greater flexibility and cost-effectiveness for factory production.

[0248] Since the control module on the adapter device has flexible programmable and configurable functions, this application provides a flexible and convenient interface for factory FCT testing, greatly improving the automation program in the testing process and improving the level of factory automation and intelligent testing.

[0249] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0250] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A switching device, characterized in that: The switching device comprises: a control module electrically connected to the slot module, configured to adjust the presence signal of the control module to a signal adapted to the target interface of the motherboard to be tested in response to a level control signal from an external test system, and to send the adjusted presence signal to the slot module; The slot module is electrically connected to the target interface and is used to transmit the received adjusted in-place signal to the target interface, so that the motherboard to be tested detects the in-place status of the adapter based on the adjusted in-place signal; The control module is also used to sending a pulse signal to the target interface in response to a fault detection signal from the external test system when the switching device is in place; Reading the level of a first target pin in the target interface; transmitting the level of the first target pin to the external test system, so that the external test system detects a fault state of the first target pin on the motherboard under test based on the level of the first target pin, and sends a target bus detection signal to the control module if it is determined that the pin of the motherboard under test does not have a fault; In response to the target bus detection signal from the external test system, the target bus signal of the target interface is obtained, and a response signal for the target bus signal is transmitted to the target interface, so that the motherboard under test detects the path status of the link used to transmit the target bus signal based on the response signal.

2. The switching device according to claim 1, characterized in that: The fault detection signal includes a pin disconnection detection signal and a pin short circuit detection signal, the fault state includes a disconnection state, and the pulse signal includes a first pulse signal; The control module is also used to In response to the pin disconnection detection signal, sending the first pulse signal at a preset frequency to a pin in the target interface electrically connected to the second target pin through a second target pin on the control module; reading a level of the first target pin, wherein a pin in the target interface electrically connected to the second target pin and the first target pin are electrically connected on the motherboard to be tested; The electrical level of the first target pin is transmitted to the external test system, so that the external test system determines the short circuit state of the first target pin on the motherboard to be tested based on the electrical level of the first target pin, and sends a pin short circuit detection signal to the control module when it is determined that the pin of the motherboard to be tested is not short circuited.

3. The switching device according to claim 2, characterized in that: The fault state also includes a short circuit state, and the pulse signal also includes a second pulse signal; The control module is also used to In response to the pin short circuit detection signal, sending a second pulse signal to a third target pin in the target interface; reading the level of the first target pin, wherein the third target pin and the first target pin are any two adjacent pins in the target interface; The electrical level of the first target pin is transmitted to the external test system, so that the external test system determines the short-circuit state between the first target pin and the third target pin based on the electrical level of the first target pin, and sends a functional detection signal to the control module when it is determined that there is no short circuit between any two adjacent pins on the motherboard to be tested.

4. The switching device according to claim 3, characterized in that: The control module includes an input and output pin, and the second target pin is the input and output pin; The control module is further configured to set the mode of the input / output pin to an input mode or an output mode in response to a mode control signal for the input / output pin from the external test system.

5. The switching device according to claim 4, characterized in that: The adapter device further includes a plug-in module, the plug-in module is electrically connected to the control module and the external device, a first bus pin of the control module is electrically connected to the slot module, a second bus pin of the control module is electrically connected to the plug-in module, and the function detection signal includes the target bus detection signal; The control module is also used to In response to a target bus detection signal from the external test system, determining whether the external device supports target bus communication by scanning the external device; In a case where the external device supports target bus communication, the address of the first bus pin is set as the target bus address of the external device.

6. The switching device according to claim 5, characterized in that: The first bus pin is used to receive a target bus signal from the target interface; The control module is further configured to forward the target bus signal to the second bus pin when the external device supports target bus communication; The second bus pin is used to transmit the target bus signal to the external device, and transmit the response signal from the external device to the motherboard under test through the first bus pin, so that the motherboard under test can detect the path status of the link used to transmit the target bus signal based on the response signal from the external device.

7. The switching device according to claim 6, characterized in that: The control module is further configured to: When the external device does not support target bus communication, a response signal to the target bus signal is transmitted to the motherboard under test through the first bus pin, so that the motherboard under test detects the path status of the link used to transmit the target bus signal based on the response signal to the target bus signal.

8. The switching device according to claim 4, characterized in that: The adapter device also includes a serial port, a first end of the serial port is electrically connected to the control module, and a second end of the serial port is electrically connected to the external test system. The serial port is used to transmit the mode control signal, level control signal, fault detection signal and function detection signal from the external test system to the control module.

9. The switching device according to claim 8, characterized in that: The input and output pins of the control module include in-position signal pins; The control module is configured to adjust the level of the presence signal pin to a predetermined level according to the level control signal when the presence signal pin is in output mode, and send the generated adjusted presence signal to the slot module.

10. The switching device according to claim 4, characterized in that: The adapter device further includes a sensing unit, an input end of the sensing unit is electrically connected to the motherboard to be tested, an output end of the sensing unit is electrically connected to the control module, and the function detection signal includes a power supply detection signal; The sensing unit is used to detect the power supply signal of the target interface and send the detected power supply information to the control module; The control module is also used to In response to a power supply detection signal from the external test system, the power supply information is sent to the external test system, so that the external test system detects the power supply signal of the target interface of the motherboard to be tested based on the power supply information, and sends a power supply signal abnormality instruction to the control module if it is determined that the power supply signal of the target interface is abnormal; In response to the power supply signal abnormality instruction, an alarm message is issued.

11. The switching device according to claim 1, characterized in that: The control module is further configured to update the firmware of the control module in response to a firmware update signal from the external test system.

12. The switching device according to claim 4, characterized in that: The function detection signal also includes an enable state detection signal; The control module is also used to In response to an enable status detection signal from the external test system, reading a level of an enable status pin in the target interface; The level of the enable state pin is transmitted to the external test system, so that the external test system detects the enable state of the enable state pin according to the level of the enable state pin.

13. The switching device according to claim 5, characterized in that: The function detection signal also includes a power management detection signal; The control module is also used to acquiring a power management signal of the target interface in response to a power management detection signal from the external test system; transmitting the power management signal to the external device; A response signal from the external device to the power management signal is transmitted to the mainboard under test, so that the mainboard under test detects a path status of a link for transmitting the power management signal based on the response signal to the power management signal.

14. A motherboard detection method, applied to the adapter device according to any one of claims 1 to 13, characterized in that: The mainboard detection method comprises: Using the control module, in response to a level control signal from an external test system, adjusting the presence signal of the control module to a signal adapted to a target interface of the motherboard to be tested, and sending the adjusted presence signal to the slot module; Using the slot module, transmitting the received adjusted in-place signal to the target interface, so that the motherboard to be tested detects the in-place status of the adapter device based on the adjusted in-place signal; Using the control module, sending a pulse signal to the target interface in response to a fault detection signal from the external test system when the switching device is in place; Reading the level of a first target pin in the target interface; transmitting the level of the first target pin to the external test system, so that the external test system detects a fault state of the first target pin on the motherboard under test based on the level of the first target pin, and sends a target bus detection signal to the control module if it is determined that the pin of the motherboard under test does not have a fault; In response to the target bus detection signal from the external test system, the target bus signal of the target interface is obtained, and a response signal for the target bus signal is transmitted to the target interface, so that the motherboard under test detects the path status of the link used to transmit the target bus signal based on the response signal.

15. The motherboard detection method according to claim 14, characterized in that: The multiple target interfaces on the mainboard to be tested are electrically connected to their respective adapters.

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