A small signal parameter extraction method and system for large gate width gallium nitride transistors

Abstract

The present invention discloses a small-signal parameter extraction method and system for large-gate-width gallium nitride transistors, which are applied to circuit analysis and semiconductor device applications. The method comprises: obtaining the measured Y parameters of the transistor under low-frequency cold pinch-off conditions to define the optimization range of the transistor's parasitic capacitance, and optimizing the parasitic capacitance using the SQP algorithm; obtaining the measured Y parameters of the transistor under cold unbiased conditions, combining them with the obtained parasitic capacitance to perform parasitic capacitance parameter stripping, and extracting the transistor's parasitic inductance and parasitic resistance based on the Z parameters; stripping the obtained parasitic inductance and parasitic resistance, converting the Z parameters into Y parameters, and extracting the initial values ​​of the intrinsic transconductance and output resistance using a frequency-band weighted method; obtaining the initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance, and optimizing each intrinsic parameter using the SQP algorithm. The present invention effectively improves the accuracy and efficiency of small-signal parameter extraction for large-gate-width gallium nitride transistors.

Description

Technical Field

[0001] The present invention relates to the fields of circuit analysis and semiconductor device applications, and in particular to a small-signal parameter extraction method and system for large-gate-width gallium nitride transistors. Background Art

[0002] Accurate and efficient small-signal model parameter extraction methods can improve the consistency between transistor model predictions and actual device characteristics, thereby providing a reliable foundation for subsequent large-signal model development and circuit design optimization. Large-gate-width gallium nitride (GaN) transistors are larger in size and more complex in structure, with more significant parasitic and secondary effects (such as skin effect, proximity effect, and non-quasi-static effects). Using traditional small-signal parameter extraction methods will make it difficult to avoid low-frequency dispersion effects, which in turn introduces significant errors in the S-parameter predictions of the small-signal model. Therefore, achieving accurate and efficient small-signal parameter extraction for high-precision modeling of large-gate-width GaN HEMTs has become a pressing issue.

[0003] Currently, numerous researchers, both domestically and internationally, have conducted extensive research on small-signal equivalent circuit model parameter extraction methods for GaN HEMTs. In 2016, Ahmed S. Hussein et al. from the University of Sharjah, UAE, proposed a hybrid small-signal parasitic parameter extraction method based on a combination of particle swarm optimization (PSO) and least-squares fitting. This method first obtains initial parasitic parameter values ​​using S-parameter fitting under cold pinch-off and zero-bias conditions. PSO is then used to optimize the parasitic parameters, ultimately determining the optimal solution based on an error minimization criterion. While this method improves parameter extraction accuracy to a certain extent, it still suffers from significant errors at high drain currents. In 2017, Wen Zhang et al. from the University of Electronic Science and Technology of China proposed a high-precision small-signal parameter extraction method that combines traditional parameter sweeping with an iterative algorithm. This method extracts parasitic and intrinsic parameters through a combination of multiple scans and iterative corrections, gradually eliminating accumulated errors. However, this method uses a pure search algorithm to optimize the external parasitic elements of the small-signal equivalent circuit model without considering their physical significance. This introduces uncertainty into the small-signal parameter extraction, and the extraction results may exceed the reasonable parameter range. In 2022, Ruilin Guan et al. from South China University of Technology proposed a small-signal parameter extraction method based on reverse differentiation and frequency band extraction. This method extracts initial parasitic parameter values ​​based on S-parameters under cold pinch-off and zero-bias conditions, and optimizes them using inverse matrix and reverse differentiation operations. A frequency segmentation strategy is also introduced to improve the accuracy of parasitic inductance and capacitance parameter extraction. Although this method improves model accuracy, it is limited by the frequency segmentation technology, requiring repeated parameter extraction and matrix operations for each segment, resulting in an increase in the overall number of operations. Therefore, its convergence speed still needs to be improved. In 2024, Aisha Mansour et al. from the University of Sharjah in the United Arab Emirates compared the performance of the Sine-Cosine algorithm, the Grey Wolf algorithm, and the Particle Swarm Optimization (PSO) algorithm for parasitic parameter extraction using GaN-on-diamond devices. This work used the parasitic parameter boundaries extracted from S-parameters as initial values, then iteratively optimized the three algorithms and compared them. The results showed that the PSO algorithm achieved the highest parameter extraction accuracy. However, this algorithm is highly dependent on the initial parameter values, which can easily lead to inappropriate parameter values.

[0004] The above methods have promoted the development of GaN transistor small signal equivalent circuit parameter extraction technology to a certain extent. However, the optimization results of pure search algorithms or heuristic algorithms used in most of the work are generally affected by the initial values ​​of the parameters, which leads to the extraction results being prone to numerical values ​​that do not have physical meaning. At the same time, the traditional small signal parameter extraction algorithms based on parameter scanning and analytical solution have limited performance in the intrinsic parameters (especially the transconductance and output resistance ) There is obvious dispersion phenomenon in the extraction, which leads to large errors in the parameter extraction of RF large gate width devices used in low frequency bands (<10GHz).

[0005] Therefore, how to provide a small-signal parameter extraction method and system for large-gate-width gallium nitride transistors that can effectively consider the low-frequency dispersion effect introduced by transistor parasitics and secondary effects in small-signal parameter extraction is an urgent problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention proposes a small signal parameter extraction method and system for large gate width gallium nitride transistors.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A small signal parameter extraction method for large gate width gallium nitride transistors, comprising:

[0009] Step 1: Obtain the measured Y parameters of the transistor under low-frequency cold pinch-off conditions to define the optimization range of the transistor parasitic capacitance, and optimize the transistor parasitic capacitance using the SQP algorithm;

[0010] Step 2: Obtain the measured Y parameters of the transistor under cold unbiased conditions, and combine them with the transistor parasitic capacitance obtained in step 1 to perform transistor parasitic capacitance parameter stripping. Based on the Z parameters after stripping the transistor parasitic capacitance, extract the transistor parasitic inductance and parasitic resistance respectively;

[0011] Step 3: Strip off the parasitic inductance and parasitic resistance of the transistor obtained in step 2, and convert the Z parameters after stripping the parasitic inductance and parasitic resistance of the transistor into Y parameters, and use the frequency band weighting method to extract the initial values ​​of the intrinsic transconductance and output resistance;

[0012] Step 4: Obtain the initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance, and optimize each intrinsic parameter using the SQP algorithm.

[0013] Optionally, in step 1, the measured Y parameters under low-frequency cold pinch-off conditions are as follows:

[0014]

[0015]

[0016]

[0017] in, is the input admittance; is the output admittance; 、 are the reverse and forward transmission admittances, respectively; is an imaginary unit; is the angular frequency; is the intrinsic gate-source capacitance; is the parasitic capacitance of the transistor gate; is the intrinsic gate-drain capacitance; is the transistor drain parasitic capacitance; is the intrinsic drain-source capacitance.

[0018] Optionally, in step 1, based on the Y parameter, an optimization range of the transistor parasitic capacitance is defined, specifically:

[0019] The slope of the curve with the imaginary part of the Y parameter as the dependent variable and the angular frequency as the independent variable corresponds to the capacitance component in the brackets in each expression; The slope of the curve is The upper boundary of the optimization range; The slope of the curve is The upper boundary of the optimization range; 、 The lower boundary of the optimization range is always 0.

[0020] Optionally, in step 1, the parasitic capacitance of the transistor is optimized using an SQP algorithm, specifically as follows:

[0021] The initial values ​​of the transistor parasitic capacitances are all set to 0.2 times the upper bound of the optimization range; the error calculation of the SQP algorithm is as follows:

[0022]

[0023] in, is the error; 、 for The port index of the parameter has a value of 1 or 2. is the input reflection coefficient, is the reverse transmission coefficient, is the forward transmission coefficient, is the output reflection coefficient; is the simulation value; is the measured value; is the absolute value function, used to calculate The amplitude value of the parameter; is the phase value function, used to calculate The phase value of the parameter.

[0024] Optionally, in step 2, the parasitic inductance and parasitic resistance of the transistor are extracted respectively based on the Z parameter after stripping the parasitic capacitance of the transistor, specifically as follows:

[0025] The parasitic inductance and resistance of the transistor are extracted based on the real and imaginary parts of the Z parameter respectively.

[0026] Optionally, in step 3, the initial values ​​of the intrinsic transconductance and output resistance are extracted using a frequency band weighted method as follows:

[0027]

[0028] in, is the total number of frequency points; For the The target parameter value calculated at the frequency point is and The value of For the The intrinsic transconductance calculated at the frequency point; For the The output resistance calculated at each frequency point; For the The weighting factor of each frequency point decreases as the frequency increases. The expression is as follows:

[0029]

[0030] in, For the Angular frequency of each frequency point; is the angular frequency of the maximum frequency point.

[0031] Optional, The calculation method of the intrinsic transconductance and output resistance at each frequency point is as follows:

[0032]

[0033]

[0034]

[0035]

[0036] in, is the angular frequency Input admittance of lower port 1; is the angular frequency The reverse transmission admittance from port 2 to port 1 is: is the angular frequency Forward transfer admittance from lower port 1 to port 2; is the angular frequency Input admittance of lower port 2; is an imaginary unit; To perform real part extraction on complex numbers; An operation that extracts the imaginary part of a complex number.

[0037] Optionally, in step 4, the initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance are obtained, specifically:

[0038]

[0039]

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046] in, For the The channel resistance calculated at each frequency point; For the The time constant calculated at each frequency point; For the The intrinsic drain-source capacitance calculated at each frequency point; For the The intrinsic gate-drain capacitance calculated at each frequency point; For the The intrinsic gate-source capacitance calculated at each frequency point; For the The gate-drain resistance calculated at each frequency point; is the angular frequency Input admittance of lower port 1; is the angular frequency The reverse transmission admittance from port 2 to port 1 is: To perform real part extraction on complex numbers; To perform an operation to extract the imaginary part of a complex number; For the Angular frequency of each frequency point; is the angular frequency Forward transfer admittance from lower port 1 to port 2; is an imaginary unit; is the angular frequency Input admittance of lower port 2;

[0047] Take separately 、 、 、 、 、 The initial values ​​of the remaining intrinsic parameters except intrinsic transconductance and output resistance are obtained by averaging the values ​​at different frequency points in the full frequency band.

[0048] Optionally, in step 4, each intrinsic parameter is optimized using the SQP algorithm, specifically:

[0049] The lower boundary of the optimization range of each intrinsic parameter is set to 0, and the upper boundary is set to 2 times the initial value; the error calculation of the SQP algorithm is consistent with the error calculation in optimizing the parasitic capacitance of the transistor using the SQP algorithm.

[0050] The present invention also provides a small signal parameter extraction system for large gate width gallium nitride transistors using a small signal parameter extraction method for large gate width gallium nitride transistors, comprising:

[0051] Transistor parasitic capacitance extraction module: used to obtain the measured Y parameters of the transistor under low-frequency cold pinch-off conditions to define the optimization range of the transistor parasitic capacitance and optimize the transistor parasitic capacitance using the SQP algorithm;

[0052] Transistor parasitic inductance and parasitic resistance extraction module: used to obtain the measured Y parameters of the transistor under cold unbiased conditions, and combine them with the transistor parasitic capacitance obtained in the transistor parasitic capacitance extraction module to strip the transistor parasitic capacitance parameters. Based on the Z parameters after stripping the transistor parasitic capacitance, the transistor parasitic inductance and parasitic resistance are extracted respectively;

[0053] Intrinsic transconductance and output resistance extraction module: used to strip off the transistor parasitic inductance and parasitic resistance obtained in the transistor parasitic inductance and parasitic resistance extraction module, convert the Z parameters after stripping the transistor parasitic inductance and parasitic resistance into Y parameters, and use the frequency band weighted method to extract the initial values ​​of the intrinsic transconductance and output resistance;

[0054] Extraction module of other intrinsic parameters: used to obtain the initial values ​​of other intrinsic parameters except intrinsic transconductance and output resistance, and optimize each intrinsic parameter through the SQP algorithm.

[0055] Through the above technical solutions, it can be seen that compared with the existing technology, the present invention proposes a small-signal parameter extraction method and system for large-gate-width gallium nitride transistors. The present invention introduces frequency weighting rules and SQP optimization algorithms into the traditional small-signal model parameter extraction algorithm, thereby reducing the error caused by the low-frequency dispersion effect to the S parameters of the small-signal model and improving the accuracy of model parameter extraction. Through comparison and verification with traditional methods, the proposed algorithm can establish a small-signal model with higher accuracy on a GaN HEMT device with a size of 8×125μm: the average error of the full bias is 4.4%, which is 6.17% lower than the error of the traditional method. In addition, in terms of extraction efficiency, the method proposed in the present invention achieves an average extraction time of only 0.87s per bias point, which is much shorter than the 36.08s of the traditional parameter scanning algorithm, providing a very important technical means for high-precision and high-efficiency small-signal parameter extraction of large-gate-width gallium nitride transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0057] Figure 1 Schematic diagram of the method of the present invention.

[0058] Figure 2 This is a schematic diagram of the equivalent circuit topology of the 16-element small signal model used in the present invention.

[0059] Figure 3 This is a simplified small-signal equivalent circuit topology diagram of a transistor under low-frequency cold pinch-off conditions of the present invention.

[0060] Figure 4 is the input reflection coefficient of the present invention Schematic diagram of the comparison between measured and simulated results.

[0061] Figure 5 is the reverse transmission coefficient of the present invention Schematic diagram of the comparison between measured and simulated results.

[0062] Figure 6 is the forward transmission coefficient of the present invention Schematic diagram of the comparison between measured and simulated results.

[0063] Figure 7 is the output reflection coefficient of the present invention Schematic diagram of the comparison between measured and simulated results. DETAILED DESCRIPTION

[0064] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0065] Example 1:

[0066] Embodiment 1 of the present invention discloses a method for extracting small signal parameters of large gate width gallium nitride transistors, such as Figure 1 As shown, including:

[0067] The equivalent circuit topology diagram of the 16-element small signal model used in the present invention is as follows: Figure 2 As shown, it contains 8 parasitic parameters and 8 intrinsic parameters. Figure 2 In the figure, the parameters outside the red box are parasitic parameters, and the parameters inside the box are intrinsic parameters. Parasitic parameters include source, drain, and gate parasitic resistance. , source, drain, and gate parasitic inductance and pad capacitance (transistor gate parasitic capacitance , transistor drain parasitic capacitance ). Intrinsic parameters include intrinsic gate-source capacitance, intrinsic gate-drain capacitance, intrinsic drain-source capacitance ( 、 、 ), channel resistance , gate-drain resistance , output resistance , transconductance and time constant .

[0068] Step 1: Obtain the measured Y parameters of the transistor under low-frequency cold pinch-off conditions to define the optimization range of the transistor parasitic capacitance and optimize the transistor parasitic capacitance using the SQP algorithm.

[0069] Considering that the small-signal model parameter extraction problem has the characteristics of small and medium scale, continuous objective function, clear variable range and reliable initial value, the present invention uses a constrained local optimization method - Sequential Quadratic Programming (SQP) to extract transistor parasitic capacitance based on the traditional small-signal model parasitic parameter extraction method.

[0070] SQP is an iterative algorithm for solving constrained optimization problems. It gradually approaches the optimal solution by transforming the original nonlinear constrained optimization problem into a series of simpler and more efficient quadratic programming (QP) subproblems. This method accurately handles nonlinear constraints while leveraging the efficiency of quadratic programming to improve the stability and convergence speed of the optimization process. Because the initial value range of intrinsic and parasitic parameters is relatively easy to determine, combined with the local approximate optimization mechanism of SQP, it can effectively narrow the search space and reduce the number of iterations. This has the effect of improving the accuracy and computational efficiency of the small signal parameter extraction of the present invention.

[0071] Specifically, considering low frequencies (<5 GHz) and cold pinch-off (i.e. gate-source voltage , drain-source voltage ) conditions, the S-parameter characteristics of the GaN HEMT are mainly determined by the transistor parasitic capacitance, while the effects of the transistor parasitic inductance and parasitic resistance can be ignored. Therefore, its small-signal equivalent circuit can be simplified as follows: Figure 3 The simplified topology shown in the figure. Converting the S parameters into Y parameters can obtain the measured Y parameters under low-frequency cold pinch-off conditions as follows:

[0072]

[0073]

[0074]

[0075] in, is the input admittance; is the output admittance; 、 are the reverse and forward transmission admittances, respectively; is an imaginary unit; is the angular frequency; is the intrinsic gate-source capacitance; is the parasitic capacitance of the transistor gate; is the intrinsic gate-drain capacitance; is the transistor drain parasitic capacitance; is the intrinsic drain-source capacitance.

[0076] Based on the Y parameter, the optimization range of the transistor parasitic capacitance is defined as follows:

[0077] The slope of the curve with the imaginary part of the Y parameter as the dependent variable and the angular frequency as the independent variable corresponds to the capacitance component in the brackets in each expression; The slope of the curve is The upper boundary of the optimization range; The slope of the curve is The upper boundary of the optimization range; 、 The lower boundary of the optimization range is always 0.

[0078] The parasitic capacitance of the transistor is optimized by the SQP algorithm, specifically:

[0079] The initial values ​​of the transistor parasitic capacitances are all set to 0.2 times the upper boundary of the optimization range;

[0080] The parameter settings of the SQP algorithm are shown in Table 1;

[0081] Table 1 Parameter settings of the SQP algorithm

[0082] parameter meaning Numerical TolFun Objective function convergence threshold 1e-6 TolX Variable error threshold 1e-6 MaxIterations Maximum number of iterations 1000 MaxFunctionEvaluations Maximum number of function evaluations 2000

[0083] The error calculation of the SQP algorithm is as follows:

[0084]

[0085] in, is the error; 、 for The port index of the parameter has a value of 1 or 2. is the input reflection coefficient, is the reverse transmission coefficient, is the forward transmission coefficient, is the output reflection coefficient; is the simulation value; is the measured value; is the absolute value function, used to calculate The amplitude value of the parameter; is the phase value function, used to calculate The phase value of the parameter.

[0086] Step 2: Obtain cold unbiased conditions (i.e. gate-source voltage , drain-source voltage ) and combine it with the transistor parasitic capacitance obtained in step 1 to strip the transistor parasitic capacitance parameters. According to the Z parameter after stripping the transistor parasitic capacitance, the transistor parasitic inductance and parasitic resistance are extracted respectively.

[0087] According to the Z parameter after stripping the transistor parasitic capacitance, the transistor parasitic inductance and parasitic resistance are extracted respectively, specifically:

[0088] Extract transistor parasitic inductance based on the real and imaginary parts of the Z parameter and transistor parasitic resistance .

[0089] Step 3: Strip off the parasitic inductance and parasitic resistance of the transistor obtained in step 2, and convert the Z parameters after stripping the parasitic inductance and parasitic resistance of the transistor into Y parameters, and use the frequency band weighted method to extract the initial values ​​of the intrinsic transconductance and output resistance.

[0090] For each bias point, the transconductance and output resistance , which is usually obtained by extracting the mean of the calculation results at each frequency point, but this will ignore the influence of the low-frequency dispersion effect of these two parameters. For this reason, the present invention proposes a frequency band weighted extraction method to extract these two parameters to improve its accuracy.

[0091] The initial values ​​of intrinsic transconductance and output resistance are extracted using the frequency band weighted method as follows:

[0092]

[0093] in, is the total number of frequency points; For the The target parameter value calculated at the frequency point is and The value of For the The intrinsic transconductance calculated at the frequency point; For the The output resistance calculated at each frequency point; For the The weighting factor of each frequency point decreases as the frequency increases. The expression is as follows:

[0094]

[0095] in, For the Angular frequency of each frequency point; is the angular frequency of the maximum frequency point.

[0096] No. The calculation method of the intrinsic transconductance and output resistance at each frequency point is as follows:

[0097]

[0098]

[0099]

[0100]

[0101] in, is the angular frequency Input admittance of lower port 1; is the angular frequency The reverse transmission admittance from port 2 to port 1 is: is the angular frequency Forward transfer admittance from lower port 1 to port 2; is the angular frequency Input admittance of lower port 2; is an imaginary unit; To perform real part extraction on complex numbers; An operation that extracts the imaginary part of a complex number.

[0102] Step 4: Obtain the initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance, and optimize each intrinsic parameter using the SQP algorithm.

[0103] Considering that the dispersion effect of the remaining intrinsic parameters is not obvious, for the remaining intrinsic parameters except the intrinsic transconductance and output resistance, the initial values ​​of the remaining intrinsic parameters are extracted by solving the following expressions and taking the average over the entire frequency band.

[0104] Calculate the initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance, specifically:

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[0113] in, For the The channel resistance calculated at each frequency point; For the The time constant calculated at each frequency point; For the The intrinsic drain-source capacitance calculated at each frequency point; For the The intrinsic gate-drain capacitance calculated at each frequency point; For the The intrinsic gate-source capacitance calculated at each frequency point; For the The gate-drain resistance calculated at each frequency point; is the angular frequency Input admittance of lower port 1; is the angular frequency The reverse transmission admittance from port 2 to port 1 is: To perform real part extraction on complex numbers; To perform an operation to extract the imaginary part of a complex number; For the Angular frequency of each frequency point; is the angular frequency Forward transfer admittance from lower port 1 to port 2; is an imaginary unit; is the angular frequency Input admittance of lower port 2;

[0114] Take separately 、 、 、 、 、 The initial values ​​of the remaining intrinsic parameters except intrinsic transconductance and output resistance are obtained by averaging the values ​​at different frequency points in the full frequency band.

[0115] After obtaining the initial values ​​of all intrinsic parameters, the SQP algorithm is still used to calculate the values ​​of each intrinsic parameter ( 、 、 、 、 、 、 、 ) for optimization, specifically:

[0116] The lower boundary of the optimization range of each intrinsic parameter is set to 0, and the upper boundary is set to twice the initial value; the parameter setting of the SQP algorithm is consistent with the parameter setting in optimizing the transistor parasitic capacitance through the SQP algorithm; the error calculation of the SQP algorithm is consistent with the error calculation in optimizing the transistor parasitic capacitance through the SQP algorithm.

[0117] Example 2:

[0118] Example 2 of the present invention discloses verification of a small signal parameter extraction method for large gate width gallium nitride transistors disclosed in Example 1, as follows:

[0119] The present invention verifies the parameter extraction algorithm based on the measured multi-bias S parameter data of a 0.25μm process GaN HEMT device with a size of 8×125μm. The frequency range in the S parameter data is 0.2-30GHz, the gate bias voltage range is -3.2V~0.8V with a step size of 0.4V, and the drain bias voltage range is 5V~30V with a step size of 5V. After the small signal model parameter extraction of the transistor is completed based on the parameter extraction algorithm of the present invention, the extracted parasitic parameters and intrinsic parameters are respectively substituted into Figure 2 In the small signal equivalent circuit model shown, its multi-bias S parameters are calculated, and the measured and simulated S parameters under different biases are plotted on the Smith chart and polar coordinate chart for comparison. , reverse transmission coefficient , forward transmission coefficient , output reflection coefficient The comparison results of the measured and simulated results are shown in Figure 4 、 5 , 6, and 7. Figure 4-Figure 7 In the figure, red represents measured data and green represents simulation results.

[0120] To evaluate the accuracy of the proposed small-signal model parameter extraction algorithm, we calculated the accuracy of the S parameters under various bias conditions within the 0.2-30 GHz range based on the error calculation formula of the SQP algorithm. The results are shown in Table 2. The gate bias voltage range is -3.2 V to 0.8 V with a step size of 0.4 V, and the drain bias voltage range is 5 V to 30 V with a step size of 5 V. Figure 4-Figure 7 The results in Table 2 show that the model parameter extraction algorithm based on SQP and frequency weighting proposed in the present invention can more accurately simulate the small signal characteristics under different biases compared with the traditional parameter extraction method based on parameter scanning and analytical solution.

[0121] Table 2 Errors of the small signal model of the 8×125μm GaN HEMT device at different biases

[0122]

[0123] As shown in Table 2, the parameter extraction method based on SQP and frequency weighting proposed in this paper has high accuracy under different bias conditions. The average error of the full bias is 4.4%, which is 6.17% lower than that of the traditional method. In addition, in terms of extraction efficiency, the average single bias extraction time achieved by the method of the present invention is only 0.87 seconds, which is much shorter than the 36.08 seconds of the traditional parameter scanning algorithm. This verifies the effectiveness of the parameter extraction method based on SQP and frequency weighting proposed in this paper, and can improve the accuracy of the small signal model of large gate width die while ensuring computational efficiency.

[0124] Example 3:

[0125] Embodiment 3 of the present invention discloses a small-signal parameter extraction system for large-gate-width gallium nitride transistors using a small-signal parameter extraction method for large-gate-width gallium nitride transistors, comprising:

[0126] Transistor parasitic capacitance extraction module: used to obtain the measured Y parameters of the transistor under low-frequency cold pinch-off conditions to define the optimization range of the transistor parasitic capacitance and optimize the transistor parasitic capacitance using the SQP algorithm;

[0127] Transistor parasitic inductance and parasitic resistance extraction module: used to obtain the measured Y parameters of the transistor under cold unbiased conditions, and combine them with the transistor parasitic capacitance obtained in the transistor parasitic capacitance extraction module to strip the transistor parasitic capacitance parameters. Based on the Z parameters after stripping the transistor parasitic capacitance, the transistor parasitic inductance and parasitic resistance are extracted respectively;

[0128] Intrinsic transconductance and output resistance extraction module: used to strip off the transistor parasitic inductance and parasitic resistance obtained in the transistor parasitic inductance and parasitic resistance extraction module, convert the Z parameters after stripping the transistor parasitic inductance and parasitic resistance into Y parameters, and use the frequency band weighted method to extract the initial values ​​of the intrinsic transconductance and output resistance;

[0129] Extraction module of other intrinsic parameters: used to obtain the initial values ​​of other intrinsic parameters except intrinsic transconductance and output resistance, and optimize each intrinsic parameter through the SQP algorithm.

[0130] The embodiment of the present invention discloses a small-signal parameter extraction method and system for large-gate-width gallium nitride transistors. The present invention introduces frequency weighting rules and SQP optimization algorithms into the traditional small-signal model parameter extraction algorithm, thereby reducing the error caused by the low-frequency dispersion effect to the S parameters of the small-signal model and improving the accuracy of model parameter extraction. Through comparison and verification with traditional methods, the proposed algorithm can establish a small-signal model with high accuracy on a GaN HEMT device with a size of 8×125μm: the average error of the full bias is 4.4%, which is 6.17% lower than the error of the traditional method. In addition, in terms of extraction efficiency, the method proposed in the present invention achieves an average extraction time of only 0.87s per bias point, which is much shorter than the 36.08s of the traditional parameter scanning algorithm, providing a very important technical means for high-precision and high-efficiency small-signal parameter extraction of large-gate-width gallium nitride transistors.

[0131] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0132] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A small signal parameter extraction method for large gate width gallium nitride transistors, characterized in that: include: Step 1: Obtaining the measured Y parameters of the transistor under low-frequency cold pinch-off conditions to define an optimization range of the transistor parasitic capacitance, and optimizing the transistor parasitic capacitance using an SQP algorithm; Step 2: Obtain the measured Y parameter of the transistor under cold unbiased conditions, and combine it with the transistor parasitic capacitance obtained in step 1 to perform transistor parasitic capacitance parameter stripping. According to the Z parameter after stripping the transistor parasitic capacitance, respectively extract the transistor parasitic inductance and parasitic resistance; Step 3: stripping off the parasitic inductance and parasitic resistance of the transistor obtained in step 2, and converting the Z parameters after stripping off the parasitic inductance and parasitic resistance of the transistor into Y parameters, and extracting the initial values ​​of the intrinsic transconductance and output resistance using a frequency band weighted method; Step 4: Obtaining initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance, and optimizing each intrinsic parameter using the SQP algorithm; In step 1, the parasitic capacitance of the transistor is optimized by the SQP algorithm, specifically: The initial values ​​of the transistor parasitic capacitances are all set to 0.2 times the upper bound of the optimization range; the error calculation of the SQP algorithm is as follows: in, is the error; 、 for The port index of the parameter has a value of 1 or 2. is the input reflection coefficient, is the reverse transmission coefficient, is the forward transmission coefficient, is the output reflection coefficient; is the simulation value; is the measured value; is the absolute value function, used to calculate The amplitude value of the parameter; is the phase value function, used to calculate Phase value of the parameter; In step 3, the initial values ​​of intrinsic transconductance and output resistance are extracted using the frequency band weighted method as follows: in, is the total number of frequency points; For the The target parameter value calculated at the frequency point is and The value of For the The intrinsic transconductance calculated at the frequency point; For the The output resistance calculated at each frequency point; For the The weighting factor of each frequency point decreases as the frequency increases. The expression is as follows: in, For the Angular frequency of each frequency point; is the angular frequency of the maximum frequency point.

2. The method for extracting small signal parameters of a large gate width gallium nitride transistor according to claim 1, characterized in that: In step 1, the measured Y parameters under the low-frequency cold pinch-off condition are as follows: in, is the input admittance; is the output admittance; 、 are the reverse and forward transmission admittances, respectively; is an imaginary unit; is the angular frequency; is the intrinsic gate-source capacitance; is the parasitic capacitance of the transistor gate; is the intrinsic gate-drain capacitance; is the transistor drain parasitic capacitance; is the intrinsic drain-source capacitance.

3. The method for extracting small signal parameters of a large gate width gallium nitride transistor according to claim 2, characterized in that: In step 1, based on the Y parameter, the optimization range of the transistor parasitic capacitance is defined as follows: The slope of the curve with the imaginary part of the Y parameter as the dependent variable and the angular frequency as the independent variable corresponds to the capacitance component in the brackets in each expression; The slope of the curve is The upper boundary of the optimization range; The slope of the curve is The upper boundary of the optimization range; 、 The lower boundary of the optimization range is always 0.

4. The method for extracting small signal parameters of a large gate width gallium nitride transistor according to claim 1, characterized in that: In step 2, the parasitic inductance and parasitic resistance of the transistor are extracted respectively according to the Z parameter after stripping the parasitic capacitance of the transistor, specifically: The parasitic inductance and parasitic resistance of the transistor are extracted according to the real part and the imaginary part of the Z parameter respectively.

5. The method for extracting small signal parameters of a large gate width gallium nitride transistor according to claim 1, characterized in that: The said The calculation method of the intrinsic transconductance and output resistance at each frequency point is as follows: in, is the angular frequency Input admittance of lower port 1; is the angular frequency The reverse transmission admittance from port 2 to port 1 is: is the angular frequency Forward transfer admittance from lower port 1 to port 2; is the angular frequency Input admittance of lower port 2; is an imaginary unit; To perform real part extraction on complex numbers; An operation that extracts the imaginary part of a complex number.

6. The method for extracting small signal parameters of a large gate width gallium nitride transistor according to claim 1, characterized in that: In step 4, the initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance are obtained, specifically: in, For the The channel resistance calculated at each frequency point; For the The time constant calculated at each frequency point; For the The intrinsic drain-source capacitance calculated at each frequency point; For the The intrinsic gate-drain capacitance calculated at each frequency point; For the The intrinsic gate-source capacitance calculated at each frequency point; For the The gate-drain resistance calculated at each frequency point; is the angular frequency Input admittance of lower port 1; is the angular frequency The reverse transmission admittance from port 2 to port 1 is: To perform real part extraction on complex numbers; To perform an operation to extract the imaginary part of a complex number; For the Angular frequency of each frequency point; is the angular frequency Forward transfer admittance from lower port 1 to port 2; is an imaginary unit; is the angular frequency Input admittance of lower port 2; Take separately 、 、 、 、 、 The initial values ​​of the remaining intrinsic parameters except the intrinsic transconductance and output resistance are obtained by averaging the values ​​at different frequency points within the entire frequency band.

7. The method for extracting small signal parameters of a large gate width gallium nitride transistor according to claim 1, characterized in that: In step 4, each intrinsic parameter is optimized by the SQP algorithm, specifically: The lower boundary of the optimization range of each intrinsic parameter is set to 0, and the upper boundary is set to 2 times the initial value; the error calculation of the SQP algorithm is consistent with the error calculation in optimizing the parasitic capacitance of the transistor by the SQP algorithm.

8. A small signal parameter extraction system for large gate width gallium nitride transistors using the small signal parameter extraction method for large gate width gallium nitride transistors according to any one of claims 1 to 7, characterized in that: include: Transistor parasitic capacitance extraction module: used to obtain the measured Y parameters of the transistor under low-frequency cold pinch-off conditions to define the optimization range of the transistor parasitic capacitance and optimize the transistor parasitic capacitance using the SQP algorithm; Transistor parasitic inductance and parasitic resistance extraction module: used to obtain the measured Y parameters of the transistor under cold unbiased conditions, and combine them with the transistor parasitic capacitance obtained in the transistor parasitic capacitance extraction module to perform transistor parasitic capacitance parameter stripping, and extract the transistor parasitic inductance and parasitic resistance respectively based on the Z parameters after stripping the transistor parasitic capacitance; An intrinsic transconductance and output resistance extraction module is used to strip off the transistor parasitic inductance and parasitic resistance obtained in the transistor parasitic inductance and parasitic resistance extraction module, convert the Z parameters after stripping off the transistor parasitic inductance and parasitic resistance into Y parameters, and extract the initial values ​​of the intrinsic transconductance and output resistance using a frequency band weighted method; The module for extracting other intrinsic parameters is used to obtain the initial values ​​of the other intrinsic parameters except the intrinsic transconductance and output resistance, and optimize each intrinsic parameter by using the SQP algorithm.

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