Front-end low-power verification environment generation method, electronic device, and medium

Abstract

The present application relates to chip verification technical field, especially to a kind of front-end low-power verification environment generation method, electronic equipment and medium, method includes steps S1, the register transfer level code information A of chip is obtained n And unified power consumption format information B n ;Step S2, target configuration file is obtained;Step S3, the target configuration file is parsed, if C n It is set to first identification, then A1 n And B1 n Join target compilation file list, if C n It is set to second identification, then A2 n And B2 n Join target compilation file list;Step S4, at least one process angle corresponding standard cell library information file is screened from each standard cell library information file and joined target compilation file list;Step S5, based on the target compilation file list compiles and generates front-end low-power verification environment.The present application improves the generation efficiency and accuracy of front-end low-power verification environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a front-end low-power verification environment generation method, an electronic device and a medium. BACKGROUND

[0002] The front-end low-power verification is an indispensable key link in chip verification, and in the process of constructing the front-end low-power verification environment, the register transfer level (RTL) code of the chip may be adjusted. In the prior art, when the RTL code of the chip is adjusted, the unified power format (UPF) file needs to be manually adjusted, which is large in workload and prone to errors, thereby reducing the generation efficiency of the front-end low-power verification environment. In addition, in the existing front-end low-power environment generation process, all standard cell library information files need to be compiled, the number of the standard cell library information files is huge, and real voltage simulators and real sensors are not needed in the front-end low-power verification environment, so all the standard cell library information files are not needed. However, in the prior art, all the standard cell library information files are used to compile and generate the front-end low-power verification environment, which further reduces the generation efficiency of the front-end low-power verification environment. Therefore, how to improve the generation efficiency and accuracy of the front-end low-power verification environment becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a front-end low-power verification environment generation method, an electronic device and a medium, which improves the generation efficiency and accuracy of the front-end low-power verification environment.

[0004] According to a first aspect of the present application, a front-end low-power verification environment generation method is provided, comprising:

[0005] Step S1, obtaining a register transfer level code information set {A1, A2,..., An} and a unified power format information set {B1, B2,..., Bn} of a chip, An is the register transfer level code information corresponding to the n th chip component module, Bn is the power consumption information corresponding to the n th chip component unit, the value range of n is 1 to N, N is the total number of chip component modules, An=(A1, A2), A1 is the register transfer level code file of the n th chip component module, and A2 is the unified power format file of the n th chip component module. n ,...,A N} and a unified power format information set {B1, B2,..., B n ,...,B N}, An is the register transfer level code information corresponding to the n th chip component module, Bn is the power consumption information corresponding to the n th chip component unit, the value range of n is 1 to N, N is the total number of chip component modules, An=(A1, A2), A1 is the register transfer level code file of the n th chip component module, and A2 is the unified power format file of the n th chip component module. n n n n n n n ​​​​​​B is an interface code file of the nth chip composition module n = (B1 n , B2 n ), B1 n is a unified power consumption format file corresponding to the nth chip composition module, B2 n is interface power connection information corresponding to the nth chip composition module, and the chip composition module is composed of standard cells interconnected;

[0006] In step S2, a target configuration file {C1, C2,..., C n ,..., C N} is obtained, C n is the configuration information of the nth chip composition module, and C n is configured as the first identifier or the second identifier;

[0007] In step S3, the target configuration file is parsed, if C n is set as the first identifier, A1 n and B1 n are added to a target compilation file list, if C n is set as the second identifier, A2 n and B2 n are added to the target compilation file list;

[0008] In step S4, at least one standard cell library information file corresponding to a process angle is selected from each standard cell library information file and added to the target compilation file list;

[0009] In step S5, a front-end low-power verification environment is compiled and generated based on the target compilation file list.

[0010] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method of the first aspect of the present application.

[0011] According to the third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions, and the computer executable instructions are used to execute the method of the first aspect of the present application.

[0012] Compared with the prior art, the present application has obvious advantages and beneficial effects. By means of the above technical scheme, the front-end low-power verification environment generation method, electronic device and medium provided by the present application can achieve considerable technical progress and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0013] The present invention can automatically acquire a register transfer level code information set and a unified power consumption format information set, and then generate a target compilation file list based on a target configuration file. Furthermore, the present invention can filter at least one standard cell library information file corresponding to a process corner from each standard cell library information file and add it to the target compilation file list. Ultimately, the front-end low-power verification environment is compiled based on the target compilation file list. This invention improves the efficiency and accuracy of generating the front-end low-power verification environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flow chart of a method for generating a front-end low-power verification environment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0017] The embodiment of the present invention provides a method for generating a front-end low-power verification environment, such as Figure 1 Shown, including:

[0018] Step S1: Obtain the register transfer level code information set {A1, A2, ..., A n ,...,A N} and unified power consumption format information set {B1,B2,...,B n ,...,B N}, A n is the register transfer level code information corresponding to the nth chip component module, B n The power consumption information corresponding to the nth group of chip components, n ranges from 1 to N, N is the total number of chip components, A n =(A1 n ,A2 n ), A1 n Register transfer level code file for the nth chip module, A2 n The interface code file for the nth chip module, Bn = (B1 n , B2 n ), B1 n is a unified power format file corresponding to the nth chip component module, B2 n is interface power connection information corresponding to the nth chip component module, and the chip component module is composed of standard cells.

[0019] The chip design register transfer level code file is a key abstraction level in the chip design process, and is used to describe the interconnection relationship between the chip component modules and the chip component modules, and can specifically be the data flow and logic operation between registers in a digital circuit. The chip power management strategy information defined by the unified power format file includes power domain, power mode, isolation logic, and retention logic information. The standard cell level in the chip component module is set, that is, the standard cells can be interconnected to form a unit, the chip component unit, and the standard cells can be further interconnected to form a chip component unit. The chip component unit and the standard cell can be hierarchically set, that is, the standard cell has no sub-module, the sub-module of the chip component unit can be a chip component unit or a standard cell, and the sub-module of the chip component module can be a chip component unit and a standard cell. The chip can be specifically a GPU (Graphics Processing Unit) chip.

[0020] Step S2, obtaining a target configuration file {C1, C2,..., C n ,..., C N}, C n is the configuration information of the nth chip component module, and C n is configured as a first identifier or a second identifier.

[0021] It should be noted that, in the front-end low-power verification process, all chip component modules do not necessarily need to be concerned. In order to improve the efficiency of the front-end low-power verification and save resources, different chip component modules can be set different identifiers through the target configuration file. If the identifier is set as the first identifier, it means that the corresponding chip component module is a module that needs to be concerned in the front-end low-power verification process. If the identifier is set as the second identifier, it means that the corresponding chip component module is a module that does not need to be concerned in the front-end low-power verification process.

[0022] Step S3, parsing the target configuration file. If C n is set as the first identifier, A1 n and B1 n are added to the target compilation file list. If C n is set as the second identifier, A2 n and B2 n are added to the target compilation file list.

[0023] Modules that require attention need to completely load the corresponding code information, while modules that do not require attention only need to load the corresponding interface code files and the corresponding interface power connection information to ensure that the normal operation of the modules that require attention is not affected.

[0024] Step S4: Filter at least one standard cell library information file corresponding to a process corner from each standard cell library information file and add it to the target compilation file list.

[0025] In the field of low-power chips, Corner (process corner) is a way to describe the range of device parameter variations in the manufacturing process. It represents the extreme combination of process, voltage, and temperature and is used to verify the performance and power consumption of the chip under various conditions.

[0026] Step S5: compile and generate a front-end low-power verification environment based on the target compilation file list.

[0027] It should be noted that the generated front-end low-power verification environment is the design under test (DUT) for front-end low-power verification.

[0028] As an embodiment, the step S1 further includes:

[0029] Step S10: If the code information of the nth chip component module needs to be updated, then update A synchronously. n and B n , based on the updated {A1,A2,...,A n ,...,A N} and {B1,B2,...,B n ,...,B N}Execute step S2.

[0030] It should be noted that, through the above solution, when the chip RTL code is adjusted, there is no need to manually adjust the unified power consumption format, but automatically adjust the corresponding A n and B n , then based on the updated {A1,A2,...,A n ,...,A N} and {B1,B2,...,B n ,...,B N} to automate subsequent steps and generate a front-end low-power verification environment.

[0031] In one embodiment, the process corner includes identification information, a temperature value, and a voltage value. The name of each standard cell library information file includes the identification information, temperature value, and voltage value corresponding to the process corner. The identification information includes a typical process corner identifier and an atypical process corner identifier. It should be noted that the typical process corner identifier refers to a designated typical process corner, while the atypical process corner refers to an ordinary process corner. When screening standard cell library information files, the standard cell library information files corresponding to the typical process corners are preferentially selected.

[0032] A front-end low-power verification environment doesn't require a real voltage simulator or sensors, so not all standard cell library information files are required. Loading all standard cell library information files would increase compilation time. However, each standard cell requires at least one process corner to have all the corresponding standard cell library information files. The following two examples further illustrate the screening method.

[0033] Example 1

[0034] The step S4 comprises:

[0035] Step S41, obtain the standard cell library information file set {D1, D2, ..., D m ,...,D M}, D m is the library file set of the mth standard unit, the value range of m is 1 to M, M is the total number of standard units, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m}, D i m D m The i-th standard cell library information file, i ranges from 1 to f(m), and f(m) is the total number of library files for the m-th standard cell.

[0036] It is understandable that when m takes different values, f(m) may be different. Different when m takes the same value and i takes different values, different D i m They may belong to the same process corner or different process corners.

[0037] Step S42, traverse each D i m The name will include the D of the typical process angle identification i m As candidate D i mAdd to the first candidate standard cell library information file set.

[0038] It should be noted that a part of the standard cell library information files can be filtered out by identifying the typical process corner, but the number of the standard cell library information files can still be further reduced at this time.

[0039] Step S43, traverse each candidate D i m , whose temperature value is a preset temperature value and whose voltage value is a preset voltage value. i m Determine as the target D i m .

[0040] It can be understood that the combination of the preset temperature value and the preset voltage value is used as the screening condition in step S43, the preset temperature value is a temperature that each standard cell corresponding library file has, and the preset voltage value is a voltage value that each standard cell corresponding library file has. Through the screening of the combination of the preset temperature value and the preset voltage value, the number of the standard cell library information files can be further reduced, and it can also be ensured that each standard cell needs at least one process corner to have corresponding all standard cell library information files.

[0041] Step S44, add all target D i m to the target compilation file list.

[0042] Embodiment two,

[0043] The step S4 comprises:

[0044] Step C41, obtain a standard cell library information file set {D1, D2,..., D m ,...,D M}, D m is a library file set of the mth standard cell, the value range of m is 1 to M, M is the total number of standard cells, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m}, D i m is the ith standard cell library information file in D m , the value range of i is 1 to f(m), f(m) is the total number of library files of the mth standard cell.

[0045] It is understandable that when m takes different values, f(m) may be different. Different when m takes the same value and i takes different values, different D i m They may belong to the same process corner or different process corners.

[0046] Step C42, traverse each D i m The name will include the D of the typical process angle identification i m As candidate D i m Added to the candidate standard cell library information file collection.

[0047] It should be noted that, although a portion of standard cell library information files can be filtered out through typical process corner identification, the number of standard cell library information files can still be further reduced.

[0048] Step C43, traverse each candidate D in the first selected standard cell library information file set i m , set the temperature value to the candidate D of the preset temperature value i m Determined as the second candidate D i m .

[0049] It should be noted that a portion of the standard cell library information files can be further filtered out by presetting the temperature value. At this time, there may be a portion of the second candidate D corresponding to the standard cells. i m The number of standard cells has met the requirements, and the second candidate D i m The number still needs to be further reduced.

[0050] Step C44: If the second candidate D corresponding to the i-th standard cell i m The number of is less than the preset threshold, then the second candidate D corresponding to the i-th standard unit is i m Determined as target D i m Add it to the target compilation file list, otherwise, execute step C45.

[0051] It should be noted that the preset threshold value is set according to specific application requirements.

[0052] Step C45, traverse the second candidate D corresponding to the i-th standard cell i m , the second candidate whose voltage value is the preset voltage value is determined as the target D im Add the target compilation file list.

[0053] As an embodiment, the step S5 comprises:

[0054] Step S51, if the file corresponding to the n-th chip component module in the target compilation file list is A1 n and B1 n , add the low-power consumption information in B1 n to A1 n , add the low-power consumption information of the standard cell corresponding to A1 n in the standard cell library information file in the target compilation file list to A1 n .

[0055] Step S52, if the file corresponding to the n-th chip component module in the target compilation file list is A2 n and B2 n , add the low-power consumption information in B2 n to A2 n , and generate a front-end low-power consumption verification environment.

[0056] It is noted that some example embodiments are described as processes or methods depicted as flowcharts. Although the processes are described in a particular, sequential order, many of the steps described can be performed in parallel, in different order, or concurrently. Further, an order that steps are described in is not necessarily the order in which they are performed. The processes can be terminated when their operations are completed, but can also have additional steps not included in the figure. A process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0057] The embodiments of the present application also provide an electronic device, including: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method provided by the embodiments of the present application.

[0058] The embodiments of the present application also provide a computer readable storage medium storing computer executable instructions, and the computer executable instructions are used to execute the method provided by the embodiments of the present application.

[0059] The embodiments of the present application can automatically acquire a register transfer level code information set and a uniform power consumption format information set, and then generate a target compilation file list based on a target configuration file. In addition, the present application can select at least one standard cell library information file corresponding to a process angle from each standard cell library information file and add the standard cell library information file to the target compilation file list, and finally compile a front-end low-power consumption verification environment based on the target compilation file list. The present application improves the generation efficiency and accuracy of the front-end low-power consumption verification environment.

[0060] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes or modifications to the above disclosed technical contents to obtain equivalent embodiments with equivalent changes, as long as the changes or modifications do not depart from the technical solution of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A method for generating a front-end low-power verification environment, the method comprising: Comprising: Step S1: Obtain the register transfer level code information set {A1, A2, ..., A n ,...,A N } and unified power consumption format information set {B1,B2,...,B n ,...,B N }, A n is the register transfer level code information corresponding to the nth chip component module, B n The power consumption information corresponding to the nth group of chip components, n ranges from 1 to N, N is the total number of chip components, A n =(A1 n ,A2 n ), A1 n Register transfer level code file for the nth chip module, A2 n The interface code file for the nth chip module, B n =(B1 n ,B2 n ), B1 n The unified power consumption format file corresponding to the nth chip component module, B2 n The interface power connection information corresponding to the nth chip component module, where the chip component module is composed of interconnected standard cells; Step S2, obtaining a target configuration file {C1, C2,..., Cn} n ,...,C N}C n is the configuration information of the nth chip component module, C n is configured as the first identifier or the second identifier; Step S3, parsing the target configuration file, if C n is set to the first identification, then A1 n and B1 n are added to the target compilation file list, if C n is set to the second identification, then A2 n and B2 n are added to the target compilation file list; Step S4, screening at least one standard cell library information file corresponding to the process corner from each standard cell library information file to add a target compilation file list; Step S5, compiling to generate a front-end low-power verification environment based on the target compilation file list.

2. The method of claim 1, wherein, The step S1 further comprises: Step S10, if the code information of the nth chip component module needs to be updated, synchronously update A n and B n , based on the updated {A1, A2,..., A n ,...,A N} and {B1, B2,..., B n ,...,B N}, execute step S2.

3. The method of claim 1, wherein, The process corner includes identification information, temperature value and voltage value, the name of each standard cell library information file includes identification information, temperature value and voltage value corresponding to the process corner, and the identification information includes typical process corner identification and atypical process corner identification.

4. The method of claim 3, wherein, The step S4 comprises: Step S41, obtaining a standard cell library information file set {D1, D2,...,D m ,...,D M}, D m is a library file set of the mth standard cell, the value range of m is 1 to M, M is the total number of standard cells, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m}, D i m is the ith standard cell library information file in D m , the value range of i is 1 to f(m), f(m) is the total number of library files of the mth standard cell; Step S42, iterate through each D i m name, will contain the D i m as candidate D i m add to the first candidate standard cell library information file set; Step S43, traversing each candidate D in the first candidate standard cell library information file set i m candidate D whose temperature value is the preset temperature value and whose voltage value is the preset voltage value i m determined as the target D i m ; Step S44, all targets D i m Add to target compile file list.

5. The method of claim 3, wherein, The step S4 comprises: Step C41, obtain a standard cell library information file set {D1, D2,..., D m ,...,D M}, D m is the library file set of the mth standard cell, the value range of m is 1 to M, M is the total number of standard cells, D m ={D1 m ,D2 m ,...,D i m ,...,D f(m) m}, D i m is the ith standard cell library information file in D m , the value range of i is 1 to f(m), f(m) is the total number of library files of the mth standard cell; Step C42, iterate through each D i m Name, will contain the typical process corner identification of D i m as a candidate D i m is added to the candidate standard cell library information file set; Step C43, traversing each candidate D in the first candidate standard cell library information file set i m determining the candidate D whose temperature value is the preset temperature value i m determining the second candidate D i m ; Step C44, if the number of the second candidate D i m corresponding to the i-th standard unit is less than a preset threshold, the second candidate D i m corresponding to the i-th standard unit is determined as the target D i m is added into the target compilation file list, otherwise, step C45 is executed. Step C45, traversing the second candidate D corresponding to the i-th standard cell i m determining the second candidate with the voltage value being the preset voltage value as the target D i m adding the target compilation file list.

6. The method of claim 1, wherein, The step S5 comprises: Step S51, if the file corresponding to the nth chip set module in the target compiling file list is A1 n and B1 n , then add the low power consumption information in B1 n to A1 n , and add the low power consumption information of the standard cell corresponding to A1 n in the standard cell library information file in the target compiling file list to A1 n ; Step S52, if the file corresponding to the nth chip set module in the target compilation file list is A2 n and B2 n , then add the low power information in B2 n to A2 n to generate a front-end low power verification environment.

7. The method of claim 1, wherein, The standard cell hierarchy is set in a chip composition module.

8. The method of claim 1, wherein, The chip is a GPU chip.

9. An electronic device, comprising: Comprising: At least one processor; And a memory connected in communication with the at least one processor; Wherein the memory stores instructions executed by the at least one processor, and the instructions are set to execute the method of any one of the preceding claims 1-8.

10. A computer-readable storage medium, characterized in that, Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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