Gate drive circuit, display panel and detection method thereof

Abstract

The invention provides a gate drive circuit, a display panel and a detection method of the display panel, relates to the technical field of display, and is used for accurately positioning which stage of shifting register is defective when the gate drive circuit is abnormal. In the gate drive circuit, a coupling sub-circuit included in a shift register is respectively coupled with a scanning signal output end, an inverted scanning signal output end and an output detection node, and is used for controlling the potential of the inverted scanning signal output end to be coupled with the potential of the output detection node under the control of the scanning signal output end; the first transmission sub-circuit is used for controlling to connect or disconnect the electric connection between the first active reference signal input end and the output detection nodes of the odd-numbered shift registers under the control of the first active reference signal input end; and the second transmission sub-circuit is used for controlling the second active reference signal input end to be electrically connected or disconnected with the output detection nodes of the even-numbered shift registers under the control of the second active reference signal input end.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate drive circuit, a display panel and a detection method thereof. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly extensive. During the routine cell test process of display products, the gate drive circuit included in the display product is tested. This gate drive circuit generally includes cascaded shift registers. During the test, the first and last shift registers are usually monitored. However, when the last shift register has a poor output, it is impossible to locate the specific shift register stage with the problem. This makes it more difficult to analyze the gate drive circuit anomaly and resolve the problem. Summary of the Invention

[0003] The object of the present invention is to provide a gate drive circuit, a display panel and a detection method thereof, which are used to accurately locate which stage of the shift register is defective when an abnormality occurs in the gate drive circuit.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a gate drive circuit, comprising: a first transmission sub-circuit, a second transmission sub-circuit, and a cascaded multi-stage shift register;

[0006] The shift register includes a scan signal output terminal, an inverted scan signal output terminal, an output detection node, and a coupling subcircuit; the coupling subcircuit is coupled to the scan signal output terminal, the inverted scan signal output terminal, and the output detection node, respectively, and is used to control the potential of the inverted scan signal output terminal to be coupled with the potential of the output detection node under the control of the scan signal output terminal;

[0007] The first transmission sub-circuit is respectively coupled to the first active reference signal input terminal and the output detection node of each odd-numbered shift register; and is used to control the electrical connection between the first active reference signal input terminal and the output detection node of each odd-numbered shift register to be turned on or off under the control of the first active reference signal input terminal;

[0008] The second transmission sub-circuit is respectively coupled to the second active reference signal input terminal and the output detection node of each even-numbered shift register; and is used to control the conduction or disconnection of the electrical connection between the second active reference signal input terminal and the output detection node of each even-numbered shift register under the control of the second active reference signal input terminal.

[0009] Optionally, the gate drive circuit further includes: a first voltage stabilization subcircuit and / or a second voltage stabilization subcircuit;

[0010] A first terminal of the first voltage stabilizing sub-circuit is coupled to the first level signal input terminal, and a second terminal of the first voltage stabilizing sub-circuit is coupled to the output detection node of the odd-numbered shift register;

[0011] A first terminal of the second voltage stabilizing sub-circuit is coupled to the first level signal input terminal, and a second terminal of the second voltage stabilizing sub-circuit is coupled to the output detection node of the even-numbered shift register.

[0012] Optionally, the shift register further includes a first load sub-circuit, and the coupling sub-circuit is coupled to the output detection node through the first load sub-circuit.

[0013] Optionally, the gate drive circuit further includes at least one second load sub-circuit and / or at least one third load sub-circuit; the second load sub-circuit is connected in series between the output detection nodes of adjacent odd-numbered shift registers; and the third load sub-circuit is connected in series between the output detection nodes of adjacent even-numbered shift registers.

[0014] Optionally, the coupling sub-circuit includes a first transistor, a gate of the first transistor is coupled to the scan signal output terminal, a first electrode of the first transistor is coupled to the inverted scan signal output terminal, and a second electrode of the first transistor is coupled to the output detection node;

[0015] The first transmission sub-circuit includes a second transistor, a gate of the second transistor is coupled to the first active reference signal input terminal, a first electrode of the second transistor is coupled to the gate of the second transistor, and a second electrode of the second transistor is coupled to the output detection node of each odd-numbered shift register;

[0016] The second transmission sub-circuit includes a third transistor, the gate of the third transistor is coupled to the second active reference signal input terminal, the first electrode of the third transistor is coupled to the gate of the third transistor, and the second electrode of the third transistor is coupled to the output detection node of each even-numbered shift register.

[0017] Optionally, the first transmission sub-circuit further includes a first resistance structure, wherein a first end of the first resistance structure is coupled to the first electrode of the second transistor, and a second end of the first resistance structure is coupled to the gate of the second transistor;

[0018] The second transmission sub-circuit further includes a second resistance structure, a first end of the second resistance structure is coupled to the first electrode of the third transistor, and a second end of the second resistance structure is coupled to the gate of the third transistor.

[0019] Optionally, the first voltage stabilization sub-circuit includes a first capacitor, a first end of the first capacitor is coupled to the first level signal input end, and a second end of the first capacitor is coupled to the output detection node of the odd-numbered shift register;

[0020] The second voltage stabilization sub-circuit includes a second capacitor, a first end of the second capacitor is coupled to the first level signal input end, and a second end of the second capacitor is coupled to the output detection node of the even-numbered shift register.

[0021] Optionally, the first load sub-circuit includes a third resistance structure, a first end of the third resistance structure is coupled to the coupling sub-circuit, and a second end of the third resistance structure is coupled to the output detection node.

[0022] Optionally, the second load sub-circuit includes a fourth resistance structure, and the fourth resistance structure is connected in series between the output detection nodes of adjacent odd-numbered shift registers;

[0023] The third load sub-circuit includes a fifth resistance structure connected in series between the output detection nodes of adjacent even-numbered shift registers.

[0024] Optionally, the shift register also includes a shift register sub-circuit, which includes a shift register unit and an inverting unit. The shift register unit is coupled to the scan signal output end and is used to control the scan signal output end to output the scan signal; the inverting unit is coupled between the scan signal output end and the inverted scan signal output end, and is used to obtain an inverted scan signal based on the scan signal output from the scan signal output end, and transmit it to the inverted scan signal output end.

[0025] Based on the technical solution of the above-mentioned gate drive circuit, the second aspect of the present invention provides a display panel, including the above-mentioned gate drive circuit; the display panel also includes: a first test terminal and a second test terminal, the first test terminal is coupled to the output detection node of each odd-numbered shift register, and the second test terminal is coupled to the output detection node of each even-numbered shift register.

[0026] Based on the technical solution of the above display panel, a third aspect of the present invention provides a method for detecting a display panel, which is used to detect the above display panel. The method includes:

[0027] detecting a signal at a first test terminal to generate a first test signal;

[0028] detecting a signal at a second test terminal to generate a second test signal;

[0029] According to the first test signal and the second test signal, it is determined which stage of the multi-stage shift register included in the gate driving circuit of the display panel has an abnormal output.

[0030] In the technical solution provided by the present invention, the first transmission sub-circuit is capable of controlling the transmission of the first active reference signal to the output detection node of each odd-numbered shift register, and the second transmission sub-circuit is capable of controlling the transmission of the second active reference signal to the output detection node of each even-numbered shift register. The coupling sub-circuit in each shift register is capable of controlling the coupling of the potential of the inverted scan signal output end with the potential of the output detection node under the control of the scan signal output end; in this way, when the scan signal output end and the inverted scan signal output end of the shift register can output normally, the coupling sub-circuit is capable of coupling the potential of the inverted scan signal output end with the potential of the output detection node, thereby changing the potential of the output detection node; and when the scan signal output end and the inverted scan signal output end of the shift register cannot output normally, the coupling sub-circuit cannot couple the potential of the inverted scan signal output end with the potential of the output detection node, thereby failing to change the potential of the output detection node.

[0031] Therefore, in the gate drive circuit provided by the present invention, during detection, the waveforms of the output detection nodes of the odd-numbered shift registers and the waveforms of the output detection nodes of the even-numbered shift registers are directly observed through an oscilloscope. If the waveforms of the output detection nodes of the odd-numbered shift registers are not coupled in a certain row, then the output of the shift register in that row is abnormal. Similarly, if the waveforms of the output detection nodes of the even-numbered shift registers are not coupled in a certain row, then the output of the shift register in that row is abnormal. Therefore, when detecting the gate drive circuit provided by the embodiment of the present invention, it is possible to accurately locate which row of shift registers has a problem, thereby being able to find the problem point more quickly, improving the efficiency of defect analysis, and avoiding wasting a lot of time. When detecting the gate drive circuit provided by the embodiment of the present invention, it is not necessary to lead out a test pad for each row of shift registers, which is easier to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1A circuit schematic diagram of a gate drive circuit provided by an embodiment of the present invention;

[0034] Figure 2 A specific circuit structure diagram of a gate drive circuit provided by an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of waveforms of a gate drive circuit under normal output conditions provided by an embodiment of the present invention;

[0036] Figure 4 A waveform diagram of the gate drive circuit provided by an embodiment of the present invention under abnormal output conditions. DETAILED DESCRIPTION

[0037] In order to further illustrate the gate driving circuit, display panel and detection method thereof provided by the embodiments of the present invention, they are described in detail below with reference to the accompanying drawings.

[0038] See also Figure 1 and Figure 2 , an embodiment of the present invention further provides a gate driving circuit, comprising: a first transmission sub-circuit 10, a second transmission sub-circuit 20 and a cascaded multi-stage shift register 30;

[0039] The shift register 30 includes a scan signal output terminal Gout, an inverted scan signal output terminal Gout_F, an output detection node (the output detection node of the odd-numbered shift register 30 is out1, and the output detection node of the even-numbered shift register 30 is out2), and a coupling sub-circuit 301; the coupling sub-circuit 301 is coupled to the scan signal output terminal Gout, the inverted scan signal output terminal Gout_F, and the output detection node, respectively, and is used to control the potential of the inverted scan signal output terminal Gout_F to be coupled with the potential of the output detection node under the control of the scan signal output terminal Gout;

[0040] The first transmission sub-circuit 10 is respectively coupled to the first active reference signal input terminal Ref1 and the output detection node out1 of each odd-numbered shift register 30; and is used to control the electrical connection between the first active reference signal input terminal Ref1 and the output detection node out1 of each odd-numbered shift register 30 under the control of the first active reference signal input terminal Ref1.

[0041] The second transmission sub-circuit 20 is respectively coupled to the second active reference signal input terminal Ref2 and the output detection node out2 of each even-numbered shift register 30; and is used to control the conduction or disconnection of the electrical connection between the second active reference signal input terminal Ref2 and the output detection node of each even-numbered shift register 30 under the control of the second active reference signal input terminal Ref2.

[0042] Exemplarily, the shift register 30 also includes a shift register sub-circuit (such as: GOA1, GOA2, GOA3, GOA4), and the shift register sub-circuit includes a shift register unit and an inverting unit. The shift register unit is coupled to the scan signal output terminal Gout and is used to control the scan signal output terminal Gout to output the scan signal; the inverting unit is coupled between the scan signal output terminal Gout and the inverted scan signal output terminal Gout_F, and is used to obtain an inverted scan signal according to the scan signal output from the scan signal output terminal Gout, and transmit it to the inverted scan signal output terminal Gout_F.

[0043] Exemplarily, the multi-stage shift register 30 includes multiple stages of shift register sub-circuits connected in cascade. For example, the scan signal output by the cascade signal output terminal Gout_C of the n-th stage shift register 30 serves as the signal input terminal of the (n+1)-th stage shift register 30, but the present invention is not limited thereto. When the gate drive circuit is applied to a display panel, the scan signal output terminal Gout of each stage of the shift register 30 is coupled to at least one corresponding row of sub-pixels to provide corresponding scan signals to the at least one corresponding row of sub-pixels.

[0044] For example, the specific structure of the shift register unit is not limited, and conventional shift register unit structures are applicable, for example, a shift register unit with an 18T1C circuit structure (i.e., including 18 transistors and 1 capacitor), but is not limited thereto. Optionally, the shift register unit can be connected to a first clock signal line and a second clock signal line, the first clock signal line is used to provide a first clock signal to the shift register unit, and the second clock signal line is used to provide a second clock signal to the shift register unit, and the timing sequence of the first clock signal and the second clock signal are opposite.

[0045] For example, the specific structure of the inverting unit is not limited, and conventional circuit structures with an inverting function are applicable. For example, the inverting unit includes two transistors connected in series between the first level signal input terminal VGH and the second level signal input terminal, the two transistors include an NMOS transistor and a PMOS transistor, the gates of the two transistors are coupled to the scan signal output terminal Gout, and the output terminals of the two transistors coupled together are coupled to the inverted scan signal output terminal Gout_F;

[0046] For another example, the inverting unit includes four transistors, a gate of a first transistor coupled to the second clock signal line, a first electrode of the first transistor coupled to the first level signal input terminal VGH, a second electrode of the first transistor coupled to the second electrode of the second transistor and coupled to the first clock signal line via a capacitor structure, a gate of the second transistor coupled to the scan signal output terminal Gout, a first electrode of the second transistor coupled to the second level signal input terminal, a gate of a third transistor coupled to the second electrode of the first transistor, a first electrode of the third transistor coupled to the first level signal input terminal VGH, a second electrode of the third transistor coupled to the inverted scan signal output terminal Gout_F, a gate of a fourth transistor coupled to the scan signal output terminal Gout, a first electrode of the fourth transistor coupled to the second level signal input terminal, and a second electrode of the fourth transistor coupled to the inverted scan signal output terminal Gout_F. The four transistors are of the same type.

[0047] Exemplarily, the coupling sub-circuit 301 is coupled to the scan signal output terminal Gout, the inverted scan signal output terminal Gout_F and the output detection node, respectively, and is used to control the potential of the inverted scan signal output terminal Gout_F to be coupled with the potential of the output detection node under the control of the scan signal output terminal Gout, thereby changing the potential of the output detection node.

[0048] Exemplarily, the first active reference signal inputted by the first active reference signal input terminal Ref1 has the same timing as the first clock signal, and the second active reference signal inputted by the second active reference signal input terminal Ref2 has the same timing as the second clock signal, but is not limited thereto.

[0049] Exemplarily, the first transmission sub-circuit 10 is used to transmit the first active reference signal inputted by the first active reference signal input terminal Ref1 to the output detection node of each odd-numbered shift register 30, and the second transmission sub-circuit 20 is used to transmit the second active reference signal inputted by the second active reference signal input terminal Ref2 to the output detection node of each even-numbered shift register 30.

[0050] Exemplarily, the coupling sub-circuit 301 includes a first transistor T1, the gate of the first transistor T1 is coupled to the scan signal output terminal Gout, the first electrode of the first transistor T1 is coupled to the inverted scan signal output terminal Gout_F, and the second electrode of the first transistor T1 is coupled to the output detection node; the first transmission sub-circuit 10 includes a second transistor T2, the gate of the second transistor T2 is coupled to the first active reference signal input terminal Ref1, the first electrode of the second transistor T2 is coupled to the gate of the second transistor T2, and the second electrode of the second transistor T2 is coupled to the output detection node out1 of each odd-numbered shift register 30; the second transmission sub-circuit 20 includes a third transistor T3, the gate of the third transistor T3 is coupled to the second active reference signal input terminal Ref2, the first electrode of the third transistor T3 is coupled to the gate of the third transistor T3, and the second electrode of the third transistor T3 is coupled to the output detection node out2 of each even-numbered shift register 30.

[0051] For example, the potential output by the inverted scan signal output terminal Gout_F is -18 V, and the potential transmitted to each output detection node by the first transmission sub-circuit 10 and the second transmission sub-circuit 20 is 5 V. When the coupling sub-circuit 301 is turned on and controls the potential of the inverted scan signal output terminal Gout_F to be coupled with the potential of the output detection node, the potential of the output detection node is expected to reach -10 V. Figure 3 As shown, under normal circumstances, the waveform of the output detection node out1 of each odd-numbered shift register 30 and the waveform of the output detection node out2 of each even-numbered shift register 30 are detected. It can be seen that when the scan signal output terminals Gout of the 8-row shift register 30 are all output normally, the potentials of the output detection nodes of the odd-numbered and even-numbered shift registers 30 in the 8-row shift register 30 are coupled, as shown in the dotted box. Based on the above two waveform simulations, the waveform Scan of the scan signal output terminal Gout of the 8-row cascaded shift register 30 includes 8 pulses.

[0052] like Figure 4As shown, when an abnormality occurs in the 5th row of shift registers 30 and the scan signal output terminal Gout of the 5th row of shift registers 30 has no output, the shift registers 30 after the 5th row have no input. Through simulation, it is found that the first active reference signal written into the output detection node of the 5th row of shift registers 30 is not coupled, as shown in the dotted box, so that it can be determined that the failure position of the shift register 30 is in the 5th row of shift registers 30; based on the above two waveform simulations, the waveform Scan of the scan signal output terminal Gout of the 8-row cascaded shift register 30 includes 4 pulses, that is, the scan signal output terminal Gout of the 5th row of shift registers 30 has no output.

[0053] According to the specific structure of the above-mentioned gate drive circuit, in the gate drive circuit provided by the embodiment of the present invention, the first transmission sub-circuit 10 can control the transmission of the first active reference signal to the output detection node out1 of each odd-numbered shift register 30, and the second transmission sub-circuit 20 can control the transmission of the second active reference signal to the output detection node out2 of each even-numbered shift register 30. The coupling sub-circuit 301 in each shift register 30 can control the potential of the inverted scan signal output terminal Gout_F to be coupled with the potential of the output detection node under the control of the scan signal output terminal Gout; in this way, when When the scan signal output terminal Gout and the inverted scan signal output terminal Gout_F of the shift register 30 can output normally, the coupling sub-circuit 301 can couple the potential of the inverted scan signal output terminal Gout_F with the potential of the output detection node, thereby changing the potential of the output detection node; and when the scan signal output terminal Gout and the inverted scan signal output terminal Gout_F of the shift register 30 cannot output normally, the coupling sub-circuit 301 cannot couple the potential of the inverted scan signal output terminal Gout_F with the potential of the output detection node, thereby failing to change the potential of the output detection node.

[0054] Therefore, in the gate drive circuit provided by the embodiment of the present invention, during detection, the waveforms of the output detection nodes of the odd-numbered shift registers 30 and the waveforms of the output detection nodes of the even-numbered shift registers 30 are directly observed through an oscilloscope. If the waveforms of the output detection nodes of the odd-numbered shift registers 30 are not coupled in a certain row, then the output of the shift register 30 in that row is abnormal. Similarly, if the waveforms of the output detection nodes of the even-numbered shift registers 30 are not coupled in a certain row, then the output of the shift register 30 in that row is abnormal. Therefore, when detecting the gate drive circuit provided by the embodiment of the present invention, it is possible to accurately locate which row of shift registers 30 has a problem, thereby being able to find the problem point more quickly, improving the efficiency of defect analysis, and avoiding wasting a lot of time. When detecting the gate drive circuit provided by the embodiment of the present invention, it is not necessary to lead out a test pad for each row of shift registers 30, which is easier to implement.

[0055] like Figure 1 and Figure 2 As shown, in some embodiments, the gate driving circuit further includes: a first voltage stabilizing sub-circuit 41 and / or a second voltage stabilizing sub-circuit 42;

[0056] A first terminal of the first voltage stabilizing sub-circuit 41 is coupled to the first level signal input terminal VGH, and a second terminal of the first voltage stabilizing sub-circuit 41 is coupled to the output detection node out1 of the odd-numbered shift register 30;

[0057] A first terminal of the second voltage stabilizing sub-circuit 42 is coupled to the first level signal input terminal VGH, and a second terminal of the second voltage stabilizing sub-circuit 42 is coupled to the output detection node out2 of the even-numbered shift register 30 .

[0058] Exemplarily, the first voltage stabilizing sub-circuit 41 includes a first capacitor C1, the first end of the first capacitor C1 is coupled to the first level signal input terminal VGH, and the second end of the first capacitor C1 is coupled to the output detection node of the odd-numbered shift register 30; the second voltage stabilizing sub-circuit 42 includes a second capacitor C2, the first end of the second capacitor C2 is coupled to the first level signal input terminal VGH, and the second end of the second capacitor C2 is coupled to the output detection node of the even-numbered shift register 30.

[0059] Exemplarily, the first level signal inputted by the first level signal input terminal VGH includes a high level signal, and the second level signal inputted by the second level signal input terminal includes a low level signal, but the present invention is not limited thereto.

[0060] Since the voltage values ​​of the first active reference signal and the second active reference signal both vary between positive and negative voltage values ​​(e.g., ±5 V), and the first transmission sub-circuit 10 and the second transmission sub-circuit 20 are formed into structures that function like diodes, when the voltage values ​​of the first active reference signal and the second active reference signal are negative, the output detection node may be floating. The provision of the first voltage stabilizing sub-circuit 41 and the second voltage stabilizing sub-circuit 42 can better stabilize the potential of the output detection nodes of each stage of the shift register 30.

[0061] like Figure 1 and Figure 2 As shown, in some embodiments, the shift register 30 further includes a first load sub-circuit 51 , and the coupling sub-circuit 301 is coupled to the output detection node through the first load sub-circuit 51 .

[0062] Exemplarily, the first load sub-circuit 51 includes a third resistance structure R3 , a first end of the third resistance structure R3 is coupled to the coupling sub-circuit 301 , and a second end of the third resistance structure R3 is coupled to the output detection node.

[0063] Exemplarily, the third resistance structure R3 includes an IGZO resistance pattern, but is not limited thereto.

[0064] The shift register 30 further includes a first load sub-circuit 51 , which can effectively prevent voltage backflow, thereby ensuring the stability of the gate drive circuit.

[0065] like Figure 1 and Figure 2 As shown, in some embodiments, the gate drive circuit further includes at least one second load sub-circuit 52 and / or at least one third load sub-circuit 53; the second load sub-circuit 52 is connected in series between the output detection nodes out1 of adjacent odd-numbered shift registers 30; and the third load sub-circuit 53 is connected in series between the output detection nodes out2 of adjacent even-numbered shift registers 30.

[0066] Exemplarily, the second load sub-circuit 52 includes a fourth resistance structure R4, which is connected in series between the output detection nodes of adjacent odd-numbered shift registers 30; the third load sub-circuit 53 includes a fifth resistance structure R5, which is connected in series between the output detection nodes of adjacent even-numbered shift registers 30.

[0067] Exemplarily, the fourth resistance structure R4 is provided between the output detection nodes of every two adjacent odd-numbered shift registers 30; the fifth resistance structure R5 is provided between the output detection nodes of every two adjacent even-numbered shift registers 30, but is not limited thereto.

[0068] The above configuration that the gate drive circuit further includes the second load sub-circuit 52 and / or the third load sub-circuit 53 can effectively prevent voltage backflow, thereby ensuring the stability of the operation of the gate drive circuit.

[0069] like Figure 1 and Figure 2 As shown, in some embodiments, the first transmission sub-circuit 10 further includes a first resistance structure R1, a first end of the first resistance structure R1 is coupled to the first electrode of the second transistor T2, and a second end of the first resistance structure R1 is coupled to the gate of the second transistor T2; the second transmission sub-circuit 20 further includes a second resistance structure R2, a first end of the second resistance structure R2 is coupled to the first electrode of the third transistor T3, and a second end of the second resistance structure R2 is coupled to the gate of the third transistor T3.

[0070] The above configuration in which the first transmission sub-circuit 10 further includes a first resistance structure R1 and the second transmission sub-circuit 20 further includes a second resistance structure R2 can effectively prevent voltage backflow, thereby ensuring the stability of the gate drive circuit.

[0071] An embodiment of the present invention also provides a display panel, including the gate drive circuit provided by the above embodiment; the display panel also includes: a first test terminal PIN1 and a second test terminal PIN2, the first test terminal PIN1 is coupled to the output detection node out1 of each odd-numbered shift register 30, and the second test terminal PIN2 is coupled to the output detection node out2 of each even-numbered shift register 30.

[0072] The display panel provided by the embodiment of the present invention includes the gate drive circuit provided by the above embodiment. When testing the gate drive circuit, an oscilloscope is used to detect the first test terminal PIN1 and the second test terminal PIN2, so that the waveform of the output detection node of the odd-numbered shift register 30 and the waveform of the output detection node of the even-numbered shift register 30 are directly observed by the oscilloscope. If the waveform of the output detection node of the odd-numbered shift register 30 is not coupled in a certain row, then the output of the shift register 30 in that row has an abnormality. Similarly, if the waveform of the output detection node of the even-numbered shift register 30 is not coupled in a certain row, then the output of the shift register 30 in that row has an abnormality. Therefore, when testing the gate drive circuit in the display panel provided by the embodiment of the present invention, it is possible to accurately locate which row of shift registers 30 has a problem, thereby being able to find the problem point more quickly, improving the efficiency of defect analysis, and avoiding wasting a lot of time. In the display panel provided by the embodiment of the present invention, when testing the gate drive circuit, it is not necessary to lead out a test pad for each row of shift registers 30, which is easier to implement.

[0073] An embodiment of the present invention further provides a method for detecting a display panel, which is used to detect the display panel provided by the above embodiment. The detection method includes:

[0074] Detecting a signal of a first test terminal PIN1 to generate a first test signal;

[0075] Detecting a signal of the second test terminal PIN2 to generate a second test signal;

[0076] According to the first test signal and the second test signal, it is determined which stage of the shift register 30 in the gate driving circuit of the display panel has an abnormal output.

[0077] For example, based on the waveform of the first test signal and the waveform of the second test signal, it is possible to determine which level of the multi-level shift register 30 included in the gate drive circuit of the display panel has an abnormal output; the waveform of the first test signal is the waveform of the output detection node of the odd-numbered shift register 30, and the waveform of the second test signal is the waveform of the output detection node of the even-numbered shift register 30.

[0078] When the gate drive circuit included in the display panel is detected by the detection method provided by the embodiment of the present invention, the first test terminal PIN1 and the second test terminal PIN2 are detected by an oscilloscope, so that the waveform of the output detection node of the odd-numbered shift register 30 and the waveform of the output detection node of the even-numbered shift register 30 are directly observed by the oscilloscope. If the waveform of the output detection node of the odd-numbered shift register 30 is not coupled in a certain row, then the output of the shift register 30 in that row has an abnormality. Similarly, if the waveform of the output detection node of the even-numbered shift register 30 is not coupled in a certain row, then the output of the shift register 30 in that row has an abnormality. Therefore, when detecting the gate drive circuit in the display panel provided by the embodiment of the present invention, it is possible to accurately locate which row of shift registers 30 has a problem, thereby being able to find the problem point more quickly, improving the efficiency of defect analysis, and avoiding wasting a lot of time. In the display panel provided by the embodiment of the present invention, when detecting the gate drive circuit, it is not necessary to lead out a test pad for each row of shift registers 30, which is easier to implement.

[0079] It should be noted that in the embodiments of the present invention, "the same layer" may refer to film layers on the same structural layer. Alternatively, for example, the film layers on the same layer may be formed using the same film-forming process to form a specific pattern, and then patterned using the same mask through a single patterning process to form the film layer. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0080] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present invention.

[0081] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0082] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0083] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0084] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0085] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A gate drive circuit, characterized in that: include: A first transmission sub-circuit, a second transmission sub-circuit, and a cascaded multi-stage shift register; The shift register includes a scan signal output terminal, an inverted scan signal output terminal, an output detection node, and a coupling subcircuit; the coupling subcircuit is coupled to the scan signal output terminal, the inverted scan signal output terminal, and the output detection node, respectively, and is used to control the potential of the inverted scan signal output terminal to be coupled with the potential of the output detection node under the control of the scan signal output terminal; The first transmission sub-circuit is respectively coupled to the first active reference signal input terminal and the output detection node of each odd-numbered shift register; and is used to control the electrical connection between the first active reference signal input terminal and the output detection node of each odd-numbered shift register to be turned on or off under the control of the first active reference signal input terminal; The second transmission sub-circuit is respectively coupled to the second active reference signal input terminal and the output detection node of each even-numbered shift register; and is used to control the conduction or disconnection of the electrical connection between the second active reference signal input terminal and the output detection node of each even-numbered shift register under the control of the second active reference signal input terminal.

2. The gate drive circuit according to claim 1, wherein: The gate drive circuit further includes: a first voltage stabilization subcircuit and / or a second voltage stabilization subcircuit; A first terminal of the first voltage stabilizing sub-circuit is coupled to the first level signal input terminal, and a second terminal of the first voltage stabilizing sub-circuit is coupled to the output detection node of the odd-numbered shift register; A first terminal of the second voltage stabilizing sub-circuit is coupled to the first level signal input terminal, and a second terminal of the second voltage stabilizing sub-circuit is coupled to the output detection node of the even-numbered shift register.

3. The gate drive circuit according to claim 1, wherein: The shift register further includes a first load sub-circuit, and the coupling sub-circuit is coupled to the output detection node through the first load sub-circuit.

4. The gate drive circuit according to claim 1, wherein: The gate drive circuit also includes at least one second load sub-circuit and / or at least one third load sub-circuit; the second load sub-circuit is connected in series between the output detection nodes of adjacent odd-numbered shift registers; and the third load sub-circuit is connected in series between the output detection nodes of adjacent even-numbered shift registers.

5. The gate drive circuit according to any one of claims 1 to 4, characterized in that: The coupling sub-circuit includes a first transistor, a gate of the first transistor is coupled to the scan signal output terminal, a first electrode of the first transistor is coupled to the inverted scan signal output terminal, and a second electrode of the first transistor is coupled to the output detection node; The first transmission sub-circuit includes a second transistor, a gate of the second transistor is coupled to the first active reference signal input terminal, a first electrode of the second transistor is coupled to the gate of the second transistor, and a second electrode of the second transistor is coupled to the output detection node of each odd-numbered shift register; The second transmission sub-circuit includes a third transistor, the gate of the third transistor is coupled to the second active reference signal input terminal, the first electrode of the third transistor is coupled to the gate of the third transistor, and the second electrode of the third transistor is coupled to the output detection node of each even-numbered shift register.

6. The gate driving circuit according to claim 5, wherein: The first transmission sub-circuit further includes a first resistance structure, a first end of the first resistance structure is coupled to the first electrode of the second transistor, and a second end of the first resistance structure is coupled to the gate of the second transistor; The second transmission sub-circuit further includes a second resistance structure, a first end of the second resistance structure is coupled to the first electrode of the third transistor, and a second end of the second resistance structure is coupled to the gate of the third transistor.

7. The gate driving circuit according to claim 2, wherein: The first voltage stabilization sub-circuit includes a first capacitor, a first end of the first capacitor is coupled to the first level signal input end, and a second end of the first capacitor is coupled to the output detection node of the odd-numbered shift register; The second voltage stabilization sub-circuit includes a second capacitor, a first end of the second capacitor is coupled to the first level signal input end, and a second end of the second capacitor is coupled to the output detection node of the even-numbered shift register.

8. The gate driving circuit according to claim 3, wherein: The first load sub-circuit includes a third resistance structure, a first end of the third resistance structure is coupled to the coupling sub-circuit, and a second end of the third resistance structure is coupled to the output detection node.

9. The gate driving circuit according to claim 4, wherein: The second load sub-circuit includes a fourth resistance structure, wherein the fourth resistance structure is connected in series between the output detection nodes of adjacent odd-numbered shift registers; The third load sub-circuit includes a fifth resistance structure connected in series between the output detection nodes of adjacent even-numbered shift registers.

10. The gate driving circuit according to claim 1, wherein: The shift register also includes a shift register sub-circuit, which includes a shift register unit and an inverting unit. The shift register unit is coupled to the scan signal output end and is used to control the scan signal output end to output the scan signal; the inverting unit is coupled between the scan signal output end and the inverted scan signal output end and is used to obtain an inverted scan signal based on the scan signal output from the scan signal output end and transmit it to the inverted scan signal output end.

11. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit as described in any one of claims 1 to 10; the display panel further comprises: a first test terminal and a second test terminal, the first test terminal is coupled to the output detection node of each odd-numbered shift register, and the second test terminal is coupled to the output detection node of each even-numbered shift register.

12. A method for detecting a display panel, characterized in that: For detecting the display panel according to claim 11, the detection method comprises: detecting a signal at a first test terminal to generate a first test signal; detecting a signal at a second test terminal to generate a second test signal; According to the first test signal and the second test signal, it is determined which stage of the multi-stage shift register included in the gate driving circuit of the display panel has an abnormal output.

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