Double pattern etching method

Abstract

The invention discloses a double pattern etching method, which belongs to the technical field of semiconductors, and comprises the following steps: providing a substrate which is provided with a first region and a second region which are opposite to each other; an amorphous silicon layer, a stop layer, a nitride layer and an oxide layer are sequentially formed on the substrate, and a preset etching selection ratio exists between the stop layer and the nitride layer; etching the film layer on the substrate until the stop layer, forming a first target pattern in the first region, and forming an intermediate pattern in the second region; etching the middle pattern until the stop layer, and forming a second target pattern in the second region; and continuously etching by taking the first target pattern and the second target pattern as masks, and forming the required mandrel on the substrate. The stop layer is added, and the two etching processes are stopped on the stop layer, so that the subsequent etching load is consistent, the defects caused by oxidation in the two etching processes are reduced, the difference of line width load can be increased, and the problem of dual pattern etching load is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a double pattern etching method. Background Art

[0002] Nowadays, the critical dimension (CD) of semiconductor devices is shrinking, and the wavelength of photolithography used is much larger than the feature size. This can cause severe distortion in the photoresist pattern formed on the silicon wafer surface, known as the optical proximity effect. As photolithography technology faces higher requirements and challenges, various resolution enhancement technologies (RETs) have been proposed to improve image quality and enhance resolution.

[0003] Double patterning, as an effective lithography resolution enhancement technique, is widely used across various technology nodes. Double patterning is primarily implemented using the Lithography-Etch-Lithography-Etch (LELE) process. The basic principle is to split the lithographic pattern, originally formed by etching a single mask, onto two or more masks according to specific design rules. Multiple exposures and etching cycles are then used to achieve the original pattern.

[0004] After 28nm, due to the limitation of lithography capability, the polysilicon gate process adopts the above-mentioned double lithography technology, such as Figure 1 The multi-layer structure of the substrate 10 is formed. In the first etching process, the multi-layer structure is subjected to a photolithography etching process to form a first region of the substrate 10. Figure 2 The first target pattern shown in FIG. 1 forms an intermediate pattern to be etched again in the second region; in the second etching process, the ODL layer 35 is covered on the amorphous silicon layer 22 and the target pattern, and the ODL layer 35 is etched, as shown in FIG. Figure 3 and Figure 4 The ODL layer 35 in the second region is opened, the excess photoresist 34 and SHB layer (Si-O-based Hard Mask, SHB) 33 are removed, and the organic bottom structure (Organic Dielectric Layer, ODL layer) layer, the silicon-based hard mask intermediate layer structure (Si-O-based Hard Mask, SHB) layer and the photoresist (PR) layer form a three-layer photolithography structure plate. The SHB layer uses a silicon-based anti-reflective layer such as a silicon bottom anti-reflective coating (BARC). The ODL layer usually uses a carbon coating (Spin-On-Carbon, SOC), which is a polymer with a high carbon content, such as Figure 5 and Figure 6 , etching the middle pattern to form the second target pattern, and then removing the ODL layer 35 to form Figure 7 and Figure 8 The first target pattern and the second target pattern shown in FIG. 1 are used as masks in the subsequent etching process to continue etching until a core shaft is formed. Figure 9 and 10 shown.

[0005] Ideally, the amorphous silicon layer 22 is hardly etched or consumed in the two etching processes. However, due to the characteristics of dry etching, the etching selectivity between the nitride layer 23 and the amorphous silicon layer 22 is relatively poor. Due to the different consumption of the amorphous silicon layer 22 in the two etching processes, the XY-direction morphology of the final core shaft is difficult to control, resulting in defects. In the first etching process, after the etching is completed, the photoresist stripping process will be carried out. In this process, the amorphous silicon layer 22 will be exposed and oxidized to form native oxide, which will affect the subsequent etching. Figure 9 Topographic defects 40 and oxidation defects 50 are shown.

[0006] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0007] The object of the present invention is to provide a double pattern etching method to solve the problem of double pattern etching load.

[0008] In order to solve the above technical problems, the present invention provides a double pattern etching method, comprising:

[0009] providing a substrate having a first region and a second region facing each other;

[0010] forming an amorphous silicon layer, a stop layer, a nitride layer, and an oxide layer in sequence on the substrate, wherein a predetermined etching selectivity ratio exists between the stop layer and the nitride layer;

[0011] Etching the film layer on the substrate until the stop layer is reached, forming a first target pattern in the first area and an intermediate pattern in the second area;

[0012] etching the intermediate pattern until reaching the stop layer to form a second target pattern in the second region;

[0013] Etching is continued using the first target pattern and the second target pattern as masks to form desired core shafts on the substrate.

[0014] Preferably, before forming the amorphous silicon layer, a high-K dielectric layer and a metal capping layer are sequentially formed on the substrate.

[0015] Preferably, the stop layer and the oxide layer are both made of silicon oxide.

[0016] Preferably, etching the intermediate pattern comprises:

[0017] sequentially covering the stop layer with an ODL layer, an SHB layer, and a photoresist, forming a desired pattern on the photoresist by photolithography, and etching the ODL layer in the second region to the oxide layer;

[0018] removing the photoresist and SHB layers;

[0019] The intermediate pattern is etched through the exposed area of ​​the ODL layer.

[0020] Preferably, the ODL layer is made of silicon nitride.

[0021] Preferably, continuing etching using the first target pattern and the second target pattern as masks to form the desired mandrels on the substrate comprises:

[0022] etching the stop layer using the first target pattern and the second target pattern as masks;

[0023] The amorphous silicon layer is continuously etched using the first target pattern and the second target pattern as masks.

[0024] Preferably, after etching the amorphous silicon layer, the metal capping layer and the high-K dielectric layer are further etched using the first target pattern and the second target pattern as masks to form the core shaft.

[0025] Preferably, in the first region, a plurality of well regions are distributed in the substrate, and the well regions are separated by isolation structures.

[0026] Preferably, the well region includes NWIO, PWIO, NW and PW.

[0027] Preferably, the first target pattern and the second target pattern have different line widths.

[0028] In the double pattern etching method provided by the present invention, a stop layer is covered on the amorphous silicon layer. Since the nitride layer and the stop layer have a high etching selectivity ratio, the stop layer can be used as an etching stop layer for the hard mask layer. There is no need to calculate the etching amount of the amorphous silicon layer. Both etching processes stop on the stop layer, which can make the subsequent etching load consistent, reduce the defects caused by oxidation during the two etching processes, help control the side wall morphology of the core shaft, and increase the difference in line width load to solve the double pattern etching load problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0030] Figure 1 It is a schematic diagram of the membrane structure in the prior art;

[0031] Figure 2 It is a structural schematic diagram of the first target pattern in the first area in the prior art;

[0032] Figure 3 It is a structural diagram of the ODL layer in the first region in the prior art;

[0033] Figure 4 It is a structural diagram of the ODL layer in the second region in the prior art;

[0034] Figure 5 This is a schematic diagram of the structure after the photoresist is removed from the first area in the prior art;

[0035] Figure 6 It is a schematic diagram of the structure after the photoresist is removed from the second area in the prior art;

[0036] Figure 7 It is a schematic diagram of the structure after the first area is etched in the prior art;

[0037] Figure 8 It is a schematic diagram of the structure after the second region is etched in the prior art;

[0038] Figure 9 It is a schematic diagram of the core shaft structure of the first area in the prior art;

[0039] Figure 10 It is a schematic diagram of the core shaft structure in the second area in the prior art;

[0040] Figure 11 Schematic diagram of the membrane structure of the present invention;

[0041] Figure 12 Schematic diagram of the ODL layer structure of the first region in the present invention;

[0042] Figure 13 is a schematic diagram of the ODL layer structure of the second region in the present invention;

[0043] Figure 14 It is a schematic diagram of the structure after the first area is etched in the present invention;

[0044] Figure 15 is a schematic diagram of the structure after the second region is etched in the present invention;

[0045] Figure 16It is a schematic structural diagram of etching the amorphous silicon layer in the first region of the present invention;

[0046] Figure 17 It is a schematic structural diagram of etching the amorphous silicon layer in the second region of the present invention;

[0047] Figure 18 It is a schematic diagram of the core shaft structure of the first area in the present invention;

[0048] Figure 19 It is a schematic diagram of the core shaft structure of the second area in the present invention;

[0049] Figure 20 It is an execution flow chart of the present invention.

[0050] In the attached figure:

[0051] 10. Substrate; 11. NWIO; 12. PWIO; 13. NW; 14. PW; 15. Isolation structure; 20. High-K dielectric layer; 21. Metal cap layer; 22. Amorphous silicon layer; 23. Nitride layer; 24. Oxide layer; 25. Stop layer; 30. APF; 31. NFDARC; 32. Cover oxide layer; 33. SHB layer; 34. Photoresist; 35. ODL layer; 40. Morphology defects; 50. Oxidation defects. DETAILED DESCRIPTION

[0052] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0053] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium; they can be internal communication between two elements or an interactive relationship between two elements. In addition, as used in the present invention, "one element is arranged on another element" generally only means that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element, and it should not be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0054] The inventors have found that semiconductor devices at the 28nm technology node and below are limited by lithography capabilities. The polysilicon gate process has changed from the original one-mask one-pass etching method to a two-mask two-pass etching method. In both etching processes, a certain thickness of the amorphous silicon layer will be consumed when etching the nitride layer, resulting in morphological defects and oxidation defects in the subsequent etching process. Figure 9 As shown in FIG, the above problems are often solved by controlling the etching amount, such as Figure 2 Circle the area to avoid defects caused by repeated etching, but fine-tuning the process parameters often requires considering the influence of various factors, which makes actual operation difficult.

[0055] Based on this, the core idea of ​​the present invention is to cover the amorphous silicon layer with a stop layer. Since the nitride layer and the stop layer have a high etching selectivity ratio, it can be used as an etching stop layer for the hard mask layer. There is no need to calculate the etching amount of the amorphous silicon layer. During the second etching process, the hard mask layer also stops on the stop layer when etching, which can achieve consistent load and reduce the defects caused by oxidation during the two etching processes. It can also increase the difference in line width load and solve the problem of double pattern etching load.

[0056] For details, please refer to Figures 11-20 , which is a schematic diagram of an embodiment of the present invention. Figure 20 As shown, a double pattern etching method includes:

[0057] S1 , providing a substrate 10 , wherein the substrate 10 has a first region and a second region facing each other.

[0058] like Figure 11 As shown, the first region here is, for example, a device region of the substrate 10. In subsequent processes, several devices, such as MOS transistors, are often formed in the device region. In the first region, several well regions are distributed in the substrate 10, and the well regions are separated by isolation structures 15. The well regions include NWIO (Nwell I / O device, IO device N well) 11, PWIO (P well I / O device, IO device P well) 12, NW (N well, N-type well region) 13, and PW (P well, P-type well region) 14.

[0059] In one embodiment, Figure 13 As shown, the second region is the peripheral region of the substrate 10 , and isolation structures 15 are often distributed in the second region.

[0060] S2, forming an amorphous silicon layer 22, a stop layer 25, a nitride layer 23 and an oxide layer 24 in sequence on the substrate 10, wherein there is a predetermined etching selectivity ratio between the stop layer 25 and the nitride layer 23, so that the stop layer 25 is almost not consumed when the nitride layer 23 is etched.

[0061] The preparation methods of the amorphous silicon layer 22 mainly include vacuum evaporation, sputtering, chemical vapor deposition, plasma chemical vapor deposition, and the like.

[0062] It is understandable that before forming the amorphous silicon layer 22, a high-K dielectric layer 20 and a metal capping layer 21 are sequentially formed on the substrate 10. The material of the high-K dielectric layer 20 is, for example, HfO2, and the material of the metal capping layer 21 is, for example, TiN.

[0063] More preferably, the stop layer 25 and the oxide layer 24 are both made of silicon oxide. However, the material of the stop layer 25 is not limited thereto, and may be other materials that have a certain etching selectivity with silicon nitride.

[0064] like Figure 11 As shown, after the oxide layer 24 is formed, an APF (Advanced patterning film) 30, an NFDARC (N-free DARC, nitrogen-free dielectric anti-reflective coating) 31, a cap oxide layer (Cap Oxide) 32, an SHB layer 33 and a photoresist 34 are formed on the oxide layer 24, and the photolithography pattern is transferred and etched to the lower layer from top to bottom. APF30 is a thin film that realizes a multiple patterning integration solution, which can realize the patterning of high aspect ratio (HAR) features. The multi-film structure above the oxide layer 24 can be etched once or multiple times until the stop layer 25 is reached to remove the residual structure on the top of the oxide layer 24 to form a structure as shown in FIG. Figure 12 The first target graphic is shown.

[0065] S3 , etching the film layer on the substrate 10 until the stop layer 25 , forming a first target pattern in the first region, and forming an intermediate pattern in the second region.

[0066] In one embodiment, the oxide layer 24 and the nitride layer 23 are etched through the APF 30, NFDARC 31, the covering oxide layer 32, the SHB layer 33 and the photoresist 34 above the oxide layer 24, and the excess film layer on the top of the oxide layer 24 is removed after etching. Due to the presence of the stop layer 25, the amorphous silicon layer 22 is blocked from being exposed to form a native oxide, thereby preventing the amorphous silicon layer 22 from being etched.

[0067] In one embodiment, an ODL layer 35 and a photoresist 34 are covered on the oxide layer 24, the photoresist 34 is photolithographically formed into a specified pattern, the ODL layer 35 is etched, and the oxide layer 24 and the nitride layer 23 are etched using the ODL layer 35. The oxide layer 24 and the nitride layer 23 can be etched in batches or all at once until the surface of the stop layer 25 is reached. There is no specific limitation here.

[0068] S4, etching the intermediate pattern until the stop layer 25 is reached, forming a second target pattern in the second region. After the desired first target pattern is formed in the first region, etching the intermediate pattern in the second region is continued. The etching method of the second region can also be used to etch the ODL layer 35. Specifically, etching the intermediate pattern includes:

[0069] S4.1, sequentially covering the ODL layer 35, the SHB layer 33 and the photoresist 34 on the stop layer 25, forming the photoresist 34 into a desired pattern by photolithography, and etching the ODL layer 35 in the second region to the oxide layer 24. Figure 12 and Figure 13 As shown, an ODL layer 35 is etched through the pattern formed by the photoresist 34 to the top surface of the oxide layer 24. The ODL layer 35 (organic dielectric layer), SHB (Si-O-based hard mask intermediate layer structure), and photoresist (PR) layer constitute a three-layer photolithography structure. The SHB layer 33 is a silicon-based anti-reflective layer such as a silicon bottom anti-reflective coating (BARC). The ODL layer 35 is typically coated with a carbon coating (Spin-On-Carbon, SOC), which is a polymer with a high carbon content.

[0070] S4.2, removing the photoresist 34 and the SHB layer 33.

[0071] S4.3, etching the intermediate pattern through the exposed area of ​​the ODL layer 35 until the surface of the stop layer 25. After forming the first target pattern and the second target pattern, the top ODL layer 35 is removed, as shown in FIG. Figure 14 and Figure 15 The first target graphic and the second target graphic are shown.

[0072] S5, continue etching using the first target pattern and the second target pattern as masks to form the desired core shaft on the substrate 10. Figure 16 and Figure 17 As shown, continuing etching with the first target pattern and the second target pattern as masks to form the required mandrels on the substrate 10 includes:

[0073] etching the stop layer 25 using the first target pattern and the second target pattern as masks;

[0074] The amorphous silicon layer 22 is continuously etched using the first target pattern and the second target pattern as masks.

[0075] like Figure 18 and Figure 19 As shown, after etching the amorphous silicon layer 22, the metal cover layer 21 and the high-K dielectric layer 20 are further etched using the first target pattern and the second target pattern as masks to form the core shaft.

[0076] However, the etching of the stop layer 25, the amorphous silicon layer 22, the metal cap layer 21 and the high-K dielectric layer 20 can be achieved by etching once or multiple times because the first target pattern and the second target pattern have the same etching load. For example, after etching the stop layer 25, the stop layer 25 and the amorphous silicon layer 22 of a certain thickness are etched at one time, such as Figure 16 and Figure 17 The first and second regions are separated, and the metal cap layer 21 and the high-K dielectric layer 20 are then etched. Here, the stop layer 25 can be made of a material having a higher etching selectivity than silicon nitride and a lower etching selectivity than amorphous silicon. When etching amorphous silicon subsequently, in addition to reducing defects caused by oxidation during the two etching processes and reducing the formation of native oxide in the etching gap, the difference in line width load can also be increased.

[0077] Specifically, the first target pattern and the second target pattern have different line widths. Alternatively, the first target pattern and the second target pattern have different critical dimensions. During the double patterning process, two target pattern sizes can be formed. It is understood that the line width of the second target pattern can be smaller than that of the first target pattern. First, the larger first target pattern and the intermediate pattern are formed. Then, by further etching the intermediate pattern, the size of the intermediate pattern is reduced to form the smaller second target pattern. Consequently, the mandrel sizes ultimately formed in the first region and the second region are also different.

[0078] In the double pattern etching method provided by the present invention, due to the high etching selectivity between silicon nitride and silicon oxide, silicon oxide can be used as the stop layer 25 of the silicon nitride hard mask layer 35. When the silicon nitride hard mask layer is etched for the second time, it also stops on the silicon oxide, thereby achieving a consistent etching load. In this way, there is no need to calculate the amorphous silicon etching amount, and the process window for different line width loads can also be increased.

[0079] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A double pattern etching method, characterized in that: include: providing a substrate having a first region and a second region facing each other; forming an amorphous silicon layer, a stop layer, a nitride layer, and an oxide layer in sequence on the substrate, wherein a predetermined etching selectivity ratio exists between the stop layer and the nitride layer; Etching the film layer on the substrate until the stop layer is reached, forming a first target pattern in the first area and an intermediate pattern in the second area; etching the intermediate pattern until reaching the stop layer to form a second target pattern in the second region; Etching is continued using the first target pattern and the second target pattern as masks to form desired core shafts on the substrate.

2. The double pattern etching method according to claim 1, wherein: Before forming the amorphous silicon layer, a high-K dielectric layer and a metal capping layer are sequentially formed on the substrate.

3. The double pattern etching method according to claim 1, wherein: The stop layer and the oxide layer are both made of silicon oxide.

4. The double pattern etching method according to claim 1, wherein: Etching the intermediate pattern includes: sequentially covering the stop layer with an ODL layer, an SHB layer, and a photoresist, forming a desired pattern on the photoresist by photolithography, and etching the ODL layer in the second region to the oxide layer; removing the photoresist and SHB layers; The intermediate pattern is etched through the exposed area of ​​the ODL layer.

5. The double pattern etching method according to claim 4, characterized in that: The material of the ODL layer is silicon nitride.

6. The double pattern etching method according to claim 2, wherein: Continuing etching using the first target pattern and the second target pattern as masks to form a desired mandrel on the substrate includes: etching the stop layer using the first target pattern and the second target pattern as masks; The amorphous silicon layer is continuously etched using the first target pattern and the second target pattern as masks.

7. The double pattern etching method according to claim 6, wherein: After etching the amorphous silicon layer, the metal cover layer and the high-K dielectric layer are further etched using the first target pattern and the second target pattern as masks to form the core shaft.

8. The double pattern etching method according to claim 7, wherein: In the first region, a plurality of well regions are distributed in the substrate, and the well regions are separated by isolation structures.

9. The double pattern etching method according to claim 8, characterized in that: The well region includes NWIO, PWIO, NW, and PW.

10. The double pattern etching method according to claim 1, wherein: The first target pattern and the second target pattern have different line widths.

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