HgTe zero-dimensional semiconductor patterning method based on orthogonal ligand

Abstract

The invention relates to an electron beam lithography patterning method for an HgTe zero-dimensional semiconductor, and belongs to the field of semiconductor device preparation. According to the method, a non-polar ligand orthogonal to PMMA is selected to modify an HgTe zero-dimensional semiconductor, so that the HgTe zero-dimensional semiconductor is kept stable in an electron beam lithography process and is not damaged by a polar solvent, then high-precision patterning is realized through a stripping process, and solid ligand exchange is performed to optimize photoelectric properties. According to the method, the problems that in a traditional method, the HgTe zero-dimensional semiconductor is prone to damage and the performance is degraded in the micro-nano machining process are solved, excellent photoelectric characteristics are kept while high-precision patterning is achieved, and an effective technical path is provided for preparation of high-performance devices such as infrared detectors and quantum communication devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing, and in particular to an electron beam lithography patterning method for HgTe zero-dimensional semiconductors. Background Art

[0002] HgTe zero-dimensional semiconductors, with their tunable optoelectronic properties in the mid- and far-infrared bands, hold significant application prospects in infrared detection, thermoelectric conversion, and quantum communications. Precise patterning of HgTe zero-dimensional semiconductors is crucial for fabricating high-performance devices. However, due to their environmental sensitivity and the susceptibility of their surface ligands to damage, HgTe zero-dimensional semiconductors present significant challenges in micro- and nanofabrication.

[0003] Traditional patterning usually uses technologies such as ultraviolet lithography, but HgTe zero-dimensional semiconductors encounter the following problems in the lithography process: First, polar solvents such as developers and stripping solutions used in the lithography process can easily lead to dissolution of quantum dot films, surface ligand stripping, or quantum dot agglomeration; second, the stripping process between zero-dimensional semiconductor films and traditional photoresists (such as AZ5214, etc.) and electron beam photoresists such as PMMA is difficult to precisely control, which can easily lead to residues or excessive stripping; finally, conventional photosensitive zero-dimensional semiconductor ligands are usually not conducive to charge transport, limiting device performance.

[0004] There are two main approaches to addressing this problem: one bypasses conventional photolithography and employs alternative methods such as spray coating, but this suffers from poor precision (>10 microns) and repeatability; the other involves special coatings to protect quantum dots, which often compromises their optoelectronic properties. None of these approaches can simultaneously achieve high-precision patterning and excellent optoelectronic performance.

[0005] Therefore, a new processing method is urgently needed that can achieve high-precision patterning while maintaining the optoelectronic properties of HgTe zero-dimensional semiconductors to meet the preparation requirements of high-performance electronic and optoelectronic devices. Summary of the Invention

[0006] In order to improve the technical problems of high-precision patterning and excellent optoelectronic performance in photolithography technology, the present application provides a HgTe zero-dimensional semiconductor patterning method based on orthogonal ligands.

[0007] The present application provides a method for patterning HgTe zero-dimensional semiconductors based on orthogonal ligands, which adopts the following technical solution: A method for patterning HgTe zero-dimensional semiconductors based on orthogonal ligands, comprising the following steps: a) Synthesize HgTe zero-dimensional semiconductors and modify their surfaces with non-polar ligands; b) performing PMMA electron beam lithography on the substrate to form a desired pattern; c) depositing a non-polar ligand-modified HgTe zero-dimensional semiconductor on a substrate that has undergone photolithography; d) performing a post-baking process to further solidify the attachment of the zero-dimensional semiconductor to the substrate; e) performing a stripping process to selectively remove the HgTe quantum dots on the PMMA to form a target pattern; f) Solid-state ligand exchange of patterned HgTe zero-dimensional semiconductors to replace non-polar ligands with ligands that facilitate charge transport; g) post-processing the obtained patterned HgTe semiconductor film to obtain a patterned structure with excellent optoelectronic properties.

[0008] By adopting the above technical solution and the above-mentioned orthogonal ligand-based HgTe zero-dimensional semiconductor patterning method, high-resolution and high-fidelity semiconductor pattern construction is achieved while maintaining the structural integrity and optoelectronic properties of the material. This method utilizes non-polar ligands to provide excellent solution stability and pattern selectivity during the lithography process, and precisely defines the spatial distribution of HgTe quantum dots through electron beam lithography and lift-off treatment. The initial non-conductive ligands are then replaced with ligands that are conducive to charge transport through solid-state ligand exchange, significantly improving the charge mobility and photoresponse ability of the film. The resulting patterned HgTe structure has good adhesion, stability and excellent near-infrared optoelectronic properties, and is suitable for the micro-nano manufacturing needs in cutting-edge fields such as infrared detection, optoelectronic device integration and flexible electronics.

[0009] Optionally, the non-polar ligand in step a) is selected from one or more combinations of long-chain alkylamines, long-chain alkylthiols, long-chain carboxylic acids or long-chain phosphine ligands.

[0010] By adopting the above technical solution and using non-polar ligands such as long-chain alkylamines, alkylthiols, carboxylic acids or phosphines, the dispersibility and solution stability of HgTe zero-dimensional semiconductors can be effectively improved, the occurrence of agglomeration can be prevented, and at the same time, its processability in non-polar solvents can be enhanced, providing a good material basis for subsequent photolithographic pattern transfer, helping to achieve highly uniform and high-resolution graphic deposition effects, and providing support for the construction of excellent performance nano-photoelectric devices.

[0011] Optionally, in step c), the HgTe zero-dimensional semiconductor deposition method is selected from one or more of spin coating, dip coating, spray coating or drop coating.

[0012] By adopting the above technical solution and using various deposition methods such as spin coating, dip coating, spray coating or drop coating, the adaptive process can be flexibly selected according to different substrate structures and pattern sizes to improve the coverage uniformity and film quality of HgTe zero-dimensional semiconductors in the pattern area. At the same time, the process is simple and highly adaptable, which is conducive to large-area preparation and high-throughput processing, meeting the requirements of different application scenarios for graphical accuracy and efficiency.

[0013] Optionally, the post-baking treatment in step d) includes annealing at 60-120° C. for 1-20 minutes in an inert gas environment.

[0014] By adopting the above technical solution, a post-baking treatment at 60-120°C for 1-20 minutes in an inert gas environment can effectively promote the adhesion stability between the HgTe zero-dimensional semiconductor and the substrate, enhance the structural integrity of the film, prevent material shedding or migration during subsequent processing, and gently avoid material performance degradation through heat treatment, maintaining its excellent optoelectronic properties and providing a stable foundation for subsequent ligand exchange and device integration.

[0015] Optionally, the stripping solvent in step e) is selected from one or more of acetone, chloroform or toluene, and the stripping time is 2-10 minutes.

[0016] By adopting the above technical solution, using organic solvents such as acetone, chloroform or toluene, and controlling the stripping time to 2-10 minutes, the residual HgTe zero-dimensional semiconductor material on the PMMA photoresist can be efficiently removed, ensuring clear pattern edges and complete structure, improving graphic accuracy, avoiding damage to the pattern area on the substrate, achieving selective pattern retention, and enhancing process reliability and repeatability.

[0017] Optionally, the solid-state ligand exchange in step f) uses a combination of thiol and phosphine ligands, wherein the thiol ligand is selected from one or more of mercaptopropionic acid, mercaptoethanol, mercaptopropanol or thioglycolic acid, and the phosphine ligand is selected from one or more of triphenylphosphine, trioctylphosphine, tributylphosphine or tris(hydroxymethyl)phosphine.

[0018] By adopting the above technical solution, a combination of thiol and phosphine ligands is used for solid-state ligand exchange, effectively replacing the original non-polar ligands, significantly improving the charge transfer efficiency of the HgTe zero-dimensional semiconductor and the photoelectric response performance of the film. The thiol ligands provide excellent electronic coupling ability, while the phosphine ligands enhance the stability of the film layer. The synergistic effect of the two achieves high conductivity and functionality of the patterned structure, which is beneficial to improving device performance and long-term operation reliability.

[0019] Optionally, the solid-state ligand exchange is performed by immersing the patterned HgTe zero-dimensional semiconductor film in a ligand solution or drop-coating the ligand solution on the film surface, with an exchange time of 1-120 minutes and an exchange temperature of room temperature to 80°C.

[0020] By adopting the above technical solution, the patterned HgTe zero-dimensional semiconductor film is immersed in a ligand solution or dripped with a ligand solution for solid-state ligand exchange, and the exchange time and temperature are controlled, so that sufficient replacement of the ligand and uniform modification of the structure can be achieved. The operation is simple and the adaptability is strong, which helps to improve the ligand exchange efficiency, enhance the charge transfer performance and photoelectric response stability of the semiconductor film, and thus realize the application of high-quality patterned structures in device preparation.

[0021] Optionally, the post-treatment in step g) includes annealing at 60-120° C. for 5-30 minutes under an inert gas environment.

[0022] By adopting the above technical solution, the patterned HgTe semiconductor film is annealed at 60–120°C for 5–30 minutes in an inert gas environment, effectively removing residual solvents and impurities, promoting ligand rearrangement and interface reconstruction, further improving the density and crystallization quality of the film, and helping to optimize the material's band structure and charge transport channels, thereby significantly enhancing the optoelectronic performance and stability of the device.

[0023] Optionally, the characteristic size of the patterned HgTe zero-dimensional semiconductor structure is between 100 nanometers and 10 micrometers, the pattern edge has a clear boundary, and the edge roughness is less than 20 nanometers.

[0024] By adopting the above technical solution, the pattern feature size is precisely controlled in the range of 100 nm-10 µm, and the edge roughness is reduced to less than 20 nm, significantly improving the spatial resolution and geometric fidelity of the HgTe zero-dimensional semiconductor patterned structure, thereby reducing carrier scattering and interface defect density, achieving efficient charge transport and uniform light field distribution; at the same time, it provides design freedom for the compact integration and array layout of micro-nano optoelectronic devices, meeting the stringent requirements of high-sensitivity detection, fast response and low-power applications.

[0025] Optionally, the HgTe graphic structure formed by the method has obvious light absorption characteristics in the near-infrared band and exhibits good carrier mobility and light response characteristics in the range of 77K to room temperature.

[0026] By adopting the above technical solution, the formed HgTe graphic structure is endowed with significant light absorption ability in the near-infrared band, and it is ensured to have excellent carrier mobility and stable light response performance in the range of 77K to room temperature. This technical solution can achieve high-sensitivity, wide-temperature near-infrared photoelectric detection functions, and is suitable for constructing high-performance infrared imaging devices, low-temperature photoelectric sensors and tunable photoelectric response platforms, significantly improving the stability and response efficiency of the devices in complex environments.

[0027] In summary, this application includes at least one of the following beneficial technical effects: 1. By selecting non-polar ligands that are orthogonal to PMMA and polar solvents, the HgTe zero-dimensional semiconductor remains stable during the photolithography process, avoiding damage to the quantum dots by developers, stripping solutions, etc.

[0028] 2. The lift-off process is used to achieve precise patterning with clear pattern edges and high resolution, meeting the high-precision requirements for micro-nano device preparation.

[0029] 3. Introduce orthogonal ligand exchange and post-baking curing steps to achieve a balance between patterning, precision, and device performance.

[0030] 4. The entire process is compatible with standard microelectronics processes and can be easily integrated into various device preparation processes, with good industrialization prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the process flow of the graphical method of the embodiment of the present application.

[0032] Figure 2 These are optical microscope images of HgTe zero-dimensional semiconductor patterns under different ligand combination conditions in the examples of the present application.

[0033] Figure 3 This is a performance diagram of the HgTe zero-dimensional semiconductor device after the graphical process flow of the embodiment of the present application.

[0034] Explanation of the accompanying symbols: A, output characteristic curve; B, transfer characteristic curve; C, electrical parameter summary table. DETAILED DESCRIPTION

[0035] The following is combined with Figure 1-3 This application is described in further detail.

[0036] The present invention discloses a method for patterning HgTe zero-dimensional semiconductors based on orthogonal ligands, comprising the following steps: a) Synthesize HgTe zero-dimensional semiconductors and modify their surfaces with non-polar ligands; b) performing PMMA electron beam lithography on the substrate to form a desired pattern; c) depositing a non-polar ligand-modified HgTe zero-dimensional semiconductor on a substrate that has undergone photolithography; d) performing a post-baking process to further solidify the attachment of the zero-dimensional semiconductor to the substrate; e) performing a stripping process to selectively remove the HgTe quantum dots on the PMMA to form a target pattern; f) Solid-state ligand exchange of patterned HgTe zero-dimensional semiconductors to replace non-polar ligands with ligands that facilitate charge transport; g) post-processing the obtained patterned HgTe semiconductor film to obtain a patterned structure with excellent optoelectronic properties.

[0037] The embodiment of the present application provides a method for patterning HgTe zero-dimensional semiconductors based on orthogonal ligands. By organically integrating multiple steps such as non-polar ligand modification, electron beam lithography pattern definition, selective deposition of materials within the pattern, post-baking and curing, stripping and development, solid-state ligand exchange, and final heat treatment, it is possible to achieve the construction of a HgTe quantum dot patterned structure with high precision, high fidelity, and excellent optoelectronic properties. The method has the following technical effects: First, by introducing non-polar ligands for surface modification during the synthesis of HgTe quantum dots, the dispersibility and processability of the HgTe zero-dimensional semiconductor are significantly improved, so that it has good solution phase processing capabilities, which facilitates the subsequent low-cost large-area processes such as spin coating and drop coating to complete material deposition on the photolithographic substrate, while preventing the quantum dots from being deposited during the deposition process. Aggregation is prevented, laying the foundation for high-quality graphics. Second, using PMMA as an electron beam lithography resist layer on the substrate for pattern preparation can precisely define the target area and obtain pattern openings with clear boundaries and high resolution by controlling the electron beam dose and development conditions. This provides a physical template for the high-fidelity deposition of subsequent patterned materials and enhances the controllability and uniformity of pattern transfer. Third, the deposition process of non-polar ligand-modified HgTe quantum dots in the pattern opening area combined with a post-baking step can effectively improve their adhesion and stability to the substrate surface. Appropriate annealing in an inert atmosphere at 60–120°C causes initial "sintering" or ligand arrangement reconstruction between the quantum dots, which helps maintain the conformality of the pattern edge and improves the mechanical stability of the quantum dot film. Furthermore, in the stripping step, the PMMA photoresist layer is removed using a selective solvent such as acetone, chloroform, or toluene. This removes the HgTe quantum dots deposited in non-target areas, preserving the structure within the pattern openings and enabling high-resolution pattern transfer. This step ensures clear structural boundaries and keeps edge roughness below 20nm, meeting the requirements for micro-nano pattern boundary control in subsequent device construction. The solid-state ligand exchange step in this method improves the functional performance of the material. By replacing non-polar long-chain ligands with ligands with high electronic coupling ability (such as mercaptopropionic acid and triphenylphosphine), not only does the insulating ligand barrier between quantum dots be broken, but it also promotes efficient electron transfer between quantum dots, significantly improving the conductivity and carrier mobility of the overall film. This orthogonal ligand design strategy not only takes into account the film stability of the initial patterning, but also ensures the optimization of subsequent performance. It is a key technological breakthrough in achieving high-performance patterned quantum dot devices. Finally, the post-processing annealing performed after the completion of ligand exchange can further optimize the quantum dot film structure, enhance the degree of inter-grain coupling, reduce structural defects, and improve the consistency of photoresponse and thermal stability. The resulting graphic structure has significant light absorption characteristics in the near-infrared band, and still maintains excellent carrier mobility and response sensitivity in the range of 77K to room temperature, showing good photoelectric conversion efficiency and environmental adaptability. This method breaks through the dependence of traditional patterning processes on high-temperature and high-vacuum equipment. By adopting a low-temperature, solution-processable and orthogonal ligand-regulatable strategy, it realizes high-resolution pattern construction and performance optimization of HgTe zero-dimensional semiconductors. It has the advantages of simple process, pattern fidelity, and excellent performance, providing key manufacturing technology support for the next generation of infrared detection devices, flexible optoelectronic devices and integrated optoelectronic systems.

[0038] Example 1 (1) Synthesis and non-polar ligand modification of HgTe zero-dimensional semiconductors: Under nitrogen protection, HgTe zero-dimensional semiconductors with a diameter of 7.5 nm were synthesized by hot injection. The surface of the initially synthesized zero-dimensional semiconductor was coated with oleylamine ligands. Octadecanethiol was introduced as a non-polar ligand via ligand exchange, which stabilized the quantum dots in polar solvents and prevented adverse interactions with PMMA.

[0039] (2) PMMA electron beam lithography: PMMA patterning is completed on Si / SiO2 substrate using standard electron beam lithography process.

[0040] (3) Deposition of HgTe zero-dimensional semiconductor thin film: Octadecanethiol-modified HgTe zero-dimensional semiconductor was prepared into a 10 mg / mL n-hexane solution and evenly deposited on the PMMA patterned substrate by spin coating (1000 rpm, 45 s) to form a semiconductor film with a thickness of approximately 60 nm.

[0041] (4) Post-baking treatment: The sample was annealed at 100°C for 10 minutes in a nitrogen atmosphere to remove residual solvent and promote the bonding of the zero-dimensional semiconductor film to the substrate.

[0042] (5) Peeling treatment: The sample was immersed in acetone and gently ultrasonicated for 1 minute to selectively dissolve the PMMA and peel off the HgTe zero-dimensional semiconductor film on it, leaving the zero-dimensional semiconductor in direct contact with the substrate. It was then rinsed with isopropyl alcohol and dried with nitrogen.

[0043] (6) Solid-state ligand exchange: The patterned HgTe zero-dimensional semiconductor film was immersed in a methanol solution of mercaptopropionic acid (20 mM) and triphenylphosphine (10 mM). Solid-state ligand exchange was performed at room temperature for 10 minutes to replace the non-polar octadecylthiol ligand with a short-chain thiolphosphine ligand that facilitates charge transport. The film was then rinsed with methanol to remove excess ligands and dried with nitrogen.

[0044] (7) Post-processing: Annealing at 80°C for 15 minutes in a nitrogen atmosphere promotes ligand rearrangement and stabilization of the zero-dimensional semiconductor film, thereby improving device performance.

[0045] The difference between Example 2 and Example 1 is that: (1) the non-polar ligand uses an oleylamine mixture (equivalent ratio 1:10) instead of octadecyl mercaptan.

[0046] (2) Solid-state ligand exchange was performed using a combination of mercaptoethanol and 1-dodecylmercaptan (equivalent ratio 1:1).

[0047] (3) The annealing temperature in step 6 is 100°C and the annealing time is 10 minutes.

[0048] The difference between Example 3 and Example 1 is that: (1) the size of the zero-dimensional semiconductor is 8 nm.

[0049] Solid-state ligand exchange adopts a step-by-step method: first, 1-dodecyl mercaptan is used for exchange for 3 minutes, and then mercaptoethanol is used for exchange for 5 minutes. The purpose of using the step-by-step method is to reduce the spacing changes between zero-dimensional semiconductors caused by ligand exchange, and ultimately reduce the cracking of zero-dimensional semiconductor films caused by spacing changes.

[0050] The above examples demonstrate that the orthogonal ligand-based HgTe zero-dimensional semiconductor lithographic patterning method provided herein, by selecting non-polar ligands compatible with PMMA and lithographic processes, combined with subsequent solid-state ligand exchange, achieves high-precision patterning while significantly improving the device's optoelectronic performance. Specifically, the solid-state exchange combination of the octadecylmercaptan initial ligand and mercaptopropionic acid / triphenylphosphine used in Example 1 exhibits optimal pattern integrity and optoelectronic response, making it particularly suitable for the preparation of infrared photodetectors.

[0051] The implementation principle of the HgTe zero-dimensional semiconductor patterning method based on orthogonal ligands in the embodiment of the present application is as follows: by introducing non-polar ligands to modify the surface of HgTe quantum dots, it has good solution dispersibility and film-forming stability, and is compatible with the PMMA electron beam lithography process to achieve selective deposition of quantum dots in a preset pattern area, followed by thermal annealing and curing to enhance the adhesion between the quantum dot film and the substrate, and maintain the conformality of the pattern boundary, and then use a selective solvent for stripping to remove excess quantum dots in the non-pattern area, thereby obtaining a graphic structure with clear structural edges and an edge roughness of less than 20nm; in order to improve the optoelectronic performance of the film, further while maintaining the pattern integrity, On the premise of maintaining the integrity of the structure, a solid-state ligand exchange process is introduced to replace the insulating long-chain non-polar ligands with short-chain, electronically strongly coupled thiol or phosphine ligands, thereby significantly improving the electron transmission efficiency between quantum dots; finally, mild annealing is used to promote ligand rearrangement and film structure densification, further optimizing the device performance, so that the final HgTe patterned film exhibits excellent light absorption ability and high carrier mobility in the near-infrared band; this method has mild process conditions, both high-resolution pattern transfer capability and performance controllability, and provides a new preparation strategy for the construction of high-performance flexible optoelectronic devices, infrared imaging detectors and integrated optoelectronic systems, with good application prospects and promotion value.

[0052] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A HgTe zero-dimensional semiconductor lithography patterning method based on orthogonal ligands, characterized in that: The following steps are involved: a) Synthesize HgTe zero-dimensional semiconductors and modify their surfaces with non-polar ligands; b) performing PMMA electron beam lithography on the substrate to form a desired pattern; c) depositing a non-polar ligand-modified HgTe zero-dimensional semiconductor on a substrate that has undergone photolithography; d) performing a post-baking process to further solidify the attachment of the zero-dimensional semiconductor to the substrate; e) performing a stripping process to selectively remove the HgTe quantum dots on the PMMA to form a target pattern; f) Solid-state ligand exchange of patterned HgTe zero-dimensional semiconductors to replace non-polar ligands with ligands that facilitate charge transport; g) post-processing the obtained patterned HgTe semiconductor film to obtain a patterned structure with excellent optoelectronic properties.

2. The method according to claim 1, wherein: The non-polar ligand in step a) is selected from one or more combinations of long-chain alkylamines, long-chain alkylthiols, long-chain carboxylic acids or long-chain phosphine ligands.

3. The method according to claim 1, wherein: In the step c), the HgTe zero-dimensional semiconductor deposition method is selected from one or more of spin coating, dip coating, spray coating or drop coating.

4. The method according to claim 1, wherein The post-baking treatment in step d) includes annealing at 60-120° C. for 1-20 minutes in an inert gas environment.

5. The method according to claim 1, wherein: The stripping solvent in step e) is selected from one or more of acetone, chloroform or toluene, and the stripping time is 2-10 minutes.

6. The method according to claim 1, wherein: The solid-state ligand exchange in step f) uses a combination of thiol and phosphine ligands, wherein the thiol ligand is selected from one or more of mercaptopropionic acid, mercaptoethanol, mercaptopropanol or thioglycolic acid, and the phosphine ligand is selected from one or more of triphenylphosphine, trioctylphosphine, tributylphosphine or tris(hydroxymethyl)phosphine.

7. The method according to claim 5, characterized in that: The solid-state ligand exchange is performed by immersing the patterned HgTe zero-dimensional semiconductor film in a ligand solution or drop-coating the ligand solution on the surface of the film. The exchange time is 1-120 minutes and the exchange temperature is room temperature to 80°C.

8. The method according to claim 1, wherein: The post-treatment in step g) comprises annealing at 60-120° C. for 5-30 minutes under an inert gas environment.

9. The method according to any one of claims 1 to 8, characterized in that: The characteristic size of the patterned HgTe zero-dimensional semiconductor structure is between 100 nanometers and 10 micrometers, the pattern edge has a clear boundary, and the edge roughness is less than 20 nanometers.

10. The method according to any one of claims 1 to 8, characterized in that: The HgTe graphic structure formed by the method has obvious light absorption characteristics in the near-infrared band and shows good carrier mobility and light response characteristics in the range of 77K to room temperature.

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