A semiconductor structure, a manufacturing method and a semiconductor device

Abstract

The application discloses a semiconductor structure, a preparation method and a semiconductor device. The semiconductor structure comprises a substrate, a doped buried layer embedded in the substrate, a shallow trench isolation structure exposed to a surface of the substrate, a gate electrode on the substrate, a barrier layer covering the gate electrode and the surface of the substrate, a first dielectric layer stacked on the barrier layer, and a first metal layer on the first dielectric layer. A deep trench is formed in a preparation process of an intermediate metal layer after the first metal layer is prepared, the deep trench extends to the substrate through the first dielectric layer, the barrier layer and the shallow trench isolation structure. The deep trench is filled to form a deep trench isolation structure, and the deep trench isolation structure and the doped buried layer are used for isolating adjacent device modules. The application forms the deep trench in the preparation process of the intermediate metal layer after the first metal layer, reduces the adverse effect on device layers in a BCD device, simplifies a preparation process of the BCD device, and reduces process integration difficulty and cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to a semiconductor structure, a preparation method and a semiconductor device. Background Art

[0002] Existing deep trench isolation (DTI) technology is primarily integrated with BCD semiconductor devices during the front-end process, prior to forming the interlayer dielectric (ILD) between the device layer and the metal layer, or before or after the shallow trench isolation (STI) process. However, the timing of DTI formation during the front-end process significantly impacts the device layer, negatively impacting device performance. For example, it can easily lead to wafer warpage, and the additional thermal process can easily cause lattice defects. Furthermore, the numerous process steps involved in process improvement make it difficult to integrate the improved process into the existing equipment process, resulting in development difficulties and high manufacturing and improvement costs. Summary of the Invention

[0003] In order to solve the problems of the prior art, the embodiments of the present application provide a semiconductor structure, a preparation method and a semiconductor device. The technical solution is as follows:

[0004] In one aspect, the present application provides a method for preparing a semiconductor structure, comprising:

[0005] Providing an initial semiconductor structure; the initial semiconductor structure includes a substrate, a doped buried layer embedded in the substrate, a shallow trench isolation structure exposed on the surface of the substrate, a gate located on the substrate, a barrier layer covering the gate surface and the substrate surface, a first dielectric layer stacked on the barrier layer, and a first metal layer located on the first dielectric layer;

[0006] During the preparation of the intermediate metal layer after the first metal layer is prepared, a deep trench is formed on the initial semiconductor structure; the deep trench penetrates the first dielectric layer, the barrier layer, the shallow trench isolation structure, and extends into the substrate;

[0007] The deep trench is filled to form a deep trench isolation structure; the deep trench isolation structure and the doped buried layer are used to isolate adjacent device modules.

[0008] Furthermore, the doped buried layer is connected to the deep trench isolation structure, and the end of the deep trench isolation structure extending in the substrate is located below the doped buried layer.

[0009] Furthermore, the deep trench isolation structure has a closed air gap.

[0010] Furthermore, in the process of forming the deep trench isolation structure, a filling dielectric layer is formed which is stacked on the initial semiconductor structure and covers at least the wall of the deep trench;

[0011] After filling the deep trench to form a deep trench isolation structure, the method further includes:

[0012] forming a first through hole penetrating the filling dielectric layer; wherein the first through hole exposes a metal layer adjacent to the filling dielectric layer;

[0013] Filling a first metal interconnection structure in the first through hole; the first metal interconnection structure is used to electrically connect to the metal layer adjacent to the filling dielectric layer;

[0014] A second metal layer is formed on the filling dielectric layer; the second metal layer is electrically connected to the first metal interconnect structure.

[0015] Furthermore, the filling dielectric layer region located in the deep trench in the filling dielectric layer is reused as the deep trench isolation structure.

[0016] Furthermore, the longitudinal depth of the deep groove in the substrate is 20 μm to 40 μm.

[0017] Furthermore, forming a deep trench on the initial semiconductor structure includes:

[0018] After forming the first metal layer, forming an isolation layer on the first metal layer; the isolation layer covers the first metal layer and the first dielectric layer;

[0019] Deep trench etching is performed on the initial semiconductor structure having the isolation layer formed thereon to form the deep trench; the deep trench penetrates the isolation layer, the first dielectric layer, the barrier layer and the shallow trench isolation structure and then extends into the substrate.

[0020] Furthermore, during the process of forming the deep trench isolation structure, a filling dielectric layer is formed by high-density plasma deposition, which is stacked on the initial semiconductor structure and covers at least the walls of the deep trench.

[0021] Furthermore, the position of the air gap in the deep trench isolation structure is determined based on a sputtering rate and a deposition rate of the high-density plasma deposition.

[0022] Furthermore, the initial semiconductor structure further includes a second dielectric layer covering the first metal layer; the deep trench penetrates the second dielectric layer, the first dielectric layer, the barrier layer, the shallow trench isolation structure, and then extends into the substrate.

[0023] Furthermore, filling the deep trench to form a deep trench isolation structure includes:

[0024] forming an initial filling dielectric layer on the second dielectric layer; the initial filling dielectric layer covers the second dielectric layer and covers the sidewalls and bottom walls of the deep trench;

[0025] Etching back the initial filling dielectric layer region on the bottom wall of the deep trench until the bottom wall of the deep trench is exposed; after the etching back process, the remaining initial filling dielectric layer forms a filling dielectric layer stacked on the initial semiconductor structure and covering at least the wall of the deep trench;

[0026] The deep trench is filled based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure; the deep trench isolation structure includes the deep trench metal isolation structure and a filling dielectric layer covering the deep trench wall.

[0027] Furthermore, before filling the deep trench based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes:

[0028] After the etching back process, ion implantation is performed at the bottom of the deep trench to form a doping structure.

[0029] Furthermore, before filling the deep trench based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes:

[0030] forming a first through hole penetrating the filling dielectric layer and the second dielectric layer;

[0031] In the process of filling the deep trench based on a metal filling process to form the deep trench metal isolation structure, the first through hole is collaboratively filled to form a metal interconnection structure;

[0032] After forming the first metal interconnect structure, a second metal layer is formed on the filling dielectric layer.

[0033] Furthermore, the air gap in the deep trench isolation structure is located in the deep trench metal isolation structure.

[0034] On the other hand, the present application further provides a semiconductor structure, which is manufactured based on the method for manufacturing a semiconductor structure as described in any one of the above items; the semiconductor structure comprises:

[0035] substrate;

[0036] a doped buried layer embedded in the substrate;

[0037] a shallow trench isolation structure exposed on the surface of the substrate;

[0038] a gate located on the substrate;

[0039] a barrier layer covering the surface of the gate and the surface of the substrate;

[0040] a first dielectric layer stacked on the barrier layer;

[0041] a first metal layer located on the first dielectric layer;

[0042] a deep trench, the deep trench penetrating the first dielectric layer, the barrier layer, the shallow trench isolation structure, and extending into the substrate;

[0043] A deep trench isolation structure is filled in the deep trench, and the deep trench isolation structure and the doped buried layer are used to isolate adjacent device modules.

[0044] On the other hand, the present application also provides a semiconductor device comprising the semiconductor structure described above.

[0045] The implementation of this application has the following beneficial effects:

[0046] The present application places the deep trench formation step in the back-end process, specifically in the preparation process of the intermediate metal layer after the first metal layer is formed. Compared with forming the deep trench in the front-end process, it can greatly reduce the adverse effects on the morphology and performance of the device layer, and can also greatly avoid wafer warping and lattice damage caused by thermal stress changes in the front-end process, thereby improving the overall morphology accuracy and performance reliability of the semiconductor structure obtained; in addition, the preparation method does not change the structure of the original semiconductor structure, simplifies the process steps to a certain extent, and can also be prepared using the equipment in the original process, which facilitates the integration of the various process steps of the preparation method into the original equipment process, reduces the development difficulty, and is conducive to reducing the preparation cost and improvement cost; the preparation method is applied to the preparation process of BCD devices, which can greatly simplify the preparation process, reduce the preparation cost, and improve the preparation yield of BCD devices and their device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] Figure 1 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0049] Figure 2 A flow chart of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0050] Figure 3 A schematic cross-sectional view of an initial semiconductor structure provided in an embodiment of the present application;

[0051] Figure 4 A schematic cross-sectional view of another initial semiconductor structure provided in an embodiment of the present application;

[0052] Figure 5 A flow chart of a method for forming an initial semiconductor structure provided in an embodiment of the present application;

[0053] Figure 6 for Figure 1 A schematic cross-sectional view of a semiconductor structure obtained by the preparation method;

[0054] Figure 7 for Figure 2 A schematic cross-sectional view of a semiconductor structure obtained by the preparation method;

[0055] Figure 8 for Figure 6 Flowchart of a method for forming a second metal layer;

[0056] Figure 9 for Figure 7 Flowchart of a method for forming a second metal layer;

[0057] Figure 10 for Figure 6 Flowchart of a method for forming a medium-depth trench;

[0058] Figure 11 for Figure 7 Flowchart of a method for forming a medium-depth trench;

[0059] Figure 12 for Figure 7 A flow chart of a method for forming a medium-depth trench metal isolation structure;

[0060] Figure 13 for Figure 7Flow chart of method for forming middle doped structure

[0061] Figure 14 Cross-sectional view of semiconductor structure made in other alternative embodiment.

[0062] Wherein, the reference signs are:

[0063] 1-device layer, 11-substrate layer, 12-epitaxial layer, 13-doped buried layer, 14-shallow trench isolation structure, 15-gate, 16-barrier layer, 2-first dielectric layer, 21-second via hole, 22-contact structure, 3-first metal layer, 31-isolation layer, 4-wiring layer, 41-third metal layer, 42-third dielectric layer, 43-second metal interconnection structure, 5-deep trench, 6-deep trench isolation structure, 61-filling dielectric layer, 610-first via hole, 611-first metal interconnection structure, 612-initial filling dielectric layer, 62-deep trench metal isolation structure, 63-doped structure, 7-gas gap, 8-second dielectric layer, 9-second metal layer, 91-second initial metal layer. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0065] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific object or a sequence order. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or server including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0066] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that the depth direction of an element or layer is the direction perpendicular to the surface of the element or layer, and the direction of the cross-section of an element or layer is the direction parallel to the surface of the element or layer. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. When discussing a second element, component, region, layer or section, it does not necessarily mean that the first element, component, region, layer or section must be present.

[0067] In response to at least one of the technical problems that the formation of deep trenches in the existing front-end process will have an adverse effect on the device, and the process integration is difficult and the improvement cost is high, the embodiments of the present application provide a semiconductor structure, a preparation method and a semiconductor device, the semiconductor device includes the semiconductor structure, and the semiconductor structure is prepared based on the preparation method of the semiconductor structure; first, an initial semiconductor structure is provided, the initial semiconductor structure includes a substrate, a doped buried layer embedded in the substrate, a shallow trench isolation structure exposed on the surface of the substrate, a gate located on the substrate, a barrier layer covering the gate surface and the substrate surface, a first dielectric layer stacked on the barrier layer and a first metal layer located on the first dielectric layer; then, in the preparation process of the intermediate metal layer after preparing the first metal layer, a deep trench is formed on the initial semiconductor structure, the deep trench penetrates the first dielectric layer, the barrier layer, the shallow trench isolation structure and then extends into the substrate; then, the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure and the doped buried layer are used to isolate adjacent device modules.

[0068] The preparation method places the deep groove formation step in the back-end process, specifically after the first metal layer formation step. The first metal layer can be the first metal layer formed in the back-end process or the intermediate metal layer located at the top of at least one intermediate metal layer, thereby effectively avoiding the adverse effects of the deep grooves formed in the front-end process on the device performance, and can also greatly avoid the wafer warping caused by the deep grooves undergoing more thermal processes in the front-end process, further improving the structural accuracy and device performance; and, the preparation method can simplify the process steps to a certain extent without changing the structure of the original semiconductor structure, and can also use the equipment in the original process for preparation, so as to facilitate the integration of the various process steps of the preparation method into the original equipment process, reduce the development difficulty, and thus help reduce the preparation cost and improvement cost.

[0069] The following is combined with Figures 1-14 The preparation method of the semiconductor structure of the embodiment of the present application is introduced in detail.

[0070] First, see Figure 1 and Figure 2 , providing an initial semiconductor structure.

[0071] like Figure 3 As shown, the initial semiconductor structure includes a substrate, a doped buried layer 13 embedded in the substrate, a shallow trench isolation structure 14 exposed on the surface of the substrate, a gate 15 located on the substrate, a barrier layer 16 covering the surface of the gate 15 and the surface of the substrate, a first dielectric layer 2 stacked on the barrier layer 16, and a first metal layer 3 located on the first dielectric layer 2.

[0072] Among them, the substrate includes a substrate layer 11 and an epitaxial layer 12 located on the substrate layer 11, the doped buried layer 13 is embedded at the interface between the substrate layer 11 and the epitaxial layer 12, the shallow trench isolation structure 14 is filled in the epitaxial layer 12, and the shallow trench isolation structure 14 is exposed on the surface of the epitaxial layer 12, the gate 15 is located on the epitaxial layer 12, and the barrier layer 16 covers the surface of the gate 15, the surface of the epitaxial layer 12 and the surface of the shallow trench isolation structure 14, so that the entire device layer 1 including the substrate, the doped buried layer 13, the shallow trench isolation structure 14, the gate 15 and the barrier layer 16 is isolated from the outside, specifically, forming good isolation between the first dielectric layer 2 and the first metal layer 3 above in the non-desired area, which is beneficial to improving the performance stability of the semiconductor structure, and can also protect the non-processing area in the subsequent process, which is beneficial to improving the preparation accuracy of the semiconductor structure.

[0073] like Figure 3As shown, the first dielectric layer 2 is a first dielectric layer directly covering the device layer 1 of the semiconductor structure, i.e. an Inter-Layer Dielectric (ILD) between the bottommost first metal layer and the device layer 1 in the final semiconductor device, and has at least one contact structure 22 (contact) penetrating therethrough, and the contact structure 22 penetrates the barrier layer 16, so that each contact structure 22 can be used to realize the electrical connection of the polysilicon gate 15, the source and the drain in the device layer 1 respectively. Correspondingly, the first dielectric layer 2 is used to isolate each contact structure 22 to prevent crosstalk between the contact structures 22.

[0074] In addition, the metal material used in the electrical connection structure between the contact structure 22 and the adjacent layer structure such as the first metal interconnection structure 611 formed subsequently can optionally include tungsten, which has good electrical conductivity and can accurately control the thickness during the preparation process by chemical vapor deposition or atomic layer deposition, thereby improving the preparation yield.

[0075] In some exemplary embodiments, as shown in FIG. 1, the first metal layer 3 is located on the first dielectric layer 2 and directly contacts the first dielectric layer 2 to realize direct contact electrical connection. At this time, the first metal layer 3 is the bottommost first metal layer in the final semiconductor structure, and the first metal layer 3 is exposed at the top end of the initial semiconductor structure in the current process to perform the formation step of the deep trench 5 after the deposition and etching step of the first metal layer 3. Figure 3 In some exemplary embodiments, as shown in FIG. 1, the first metal layer 3 is located on the first dielectric layer 2 and directly contacts the first dielectric layer 2 to realize direct contact electrical connection. At this time, the first metal layer 3 is the bottommost first metal layer in the final semiconductor structure, and the first metal layer 3 is exposed at the top end of the initial semiconductor structure in the current process to perform the formation step of the deep trench 5 after the deposition and etching step of the first metal layer 3.

[0076] Figure 4 In some exemplary embodiments, as shown in FIG. 1, the first metal layer 3 is located on the first dielectric layer 2 and directly contacts the first dielectric layer 2 to realize direct contact electrical connection. At this time, the first metal layer 3 is the bottommost first metal layer in the final semiconductor structure, and the first metal layer 3 is exposed at the top end of the initial semiconductor structure in the current process to perform the formation step of the deep trench 5 after the deposition and etching step of the first metal layer 3.

[0077] ​In this way, placing the step of forming the deep trench 5 after the step of forming the first metal layer or any intermediate metal layer can effectively avoid the adverse effects of steps such as forming the deep trench 5 in the front-end process on the device performance, and can be directly inserted into the original back-end process steps, simplifying the process steps, and not disrupting the original equipment process. The process integration difficulty is low, which is conducive to reducing preparation and improvement costs.

[0078] Specifically, if Figure 5 As shown, in some exemplary embodiments, the initial semiconductor structure can be manufactured by the following steps:

[0079] providing a device layer 1;

[0080] forming a first dielectric layer 2 on the device layer 1;

[0081] A second through hole 21 is formed in the first dielectric layer 2 and filled with metal material to form a contact structure 22;

[0082] A first metal layer 3 is formed on the first dielectric layer 2 having the contact structure 22 formed thereon; the first metal layer 3 is electrically connected to the contact structure 22 .

[0083] Among them, the second through hole 21 penetrates the barrier layer 16 so that one end of the contact structure 22 can be electrically connected to the device layer 1, and the contact structure 22 specifically contacts the epitaxial layer 12, or contacts the gate 15, so that the electrical connection between the first metal layer 3 and the device layer 1 is achieved through the contact structure 22; and in the process of forming the first metal layer 3, a whole layer of metal material can be first deposited to form a first initial metal layer, and then the first initial metal layer can be patterned and etched to form a first metal layer 3 with a desired pattern.

[0084] The first metal layer 3 may be the first metal layer; or the first metal layer 3 may be an intermediate metal layer, and at least one wiring layer 4 may be provided between the first dielectric layer 2 and the first metal layer 3. Then, forming the first metal layer 3 on the first dielectric layer 2 having the contact structure 22 formed thereon includes:

[0085] forming at least one wiring layer 4 on the first dielectric layer 2 having the contact structure 22 formed thereon;

[0086] A first metal layer 3 is formed on top of at least one wiring layer 4 .

[0087] At this time, the first metal layer 3 is electrically connected to the contact structure 22 through at least one wiring layer 4, specifically through the second metal interconnection structure 43 and the third metal layer 41 in the wiring layer 4 to achieve electrical connection with the contact structure 22, and finally achieve electrical connection between the first metal layer 3 and the device layer 1.

[0088] Next, see Figure 1and Figure 2 During the preparation of the intermediate metal layer after the first metal layer 3 is prepared, a deep trench 5 is formed on the initial semiconductor structure.

[0089] The deep trench 5 extends into the substrate after passing through the first dielectric layer 2, the barrier layer 16, and the shallow trench isolation structure 14; further, the deep trench 5 extends into the substrate layer 11 after passing through the first dielectric layer 2, the barrier layer 16, the shallow trench isolation structure 14, and the epitaxial layer 12; in addition, when there is at least one wiring layer 4 in the initial semiconductor structure, the deep trench 5 extends into the substrate layer 11 after passing through at least one third dielectric layer 42, the first dielectric layer 2, the barrier layer 16, the shallow trench isolation structure 14, and the epitaxial layer 12; the deep trench 5 is formed after the formation step of the first metal layer 3 at the top in the current process, which can effectively reduce the influence of the formation of the deep trench 5 in the front-end process on the morphology and performance of the semiconductor structure, greatly improve the preparation yield and preparation accuracy of the semiconductor structure, and is conducive to improving the device performance of the semiconductor structure.

[0090] Specifically, the longitudinal depth of the deep trench 5 in the substrate is 20 μm to 40 μm, that is, the longitudinal depth of the subsequently formed deep trench isolation structure 6 in the substrate is 20 μm to 40 μm. The longitudinal depth in the substrate here refers to the total length of the deep trench 5 in the epitaxial layer 12 and the substrate layer 11, and the deep trench 5 penetrates the shallow trench isolation structure 14 in the epitaxial layer 12, that is, the longitudinal depth is specifically the total longitudinal length of the deep trench 5 in the shallow trench isolation structure 14, the portion of the epitaxial layer 12 below the shallow trench isolation structure 14, and the substrate layer 11; it can be understood that the longitudinal depth of the deep trench 5 in the substrate can be 20 μm to 40 μm. any point value in 40μm; illustratively, the longitudinal depth of the deep trench 5 in the substrate can be 20μm, 22μm, 25μm, 27μm, 30μm, 35μm, 40μm, etc.; this is beneficial to controlling the longitudinal depth of the subsequently filled deep trench isolation structure 6, while improving the isolation effect, reducing crosstalk, and improving the device performance of the manufactured semiconductor structure; in some exemplary embodiments, the longitudinal depth of the deep trench 5 in the substrate is 25μm to 35μm; in addition, in some optional embodiments, the total longitudinal depth of the deep trench 5 in the substrate and the barrier layer 16 is 20μm to 40μm.

[0091] Next, see Figure 1 and Figure 2 , filling the deep trench 5 to form a deep trench isolation structure 6; the deep trench isolation structure 6 and the doped buried layer 13 are used to isolate adjacent device modules.

[0092] Specifically, the device module may include a partial functional module in a semiconductor device, or may also be a completed semiconductor device; Figure 6 and Figure 7As shown, the doped buried layer 13 is connected to the deep trench isolation structure 6, and the end of the deep trench isolation structure 6 extending in the substrate is located below the doped buried layer 13. The deep trench isolation structure 6 and the doped buried layer 13 are used together to isolate adjacent device modules, which can effectively improve the isolation reliability and is conducive to improving the stability of device performance.

[0093] Specifically, if Figure 7 As shown, in some exemplary embodiments, the deep trench isolation structure 6 completely fills the deep trench 5, that is, no air gap 7 is formed in the deep trench isolation structure 6; and as shown in FIG. Figure 6 As shown, in other exemplary embodiments, the deep trench isolation structure 6 has a closed air gap 7, which can release thermal stress in subsequent back-end processes, which is beneficial to maintaining the morphology accuracy of the semiconductor structure and improving the device performance of the semiconductor structure.

[0094] Specifically, if Figure 1 and Figure 2 As shown, in the process of forming the deep trench isolation structure 6, a filling dielectric layer 61 is formed which is stacked on the initial semiconductor structure and covers at least the wall of the deep trench 5. The filling dielectric layer 61 area located in the deep trench 5 in the filling dielectric layer 61 is reused as the deep trench isolation structure 6, and specifically can be reused as at least part of the deep trench isolation structure 6. In some exemplary embodiments, a whole layer of initial filling dielectric layer 612 can be deposited on the first metal layer 3 first, and the initial filling dielectric layer 612 covers the first dielectric layer 2 and the first metal layer 3. At the same time, part of the dielectric material in the initial filling dielectric layer 612 is filled in the deep trench 5 and covers at least the wall of the deep trench 5. Then, through planarization treatment, the initial filling dielectric layer 612 can be thinned to form a filling dielectric layer 61. A part of the remaining filling dielectric layer 61 covers the first dielectric layer 2 and the first metal layer 3, and the other part fills and covers at least the wall of the deep trench 5. The material of the filling dielectric layer 61 can optionally include insulating materials such as silicon dioxide to improve the isolation reliability of the device module.

[0095] Moreover, placing the step of forming the deep trench isolation structure 6 after the deposition and etching steps of the first metal layer 3 allows the dielectric layer covering the deep trench isolation structure 6 and the dielectric layer covering the first metal layer 3 in the original process to be shared. Accordingly, the shared dielectric layer (including the filling dielectric layer 61, or including the filling dielectric layer 61 and the second dielectric layer 8) can be completed through one deposition and one polishing, which effectively simplifies the process steps, reduces the preparation cost, and also facilitates reducing the difficulty of process integration and saving improvement costs.

[0096] Specifically, if Figure 8 and Figure 9As shown, after filling the deep trench 5 and forming the deep trench isolation structure 6, specifically after forming the initial filling dielectric layer 612, the preparation method further includes:

[0097] A first through hole 610 is formed penetrating the filling dielectric layer 61 ; the first through hole 610 exposes the metal layer adjacent to the filling dielectric layer 61 ;

[0098] A first metal interconnect structure 611 is filled in the first through hole 610; the first metal interconnect structure 611 is used to electrically connect to the metal layer of the adjacent filled dielectric layer 61;

[0099] A second metal layer 9 is formed on the filling dielectric layer 61 ; the second metal layer 9 is electrically connected to the first metal interconnect structure 611 .

[0100] The second metal layer 9 is electrically connected to the adjacent metal layer below through the first metal interconnect structure 611, thereby achieving electrical connection between the bottom device layer 1 and the first metal layer and the second metal layer 9 through layer-by-layer connection; in some exemplary embodiments, in the process of forming the second metal layer 9, metal material can be first deposited to form an entire layer of second initial metal layer 91, and then the second initial metal layer 91 can be patterned and etched to form a second metal layer 9 with a desired pattern.

[0101] After the deep trench isolation structure 6 is formed, specifically after the second metal layer 9 is formed, the second metal layer 9 can be used as the top metal layer in the final semiconductor structure, and then the packaging process of the semiconductor structure is carried out; or, the second metal layer 9 can be used as the third metal layer 41 in the next wiring layer 4, and at least one wiring layer 4 is continued to be formed, until the top metal layer is formed on the topmost wiring layer 4, and then the packaging process of the semiconductor structure is carried out.

[0102] Specifically, if Figure 6 As shown, in some exemplary embodiments, the region of the filling dielectric layer 61 located in the deep trench 5 is used as the entire deep trench isolation structure 6. In the preparation process, through deposition and planarization treatment, the following can be obtained: Figure 1 The semiconductor structure shown uses the region of the filling dielectric layer 61 located in the deep trench 5 as the entire deep trench isolation structure 6 .

[0103] Specifically, if Figure 10 As shown, in the process of preparing the semiconductor structure in which the area of ​​the filling dielectric layer 61 located in the deep trench 5 serves as the entire deep trench isolation structure 6, forming the deep trench 5 on the initial semiconductor structure includes:

[0104] After forming the first metal layer 3, an isolation layer 31 is formed on the first metal layer 3; the isolation layer 31 covers the first metal layer 3 and the first dielectric layer 2;

[0105] A deep trench 5 is etched on the initial semiconductor structure with the isolation layer 31 to form a deep trench 5 ; the deep trench 5 penetrates the isolation layer 31 , the first dielectric layer 2 , the barrier layer 16 and the shallow trench isolation structure 14 and then extends into the substrate.

[0106] Among them, the material of the isolation layer 31 is silicon oxygen-rich silicon oxide (SRO), which can be formed on the first metal layer 3 by chemical vapor deposition. In the subsequent deep trench 5 etching process, the isolation layer 31 can effectively isolate the first metal layer 3 and the photoresist deposited on the surface of the isolation layer 31, preventing the first metal layer 3 and the photoresist from direct contact. The isolation layer 31 can also protect the first metal layer 3, preventing the metal material of the first metal layer 3 from being bombarded during the deep trench 5 etching process and damaging the first metal layer 3, which is beneficial to improving the preparation yield and the performance stability of the obtained semiconductor structure.

[0107] During the etching process of the deep trench 5, photoresist is coated on the isolation layer 31, and etched after exposure to form a process window corresponding to the morphology of the deep trench 5 in the photoresist. By adjusting the process parameters such as the duty cycle, etching rate and etching selectivity of the photolithography process, the position and size of the deep trench 5 are precisely controlled. The etching has good controllability and high precision, which is conducive to improving the etching accuracy in the process of transferring the trench morphology to the initial semiconductor structure, improving the position accuracy and morphology accuracy of the deep trench 5, and ultimately helping to improve device performance. At the same time, the photolithography process has low complexity and high etching rate, which is conducive to improving preparation efficiency.

[0108] Specifically, if Figure 10 As shown in FIG, in the process of preparing a semiconductor structure in which the area in the deep trench 5 in the filling dielectric layer 61 is used as the entire deep trench isolation structure 6, after the deep trench 5 is formed on the initial semiconductor structure having the first metal layer 3, the deep trench 5 specifically penetrates the isolation layer 31, the first dielectric layer 2, the barrier layer 16, the shallow trench isolation structure 14 and the epitaxial layer 12, and extends into the substrate layer 11; and as shown in FIG. Figure 8 As shown, in the process of forming the filling dielectric layer 61, the filling dielectric layer 61 is specifically stacked on the isolation layer 31 and filled in the deep trench 5 to at least cover the groove wall of the deep trench 5, and the area located in the deep trench 5 is reused as the entire deep trench isolation structure 6; in addition, the step of planarizing the initial filling dielectric layer 612 to form the filling dielectric layer 61 can be performed before forming the first through hole 610, or after forming the first through hole 610, or before or after forming the first metal interconnection structure 611, as long as it is performed before the step of forming the second metal layer 9.

[0109] like Figure 6As shown, the first via hole 610 specifically penetrates the isolation layer 31 and the filling medium layer 61 on the first metal layer 3, so that the first via hole 610 exposes the first metal layer 3, and after the formation of the deep trench isolation structure 6, the first metal interconnection structure 611 filled in the first via hole 610 is electrically connected with the first metal layer 3 through the filling medium layer 61 and the isolation layer 31, which improves the effectiveness and stability of the electrical connection.

[0110] Specifically, in some preferred embodiments, during the formation of the deep trench isolation structure 6, the filling medium layer 61 is formed on the initial semiconductor structure and covers at least the sidewall of the deep trench 5 by high-density plasma deposition (HDP), specifically, the high-density plasma deposition process is used in the process of forming the initial filling medium layer 612; the deposition-etch-deposition cycle process is used in the preparation process, that is, etching bombardment is performed immediately after the initial deposition is completed and the hole filling has not been pinched off, to reopen the entrance of the deep trench 5, and then deposition is performed again to complete the filling of the entire deep trench 5, which is suitable for filling deep trenches 5 with high aspect ratio and can achieve good hole filling effect, thereby better controlling the morphology of the filling medium layer 61; in addition, the isolation layer 31 is covered on the first metal layer 3, which can play a protective role in the etching process of the high-density plasma deposition process, preventing the bombardment of the metal material of the first metal layer 3, effectively preventing damage to the first metal layer 3 during the formation of the deep trench isolation structure 6, and improving the preparation precision and structural reliability of the prepared semiconductor structure.

[0111] Specifically, the air gap 7 can be formed synchronously during the formation of the filling medium layer 61 by high-density plasma deposition, specifically, the air gap 7 is formed synchronously in the deep trench 5 during the formation of the initial filling medium layer 612 by high-density plasma deposition; the region of the filling medium layer 61 in the deep trench 5 is reused as the entire deep trench isolation structure 6, and in the case that the air gap 7 exists in the region of the filling medium layer 61 in the deep trench 5, the position of the air gap 7 in the deep trench 5 is determined based on the sputtering rate and deposition rate of the high-density plasma deposition, so that the position and morphology of the air gap 7 are better regulated by the high-density plasma deposition process, which is beneficial to releasing thermal stress when experiencing thermal processes in subsequent processes, reducing the adverse effects on the morphology of the deep trench isolation structure 6 and the entire semiconductor structure, and improving the device performance of the semiconductor structure.

[0112] As shown in FIG. 6, the semiconductor structure 1 is formed by the following steps: Figure 6As shown, in the semiconductor structure in which the region of the filling dielectric layer 61 in the deep trench 5 is taken as the whole deep trench isolation structure 6, the air gap 7 at least longitudinally spans the substrate layer 11, the epitaxial layer 12, the barrier layer 16 and the first dielectric layer 2, that is, one end of the air gap 7 away from the substrate layer 11 is located below the upper surface of the first dielectric layer 2, while the other end of the air gap 7 can specifically extend into the substrate layer 11, which can release thermal stress in subsequent back-end processes, and is beneficial to maintaining the topography precision of the semiconductor structure and improving the device performance of the semiconductor structure.

[0113] Specifically, as shown in the drawings, Figure 7 In some other exemplary embodiments, the deep trench isolation structure 6 further includes a deep trench metal isolation structure 62 and a region of the partial filling dielectric layer 61 in the deep trench 5, the deep trench metal isolation structure 62 is filled in the region of the partial filling dielectric layer 61 in the deep trench 5, that is, the partial dielectric material of the filling dielectric layer 61 in the deep trench 5 covers the sidewall of the deep trench 5 and is reused as part of the deep trench isolation structure 6, and the other part of the deep trench isolation structure 6 is formed by the deep trench metal isolation structure 62; in the preparation process, the filling dielectric layer 61 is first formed, and then the metal material is further deposited in the deep trench 5 with the filling dielectric layer 61 to form the deep trench metal isolation structure 62, so as to obtain the semiconductor structure with the deep trench metal isolation structure 62 and the partial filling dielectric layer 61 as the deep trench isolation structure 6, as shown in the drawings. Figure 2 The deep trench isolation structure 6 formed by the deep trench metal isolation structure 62 and the partial filling dielectric layer 61 cooperates with each other to play a good isolation role.

[0114] Specifically, as shown in the drawings, Figure 11 In the preparation method of the semiconductor structure with the deep trench metal isolation structure 62, the initial semiconductor structure further includes a second dielectric layer 8 covering the first metal layer 3, and the second dielectric layer 8 is specifically stacked above the first dielectric layer 2 and covers the first metal layer 3. Correspondingly, the deep trench 5 formed in the initial semiconductor structure specifically extends into the substrate from the second dielectric layer 8, the first dielectric layer 2, the barrier layer 16, the shallow trench isolation structure 14, and the epitaxial layer 12; the second dielectric layer 8 can be used as an isolation dielectric between different regions of the first metal layer 3 in subsequent process steps, and can also be used as part of the isolation dielectric between the first metal layer 3 and the second metal layer 9 adjacent to the upper layer, and together with the filling dielectric layer 61 stacked above the second dielectric layer 8 as an inter-metal dielectric (IMD), which further improves the isolation effect.

[0115] Specifically, as shown in the drawings, Figure 12As shown, in some exemplary embodiments, in the method for preparing the semiconductor structure having the deep trench metal isolation structure 62, the step of filling the deep trench 5 to form the deep trench isolation structure 6 includes:

[0116] An initial filling dielectric layer 612 is formed on the second dielectric layer 8; the initial filling dielectric layer 612 covers the second dielectric layer 8 and covers the sidewalls and bottom wall of the deep trench 5;

[0117] The initial filling dielectric layer 612 region on the bottom wall of the deep trench 5 is etched back until the bottom wall of the deep trench 5 is exposed. After the etch-back process, the remaining initial filling dielectric layer 612 forms a filling dielectric layer 61 that is stacked on the initial semiconductor structure and covers at least the wall of the deep trench 5.

[0118] The deep trench 5 is filled based on a metal filling process to form a deep trench metal isolation structure 62 to obtain a deep trench isolation structure 6 ; the deep trench isolation structure 6 includes the deep trench metal isolation structure 62 and a filling dielectric layer 61 covering the wall of the deep trench 5 .

[0119] In the process of forming the initial filling dielectric layer 612, the initial filling dielectric layer 612 is formed into a thin film and covers the surface of the second dielectric layer 8 and the side walls and bottom walls of the deep trench 5 through a deposition process, and the preparation is simple and efficient. At this time, the initial filling dielectric layer 612 in the deep trench 5 causes the diameter of the deep trench 5 to be reduced to a certain extent, and the longitudinal depth of the deep trench 5 is also reduced to a certain extent.

[0120] Afterwards, by etching back, the dielectric material of part of the initial filling dielectric layer 612 on the bottom wall of the deep trench 5 is removed, exposing the bottom wall of the deep trench 5, that is, exposing the substrate layer 11 material at the bottom end of the deep trench 5, so that the bottom end of the deep trench metal isolation structure 62 formed subsequently can contact the substrate layer 11 material; and, in the etching back process, the dielectric material on the bottom wall of the deep trench 5 is removed, and the dielectric material covering the surface of the second dielectric layer 8 is simultaneously thinned to the desired thickness, that is, the remaining initial filling dielectric layer 612 forms a filling dielectric layer 61 stacked on the second dielectric layer 8 and covering the sidewalls of the deep trench 5, so as to effectively control the morphology of the semiconductor structure.

[0121] Specifically, if Figure 13 As shown, in some exemplary embodiments, before filling the deep trench 5 based on a metal filling process to form a deep trench metal isolation structure 62 to obtain a deep trench isolation structure 6, the preparation method further includes:

[0122] After the etch-back process, ion implantation is performed at the bottom of the deep trench 5 to form a doping structure 63 .

[0123] At this time, in the state where the substrate layer 11 of the bottom wall of the deep trench 5 is exposed, ion implantation is performed at the bottom of the deep trench 5, specifically, ion implantation is performed with a relatively light doping concentration, which is beneficial to improving the breakdown voltage, and thus beneficial to improving the device performance of the semiconductor structure; in addition, the morphology of the doping structure 63 is smooth, and can be circular, elliptical or arc-shaped, and the charge is relatively concentrated, which is beneficial to the dispersion of the electric field.

[0124] Specifically, if Figure 9 As shown, in some exemplary embodiments, before filling the deep trench 5 based on a metal filling process to form a deep trench metal isolation structure 62 to obtain a deep trench isolation structure 6, the preparation method further includes:

[0125] forming a first through hole 610 penetrating the filling dielectric layer 61 and the second dielectric layer 8;

[0126] In the process of filling the deep trench 5 based on the metal filling process to form the deep trench metal isolation structure 62, the first through hole 610 is cooperatively filled to form a first metal interconnection structure;

[0127] After forming the first metal interconnect structure 611 , a second metal layer 9 is formed on the filling dielectric layer 61 .

[0128] Among them, in some optional embodiments, the formation of the first through hole 610 can be specifically after the formation of the doping structure 63; after the first through hole 610 penetrates the second dielectric layer 8 and the filling dielectric layer 61, the surface of the first metal layer 3 is exposed, so that the first metal interconnection structure 611 is electrically connected to the first metal layer 3 after passing through the filling dielectric layer 61 and the second dielectric layer 8; at the same time, the first metal interconnection structure 611 and the deep trench metal isolation structure 62 use the same metal material, for example, both can be tungsten metal, and before filling the deep trench 5 based on the metal filling process, the first through hole 610 exposes the first metal layer 3 and covers the portion of the filling dielectric layer 6 on the sidewall of the deep trench 5. 1 exposes the substrate layer 11. Then, based on the metal filling process, while the deep trench metal isolation structure 62 is filled in the deep trench 5, the first through hole 610 is also filled to form the first metal interconnection structure 611. This allows the formation of the deep trench metal isolation structure 62 and the formation of the first metal interconnection structure 611 to share the same metal filling process, thereby simplifying the process steps. In other words, the process steps of the deep trench metal isolation structure 62 are directly integrated into the original process of preparing the first metal interconnection structure 611. The original process equipment for preparing the first metal interconnection structure 611 can be used, which reduces the difficulty of process integration and helps reduce the improvement cost and overall preparation cost.

[0129] Specifically, if Figure 7As shown, in some exemplary embodiments, when the deep trench isolation structure 6 includes a deep trench metal isolation structure 62 , the deep trench metal isolation structure 62 completely fills the deep trench 5 , that is, no air gap 7 exists in the deep trench metal isolation structure 62 .

[0130] Specifically, in other exemplary embodiments, during the process of filling the deep trench metal isolation structure 62, the air gap 7 is also synchronously formed in the deep trench 5; then, when the deep trench isolation structure 6 includes the deep trench metal isolation structure 62 and the air gap 7 exists in the deep trench isolation structure 6, the air gap 7 is enclosed in the deep trench metal isolation structure 62; wherein, in some exemplary embodiments, one end of the air gap 7 is located in the substrate layer 11, spanning the substrate layer 11, the epitaxial layer 12, the barrier layer 16, the first dielectric layer 2 and the second dielectric layer 8; in other exemplary embodiments, one end of the air gap 7 is located in the substrate layer 11, spanning the substrate layer 11, the epitaxial layer 12, the barrier layer 16 and the first dielectric layer 2, and the other end of the air gap 7 is located below the first metal layer 3, that is, the height of the air gap 7 does not exceed the bottom surface of the first metal layer 3; the air gap 7 facilitates the release of thermal stress in subsequent processes, improving the preparation accuracy and device performance of the semiconductor structure.

[0131] Optionally, in an embodiment of the present application, the metal material used for the first metal layer 3 and the second metal layer 9 includes aluminum metal, that is, the preparation method of the semiconductor structure is suitable for aluminum process, which can greatly improve the yield of the aluminum process.

[0132] On the other hand, the present application also provides a semiconductor structure, which is manufactured based on the preparation method of the semiconductor structure as described above, so that the semiconductor structure manufactured based on the preparation method of the semiconductor structure can have good morphological accuracy, reduce the risk of wafer warping during the preparation process, and is beneficial to improving the device performance of the semiconductor structure; the semiconductor structure includes a substrate, a doped buried layer 13 embedded in the substrate, a shallow trench isolation structure 14 exposed on the surface of the substrate, a gate 15 located on the substrate, a barrier layer 16 covering the surface of the gate 15 and the surface of the substrate, a first dielectric layer 2 stacked on the barrier layer 16, a first metal layer 3 located on the first dielectric layer 2, a deep trench 5 extending to the substrate after penetrating the first dielectric layer 2, the barrier layer 16, and the shallow trench isolation structure 14, and a deep trench isolation structure 6 filled in the deep trench 5, the deep trench isolation structure 6 and the doped buried layer 13 are used to isolate adjacent device modules.

[0133] On the other hand, the present application provides a semiconductor device, including the semiconductor structure as described above, with high structural precision and excellent performance; the semiconductor device includes at least one of a diode, a bipolar junction transistor (BJT), a field effect transistor (MOSFET / JFET), an insulated gate bipolar diode (IGBT), a complementary metal oxide semiconductor (CMOS), a high-voltage power field effect transistor (DMOS), a thyristor (SCR) and a BCD device, wherein the BCD device combines the three processes of BJT, CMOS and DMOS, has high integration, and can achieve high efficiency and low power consumption; the semiconductor device can be used in any electronic product or equipment such as mobile phones, tablet computers, laptops, netbooks, game consoles, televisions, VCDs, DVDs, navigation systems, cameras, camcorders, voice recorders, MP3s, MP4s, PSPs, etc., and can also be used in intermediate products of electronic equipment to improve the working performance of electronic equipment.

[0134] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing an initial semiconductor structure; The initial semiconductor structure includes a substrate, a doped buried layer embedded in the substrate, a shallow trench isolation structure exposed on the surface of the substrate, a gate located on the substrate, a barrier layer covering the surface of the gate and the surface of the substrate, a first dielectric layer stacked on the barrier layer, and a first metal layer located on the first dielectric layer; During the preparation of the intermediate metal layer after the first metal layer is prepared, forming a deep trench on the initial semiconductor structure; The deep trench penetrates the first dielectric layer, the barrier layer, and the shallow trench isolation structure and then extends into the substrate; The deep trench is filled to form a deep trench isolation structure; the deep trench isolation structure and the doped buried layer are used to isolate adjacent device modules.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The doped buried layer is connected to the deep trench isolation structure, and the end of the deep trench isolation structure extending in the substrate is located below the doped buried layer.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The deep trench isolation structure has a closed air gap therein.

4. The method for preparing a semiconductor structure according to claim 1, wherein: During the process of forming the deep trench isolation structure, a filling dielectric layer is formed which is stacked on the initial semiconductor structure and covers at least the wall of the deep trench; After filling the deep trench to form a deep trench isolation structure, the method further includes: forming a first through hole penetrating the filling dielectric layer; wherein the first through hole exposes a metal layer adjacent to the filling dielectric layer; Filling a first metal interconnection structure in the first through hole; the first metal interconnection structure is used to electrically connect to the metal layer adjacent to the filling dielectric layer; A second metal layer is formed on the filling dielectric layer; the second metal layer is electrically connected to the first metal interconnect structure.

5. The method for preparing a semiconductor structure according to claim 4, wherein: The filling dielectric layer region located in the deep trench in the filling dielectric layer is reused as the deep trench isolation structure.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The longitudinal depth of the deep trench in the substrate is 20 μm to 40 μm.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that The forming of a deep trench on the initial semiconductor structure includes: After forming the first metal layer, forming an isolation layer on the first metal layer; the isolation layer covers the first metal layer and the first dielectric layer; Deep trench etching is performed on the initial semiconductor structure having the isolation layer formed thereon to form the deep trench; the deep trench penetrates the isolation layer, the first dielectric layer, the barrier layer and the shallow trench isolation structure and then extends into the substrate.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 6, wherein: During the process of forming the deep trench isolation structure, a filling dielectric layer is formed by high-density plasma deposition, which is stacked on the initial semiconductor structure and covers at least the walls of the deep trench.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The position of the air gap in the deep trench isolation structure is determined based on the sputtering rate and the deposition rate of the high-density plasma deposition.

10. The method for preparing a semiconductor structure according to any one of claims 1 to 6, wherein: The initial semiconductor structure further includes a second dielectric layer covering the first metal layer; the deep trench penetrates the second dielectric layer, the first dielectric layer, the barrier layer, the shallow trench isolation structure, and then extends into the substrate.

11. The method for preparing a semiconductor structure according to claim 10, wherein: Filling the deep trench to form a deep trench isolation structure includes: forming an initial filling dielectric layer on the second dielectric layer; the initial filling dielectric layer covers the second dielectric layer and covers the sidewalls and bottom wall of the deep trench; Etching back the initial filling dielectric layer region on the bottom wall of the deep trench until the bottom wall of the deep trench is exposed; after the etching back process, the remaining initial filling dielectric layer forms a filling dielectric layer stacked on the initial semiconductor structure and covering at least the wall of the deep trench; The deep trench is filled based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure; the deep trench isolation structure includes the deep trench metal isolation structure and a filling dielectric layer covering the deep trench wall.

12. The method for preparing a semiconductor structure according to claim 11, wherein: Before filling the deep trench based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes: After the etching back process, ion implantation is performed at the bottom of the deep trench to form a doping structure.

13. The method for preparing a semiconductor structure according to claim 11, wherein: Before filling the deep trench based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes: forming a first through hole penetrating the filling dielectric layer and the second dielectric layer; In the process of filling the deep trench based on a metal filling process to form the deep trench metal isolation structure, the first through hole is collaboratively filled to form a metal interconnection structure; After forming the first metal interconnect structure, a second metal layer is formed on the filling dielectric layer.

14. The method for preparing a semiconductor structure according to claim 11, wherein: The air gap in the deep trench isolation structure is located in the deep trench metal isolation structure.

15. A semiconductor structure, characterized in that Prepared based on the method for preparing a semiconductor structure according to any one of claims 1 to 14; The semiconductor structure comprises: substrate; a doped buried layer embedded in the substrate; a shallow trench isolation structure exposed on the surface of the substrate; a gate located on the substrate; a barrier layer covering the surface of the gate and the surface of the substrate; a first dielectric layer stacked on the barrier layer; a first metal layer located on the first dielectric layer; a deep trench, the deep trench penetrating the first dielectric layer, the barrier layer, the shallow trench isolation structure, and extending into the substrate; A deep trench isolation structure is filled in the deep trench, and the deep trench isolation structure and the doped buried layer are used to isolate adjacent device modules.

16. A semiconductor device, characterized in that: Comprising the semiconductor structure as claimed in claim 15.

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