A semiconductor structure, a manufacturing method and a semiconductor device

Abstract

The application discloses a semiconductor structure, a preparation method and a semiconductor device. The semiconductor structure comprises the following steps: providing an initial semiconductor structure; the initial semiconductor structure comprises a device layer, a first dielectric layer on the device layer and at least one first wiring layer between the first dielectric layer and a top metal layer; the top first wiring layer in the at least one first wiring layer comprises a first metal layer, a second dielectric layer covering the first metal layer and a first metal interconnection structure penetrating through the second dielectric layer; after the first metal interconnection structure is formed, a deep trench is formed in the initial semiconductor structure; the deep trench extends to the device layer after penetrating through the at least one first wiring layer and the first dielectric layer; and the deep trench is filled to form a deep trench isolation structure. The application places the formation of the deep trench after the formation of the first metal interconnection structure, reduces the adverse effect on the device layer in the BCD device, simplifies the preparation process of the BCD device and reduces the process integration difficulty and cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to a semiconductor structure, a preparation method and a semiconductor device. Background Art

[0002] Existing deep trench isolation (DTI) technology is primarily integrated with BCD semiconductor devices before forming the interlayer dielectric (ILD) layer in the front-end process, or before or after the shallow trench isolation (STI) process. However, the timing of DTI formation during the front-end process significantly impacts the device layer, negatively impacting device performance. For example, it can easily lead to wafer warpage, and the additional thermal process can easily cause lattice defects. Furthermore, the numerous process steps involved in process improvement make it difficult to integrate the improved process into the existing equipment process, resulting in development difficulties and high manufacturing and improvement costs. Summary of the Invention

[0003] In order to solve the problems of the prior art, the embodiments of the present application provide a semiconductor structure, a preparation method and a semiconductor device. The technical solution is as follows:

[0004] In one aspect, the present application provides a method for preparing a semiconductor structure, comprising:

[0005] Providing an initial semiconductor structure; the initial semiconductor structure includes a device layer, a first dielectric layer located on the device layer, and at least one first wiring layer located on the first dielectric layer, the at least one first wiring layer being located between the first dielectric layer and a top metal layer, the top first wiring layer of the at least one first wiring layer including a first metal layer, a second dielectric layer covering the first metal layer, and a first metal interconnect structure penetrating the second dielectric layer, the first metal interconnect structure being electrically connected to the first metal layer;

[0006] After forming the first metal interconnect structure, forming a deep trench in the initial semiconductor structure; the deep trench penetrates the at least one first wiring layer and the first dielectric layer and extends into the device layer;

[0007] The deep trench is filled to form a deep trench isolation structure; the deep trench isolation structure is used to isolate adjacent device modules.

[0008] Furthermore, the device layer includes a substrate layer, an epitaxial layer located on the substrate layer, a doped buried layer embedded at the interface between the substrate layer and the epitaxial layer, a shallow trench isolation structure exposed on the surface of the epitaxial layer, and a gate located on the epitaxial layer;

[0009] The deep trench penetrates the at least one first wiring layer, the first dielectric layer, the shallow trench isolation structure, and the epitaxial layer and then extends into the substrate layer.

[0010] Furthermore, the doped buried layer is connected to the deep trench isolation structure, and the end of the deep trench isolation structure extending in the substrate layer is located below the doped buried layer;

[0011] The deep trench isolation structure and the doped buried layer are used to isolate adjacent device modules.

[0012] Furthermore, the deep trench isolation structure has a closed air gap.

[0013] Furthermore, during the process of forming the deep trench isolation structure, a filling dielectric layer is formed to at least cover the deep trench wall, and the filling dielectric layer is reused as the deep trench isolation structure.

[0014] Furthermore, the longitudinal depth of the deep trench in the device layer is 20 μm to 40 μm.

[0015] Furthermore, after forming the first metal interconnect structure, forming a deep trench in the initial semiconductor structure includes:

[0016] After forming the first metal interconnect structure, forming a hard mask on the second dielectric layer;

[0017] performing photolithography on the hard mask to form an etching window;

[0018] The remaining hard mask is used as an etch stop layer to perform trench etching on the area exposed by the etching window in the initial semiconductor structure to form the deep trench.

[0019] Furthermore, filling the deep trench to form a deep trench isolation structure includes:

[0020] forming an initial filling dielectric layer on the initial semiconductor structure having the deep trench formed therein; the initial filling dielectric layer is stacked on the initial semiconductor structure and at least covers the wall of the deep trench;

[0021] performing a planarization process on the initial filling dielectric layer so that the remaining initial filling dielectric layer forms a filling dielectric layer that at least covers the wall of the deep trench; during the planarization process, a hard mask covering the second dielectric layer during the formation of the deep trench is removed;

[0022] A second metal layer is formed on the second dielectric layer; the second metal layer is any intermediate metal layer between the first metal layer and the top metal layer, or the second metal layer is the top metal layer; the second metal layer is electrically connected to the first metal interconnect structure.

[0023] Furthermore, during the process of forming the deep trench isolation structure, a filling dielectric layer at least covering the deep trench wall is formed by high-density plasma deposition.

[0024] Furthermore, the position of the air gap in the deep trench isolation structure is determined based on a sputtering rate and a deposition rate of the high-density plasma deposition.

[0025] Furthermore, filling the deep trench to form a deep trench isolation structure includes:

[0026] forming an initial filling dielectric layer on the initial semiconductor structure having the deep trench formed therein; the initial filling dielectric layer is stacked on the initial semiconductor structure and covers the sidewalls and bottom wall of the deep trench;

[0027] Etching back the initial filling dielectric layer region on the bottom wall of the deep trench until the bottom wall of the deep trench is exposed; after the etching back process, the initial filling dielectric layer region located on the initial semiconductor structure is removed, and the remaining initial filling dielectric layer forms a filling dielectric layer that at least covers the wall of the deep trench;

[0028] The deep trench is filled based on a metal deposition process to form a deep trench metal isolation structure to obtain the deep trench isolation structure; the deep trench isolation structure includes the deep trench metal isolation structure and a filling dielectric layer covering the deep trench wall.

[0029] Furthermore, before filling the deep trench based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes:

[0030] After the etching back process, ion implantation is performed at the bottom of the deep trench to form a doping structure.

[0031] Furthermore, before filling the deep trench based on a metal deposition process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes:

[0032] After the filling dielectric layer is formed by etching back, the hard mask covering the second dielectric layer during the process of forming the deep trench is removed.

[0033] Furthermore, filling the deep trench based on a metal deposition process to form a deep trench metal isolation structure includes:

[0034] Depositing a metal material to form a second initial metal layer filling the deep trench and stacked on the second dielectric layer and the first metal interconnect structure, wherein a portion of the second initial metal layer filling the deep trench forms the deep trench metal isolation structure;

[0035] After filling the deep trench based on the metal deposition process to form a deep trench metal isolation structure, the method further includes:

[0036] The portion of the second initial metal layer stacked on the second dielectric layer is patterned and etched to form a second metal layer; the second metal layer is any intermediate metal layer between the first metal layer and the top metal layer, or the second metal layer is the top metal layer; the second metal layer is electrically connected to the deep trench metal isolation structure and the first metal interconnection structure, respectively.

[0037] Furthermore, the air gap in the deep trench isolation structure is enclosed in the deep trench metal isolation structure.

[0038] On the other hand, the present application further provides a semiconductor structure, which is manufactured based on the method for manufacturing a semiconductor structure as described in any one of the above items; the semiconductor structure comprises:

[0039] device layer;

[0040] a first dielectric layer located on the device layer;

[0041] at least one first wiring layer located on the first dielectric layer, the at least one first wiring layer located between the first dielectric layer and a top metal layer, the top first wiring layer of the at least one first wiring layer comprising a first metal layer, a second dielectric layer covering the first metal layer, and a first metal interconnect structure penetrating the second dielectric layer, the first metal interconnect structure being electrically connected to the first metal layer;

[0042] a deep trench, penetrating the at least one first wiring layer and the first dielectric layer and extending into the device layer;

[0043] A deep trench isolation structure is filled in the deep trench, and the deep trench isolation structure is used to isolate adjacent device modules.

[0044] On the other hand, the present application also provides a semiconductor device comprising the semiconductor structure described above.

[0045] The implementation of this application has the following beneficial effects:

[0046] The present application places the step of forming deep trenches in the back-end process, specifically after the step of forming the first metal interconnect structure at the top of at least one first wiring layer. Compared with forming deep trenches in the front-end process, it can greatly reduce the adverse effects on the morphology and performance of the device layer, and can also greatly avoid the wafer warping caused by thermal stress changes in the front-end process, thereby improving the overall morphology accuracy and performance reliability of the manufactured semiconductor structure; in addition, the preparation method does not change the structure of the original semiconductor structure, simplifies the process steps to a certain extent, and can also be prepared using the equipment in the original process, which facilitates the integration of the various process steps of the preparation method into the original equipment process, reduces the development difficulty, and is conducive to reducing the preparation cost and improvement cost; the preparation method is applied to the preparation process of BCD devices, which can greatly simplify the preparation process, reduce the preparation cost, and improve the preparation yield of BCD devices and their device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] Figure 1 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0049] Figure 2 A flow chart of another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0050] Figure 3 A schematic cross-sectional view of an initial semiconductor structure provided in an embodiment of the present application;

[0051] Figure 4 A schematic cross-sectional view of another initial semiconductor structure provided in an embodiment of the present application;

[0052] Figure 5 A flow chart of a method for forming an initial semiconductor structure provided in an embodiment of the present application;

[0053] Figure 6 for Figure 3 a flow chart of a method for forming a top first wiring layer;

[0054] Figure 7 A flowchart of a method for forming a deep trench provided in an embodiment of the present application;

[0055] Figure 8 for Figure 1A schematic cross-sectional view of a semiconductor structure obtained by the preparation method;

[0056] Figure 9 for Figure 2 A schematic cross-sectional view of a semiconductor structure obtained by the preparation method;

[0057] Figure 10 for Figure 8 A flow chart of a method for forming a filling dielectric layer;

[0058] Figure 11 for Figure 9 A flow chart of a method for forming a medium-depth trench isolation structure;

[0059] Figure 12 for Figure 9 A flow chart of a method for forming a doped structure;

[0060] Figure 13 for Figure 9 A flowchart of a method for removing a hard mask during the corresponding semiconductor structure fabrication process;

[0061] Figure 14 for Figure 9 A flow chart of a method for forming a medium-depth trench metal isolation structure;

[0062] Figure 15 for Figure 9 Flowchart of a method for forming a second metal layer.

[0063] Wherein, the accompanying drawings are marked as follows:

[0064] 1-device layer, 11-substrate layer, 12-epitaxial layer, 13-doped buried layer, 14-shallow trench isolation structure, 15-gate, 16-barrier layer, 2-first dielectric layer, 21-first through hole, 22-contact structure, 3-first wiring layer, 31-first metal layer, 32-second dielectric layer, 320-second through hole, 33-first metal interconnection structure, 4-deep trench, 5-deep trench isolation structure, 51-filling dielectric layer, 510-initial filling dielectric layer, 52-deep trench metal isolation structure, 53-doping structure, 6-air gap, 7-hard mask, 71-etching window, 8-second metal layer, 81-second initial metal layer. DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0066] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe specific objects or a sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0067] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that the depth direction of an element or layer is the direction perpendicular to the surface of the element or layer, and the direction of the cross-section of an element or layer is the direction parallel to the surface of the element or layer. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. When discussing a second element, component, region, layer or section, it does not necessarily mean that the first element, component, region, layer or section must be present.

[0068] In response to at least one of the technical problems that deep trenches formed in the front-end process of BCD devices in existing processes have adverse effects on the devices, are difficult to integrate, and have high improvement costs, embodiments of the present application provide a semiconductor structure, a preparation method, and a semiconductor device. The semiconductor device includes the semiconductor structure, and the semiconductor structure is prepared based on the preparation method of the semiconductor structure. First, an initial semiconductor structure is provided. The initial semiconductor structure includes a device layer, a first dielectric layer located on the device layer, and at least one first wiring layer located on the first dielectric layer. The at least one first wiring layer is located between the first dielectric layer and the top metal layer. The top first wiring layer of the at least one first wiring layer includes a first metal layer, a second dielectric layer covering the first metal layer, and a first metal interconnect structure penetrating the second dielectric layer. The first metal interconnect structure is electrically connected to the first metal layer. Then, after forming the first metal interconnect structure, a deep trench is formed in the initial semiconductor structure. The deep trench penetrates the at least one first wiring layer and the first dielectric layer and extends into the device layer. Then, the deep trench is filled to form a deep trench isolation structure. The deep trench isolation structure is used to isolate adjacent device modules.

[0069] The preparation method of the semiconductor structure places the step of forming the deep trench after the formation of the first metal interconnection structure, which can effectively avoid the adverse effects of the formation of the deep trench on the device performance in the front-end process, and can also greatly avoid the wafer warping caused by the deep trench undergoing more thermal processes in the front-end process, further improving the structural accuracy and device performance; and, the preparation method can simplify the process steps to a certain extent without changing the structure of the original semiconductor structure, and can also use the equipment in the original process for preparation, so as to facilitate the integration of the various process steps of the preparation method into the original equipment process, reduce the development difficulty, and thus help to reduce the preparation cost and improvement cost.

[0070] The following is combined with Figures 1-15 The method for preparing the semiconductor structure according to the embodiment of the present application is described in detail.

[0071] First, see Figure 1 and Figure 2 , providing an initial semiconductor structure.

[0072] Specifically, if Figure 3 As shown, the initial semiconductor structure includes a device layer 1, a first dielectric layer 2 located on the device layer 1, and at least one first wiring layer 3 located on the first dielectric layer 2. The device layer 1 includes a substrate layer 11, an epitaxial layer 12 located on the substrate layer 11, a doped buried layer 13 embedded at the interface between the substrate layer 11 and the epitaxial layer 12, a shallow trench isolation structure 14 exposed on the surface of the epitaxial layer 12, and a gate 15 located on the epitaxial layer 12.

[0073] like Figure 3As shown, the first dielectric layer 2 has multiple contact structures 22 (contact) running through it, and each contact structure 22 is used to realize the electrical connection between the polysilicon gate 15, the source and the drain in the device layer 1. The first dielectric layer 2 is specifically a dielectric layer (Inter-Layer Dielectric, ILD) between the bottom metal layer and the device layer 1 in the finally formed semiconductor device, and is used to isolate the contact structures 22 between the polysilicon gate 15, the source and the drain in the device layer 1 to prevent crosstalk.

[0074] At least one first wiring layer 3 is located between the first dielectric layer 2 and the subsequently formed top metal layer. The top first wiring layer 3 in the at least one first wiring layer 3 includes a first metal layer 31, a second dielectric layer 32 covering the first metal layer 31, and a first metal interconnection structure 33 penetrating the second dielectric layer 32. The first metal interconnection structure 33 is electrically connected to the first metal layer 31. Part of the dielectric in the second dielectric layer 32 is the dielectric between different first metal interconnection structures 33 located in the same metal layer, so that the first metal interconnection structures 33 in the same layer are independent of each other to prevent crosstalk. Part of the dielectric in the second dielectric layer 32 is also located between the first metal layer 31 and the adjacent metal layer to isolate the adjacent metal layers.

[0075] The metal material used for the contact structure 22 and the first metal interconnect structure 33 may optionally include tungsten, which has good conductivity and can be precisely controlled in thickness by chemical vapor deposition or atomic layer deposition during the preparation process, thereby improving the preparation yield.

[0076] In addition, when there is a first wiring layer 3 other than the top first wiring layer 3 in the current at least one first wiring layer 3, each first wiring layer 3 other than the top first wiring layer 3 may include a metal layer, a dielectric layer covering the metal layer, and a metal interconnection structure penetrating the dielectric layer, and the metal interconnection structure is electrically connected to the metal layer, wherein the metal layer may be made of the same material as the first metal layer 31, the dielectric layer may be made of the same material as the second dielectric layer 32, and the metal interconnection structure may be made of the same material as the first metal interconnection structure 33. This is only used as a naming distinction to emphasize that the timing of the subsequent formation of the deep trench 4 is after the first metal interconnection structure 33 of the first wiring layer 3 at the top of the current initial semiconductor structure is formed; similarly, in the second wiring layer formed after the subsequent formation of the deep trench isolation structure 5, it may also include a third metal layer, a third dielectric layer covering the third metal layer, and a second metal interconnection structure penetrating the third dielectric layer, and the metal interconnection structure is electrically connected to the adjacent metal layers to form a semiconductor structure with different numbers of wiring layers to meet the performance requirements of different semiconductor devices.

[0077] In this step, in the current initial semiconductor structure, the number of layers of the at least one first wiring layer 3 can be any positive integer greater than or equal to one; illustratively, the number of layers of the at least one first wiring layer 3 can be one layer, two layers, three layers, four layers, etc.; it should be noted that the top first wiring layer 3 is located at the top in the current process, and after the deep trench isolation structure 5 is subsequently formed, a top metal layer can be directly formed on the top first wiring layer 3, or at least one second wiring layer can be further formed on the at least one first wiring layer 3, and then the top metal layer is finally formed; for example, Figure 3 As shown, the current initial semiconductor structure has a first wiring layer 3, and the first wiring layer 3 is the first first wiring layer 3. The first first wiring layer 3 is located on the first dielectric layer 2, that is, the top first wiring layer 3. After the deep trench isolation structure 5 is formed, at least one second wiring layer can be further formed on the first first wiring layer 3, or a top metal layer can be directly formed on the first first wiring layer 3. For another example, Figure 4 As shown, the initial semiconductor structure in the current step has three layers of first wiring layers 3, then the first layer of first wiring layer 3 is located on the first dielectric layer 2, and then the second layer of first wiring layer 3 and the third layer of first wiring layer 3 are stacked, and the top first wiring layer 3 is the third layer of first wiring layer 3, then the subsequent formation of the deep trench 4 is performed after the first metal interconnection structure 33 in the third layer of first wiring layer 3 is formed, and after the deep trench isolation structure 5 is formed, at least one second wiring layer can be further formed on the basis of the third layer of first wiring layer 3, etc., or the top metal layer can be directly formed on the third layer of first wiring layer 3; in this way, the steps of forming the deep trench 4 and the deep trench isolation structure 5 are placed after the filling step of forming the first metal interconnection structure 33 in the first wiring layer 3 currently at the top, which can effectively avoid the adverse effects of the steps such as forming the deep trench 4 in the front-end process on the device performance, and can be directly inserted into the original back-end process steps, thereby simplifying the process steps and not disrupting the original equipment process. The process integration difficulty is low, which is conducive to reducing the preparation and improvement costs.

[0078] In some exemplary embodiments, Figure 5 As shown, the initial semiconductor structure can be prepared by the following steps:

[0079] providing a device layer 1;

[0080] forming a first dielectric layer 2 on the device layer 1;

[0081] A first through hole 21 is formed in the first dielectric layer 2 and filled with metal material to form a contact structure 22;

[0082] At least one first wiring layer 3 is formed on the first dielectric layer 2 having the contact structure 22 formed thereon.

[0083] Among them, in some exemplary embodiments, Figure 6 As shown, the top first wiring layer 3 in the at least one first wiring layer 3 can be obtained by the following steps:

[0084] Forming a first metal layer 31 on the first dielectric layer 2 or the second top first wiring layer 3;

[0085] forming a second dielectric layer 32 on the first metal layer 31;

[0086] A second through hole 320 is formed in the second dielectric layer 32 and filled with metal material to form a first metal interconnect structure 33 .

[0087] The first metal layer 31 is electrically connected to the device layer 1 through the contact structure 22 that penetrates the first dielectric layer 2, specifically, is electrically connected to the epitaxial layer 12 in the device layer 1, or is electrically connected to the adjacent first wiring layer 3 through the metal interconnection structure that penetrates the adjacent dielectric layer; and the second through-hole 320 exposes the surface of the first metal layer 31 so that the filled first metal interconnection structure 33 can be electrically connected to the first metal layer 31, and subsequently used to electrically connect to the second wiring layer or the top metal layer.

[0088] Specifically, if Figure 3 and Figure 4 As shown, in some exemplary embodiments, a barrier layer 16 is provided on the surface of the device layer 1, and the barrier layer 16 is located between the device layer 1 and the first dielectric layer 2. The barrier layer 16 covers the surface of the epitaxial layer 12, the surface of the shallow trench isolation structure 14 and the surface of the gate 15 in the device layer 1 to play an effective isolation role. In addition, the non-processing area can be protected in the subsequent process, which is beneficial to improving the preparation accuracy of the semiconductor structure and the device performance.

[0089] Then, if Figure 1 and Figure 2 As shown, after forming the first metal interconnect structure 33, a deep trench 4 is formed in the initial semiconductor structure.

[0090] Specifically, the deep trench 4 extends into the device layer 1 after passing through at least one first wiring layer 3 and the first dielectric layer 2; further, the deep trench 4 extends into the substrate layer 11 after passing through at least one first wiring layer 3, the first dielectric layer 2, the shallow trench isolation structure 14, and the epitaxial layer 12; in some exemplary embodiments, the deep trench 4 specifically extends into the substrate layer 11 after passing through at least one first wiring layer 3, the first dielectric layer 2, the barrier layer 16, the shallow trench isolation structure 14, and the epitaxial layer 12; the deep trench 4 is formed after the formation step of the first metal interconnect structure 33 in the top first wiring layer 3 in the current process, which can effectively reduce the influence of the deep trench 4 formed in the front-end process on the morphology and performance of the device layer 1, greatly improve the preparation yield and preparation accuracy of the semiconductor structure, and is conducive to improving the device performance of the semiconductor structure.

[0091] Specifically, the longitudinal depth of the deep trench 4 in the device layer 1 is 20 μm to 40 μm, that is, the longitudinal depth of the subsequently formed deep trench isolation structure 5 in the device layer 1 is 20 μm to 40 μm; it can be understood that the longitudinal depth of the deep trench 4 in the device layer 1 can be any point value between 20 μm and 40 μm; illustratively, the longitudinal depth of the deep trench 4 in the device layer 1 can be 20 μm, 22 μm, 25 μm, 27 μm, 30 μm, 35 μm, 40 μm, etc.; this is beneficial to control the longitudinal depth of the subsequently filled deep trench isolation structure 5, while improving the isolation effect, reducing crosstalk, and improving the device performance of the manufactured semiconductor structure; in some exemplary embodiments, the longitudinal depth of the deep trench 4 in the device layer 1 is 25 μm to 35 μm; in addition, in some optional embodiments, the total longitudinal depth of the deep trench 4 in the device layer 1 and the barrier layer 16 is 20 μm to 40 μm.

[0092] Specifically, if Figure 7 As shown, in some exemplary embodiments, after forming the first metal interconnect structure 33, forming the deep trench 4 in the initial semiconductor structure includes:

[0093] After forming the first metal interconnect structure 33, a hard mask 7 is formed on the second dielectric layer 32;

[0094] Performing photolithography on the hard mask 7 to form an etching window 71;

[0095] The remaining hard mask 7 is used as an etch stop layer to perform trench etching on the area exposed by the etching window 71 in the initial semiconductor structure to form a deep trench 4.

[0096] Among them, the material of the hard mask 7 can be selected from high-hardness materials such as silicon nitride and silicon dioxide, which is conducive to maintaining a stable shape during the etching process. Then, photoresist is coated on the hard mask 7, and etching is performed after exposure to form an etching window 71. In this step, an etching window 71 corresponding to the groove morphology is formed in the hard mask 7 through a photolithography process. The position and size of the etching window 71 can be accurately controlled by adjusting process parameters such as duty cycle, etching rate and etching selectivity. The etching has good controllability and high accuracy, which is conducive to improving the etching accuracy in the process of transferring the groove morphology to the initial semiconductor structure, improving the position accuracy and morphology accuracy of the deep groove 4, and ultimately helping to improve device performance. At the same time, the photolithography process has low complexity and high etching rate, which is conducive to improving preparation efficiency.

[0097] Then, if Figure 1 and Figure 2 As shown, the deep trench 4 is filled to form a deep trench isolation structure 5; the deep trench isolation structure 5 is used to isolate adjacent device modules.

[0098] Specifically, if Figure 8 and Figure 9 As shown, the doped buried layer 13 is connected to the deep trench isolation structure 5, and the end of the deep trench isolation structure 5 extending in the substrate layer 11 is located below the doped buried layer 13. The deep trench isolation structure 5 and the doped buried layer 13 are used together to isolate adjacent device modules to improve isolation reliability.

[0099] Specifically, if Figure 8 and Figure 9 As shown, in some exemplary embodiments, the deep trench isolation structure 5 has a closed air gap 6, which can release thermal stress in subsequent back-end processes, which is beneficial to maintaining the morphology accuracy of the semiconductor structure and improving the device performance of the semiconductor structure.

[0100] Specifically, if Figure 1 and Figure 2 As shown, in the process of forming the deep trench isolation structure 5, a filling dielectric layer 51 is formed that at least covers the wall of the deep trench 4, and the filling dielectric layer 51 is reused as the deep trench isolation structure 5; in some exemplary embodiments, a whole layer of initial filling dielectric layer 510 can be deposited on the second dielectric layer 32, and the initial filling dielectric layer 510 covers the second dielectric layer 32 and the hard mask 7, and part of the dielectric material in the initial filling dielectric layer 510 is filled in the deep trench 4, at least covering the wall of the deep trench 4, and then the part of the dielectric material covering the hard mask 7 is removed, and the dielectric material in the deep trench 4 remains to form the filling dielectric layer 51; the material of the filling dielectric layer 51 can optionally include insulating materials such as silicon dioxide to improve the isolation reliability of the device module.

[0101] Specifically, if Figure 8As shown, in some exemplary embodiments, the filling dielectric layer 51 is the entire deep trench isolation structure 5; in the preparation process, through deposition and planarization treatment, the following can be obtained. Figure 1 The semiconductor structure shown uses the filling dielectric layer 51 as the entire deep trench isolation structure 5 .

[0102] Specifically, if Figure 10 As shown, in a semiconductor structure using a filling dielectric layer 51 as the entire deep trench isolation structure 5, the steps of filling the deep trench 4 to form the deep trench isolation structure 5 include:

[0103] An initial filling dielectric layer 510 is formed on the initial semiconductor structure having the deep trench 4 formed therein; the initial filling dielectric layer 510 is stacked on the initial semiconductor structure and at least covers the wall of the deep trench 4;

[0104] The initial filling dielectric layer 510 is planarized so that the remaining initial filling dielectric layer 510 forms a filling dielectric layer 51 that at least covers the wall of the deep trench 4. During the planarization process, the hard mask 7 covering the second dielectric layer 32 during the formation of the deep trench 4 is removed.

[0105] A second metal layer 8 is formed on the second dielectric layer 32 ; the second metal layer 8 is any intermediate metal layer between the first metal layer 31 and the top metal layer, or the second metal layer 8 is the top metal layer; the second metal layer 8 is electrically connected to the first metal interconnect structure 33 .

[0106] Among them, the initial filling dielectric layer 510 is specifically stacked on the hard mask 7, and through the etching window 71 of the hard mask 7, part of the dielectric material of the initial filling dielectric layer 510 is filled in the deep trench 4, at least covering the side walls and bottom walls of the deep trench 4, so that part of the dielectric material in the deep trench 4 can play a good isolation role.

[0107] Afterwards, the initial filling dielectric layer 510 is planarized. The planarization process may include a chemical mechanical polishing (CMP) process to polish the filling dielectric layer 51 and the hard mask 7 thereunder. The polishing end point stops on the second dielectric layer 32 to improve the effectiveness and accuracy of removing the filling dielectric layer 51 and the hard mask 7 thereunder, and to prevent the residual filling dielectric layer 51 and the hard mask 7 above the second dielectric layer 32 from adversely affecting the morphology of the subsequent semiconductor structure. At the same time, the surface flatness is improved, which is beneficial to improving the morphology accuracy and device performance of the final semiconductor structure. In addition, the high polishing efficiency and simple process are beneficial to improving the preparation efficiency and reducing the preparation difficulty.

[0108] Afterwards, if Figure 10As shown, the second metal layer 8 is formed on the surface of the exposed second dielectric layer 32. A whole second initial metal layer 81 can be deposited on the surface of the second dielectric layer 32 first, and the second initial metal layer 81 is patterned and etched to form a second metal layer 8 with a target shape. The preparation is efficient and accurate.

[0109] Specifically, in some preferred embodiments, during the formation of the deep trench isolation structure 5, a filling dielectric layer 51 that at least covers the walls of the deep trench 4 is formed by high-density plasma deposition (HDP). Specifically, a high-density plasma deposition process is used during the formation of the initial filling dielectric layer 510. The high-density plasma deposition process uses a deposition-etching-deposition cycle during the preparation process. That is, after the initial deposition is completed and the hole filling has not yet occurred, an etching bombardment is immediately performed to reopen the entrance of the deep trench 4, and then deposition is performed again to complete the filling of the entire deep trench 4. This is suitable for filling deep trenches 4 with a high aspect ratio and can achieve a good hole filling effect, thereby better controlling the morphology of the filling dielectric layer 51. In addition, the first dielectric layer 2 and the hard mask 7 are covered above the first metal layer 31, which can play a protective role in the etching process of the high-density plasma deposition process, preventing the metal material of the first metal layer 31 from being bombarded, effectively preventing damage to the first metal layer 31 during the formation of the deep trench isolation structure 5, and improving the preparation accuracy and structural reliability of the resulting semiconductor structure.

[0110] Specifically, when the filling dielectric layer 51 serves as the entire deep trench isolation structure 5 and an air gap 6 exists in the filling dielectric layer 51, the position of the air gap 6 in the deep trench 4 is determined based on the sputtering rate and deposition rate of high-density plasma deposition, thereby better controlling the position and morphology of the air gap 6 through the high-density plasma deposition process, which is beneficial to releasing thermal stress when undergoing thermal processes in subsequent processes, reducing adverse effects on the deep trench isolation structure 5 and the overall morphology of the semiconductor structure, and improving the device performance of the semiconductor structure.

[0111] like Figure 8 As shown, in the semiconductor structure with the filling dielectric layer 51 as the entire deep trench isolation structure 5, the air gap 6 at least spans the device layer 1 and the first dielectric layer 2, that is, the end of the air gap 6 away from the substrate layer 11 is located below the surface of the first dielectric layer 2. At the same time, the end of the air gap 6 close to the device layer 1 is located in the device layer 1. The end of the air gap 6 close to the device layer 1 can specifically extend into the substrate layer 11, which can release thermal stress in subsequent back-end processes, is beneficial to maintaining the morphology accuracy of the semiconductor structure, and improves the device performance of the semiconductor structure.

[0112] Specifically, if Figure 9As shown, in other exemplary embodiments, the deep trench isolation structure 5 includes a deep trench metal isolation structure 52 and a filling dielectric layer 51, and the deep trench metal isolation structure 52 is filled in the filling dielectric layer 51, that is, the filling dielectric layer 51 is reused as part of the deep trench isolation structure 5, and the other part is the deep trench metal isolation structure 52; in the preparation process, the filling dielectric layer 51 is first formed, and then a metal material is further deposited in the trench surrounded by the filling dielectric layer 51 to form the deep trench metal isolation structure 52, and the following can be obtained. Figure 2 The semiconductor structure shown has a deep trench metal isolation structure 52 and a filling dielectric layer 51 , and the deep trench isolation structure 5 formed by the two cooperates with each other to play a good isolation role.

[0113] Specifically, if Figure 11 As shown, in the semiconductor structure having the deep trench metal isolation structure 52, the steps of filling the deep trench 4 to form the deep trench isolation structure 5 include:

[0114] An initial filling dielectric layer 510 is formed on the initial semiconductor structure having the deep trench 4 formed therein; the initial filling dielectric layer 510 is stacked on the initial semiconductor structure and covers the sidewalls and bottom wall of the deep trench 4;

[0115] The initial filling dielectric layer 510 region on the bottom wall of the deep trench 4 is etched back until the bottom wall of the deep trench 4 is exposed; after the etch-back process, the initial filling dielectric layer 510 region located on the initial semiconductor structure is removed, and the remaining initial filling dielectric layer 510 forms a filling dielectric layer 51 that at least covers the wall of the deep trench 4;

[0116] The deep trench 4 is filled based on a metal deposition process to form a deep trench metal isolation structure 52 to obtain a deep trench isolation structure 5 ; the deep trench isolation structure 5 includes the deep trench metal isolation structure 52 and a filling dielectric layer 51 covering the wall of the deep trench 4 .

[0117] Among them, in the process of forming the initial filling dielectric layer 510, the initial filling dielectric layer 510 is in the form of a thin film covering the surface of the hard mask 7 and the side walls and bottom walls of the deep trench 4, and the preparation is simple and efficient; at this time, the initial filling dielectric layer 510 in the deep trench 4 causes the diameter of the deep trench 4 to be reduced to a certain extent, and the longitudinal depth of the deep trench 4 is also reduced to a certain extent.

[0118] Afterwards, by back-etching, part of the dielectric material of the dielectric layer 510 initially filled on the bottom wall of the deep trench 4 is removed to expose the bottom wall of the deep trench 4, so that the bottom end of the deep trench metal isolation structure 52 formed subsequently can contact the substrate layer 11 material; and, in the back-etching process, the dielectric material on the bottom wall of the deep trench 4 and the dielectric material covering the surface of the hard mask 7 are simultaneously etched away, and the hard mask 7 can serve as an etching stop layer for back-etching to prevent damage to the first dielectric layer 2 and the various structures beneath it during the back-etching process. The difficulty of back-etching is effectively reduced, which is also beneficial to maintaining the morphological accuracy of the semiconductor structure and improving the preparation yield.

[0119] Specifically, if Figure 12 As shown, in some exemplary embodiments, before filling the deep trench 4 based on a metal filling process to form a deep trench metal isolation structure 52 to obtain a deep trench isolation structure 5, the preparation method further includes:

[0120] After the etch-back process, ion implantation is performed at the bottom of the deep trench 4 to form a doping structure 53 .

[0121] At this time, in the state where the substrate layer 11 of the bottom wall of the deep trench 4 is exposed, ion implantation is performed at the bottom of the deep trench 4, specifically, ion implantation is performed with a relatively light doping concentration, which is beneficial to improving the breakdown voltage, and thus is beneficial to improving the device performance of the semiconductor structure; in addition, the morphology of the doping structure 53 is smooth, and can be circular, elliptical or arc-shaped, and the charge is relatively concentrated, which is beneficial to the dispersion of the electric field.

[0122] Specifically, if Figure 13 As shown, in some exemplary embodiments, before filling the deep trench 4 based on a metal deposition process to form a deep trench metal isolation structure 52 to obtain a deep trench isolation structure 5, the preparation method further includes:

[0123] After the filling dielectric layer 51 is formed by etching back, the hard mask 7 covering the second dielectric layer 32 during the formation of the deep trench 4 is removed.

[0124] At this time, in a state where the substrate layer 11 of the bottom wall of the deep trench 4 is exposed, the hard mask 7 can be removed by mechanical polishing or etching after the doping structure 53 is formed to prevent the hard mask 7 from affecting the normal progress of subsequent processes.

[0125] Specifically, if Figure 14 As shown, in some exemplary embodiments, filling the deep trench 4 based on a metal deposition process to form a deep trench metal isolation structure 52 includes:

[0126] Metal material is deposited to form a second initial metal layer 81 filling the deep trench 4 and stacked on the second dielectric layer 32 and the first metal interconnect structure 33 . The portion of the second initial metal layer 81 filling the deep trench 4 forms a deep trench metal isolation structure 52 .

[0127] Accordingly, if Figure 15 As shown, after filling the deep trench 4 based on the metal deposition process to form the deep trench metal isolation structure 52, specifically after forming the second initial metal layer 81, the preparation method further includes:

[0128] The portion of the second initial metal layer 81 stacked on the second dielectric layer 32 is patterned and etched to form a second metal layer 8; the second metal layer 8 is any intermediate metal layer between the first metal layer 31 and the top metal layer, or the second metal layer 8 is the top metal layer; the second metal layer 8 is electrically connected to the deep trench metal isolation structure 52 and the first metal interconnection structure 33, respectively.

[0129] The metal material of the second initial metal layer 81 can be the same as the metal material of the first metal layer 31 and the metal material of the deep trench metal isolation structure 52; while forming the second initial metal layer 81, the deep trench metal isolation structure 52 is also filled in the deep trench 4 as a part of the deep trench isolation structure 5. The two are formed simultaneously, which greatly simplifies the process steps, and the process steps are also easy to integrate into the original process of preparing the second metal layer 8, and the original process equipment for preparing the second metal layer 8 can be used, which greatly reduces the difficulty of process development, reduces the process integration cost and the overall preparation cost.

[0130] Optionally, the metal material of the first metal layer 31 and the second metal layer 8 includes aluminum metal, that is, the preparation method of the semiconductor structure is applicable to the aluminum process, which can greatly improve the yield rate of the aluminum process.

[0131] Among them, when the second metal layer 8 is the top metal layer, a semiconductor structure can be obtained directly, and then subsequent packaging and other processes can be carried out; and when the second metal layer 8 is any intermediate metal layer between the first metal layer 31 and the top metal layer, the second metal layer 8 can be used as the third metal layer in the next second wiring layer, and at least one second wiring layer can be stacked, and finally a semiconductor structure is obtained after forming the top metal layer.

[0132] Specifically, if Figure 9As shown, when the deep trench isolation structure 5 includes a deep trench metal isolation structure 52 and an air gap 6 exists in the deep trench isolation structure 5, the air gap 6 is enclosed in the deep trench metal isolation structure 52; in some exemplary embodiments, the air gap 6 spans the device layer 1, the first dielectric layer 2 and the second dielectric layer 32; in other exemplary embodiments, the air gap 6 spans the epitaxial layer 12, the barrier layer 16, the first dielectric layer 2 and the second dielectric layer 32, so as to facilitate the release of thermal stress in subsequent processes and improve the preparation accuracy and device performance of the semiconductor structure.

[0133] On the other hand, an embodiment of the present application provides a semiconductor structure, which is manufactured based on the semiconductor structure manufacturing method as described above, so that the semiconductor structure manufactured based on the semiconductor structure manufacturing method can have good morphological accuracy, reduce the risk of wafer warping during the manufacturing process, and is conducive to improving the device performance of the semiconductor structure; the semiconductor structure includes: a device layer 1; a first dielectric layer 2 located on the device layer 1; at least one first wiring layer 3 located on the first dielectric layer 2, the at least one first wiring layer 3 being located between the first dielectric layer 2 and the top metal layer, the top first wiring layer 3 of the at least one first wiring layer 3 including a first metal layer 31, a second dielectric layer 32 covering the first metal layer 31, and a first metal interconnect structure 33 penetrating the second dielectric layer 32, the first metal interconnect structure 33 being electrically connected to the first metal layer 31; a deep trench 4 penetrating the at least one first wiring layer 3 and the first dielectric layer 2 and extending into the device layer 1; a deep trench isolation structure 5 filled in the deep trench 4, the deep trench isolation structure 5 being used to isolate adjacent device modules.

[0134] On the other hand, the present application provides a semiconductor device, including the semiconductor structure as described above, with high structural precision and excellent performance; the semiconductor device includes at least one of a diode, a bipolar junction transistor (BJT), a field effect transistor (MOSFET / JFET), an insulated gate bipolar diode (IGBT), a complementary metal oxide semiconductor (CMOS), a high-voltage power field effect transistor (DMOS), a thyristor (SCR) and a BCD device, wherein the BCD device combines the three processes of BJT, CMOS and DMOS, has high integration, and can achieve high efficiency and low power consumption; the semiconductor device can be used in any electronic product or equipment such as mobile phones, tablet computers, laptops, netbooks, game consoles, televisions, VCDs, DVDs, navigation systems, cameras, camcorders, voice recorders, MP3s, MP4s, PSPs, etc., and can also be used in intermediate products of electronic equipment to improve the working performance of electronic equipment.

[0135] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing an initial semiconductor structure; The initial semiconductor structure includes a device layer, a first dielectric layer located on the device layer, and at least one first wiring layer located on the first dielectric layer, wherein the at least one first wiring layer is located between the first dielectric layer and a top metal layer, and the top first wiring layer of the at least one first wiring layer includes a first metal layer, a second dielectric layer covering the first metal layer, and a first metal interconnect structure penetrating the second dielectric layer, wherein the first metal interconnect structure is electrically connected to the first metal layer; After forming the first metal interconnect structure, forming a deep trench in the initial semiconductor structure; The deep trench penetrates the at least one first wiring layer and the first dielectric layer and then extends into the device layer; The deep trench is filled to form a deep trench isolation structure; the deep trench isolation structure is used to isolate adjacent device modules.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The device layer includes a substrate layer, an epitaxial layer located on the substrate layer, a doped buried layer embedded at the interface between the substrate layer and the epitaxial layer, a shallow trench isolation structure exposed on the surface of the epitaxial layer, and a gate located on the epitaxial layer; The deep trench penetrates the at least one first wiring layer, the first dielectric layer, the shallow trench isolation structure, and the epitaxial layer and then extends into the substrate layer.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The doped buried layer is connected to the deep trench isolation structure, and the end of the deep trench isolation structure extending in the substrate layer is located below the doped buried layer; The deep trench isolation structure and the doped buried layer are used to isolate adjacent device modules.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The deep trench isolation structure has a closed air gap therein.

5. The method for preparing a semiconductor structure according to claim 1, wherein: During the process of forming the deep trench isolation structure, a filling dielectric layer is formed to at least cover the deep trench wall, and the filling dielectric layer is reused as the deep trench isolation structure.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The longitudinal depth of the deep trench in the device layer is 20 μm to 40 μm.

7. The method for preparing a semiconductor structure according to claim 1, wherein: After forming the first metal interconnect structure, forming a deep trench in the initial semiconductor structure includes: After forming the first metal interconnect structure, forming a hard mask on the second dielectric layer; performing photolithography on the hard mask to form an etching window; The remaining hard mask is used as an etch stop layer to perform trench etching on the area exposed by the etching window in the initial semiconductor structure to form the deep trench.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, wherein: Filling the deep trench to form a deep trench isolation structure includes: forming an initial filling dielectric layer on the initial semiconductor structure having the deep trench formed therein; the initial filling dielectric layer is stacked on the initial semiconductor structure and at least covers the wall of the deep trench; performing a planarization process on the initial filling dielectric layer so that the remaining initial filling dielectric layer forms a filling dielectric layer that at least covers the wall of the deep trench; during the planarization process, a hard mask covering the second dielectric layer during the formation of the deep trench is removed; A second metal layer is formed on the second dielectric layer; the second metal layer is any intermediate metal layer between the first metal layer and the top metal layer, or the second metal layer is the top metal layer; the second metal layer is electrically connected to the first metal interconnect structure.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 7, wherein: During the process of forming the deep trench isolation structure, a filling dielectric layer at least covering the deep trench wall is formed by high-density plasma deposition.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The position of the air gap in the deep trench isolation structure is determined based on the sputtering rate and the deposition rate of the high-density plasma deposition.

11. The method for preparing a semiconductor structure according to any one of claims 1 to 7, wherein: Filling the deep trench to form a deep trench isolation structure includes: forming an initial filling dielectric layer on the initial semiconductor structure having the deep trench formed therein; the initial filling dielectric layer is stacked on the initial semiconductor structure and covers the sidewalls and bottom wall of the deep trench; Etching back the initial filling dielectric layer region on the bottom wall of the deep trench until the bottom wall of the deep trench is exposed; after the etching back process, the initial filling dielectric layer region located on the initial semiconductor structure is removed, and the remaining initial filling dielectric layer forms a filling dielectric layer that at least covers the wall of the deep trench; The deep trench is filled based on a metal deposition process to form a deep trench metal isolation structure to obtain the deep trench isolation structure; the deep trench isolation structure includes the deep trench metal isolation structure and a filling dielectric layer covering the deep trench wall.

12. The method for preparing a semiconductor structure according to claim 11, wherein: Before filling the deep trench based on a metal filling process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes: After the etching back process, ion implantation is performed at the bottom of the deep trench to form a doping structure.

13. The method for preparing a semiconductor structure according to claim 11, wherein: Before filling the deep trench based on a metal deposition process to form a deep trench metal isolation structure to obtain the deep trench isolation structure, the method further includes: After the filling dielectric layer is formed by etching back, the hard mask covering the second dielectric layer during the process of forming the deep trench is removed.

14. The method for preparing a semiconductor structure according to claim 11, wherein: Filling the deep trench based on a metal deposition process to form a deep trench metal isolation structure includes: Depositing a metal material to form a second initial metal layer filling the deep trench and stacked on the second dielectric layer and the first metal interconnect structure, wherein a portion of the second initial metal layer filling the deep trench forms the deep trench metal isolation structure; After filling the deep trench based on the metal deposition process to form a deep trench metal isolation structure, the method further includes: The portion of the second initial metal layer stacked on the second dielectric layer is patterned and etched to form a second metal layer; the second metal layer is any intermediate metal layer between the first metal layer and the top metal layer, or the second metal layer is the top metal layer; the second metal layer is electrically connected to the deep trench metal isolation structure and the first metal interconnection structure, respectively.

15. The method for preparing a semiconductor structure according to claim 11, wherein: The air gap in the deep trench isolation structure is enclosed in the deep trench metal isolation structure.

16. A semiconductor structure, characterized in that Prepared based on the preparation method of the semiconductor structure according to any one of claims 1 to 15; The semiconductor structure comprises: device layer; a first dielectric layer located on the device layer; at least one first wiring layer located on the first dielectric layer, the at least one first wiring layer located between the first dielectric layer and a top metal layer, the top first wiring layer of the at least one first wiring layer comprising a first metal layer, a second dielectric layer covering the first metal layer, and a first metal interconnect structure penetrating the second dielectric layer, the first metal interconnect structure being electrically connected to the first metal layer; a deep trench, penetrating the at least one first wiring layer and the first dielectric layer and extending into the device layer; A deep trench isolation structure is filled in the deep trench, and the deep trench isolation structure is used to isolate adjacent device modules.

17. A semiconductor device, characterized in that: Comprising the semiconductor structure of claim 16.

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