Semiconductor structure manufacturing methods, semiconductor structures and semiconductor devices

Abstract

This application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor device. The method includes: providing a substrate; the substrate includes a substrate and a patterned material layer, a first hard mask layer, and a second hard mask layer sequentially formed on the surface of the substrate; etching the second hard mask layer to form an opening in the second hard mask layer; during the etching of the second hard mask layer, using the resulting etching byproducts to form a protective layer of a different material from the first hard mask layer on the side of the opening in the second hard mask layer; etching the first hard mask layer based on the opening in the second hard mask layer to form an opening in the first hard mask layer; during the etching of the first hard mask layer, the etching rate of the material of the first hard mask layer is greater than the etching rate of the material of the protective layer; and etching the patterned material layer based on the opening in the first hard mask layer to obtain a semiconductor structure. This application improves the dimensional uniformity of the pattern formed by etching the patterned material layer.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor manufacturing technology, specifically to a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor device. Background Technology

[0002] In semiconductor manufacturing technology, back-end line (BEOL) processes are used to form interconnect layers, enabling electrical connections between different conductive layers within a chip. BEOL processes involve the fabrication of wires, vias, and contacts.

[0003] Currently, for high aspect ratio (HAR) circuit designs, to improve the transfer accuracy of circuit design patterns, hard mask layers (HML) made of amorphous carbon (AC) are widely used to transfer photolithographic patterns from the photolithographic functional layer to the patterning material layer (PL). However, during the pattern transfer process, the etched pattern formed by etching the amorphous carbon hard mask layer is prone to defects, resulting in poor dimensional uniformity of the circuit pattern formed on the patterning material layer. Summary of the Invention

[0004] In view of this, several embodiments of this application provide a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor device to reduce defects in the etching pattern of the amorphous carbon hard mask layer and improve the dimensional uniformity of the circuit pattern.

[0005] In one aspect, one embodiment of this application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; the substrate including a substrate, a patterned material layer formed on the surface of the substrate, a first hard mask layer formed on a surface of the patterned material layer away from the substrate, and a second hard mask layer formed on a surface of the first hard mask layer away from the substrate; wherein the first hard mask layer and the second hard mask layer are made of different materials; etching the second hard mask layer to form a second hard mask layer opening that exposes the first hard mask layer; wherein, during the etching of the second hard mask layer, a protective layer is formed on the side of the second hard mask layer opening using the resulting etching byproducts; the protective layer is made of a different material than the first hard mask layer; etching the first hard mask layer based on the second hard mask layer opening to form a first hard mask layer opening that exposes the patterned material layer; wherein, during the etching of the first hard mask layer, the etching rate of the material of the first hard mask layer is greater than the etching rate of the material of the protective layer; and etching the patterned material layer based on the first hard mask layer opening to obtain the semiconductor structure.

[0006] Optionally, the plasma used to etch the second hard mask layer includes silicon tetrachloride.

[0007] Optionally, during the etching of the second hard mask layer, the reaction temperature falls within the range of 35°C to 40°C.

[0008] Optionally, the material of the first hard mask layer is amorphous carbon; the material of the protective layer is silicon oxide; and the material of the second hard mask layer is oxide.

[0009] Optionally, the step of etching the first hard mask layer based on the opening of the second hard mask layer to form a first hard mask layer opening that exposes the patterned material layer includes: performing a first etching on the first hard mask layer based on the opening of the second hard mask layer to form a transition opening, thereby obtaining a transition hard mask layer; wherein the transition opening has a bottom surface formed by the material of the first hard mask layer; removing the protective layer; and performing a second etching on the transition hard mask layer based on the transition opening to form the first hard mask layer opening penetrating the transition hard mask layer.

[0010] Optionally, the protective layer can be removed by reacting trifluoromethane with a fluorocarbon compound and the material of the protective layer.

[0011] Optionally, during the second etching of the transition hard mask layer based on the transition opening, the bias power of the RF power supply is less than 100 watts.

[0012] Optionally, etching the patterned material layer based on the opening of the first hard mask layer includes: etching the patterned material layer based on the opening of the first hard mask layer to form a patterned layer; wherein the patterned layer includes a plurality of patterned structures, with the normal direction of the substrate as the height direction of the patterned structure, and the direction perpendicular to the normal direction of the substrate as the width direction of the patterned structure, and the ratio of the dimension of the patterned structure along the height direction to the dimension of the patterned structure along the width direction is greater than 8.

[0013] In another aspect, one embodiment of this application provides a semiconductor structure manufactured by the semiconductor structure manufacturing method described in the above embodiments.

[0014] In another aspect, one embodiment of this application provides a semiconductor device comprising a semiconductor structure manufactured by a semiconductor structure manufacturing method as described in the above embodiments, or a semiconductor structure as described in the above embodiments.

[0015] In several embodiments of this application, the provided substrate includes a substrate and a patterned material layer, a first hard mask layer, and a second hard mask layer sequentially formed on the substrate surface. During the etching of the second hard mask layer to form an opening that exposes the first hard mask layer, a protective layer of a different material from the first hard mask layer is formed on the side of the opening using the generated etching byproducts. Then, the first hard mask layer is etched based on the opening of the second hard mask layer to form an opening that exposes the patterned material layer. Finally, the patterned material layer is etched based on the opening of the first hard mask layer to obtain a semiconductor structure. Unexpected effects include: because a protective layer formed by etching byproducts is introduced during the etching of the second hard mask layer, and the etching rate of the first hard mask layer material is greater than the etching rate of the protective layer material during the etching of the first hard mask layer, defects in the etching pattern of the first hard mask layer formed by etching the first hard mask layer are reduced under the action of the protective layer, and the dimensional uniformity of the pattern formed by etching the patterned material layer is improved. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This diagram illustrates etching based on a dual-layer photolithography functional layer at the 90nm process node, providing insights into related technologies.

[0018] Figure 2 This diagram illustrates etching based on three photolithography functional layers at the 65nm process node, providing insights into related technologies.

[0019] Figure 3 A schematic diagram illustrating the etching of an oxide layer to form an opening in the oxide layer, provided for related technologies.

[0020] Figure 4 A schematic diagram illustrating the etching pattern of an amorphous carbon layer to form an etching pattern for related technologies.

[0021] Figure 5 Microscopic images of cross-sectional views of amorphous carbon layer etching patterns provided for related technologies.

[0022] Figure 6 A top-view microscopic image of an amorphous carbon layer etching pattern provided for related technologies.

[0023] Figure 7 A schematic diagram illustrating the formation of a semiconductor patterned layer by etching a semiconductor patterning material layer, provided for related technologies.

[0024] Figure 8 for Figure 7 Microscopic images of the cross-section of the mid-structure.

[0025] Figure 9 A schematic diagram illustrating the removal of residues using related technologies.

[0026] Figure 10 This is a schematic flowchart of a semiconductor manufacturing method provided in an embodiment of this application.

[0027] Figure 11 A schematic diagram of the structure of the substrate provided in an embodiment of this application.

[0028] Figure 12 This is a schematic diagram of etching the second hard mask layer provided in an embodiment of this application.

[0029] Figure 13 This is a schematic diagram of the process for etching the first hard mask layer based on the opening of the second hard mask layer, provided in an embodiment of this application.

[0030] Figure 14 This is a schematic diagram illustrating the formation of a transition opening and the obtaining of a transition hard mask layer, as provided in an embodiment of this application.

[0031] Figure 15 This is a schematic diagram of removing the protective layer provided in an embodiment of this application.

[0032] Figure 16 This is a schematic diagram of a second etching of a transition hard mask layer based on a transition opening, provided as an embodiment of this application.

[0033] Figure 17 This is a schematic diagram of the semiconductor structure provided in an embodiment of this application.

[0034] Figure 18 for Figure 17 Microscopic images of the cross-section of the mid-structure.

[0035] Figure 19 for Figure 17 Microscopic images of the mid-structure from a top-down perspective.

[0036] Structural designation explanation

[0037] 100. Semiconductor substrate; 110. Semiconductor patterning material layer; 111. Semiconductor patterning layer; 111a. Semiconductor pattern structure; 112. Via opening; 120. Amorphous carbon layer; 121. Amorphous carbon layer etching pattern; 121a. Amorphous carbon layer pattern structure; 122. Residual amorphous carbon layer etching pattern; 130. Double-layer photolithography functional layer; 1301. Anti-reflective coating; 1302. Organic dielectric layer; 1302a. Organic dielectric layer etching pattern; 1303. Silicon oxide hard mask layer; 1304. Photoresist layer; 131. Three-layer photolithography functional layer; 140. First mask Film; 141, Second mask; 150, Oxide layer; 151, Oxide layer etching pattern; 152, Oxide layer opening; 200, Substrate; 210, Substrate; 220, Patterned material layer; 221, Patterned layer; 221a, Patterned structure; 230, First hard mask layer; 231, Transition hard mask layer; 232, Transition opening; 233, First hard mask layer opening; 234, First hard mask layer etching pattern; 240, Second hard mask layer; 241, Second hard mask layer etching pattern; 242, Second hard mask layer opening; 243, Protective layer; 300, Semiconductor structure. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0039] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.

[0040] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0041] In related technologies, after the front-end of line (FEOL) process has completed the fabrication of integrated circuit components such as transistors, the back-end process can continue to form interconnect layers and conductive layers on the semiconductor substrate where multiple components have already been formed, in order to construct the integrated circuit structure. To achieve vertical connections between different conductive layers, vias for electrical connections can be formed in the interconnect layers between different conductive layers. These vias can be formed by filling the via openings with conductive metal. Therefore, it is necessary to design openings based on the vias on the mask to form via openings on the interconnect layers.

[0042] Please see Figure 1 The via opening can be formed in the semiconductor patterned material layer 110 through the following process steps.

[0043] First, a semiconductor patterned material layer 110 is formed on the semiconductor substrate 100.

[0044] Subsequently, an amorphous carbon layer 120 and a photolithography functional layer are sequentially formed on the surface of the semiconductor patterning material layer 110 away from the semiconductor substrate 100. For process nodes of 90nm and below, the photolithography functional layer can be a double-layer photolithography functional layer 130, which may include an anti-reflection coating (ARC) 1301 and a photoresist (PR) layer 1304.

[0045] Next, the photoresist layer 1304 is patterned using exposure and development based on the first mask 140. Then, the anti-reflective coating 1301, the amorphous carbon layer 120, and the semiconductor patterned material layer 110 are etched sequentially to form a via opening in the semiconductor patterned material layer 110. In the first mask 140, the critical dimension (CD) D1 of the via opening falls within the range of 110 nm ± 3 nm. Due to the influence of photolithography effects and etching process errors, the critical dimension D2 of the via opening formed in the semiconductor patterned material layer 110 falls within the range of 90 nm ± 7 nm.

[0046] As semiconductor manufacturing process nodes continue to shrink, for process nodes of 65nm and below, especially 40nm and below, double-layer photolithography functional layers are no longer sufficient to meet the increasingly fine pattern transfer requirements, and triple-layer photolithography functional layers are gradually becoming the mainstream.

[0047] Please see Figure 2The three-layer photolithography functional layer 131 may include an organic dielectric layer (ODL) 1302, a silicon oxide hard mask layer (Si-O-Based Hard Mask) 1303, and a photoresist layer 1304, sequentially located away from the semiconductor substrate 100. The organic dielectric layer 1302 may be made of a material with good insulating properties to achieve electrical isolation. The silicon oxide hard mask layer 1303 can be used to protect the organic dielectric layer 1302 during the patterning process of the photoresist layer 1304.

[0048] When the critical dimension is 65nm or below, and the aspect ratio of the semiconductor pattern structure formed by etching the semiconductor patterning material layer 110 is greater than 8, the via openings between adjacent semiconductor pattern structures can be formed by the following process steps.

[0049] First, a semiconductor patterned material layer 110 and an amorphous carbon layer 120 are sequentially formed on a semiconductor substrate 100.

[0050] Secondly, an oxide layer 150 is formed on the surface of the amorphous carbon layer 120 away from the semiconductor substrate 100 to reduce the damage to the amorphous carbon layer 120 caused by etching the silicon oxide hard mask layer 1303 and etching the organic dielectric layer 1302.

[0051] Next, three photolithographic functional layers 131 are formed on the surface of the oxide layer 150 away from the semiconductor substrate 100.

[0052] Subsequently, the photoresist layer 1304 is patterned using the second mask 141 through exposure, development, and other processes. Then, the silicon oxide hard mask layer 1303, organic dielectric layer 1302, oxide layer 150, amorphous carbon layer 120, and semiconductor patterning material layer 110 are etched sequentially to form via openings in the semiconductor patterning material layer 110. In the second mask 141, the critical dimension (CD) D3 of the via opening falls within the range of 90nm ± 2nm. Due to the influence of photolithography effects and etching process errors, the critical dimension D4 of the via opening formed in the semiconductor patterning material layer 110 falls within the range of 65nm ± 5nm.

[0053] The following combination Figures 2 to 9 Taking the etching process from the silicon oxide hard mask layer to the formation of the via opening as an example, this paper briefly introduces the manufacturing process of via opening in related technologies.

[0054] Please refer to the following: Figure 2 and Figure 3First, based on the etching pattern formed in the silicon oxide hard mask layer 1303, the organic dielectric layer 1302 and the oxide layer 150 are etched to obtain an oxide layer opening 152 that exposes the amorphous carbon layer 120. The remaining organic dielectric layer material forms an organic dielectric layer etching pattern 1302a, and the remaining oxide layer material forms an oxide layer etching pattern 151.

[0055] Please refer to the following: Figures 4 to 6 Secondly, the organic dielectric layer etching pattern is removed, and the amorphous carbon layer is etched through (BT) based on the oxide layer opening to obtain an amorphous carbon layer etched pattern 121 including multiple amorphous carbon layer pattern structures 121a. BT etching has a decisive influence on the critical dimensions of the via opening. However, during the BT etching process of the amorphous carbon layer, due to fluctuations in the control of the etching direction, defects such as bowing, necking, or large taper appear in the amorphous carbon layer pattern structure 121a. That is, the flatness of the profile of the amorphous carbon layer pattern structure 121a is low, and the amorphous carbon layer etched pattern 121 corresponding to the via opening has blurred edges and enlarged size, i.e., a certain degree of pattern damage occurs, resulting in poor local critical dimension uniformity (LCDU) of the via opening.

[0056] Furthermore, since multiple layers, including a silicon oxide hard mask layer, an organic dielectric layer, and an oxide layer, have been etched sequentially before etching the amorphous carbon layer, a large number of impurity particles may exist in the reaction chamber during the etching of the amorphous carbon layer. These impurity particles may cause the connection between different conductive layers to fail.

[0057] Please refer to the following: Figure 7 and Figure 8 After forming the amorphous carbon layer etching pattern, the oxide layer etching pattern 151 and a portion of the amorphous carbon layer etching pattern are removed. Based on the remaining amorphous carbon layer etching pattern 122 after removing the portion of the amorphous carbon layer etching pattern, the semiconductor patterned material layer is etched to obtain a semiconductor patterned layer 111 including multiple semiconductor pattern structures 111a. Figure 8 In the diagram, the area between the two dashed lines corresponds to the semiconductor patterning layer 111.

[0058] Please see Figure 9After the semiconductor patterning layer 111 is formed, residual structures and materials other than the semiconductor substrate 100 and the semiconductor patterning layer 111 can be removed, and the region between adjacent semiconductor pattern structures 111a is used as a via opening 112. Because the amorphous carbon layer etching pattern already has pattern damage, the taper of the semiconductor pattern structure 111a in the semiconductor patterning layer 111 obtained based on the amorphous carbon layer etching pattern is relatively large, making it difficult to meet the process requirements of the semiconductor pattern structure 111a.

[0059] In summary, in related technologies, the difficulty in controlling the etching direction during the penetrating etching of amorphous carbon layers leads to various contour defects and damage to the etched patterns of amorphous carbon layers, reducing the pattern transfer accuracy and making it difficult to meet the process requirements for the uniformity of the pattern contour and local critical dimensions of the semiconductor patterned layer.

[0060] Therefore, for manufacturing high aspect ratio patterns at process nodes of 65nm and below, it is necessary to provide a method for manufacturing semiconductor structures. This method involves providing a substrate and a patterned material layer, a first hard mask layer, and a second hard mask layer sequentially formed on the substrate surface. During the etching of the second hard mask layer to form an opening that exposes the first hard mask layer, the method utilizes the resulting etching byproducts to form a protective layer of a different material from the first hard mask layer on the side of the opening. Subsequently, the first hard mask layer is etched based on the opening of the second hard mask layer to form a protective layer that exposes the patterned material. The first hard mask layer is exposed by an opening, and a patterned material layer is etched based on the opening of the first hard mask layer to obtain a semiconductor structure. Since a protective layer formed by etching byproducts is introduced during the etching of the second hard mask layer, and the etching rate of the first hard mask layer material is greater than the etching rate of the protective layer material during the etching of the first hard mask layer, the defects in the etching pattern of the first hard mask layer formed by etching the first hard mask layer can be reduced under the action of the protective layer, the local critical dimension uniformity of the patterned layer formed by etching the patterned material layer can be improved, and the etching profile of the patterned layer can be improved.

[0061] Please see Figure 10 One embodiment of this application provides a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure may include steps S310, S320, S330, and S340.

[0062] S310: Provides a substrate.

[0063] Please see Figure 11In this embodiment, the substrate 200 may include a substrate 210, a patterned material layer 220 formed on the surface of the substrate 210, a first hard mask layer 230 formed on the surface of the patterned material layer 220 away from the substrate 210, and a second hard mask layer 240 formed on the surface of the first hard mask layer 230 away from the substrate 210.

[0064] In this embodiment, the substrate 210 can be used to provide support for the interconnect layer and the conductive layer. Specifically, the substrate 210 can be a structure wafer on which integrated circuit elements such as field-effect transistors have been formed.

[0065] In this embodiment, the patterned material layer 220 can be used to form an etching pattern corresponding to the circuit design pattern. Specifically, the material of the patterned material layer 220 can be selected from silicon dioxide, silicon nitride, or a low dielectric constant material.

[0066] In this embodiment, the first hard mask layer 230 can be used as a mask layer and a protective layer for the patterned material layer 220. Specifically, the material of the first hard mask layer 230 can be amorphous carbon.

[0067] In this embodiment, the second hard mask layer 240 can be used as both a mask layer and a protective layer for the first hard mask layer 230. The material of the second hard mask layer 240 can be different from that of the first hard mask layer 230. Specifically, the material of the second hard mask layer 240 can be an oxide, such as silicon dioxide (SiO2).

[0068] S320: Etch the second hard mask layer to form an opening in the second hard mask layer that exposes the first hard mask layer.

[0069] Since the opening of the second hard mask layer has a decisive influence on the size and uniformity of the critical dimensions of the patterned layer, in order to improve the control over the critical dimensions of the patterned layer and enhance the local critical dimension uniformity of the patterned layer, plasma, including silicon tetrachloride, can be used to etch the second hard mask layer. In this way, during the etching process, the side of the opening of the second hard mask layer can be protected by the etching byproducts.

[0070] In related technologies, oxide layers are typically etched using plasma containing carbon tetrafluoride (CF4), oxygen (O2), and argon (Ar) at relatively low temperatures within the reaction temperature range of -155°C to -145°C, for example, at a reaction temperature of -150°C. However, under these conditions, the plasma etches the oxide layer and amorphous carbon layer materials at a relatively high rate, and has weak control over the etching direction. Consequently, during the subsequent etching of the amorphous carbon layer based on the openings in the oxide layer, various deformation defects in the amorphous carbon layer etching pattern are easily caused, resulting in poor local critical dimension uniformity of the etching pattern transferred from the amorphous carbon layer etching pattern to the semiconductor patterned material layer.

[0071] Please see Figure 12 To improve the uniformity of local critical dimensions of the patterned layer formed by etching the patterned material layer 220, and to better control the critical dimensions of the patterned layer, in this embodiment, the reaction temperature during the etching of the second hard mask layer can fall within the range of 35°C to 40°C. For example, the reaction temperature can be 35°C, 38°C, or 40°C. Furthermore, in this embodiment, the plasma used to etch the second hard mask layer can include silicon tetrachloride (SiCl4). Specifically, silicon tetrachloride can be used to replace carbon tetrafluoride in related technologies, while retaining auxiliary plasmas such as oxygen and argon. That is, under the condition that the reaction temperature falls within the range of 35°C to 40°C, a plasma including silicon tetrachloride, oxygen, and argon is used to etch the second hard mask layer. Under the above conditions, the etching rate of the plasma on the materials of the second hard mask layer and the first hard mask layer 230 is slower, and the control over the etching direction is stronger, thereby reducing the possibility of deformation defects in the etched pattern of the first hard mask layer. Simultaneously, during the etching of the second hard mask layer under the aforementioned conditions, etching byproducts of a different material than that of the first hard mask layer 230 will be generated. Due to the enhanced control over the etching direction, these etching byproducts will adhere to the side of the opening 242 of the second hard mask layer, forming a protective layer 243. During the subsequent etching of the first hard mask layer 230 to form the opening of the first hard mask layer, this protective layer 243 can block some lateral etching, thereby protecting the side of the opening of the first hard mask layer to a certain extent and improving the smoothness of the etching contour on the side of the opening of the first hard mask layer.

[0072] In this embodiment, the etching byproducts can be generated by the reaction of silicon in silicon tetrachloride plasma with oxygen in the material removed by etching. Therefore, the material of the protective layer 243 formed by the etching byproducts can be a silicon oxide compound.

[0073] S330: Etch the first hard mask layer based on the opening of the second hard mask layer to form the opening of the first hard mask layer that exposes the patterned material layer.

[0074] Please see Figure 13 In some embodiments, the step of etching the first hard mask layer based on the opening of the second hard mask layer to form an opening in the first hard mask layer that exposes the patterned material layer may include sub-steps S331, S332 and S333.

[0075] S331: Based on the opening of the second hard mask layer, the first hard mask layer is etched to form a transition opening, thereby obtaining a transition hard mask layer.

[0076] Depend on Figure 4 It is known that in related technologies, the necking defects in the amorphous carbon layer etching pattern 121 are mainly concentrated in the portion of the amorphous carbon layer near the oxide layer etching pattern 151. Please refer to... Figure 14 To reduce defects in the etching pattern of the first hard mask layer during the etching process using the protective layer 243, the first hard mask layer can be etched first to obtain a transition hard mask layer 231 while the protective layer 243 is attached to the side of the opening of the second hard mask layer. Then, the protective layer 243 is removed, and the transition hard mask layer 231 is etched again to form the opening of the first hard mask layer.

[0077] In this embodiment, the process parameters used for the first etching can be those used in the etching of amorphous carbon layers in related technologies. Specifically, the first etching can be achieved using a plasma etching process. The plasma used has a higher etching rate on the material of the first hard mask layer than on the material of the protective layer 243. This ensures that the protective layer 243 remains attached to the side of the opening in the second hard mask layer during the formation of the transition opening 232, thereby improving the morphology of the transition opening 232. For example, the etching plasma for the first etching can include oxygen, fluorine-based gas, and argon.

[0078] In this embodiment, the transition opening 232 may have a bottom surface formed of the material of the first hard mask layer. The transition hard mask layer 231 may be formed from the remaining material of the first hard mask layer after etching the first hard mask layer to form the transition opening 232. Specifically, the transition depth of the transition opening 232 is defined as the distance between the bottom surface of the transition opening 232 and the surface of the transition hard mask layer 231 near the patterned material layer 220, and the thickness of the transition hard mask layer 231 is defined as the distance between the surface of the transition hard mask layer 231 furthest from the patterned material layer 220 and the surface of the transition hard mask layer 231 near the patterned material layer 220. The ratio of the transition depth of the transition opening 232 to the thickness of the transition hard mask layer 231 may fall within the range of 1:4 to 2:5. For example, the ratio of the transition depth of the transition opening 232 to the thickness of the transition hard mask layer 231 may be 1:4, 3:10, or 2:5.

[0079] S322: Remove the protective layer.

[0080] Please see Figure 15 Since the size of critical dimensions in the patterned layer is mainly determined by the opening of the second hard mask layer, subsequent etching processes have little impact on the size of critical dimensions in the patterned layer. Furthermore, because the protective layer and the transition hard mask layer 231 are made of different materials, if the protective layer is retained throughout the etching process of the transition hard mask layer 231, impurity particles of different materials generated during etching may cause connection failure between different conductive layers. Therefore, to reduce impurity particles generated during etching, the protective layer can be removed after the first etching step.

[0081] In related technologies, after the first etching is completed, oxygen or carbon tetrafluoride is typically used to remove impurity particles generated during the first etching process. However, oxygen and carbon tetrafluoride are difficult to remove the protective layer without damaging the transition opening morphology. Therefore, in this embodiment, trifluoromethane (CHF3) and fluorocarbon compounds (C) can be used. x F y The protective layer is removed by a reaction between the material and the protective layer. For details, please refer to Formula 1. Trifluoromethane and fluorocarbons can react with a protective layer made of silicon oxide to produce silicon tetrafluoride (SiF4) gas and carbon oxides.

[0082] CHF3+C x F y +Si-O→SiF4(g)+C x O y Formula 1

[0083] In fluorocarbon compounds, the number of carbon atoms and fluorine atoms can have various correspondences. For example, a fluorocarbon compound can be octafluorocyclobutane (C4F8).

[0084] It is worth noting that researchers have found through experiments that in the process of removing the protective layer using trifluoromethane and fluorocarbon compounds, an excessively long reaction time may cause damage to the morphology of the transition opening 232, which in turn leads to a reduction in the uniformity of the critical dimensions of the patterned layer. Therefore, in some embodiments, it is necessary to control the reaction time of the process of removing the protective layer to be within a reasonable time range.

[0085] S333: The transition hard mask layer is etched a second time based on the transition opening to form a first hard mask layer opening that penetrates the transition hard mask layer.

[0086] Please see Figure 16 To improve the transfer accuracy of the etched pattern, after removing the protective layer, a second etching can be performed on the transition hard mask layer to form an opening 233 in the first hard mask layer that exposes the patterned material layer 220. The remaining material of the transition hard mask layer can form the etched pattern 234 of the first hard mask layer.

[0087] To improve the verticality of the etching profile of the first hard mask layer etching pattern 234 formed by the second etching, in this embodiment, during the second etching of the transition hard mask layer based on the transition opening, the bias power of the radio frequency power supply can be controlled to be less than 100 watts (W). This controls the etching rate of the plasma along the normal direction of the patterned material layer 220 to be greater than the etching rate perpendicular to the normal direction of the patterned material layer 220, reducing the impact of the second etching on the side of the first hard mask layer opening 233. Specifically, the direction perpendicular to the normal direction of the patterned material layer 220 is used as the width direction of the transition opening and the first hard mask layer opening 233. Along this width direction, the width of the first hard mask layer opening 233 can be determined by the width of the transition opening.

[0088] In this embodiment, the other process parameters used for the second etching, such as etching plasma and pressure in the etching reaction chamber, can be the process parameters used for etching amorphous carbon layers in related technologies, and will not be elaborated here.

[0089] S340: The patterned material layer is etched based on the opening of the first hard mask layer to obtain the semiconductor structure.

[0090] To improve the pattern accuracy of the patterned layer and improve the taper of the patterned structure included in the patterned layer, the patterned material layer can be etched based on the opening of the first hard mask layer with high etching profile flatness.

[0091] Please see Figure 17 In this embodiment, etching the patterned material layer based on the opening of the first hard mask layer can include: etching the patterned material layer based on the opening of the first hard mask layer to form a patterned layer 221. Specifically, the patterned layer 221 can include multiple patterned structures 221a, with the normal direction of the substrate 210 as the height direction of the patterned structure 221a, and the direction perpendicular to the normal direction of the substrate 210 as the width direction of the patterned structure 221a. The ratio of the dimension of the patterned structure 221a along the height direction to the dimension of the patterned structure 221a along the width direction can be greater than 8. The opening between adjacent patterned structures 221a can serve as a via opening for forming vias.

[0092] One embodiment of this application provides a semiconductor structure 300, which can be manufactured by the semiconductor structure manufacturing method described in any of the above embodiments.

[0093] Please refer to the following: Figures 17 to 19 .exist Figure 18In the image, the white dashed line can be used to represent the boundary between the patterned layer 221 and the substrate 210. As can be seen from the multi-view microscopic images of the semiconductor structure 300, in the semiconductor structure 300 manufactured by the above-described semiconductor structure manufacturing method, the sides of the multiple patterned structures 221a in the patterned layer 221 are nearly perpendicular to the substrate 210, and the edges of the etched patterns corresponding to the via openings are clear, with good uniformity in local critical dimensions.

[0094] The technical effects of the semiconductor structure described in the above embodiments can be explained by referring to other embodiments of this application, and will not be repeated here.

[0095] Another embodiment of this application provides a semiconductor device, which may include: a semiconductor structure as described in the above embodiments, or a semiconductor structure manufactured by the manufacturing method of the semiconductor structure as described in the above embodiments.

[0096] The technical effects of the semiconductor devices described in the above embodiments can be explained by referring to other embodiments of this application, and will not be repeated here.

[0097] In this embodiment, for fabricating patterns with an aspect ratio greater than 8 at process nodes of 65nm and below, a substrate is provided comprising a substrate and a patterned material layer, a first hard mask layer, and a second hard mask layer sequentially formed on the substrate surface. During the etching of the second hard mask layer to form an opening in the second hard mask layer that exposes the first hard mask layer, a protective layer of a different material from the first hard mask layer is formed on the side of the opening in the second hard mask layer using the resulting etching byproducts. Subsequently, the first hard mask layer is etched based on the opening in the second hard mask layer to form an opening in the first hard mask layer that exposes the patterned material layer, and based on the first hard mask layer... A patterned material layer is etched through an opening in a hard mask layer to obtain a semiconductor structure. Unexpected effects achieved include: because a protective layer formed by etching byproducts is introduced during the etching of the second hard mask layer, and the etching rate of the first hard mask layer material is greater than the etching rate of the protective layer material during the etching of the first hard mask layer, the defects in the etching pattern of the first hard mask layer formed by etching the first hard mask layer can be reduced under the action of the protective layer, the local critical dimension uniformity of the patterned layer formed by etching the patterned material layer through the opening in the first hard mask layer can be improved, and the etching profile of the patterned layer can be improved.

[0098] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0099] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0100] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0101] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0102] As should be understood from the several embodiments provided in this application, the disclosed semiconductor structures and devices can be implemented in other ways. For example, the embodiments of semiconductor structures and devices described above are merely illustrative.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; The substrate includes a substrate, a patterned material layer formed on the surface of the substrate, a first hard mask layer formed on the surface of the patterned material layer away from the substrate, and a second hard mask layer formed on the surface of the first hard mask layer away from the substrate; wherein the first hard mask layer and the second hard mask layer are made of different materials; The second hard mask layer is etched to form an opening in the second hard mask layer that exposes the first hard mask layer; wherein the plasma used to etch the second hard mask layer includes silicon tetrachloride; during the etching of the second hard mask layer, the reaction temperature falls within the range of 35°C to 40°C, and a protective layer is formed on the side of the opening in the second hard mask layer using the resulting etching byproducts; the protective layer is made of a different material than the first hard mask layer. Etching the first hard mask layer based on the opening of the second hard mask layer to form a first hard mask layer opening that exposes the patterned material layer includes: performing a first etching on the first hard mask layer based on the second hard mask layer opening to form a transition opening, resulting in a transition hard mask layer; wherein the transition opening has a bottom surface formed of the material of the first hard mask layer; removing the protective layer; performing a second etching on the transition hard mask layer based on the transition opening to form the first hard mask layer opening penetrating the transition hard mask layer; during the etching of the first hard mask layer, the etching rate of the material of the first hard mask layer is greater than the etching rate of the material of the protective layer; The patterned material layer is etched based on the opening of the first hard mask layer to obtain the semiconductor structure.

2. The method according to claim 1, characterized in that, The first hard mask layer is made of amorphous carbon; the protective layer is made of silicon oxide; and the second hard mask layer is made of oxide.

3. The method according to claim 1, characterized in that, The protective layer is removed by reacting trifluoromethane with fluorocarbons and the material of the protective layer.

4. The method according to claim 1, characterized in that, During the second etching of the transition hard mask layer based on the transition opening, the bias power of the RF power supply is less than 100 watts.

5. The method according to claim 1, characterized in that, Etching the patterned material layer based on the opening in the first hard mask layer includes: The patterned material layer is etched based on the opening of the first hard mask layer to form a patterned layer; wherein the patterned layer includes a plurality of patterned structures, with the normal direction of the substrate as the height direction of the patterned structure, and the direction perpendicular to the normal direction of the substrate as the width direction of the patterned structure, and the ratio of the dimension of the patterned structure along the height direction to the dimension of the patterned structure along the width direction is greater than 8.

6. A semiconductor structure, characterized in that, The semiconductor structure is manufactured by the semiconductor structure manufacturing method as described in any one of claims 1 to 5.

7. A semiconductor device, characterized in that, The semiconductor device includes a semiconductor structure manufactured by the manufacturing method of any one of claims 1 to 5 or a semiconductor structure as described in claim 6.

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