High-thermal-conductivity boron arsenide ceramic substrate and preparation method and application thereof

Abstract

The invention discloses a high-thermal-conductivity boron arsenide ceramic substrate and a preparation method and application thereof, and relates to the technical field of microelectronic materials. According to the high-thermal-conductivity boron arsenide ceramic substrate provided by the invention, the buffer layer of which the thermal expansion coefficient is within a specific range is introduced between the boron arsenide substrate and the conductive layer for transition, and the thickness of the buffer layer is controlled according to the difference of the thermal expansion coefficients of materials on two sides of the buffer layer, so that the stress between layers in the ceramic substrate can be reduced, and the thermal conductivity of the ceramic substrate is improved. And the long-acting stability of the substrate is improved while the excellent heat-conducting property is considered.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic materials, and in particular to a high thermal conductivity boron arsenide ceramic substrate and a preparation method and application thereof. Background Art

[0002] With the advancement of technology, high-power chips are becoming increasingly widely used in fields such as consumer electronics, aerospace, and high-performance computing, placing higher demands on heat dissipation technology. The substrate is the foundational material for chip packaging, providing physical support and electrical connections for the chip. During the packaging process, the chip is secured to the substrate and electrically connected to the substrate through methods such as soldering. Therefore, improving the heat dissipation performance of the chip first requires improving the heat dissipation performance of the substrate. However, existing substrates, typically based on ceramics (such as alumina and aluminum nitride), have significant shortcomings in heat dissipation: the thermal conductivity of alumina is only 20-30 W / m K. While the thermal conductivity of aluminum nitride has improved (approximately 170-220 W / m K), it is still insufficient compared to the heat generated by high-power chips during use. This inefficient heat dissipation makes it difficult to conduct heat quickly, easily leading to localized heat accumulation, which in turn affects the stability and service life of the chip.

[0003] Using a boron arsenide ceramic substrate with a higher thermal conductivity (1300W / m K) to construct a substrate is a feasible way to improve the thermal conductivity of the substrate. However, the ceramic substrate needs to be covered with a metal conductive layer before it is made into a substrate. Commonly used conductive layer materials, for example, have a high thermal expansion coefficient (for example, the thermal expansion coefficient of copper reaches ~16.5×10 -6 / K, silver reaches ~19×10 -6 / K), which is more than three times different from the thermal expansion coefficient of boron arsenide (the thermal expansion coefficient of boron arsenide is ~4.5×10 -6 The strain mismatch between the two during heating can weaken the bonding between the conductive layer and the substrate, reducing the reliability of the chip during long-term use. Therefore, there is an urgent need to develop a high-thermal-conductivity boron arsenide ceramic substrate that combines excellent thermal conductivity with long-term stability. Summary of the Invention

[0004] To address the shortcomings of the existing technology, the present invention provides a high thermal conductivity boron arsenide ceramic substrate. A buffer layer with a thermal expansion coefficient within a specific range is introduced as a transition between the boron arsenide base and the conductive layer. The thickness of the buffer layer is controlled according to the difference in thermal expansion coefficients of the materials on both sides of the buffer layer. This can reduce the stress between the layers within the ceramic substrate, thereby improving the long-term stability of the substrate while maintaining excellent thermal conductivity.

[0005] Another object of the present invention is to provide a method for preparing a high thermal conductivity boron arsenide ceramic substrate.

[0006] Another object of the present invention is to provide an application of a high thermal conductivity boron arsenide ceramic substrate.

[0007] The above-mentioned purpose of the present invention is achieved through the following technical solutions:

[0008] A high thermal conductivity boron arsenide ceramic substrate, comprising a boron arsenide base layer, a buffer layer and a conductive layer sequentially covering the surface of the boron arsenide base layer;

[0009] The buffer layer includes one or more component layers n, and the thermal expansion coefficient of the component layer is 6×10 -6 / K~13×10 -6 / K;

[0010] The difference in thermal expansion coefficient between the conductive layer and the adjacent component layer is 3×10 -6 / K~10×10 -6 / K;

[0011] In the high thermal conductivity boron arsenide ceramic substrate, the thermal expansion coefficients of different layers increase sequentially from the boron arsenide base layer to the conductive layer;

[0012] The thermal expansion coefficient of the adjacent lower layer of any component layer is α1, and the thermal expansion coefficient of the adjacent upper layer is α2. Calculated by Δα=|α1-α2|, any component layer in the buffer layer satisfies the following relationship:

[0013] Δα≤5×10 -6 / K, h=2~5μm;

[0014] 5×10 -6 / K<Δα≤10×10 -6 / K, h=5~10μm;

[0015] Δα>10×10 -6 / K, h=10-20 μm; h is the thickness of any component layer n.

[0016] The present application adopts boron arsenide as the substrate in the high thermal conductivity boron arsenide ceramic substrate, which gives the substrate a higher thermal conductivity, enabling it to play an efficient heat dissipation function after the high-power chip is made. However, due to the mismatch of thermal expansion coefficients between the conductive layer and the boron arsenide substrate in the substrate, directly covering the conductive layer on the surface of the boron arsenide substrate will cause the obtained high thermal conductivity boron arsenide ceramic substrate to undergo interface cracking due to internal stress accumulation under long-term use, and the long-term stability of the substrate is insufficient. Based on this, the present application introduces a buffer layer having one or more component layers in the ceramic substrate and the conductive layer, wherein the thermal expansion coefficients of the different layers increase successively along the direction from the boron arsenide base layer to the conductive layer. Thus, the present application can not only optimize the heat conduction path, thereby further improving the thermal conductivity of the obtained high thermal conductivity boron arsenide ceramic substrate, but also improve the long-term stability of the substrate. Specifically, the addition of the buffer layer can relieve the interfacial stress between the substrate and the conductive layer in the substrate through the gradual transition of the thermal expansion coefficient, thereby improving the bonding strength and reliability of the boron arsenide substrate and the metal conductive layer. Among them, the buffer layer can include one or more component layers. However, after the buffer layer is introduced into the substrate, it replaces the original conductive layer-boron arsenide substrate interface, forming a new stress source. The stress caused by the buffer layer is affected by the difference in thermal expansion coefficient Δα between the two adjacent layers and its own thickness. The inventors of this application have found through extensive experimental research that the thickness h of any component layer in the buffer layer and the difference in thermal expansion coefficient Δα between the two adjacent layers satisfy Δα≤5×10 -6 / K, h=2~5μm; 5×10 -6 / K<Δα≤10×10 -6 / K, h=5~10μm; Δα>10×10 -6 / K, h=10~20μm, the internal stress in the obtained high thermal conductivity boron arsenide ceramic substrate can be fully reduced, thereby enabling the substrate to exhibit excellent long-term stability. This is because the greater the lattice mismatch between the two materials, the thicker the intermediate layer needs to be added to relieve the stress. It should be noted that the thickness of the component layer in the buffer layer will also affect the thermal resistance of the buffer layer. The higher the thickness, the higher the thermal resistance. Therefore, the thickness of the component layer in this application is determined after comprehensively considering the internal stress and thermal resistance.

[0017] In a specific embodiment of the present invention, when the component layer is adjacent to the base layer, the thermal expansion coefficient of the base layer is α1.

[0018] In a specific embodiment of the present invention, when the component layer is adjacent to the conductive layer, the thermal expansion coefficient of the conductive layer is α2.

[0019] Preferably, the thickness h of any component layer in the buffer layer and Δα satisfy the following relationship:

[0020] Δα≤5×10 -6 / K, h=3~4.5μm;

[0021] 5×10 -6 / K<Δα≤10×10 -6 / K, h=7~8μm;

[0022] Δα>10×10 -6 / K, h=13~15μm.

[0023] Preferably, the thermal expansion coefficient of the conductive layer is 16×10 -6 / K~23×10 -6 / K.

[0024] In a specific embodiment of the present invention, the conductive layer can be a single metal material, or an alloy or a composite material, such as an Ag-graphene layer.

[0025] Preferably, the conductive layer includes at least one of a copper layer, a silver layer, and an aluminum layer.

[0026] The conductive layer should have good conductive properties and be able to match the lattice of the buffer layer material as much as possible. Therefore, after comprehensively considering the thermal expansion coefficient and conductive properties, copper, silver, and aluminum are preferably used as the material of the conductive layer.

[0027] Preferably, the component layers in the buffer layer include at least one layer selected from the group consisting of an antimony layer, a beryllium layer, an iron layer, a platinum layer, a niobium layer, an aluminum oxide layer, a chromium layer, and a nickel layer.

[0028] The thermal expansion coefficients of the above layers are: antimony layer 10.5×10 -6 / K, beryllium layer 12.3×10 -6 / K, iron layer 12.2×10 -6 / K, platinum layer 9×10 -6 / K, niobium layer 7.3×10 -6 / K, aluminum oxide layer 6.5×10 -6 / K~8×10 -6 / K, chromium layer 6.2×10 -6 / K, nickel layer 13×10 -6 The thermal expansion coefficient of the above material is based on the difference between the conductive layer and the boron arsenide substrate, and it also has good thermal conductivity, so it can be used as a buffer layer material.

[0029] Preferably, the thickness of the boron arsenide base layer is 0.1-5 mm.

[0030] Preferably, the above thickness can ensure good thermal diffusion performance and provide sufficient mechanical strength to support the entire substrate.

[0031] Preferably, the thickness of the conductive layer is 10 to 5000 μm.

[0032] Preferably, the buffer layer has a thickness of 5 to 50 μm.

[0033] The preferred thickness of the buffer layer is 5 to 50 μm, which can effectively balance thermal stress and heat conduction requirements, ensuring good interface bonding, mechanical strength and thermal conductivity.

[0034] More preferably, the buffer layer includes 2 to 3 component layers.

[0035] Increasing the number of component layers can provide a smoother transition in thermal expansion coefficient, but it also increases the interface within the substrate, making heat conduction more difficult. Taking all factors into consideration, the present application preferably includes 2 to 3 component layers in the buffer layer.

[0036] More preferably, the component layers in the buffer layer include at least two layers selected from the group consisting of a beryllium layer, a chromium layer, and a platinum layer.

[0037] The present invention also provides a method for preparing the above-mentioned high thermal conductivity boron arsenide ceramic substrate, comprising the following steps:

[0038] A buffer layer and a conductive layer are sequentially deposited on the surface of a boron arsenide substrate to obtain a high thermal conductivity boron arsenide ceramic substrate.

[0039] In a specific embodiment of the present invention, when the buffer layer includes a single component layer, a buffer layer and a conductive layer are sequentially deposited on the surface of a boron arsenide substrate to obtain a high thermal conductivity boron arsenide ceramic substrate; when the buffer layer includes multiple component layers, each component layer is sequentially deposited on the surface of a boron arsenide substrate to form a buffer layer, and then a conductive layer is deposited on the surface of the buffer layer to obtain a high thermal conductivity boron arsenide ceramic substrate.

[0040] In a specific embodiment of the present invention, the deposition can be performed using conventional methods in the art, such as at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and electroplating. More specifically, the physical vapor deposition includes magnetron sputtering.

[0041] Preferably, the method further includes a pretreatment step before depositing the buffer layer on the surface of the boron arsenide substrate, and the pretreatment includes at least one of cleaning and roughening.

[0042] Cleaning and / or roughening processes can improve the adhesion of the buffer layer to the substrate and reduce interface defects. The roughening process increases the surface roughness of the substrate, thereby improving the mechanical adhesion of the buffer layer to the substrate surface; the cleaning process removes impurities and contaminants on the substrate surface, providing a high-quality interface for subsequent buffer layer deposition.

[0043] More preferably, the cleaning comprises at least one of acid cleaning, water cleaning, and UV light cleaning. More preferably, the acid cleaning is performed using dilute acid under ultrasonic conditions. More preferably, the dilute acid is dilute hydrofluoric acid with a concentration of 1 to 5 vol%, and the ultrasonication can be performed at an ultrasonic frequency conventional in the art. More preferably, the UV light cleaning treatment time is 5 to 10 minutes.

[0044] In a specific embodiment of the present invention, the cleaning step further includes a drying step, and the drying is performed in an inert atmosphere.

[0045] More preferably, the roughening is plasma roughening, and the plasma roughening is performed using Ar-H2 mixed plasma.

[0046] Preferably, the method further includes a post-processing step after depositing the buffer layer and / or the conductive layer, and the post-processing step includes at least one of annealing, hot pressing, induction heating, laser cladding, and welding.

[0047] The purpose of post-processing is to improve the bonding strength between the internal layers of high-thermal-conductivity boron arsenide ceramic substrates. Annealing ensures the diffusion of elements at the heterogeneous interface, forming new interface compounds, improving bonding strength, and optimizing the grain structure to further enhance the thermal conductivity of the ceramic substrate. Hot pressing achieves bonding through heating and pressure. Laser cladding uses high-energy lasers to locally melt the material interface, forming a metallurgical bond. Welding utilizes solder to promote the diffusion and bonding of interface materials.

[0048] More preferably, the temperature of the annealing after the buffer layer is deposited is 800-1000° C. More preferably, the time of the annealing after the buffer layer is deposited is 25-35 minutes.

[0049] More preferably, the annealing temperature after depositing the conductive layer is 200-300°C.

[0050] More preferably, the hot pressing temperature is 300-600° C., the pressure is 20-80 MPa, and the holding time is 10-60 min.

[0051] More preferably, the frequency of the induction heating is 50-400 kHz, the heating temperature is 200-500° C., and the heating time is 10-300 s.

[0052] More preferably, the laser power of the laser cladding is 500-1500 W, the scanning speed is 5-20 mm / s, the spot diameter is 1-3 mm, and the shielding gas is argon.

[0053] More preferably, the welding comprises at least one of laser welding, electron beam welding, ultrasonic welding, and arc welding.

[0054] More preferably, the solder comprises at least one of a Sn-Ag alloy and an In-based alloy. Using the aforementioned solder with a relatively low melting point as a medium and melting it by heating or other means to form solder joints on the interfaces within the substrate can promote bonding between interfaces and element diffusion, thereby generating chemically bonded interface compounds.

[0055] More preferably, the welding is ultrasonic welding. More preferably, the ultrasonic welding has an ultrasonic frequency of 20 to 40 kHz, a welding pressure of 50 to 100 MPa, a welding temperature of 100 to 300° C., and a welding time of 5 to 10 seconds.

[0056] The present invention also protects the application of the above-mentioned high thermal conductivity boron arsenide ceramic substrate in the field of microelectronic materials.

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] The high thermal conductivity boron arsenide ceramic substrate provided by the present invention achieves a reduction in both thermal resistance and internal stress by introducing a buffer layer having one or more component layers between the conductive layer and the base layer. Not only does it have excellent thermal conductivity, but also, due to the lower internal stress during use, it is less likely to experience interface cracking, shedding, and the like, and has excellent long-term stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Schematic diagram of the structure of the high thermal conductivity boron arsenide ceramic substrate in the present invention. DETAILED DESCRIPTION

[0060] The present invention will be further described below in conjunction with specific embodiments, but the examples do not limit the present invention in any form. Unless otherwise specified, the raw materials and reagents used in the examples of the present invention are conventionally purchased raw materials and reagents. Among them, the raw material information used in each example and comparative example is as follows:

[0061] Beryllium: Commercially available, with a thermal expansion coefficient of 12.3×10 -6 / K.

[0062] Platinum: Commercially available, with a thermal expansion coefficient of 9×10 -6 / K.

[0063] Chromium: Commercially available, with a thermal expansion coefficient of 6.2×10 -6 / K.

[0064] Copper: Commercially available, with a thermal expansion coefficient of 16.5×10 -6 / K.

[0065] Boron arsenide: commercially available, with a thermal expansion coefficient of 4.5×10 -6 / K.

[0066] Examples 1 to 5

[0067] This embodiment provides a series of high thermal conductivity boron arsenide ceramic substrates including two layers in the buffer layer, wherein the two layers have different thicknesses and materials, and include a boron arsenide base layer with a thickness of 0.5 mm, a buffer layer sequentially covering the surface of the boron arsenide base layer, and a copper layer with a thickness of 100 μm;

[0068] In the high thermal conductivity boron arsenide ceramic substrate, the thermal expansion coefficients of different layers increase sequentially along the direction from the boron arsenide base layer to the conductive layer.

[0069] The method for preparing the high thermal conductivity boron arsenide ceramic substrate in this embodiment includes the following steps:

[0070] The surface of the boron arsenide substrate was pickled using a 2 vol% hydrofluoric acid aqueous solution, then rinsed with water and dried under a nitrogen environment. The substrate surface was treated with an Ar-H2 mixed plasma, and then the component layers of the buffer layer were sequentially deposited on the surface of the boron arsenide substrate using magnetron sputtering technology. After the buffer layer was deposited, it was annealed at 900°C for 30 minutes, and then a copper layer was deposited on the surface of the buffer layer by electroplating. The electroplating solution composition was: 150g / L CuSO4+75g / L H2SO4, and the current density during electroplating was 2A / dm 2 .

[0071] The composition of the buffer layer in this embodiment, the difference in thermal expansion coefficient Δα between the two sides of each component layer, and the thickness h are shown in Table 1 below:

[0072] Table 1. Composition and thickness of the buffer layer in Examples 1 to 5

[0073]

[0074] Note: In Table 1 above, the calculation method of the difference in thermal expansion coefficient Δα between two layers adjacent to any component layer is described using Example 1 as an example: In Example 1, the lower layer adjacent to the chromium layer is a boron arsenide base layer, and its thermal expansion coefficient is 4.5×10 -6 / K; the upper layer adjacent to the chromium layer is the platinum layer, and the thermal expansion coefficient is 9×10 -6 / K; therefore, the difference in thermal expansion coefficient between the two layers adjacent to the chromium layer, that is, the difference in thermal expansion coefficient between the platinum layer and the boron arsenide base layer, is 4.5×10 -6 / K; In Example 1, the lower layer adjacent to the platinum layer is a chromium layer, and the thermal expansion coefficient is 6.2×10 -6 / K; the upper layer adjacent to the platinum layer is a copper conductive layer with a thermal expansion coefficient of 16.5×10 -6 / K; therefore, the difference in thermal expansion coefficient between the two layers adjacent to the platinum layer, that is, the difference in thermal expansion coefficient between the chromium layer and the copper conductive layer, is 10.3×10 -6 / K.

[0075] Example 6

[0076] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0077] The buffer layer includes three layers, namely, a chromium layer, a platinum layer, and a beryllium layer, in sequence from the base layer to the conductive layer, with thicknesses of 4.5 μm, 8 μm, and 8 μm, respectively.

[0078] The method for preparing the high thermal conductivity boron arsenide ceramic substrate in this embodiment is carried out according to that in Example 1.

[0079] Comparative Example 1

[0080] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0081] The thickness of the chromium layer is 8 μm.

[0082] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0083] Comparative Example 2

[0084] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0085] The thickness of the chromium layer is 1 μm.

[0086] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0087] Comparative Example 3

[0088] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0089] The platinum layer thickness is 8 μm.

[0090] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0091] Comparative Example 4

[0092] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0093] The platinum layer thickness is 25 μm.

[0094] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0095] Comparative Example 5

[0096] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 3 only in that:

[0097] The thickness of the chromium layer is 4.5 μm.

[0098] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0099] Comparative Example 6

[0100] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 3 only in that:

[0101] The thickness of the chromium layer is 15 μm.

[0102] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0103] Comparative Example 7

[0104] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 3 only in that:

[0105] The beryllium layer thickness is 8 μm.

[0106] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0107] Comparative Example 8

[0108] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 3 only in that:

[0109] The beryllium layer thickness is 25 μm.

[0110] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0111] Comparative Example 9

[0112] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0113] The buffer layer includes three layers, namely, a chromium layer, a platinum layer, and a beryllium layer, in sequence from the base layer to the conductive layer, with thicknesses of 10 μm, 8 μm, and 8 μm, respectively.

[0114] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0115] Comparative Example 10

[0116] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0117] The buffer layer includes three layers, namely, a chromium layer, a platinum layer, and a beryllium layer, in sequence from the base layer to the conductive layer, with thicknesses of 1 μm, 8 μm, and 8 μm, respectively.

[0118] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0119] Comparative Example 11

[0120] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0121] The buffer layer includes three layers, namely, a chromium layer, a platinum layer, and a beryllium layer, in sequence from the base layer to the conductive layer, with thicknesses of 4.5 μm, 12 μm, and 8 μm, respectively.

[0122] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0123] Comparative Example 12

[0124] A high thermal conductivity boron arsenide ceramic substrate, which differs from Example 1 only in that:

[0125] The buffer layer includes three layers, namely, a chromium layer, a platinum layer, and a beryllium layer, in sequence from the base layer to the conductive layer, with thicknesses of 4.5 μm, 8 μm, and 12 μm, respectively.

[0126] The preparation method of the high thermal conductivity boron arsenide ceramic substrate in this comparative example was carried out according to that in Example 1.

[0127] Performance Testing

[0128] Thermal conductivity test: Finite element analysis (FEA) simulation is used to obtain the effect of the buffer layer on the thermal stress relief of the interface, and the corresponding thermal resistance is calculated. The smaller the thermal resistance, the better the thermal conductivity. The finite element analysis parameters are set as follows: the chip power is set to 50W, the bottom is set to a constant temperature surface, and the convection heat transfer coefficient with air is set to 30W / (m 2 ·K), and the bottom is set as a fixed constraint. After the junction temperature is obtained by simulation, the thermal resistance is calculated according to the following formula:

[0129] R th =ΔT / P;

[0130] Among them, R th is the thermal resistance, ΔT is the temperature difference between the base layer and the conductive layer at both ends of the buffer layer, and P is the chip power. The thermal resistance value calculated from the above formula is rounded to four decimal places.

[0131] Internal Stress Test: Finite Element Analysis (FEA) is used to simulate the internal stress of each component layer in the buffer layer. The FEA procedure is the same as that for the thermal resistance test.

[0132] The test data is shown in Table 2 below:

[0133] Table 2. Thermal resistance and internal stress test data of examples and comparative examples

[0134]

[0135]

[0136] It should be noted that in the ceramic substrates provided in the embodiments of the present invention and the comparative examples, the stress of the component layer directly adjacent to the base layer in the buffer layer does not change significantly because the thickness of the base layer remains unchanged. Therefore, the present invention mainly focuses on the stress changes of the component layer in the conductive layer and the buffer layer that is not directly adjacent to the base layer.

[0137] As can be seen from Table 2 above, the high thermal conductivity boron arsenide ceramic substrate provided by the present invention achieves a reduction in both thermal resistance and internal stress by introducing a buffer layer having one or more constituent layers between the conductive layer and the base layer. This not only provides excellent thermal conductivity, but also, due to the lower internal stress during use, is less prone to interfacial cracking and shedding, and exhibits excellent long-term stability.

[0138] It should be noted that the buffer layer materials used in each embodiment are not exactly the same, and based on the characteristics of the material itself, the thermal resistance and internal stress exhibited by the ceramic substrate will be different. Therefore, when the buffer layer materials are not exactly the same, it is difficult to make a direct comparison. However, by comparing the performance data of ceramic substrates with exactly the same buffer layer composition, it can be seen that the buffer layer constructed with platinum layers and chromium layers of different thicknesses as constituent layers (Examples 1 to 2, Comparative Examples 1 to 4), when both layers satisfy the relationship proposed by the present invention (Examples 1 to 2), the thermal resistance of the ceramic substrate can be reduced to below 0.8263 K / W, and the average internal stress can be reduced to below 85.113 MPa. According to Comparative Examples 1 to 4, the thickness of the two layers is too large or too small, respectively, which will result in the inability to take into account both thermal resistance and internal stress at the same time.

[0139] By comparison with ceramic substrates having a buffer layer composed of a chromium layer and a beryllium layer (Examples 3 to 5, Comparative Examples 5 to 8), it can be seen that when the thicknesses of the two layers satisfy the relationship proposed by the present invention (Examples 3 to 5), the thermal resistance of the ceramic substrate can be reduced to below 0.8516 K / W, and the average internal stress can be reduced to below 138.186 MPa. At the same time, if the thickness of any layer does not satisfy the corresponding relationship, it will result in the inability to achieve both lower thermal resistance and lower stress.

[0140] By comparison with ceramic substrates (Example 6 and Comparative Examples 9-12) in which a buffer layer is formed by three layers consisting of a chromium layer, a platinum layer, and a beryllium layer, it can be seen that when the thickness of each of the three layers and the difference in thermal expansion coefficient Δα between the two adjacent layers all meet the relationship of the present invention, a thermal resistance reduced to below 0.8400 K / W and an internal stress of 124.5113 MPa can be obtained. Ceramic substrates that do not meet the relationship of the present invention are also unable to achieve a simultaneous reduction in thermal resistance and internal stress.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A high thermal conductivity boron arsenide ceramic substrate, characterized in that: It includes a boron arsenide base layer, a buffer layer and a conductive layer sequentially covering the surface of the boron arsenide base layer; The buffer layer includes one or more component layers n, and the thermal expansion coefficient of the component layer is 6×10 -6 / K~13×10 -6 / K; The difference in thermal expansion coefficient between the conductive layer and the adjacent component layer is 3×10 -6 / K~10×10 -6 / K; In the high thermal conductivity boron arsenide ceramic substrate, the thermal expansion coefficients of different layers increase sequentially from the boron arsenide base layer to the conductive layer; The thermal expansion coefficient of the adjacent lower layer of any component layer is α1, and the thermal expansion coefficient of the adjacent upper layer is α2. Calculated by Δα=|α1-α2|, any component layer in the buffer layer satisfies the following relationship: Δα≤5×10 -6 / K,h=2~5μm; 5×10 -6 / K<Δα≤10×10 -6 / K,h=5~10μm; Δα>10×10 -6 / K, h=10-20 μm; h is the thickness of any component layer n.

2. The high thermal conductivity boron arsenide ceramic substrate according to claim 1, characterized in that: Include at least one of the following (a) to (c): (a) The thermal expansion coefficient of the conductive layer is 16×10 -6 / K~23×10 -6 / K; (b) the conductive layer comprises at least one of a copper layer, a silver layer, and an aluminum layer; (c) The component layers in the buffer layer include at least one layer selected from the group consisting of an antimony layer, a beryllium layer, an iron layer, a platinum layer, a niobium layer, an aluminum oxide layer, a chromium layer, and a nickel layer.

3. The high thermal conductivity boron arsenide ceramic substrate according to claim 1, characterized in that: The thickness of the boron arsenide base layer is 0.1-5 mm.

4. The high thermal conductivity boron arsenide ceramic substrate according to claim 1, wherein: The thickness of the conductive layer is 10 to 5000 μm.

5. The high thermal conductivity boron arsenide ceramic substrate according to any one of claims 1 to 4, characterized in that: The thickness of the buffer layer is 5 to 50 μm.

6. The high thermal conductivity boron arsenide ceramic substrate according to claim 5, characterized in that: The buffer layer includes 2 to 3 component layers.

7. The high thermal conductivity boron arsenide ceramic substrate according to claim 6, characterized in that: The component layers in the buffer layer include at least two layers of a beryllium layer, a chromium layer, and a platinum layer.

8. A method for preparing the high thermal conductivity boron arsenide ceramic substrate according to any one of claims 1 to 7, characterized in that: The steps include: A buffer layer and a conductive layer are sequentially deposited on the surface of a boron arsenide substrate to obtain a high thermal conductivity boron arsenide ceramic substrate.

9. The method for preparing a high thermal conductivity boron arsenide ceramic substrate according to claim 8, wherein: The method further includes a post-processing step after depositing the buffer layer and / or the conductive layer, wherein the post-processing step includes at least one of annealing, hot pressing, ultrasound, induction heating, laser cladding, and welding.

10. Use of the high thermal conductivity boron arsenide ceramic substrate according to any one of claims 1 to 7 in the field of microelectronic materials.

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