Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: a first metal interconnection layer comprises a first welding layer and a first interconnection layer, and the first welding layer is provided with a first projection pattern on a first surface; the second dielectric layer is located on the surfaces of the first dielectric layer and the first metal interconnection layer, the second metal interconnection layer is arranged in the second dielectric layer, and the second metal interconnection layer comprises a second welding layer located on the surface of the first welding layer and a plurality of first conductive plugs which are located on the surface of the first interconnection layer and are separated from one another. The second welding layer is provided with a second projection pattern on the first surface, an overlapping area exists between the first projection pattern and the second projection pattern, and the area ratio of the overlapping area to the first projection pattern is larger than a preset value; the second conductive plug penetrates through the first wafer from the second surface to the surface of the first welding layer; and the first surface of the second wafer is bonded with the first wafer, so that the warping probability of the first welding layer is reduced, and the over-current capability of the second conductive plug is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Through-Silicon-Via (TSV) technology is a core technology in three-dimensional electronic packaging (3D IC). It creates vertical connections between chips and wafers, enabling interconnection between chips. Unlike conventional IC packaging bonding and bump stacking technologies, TSV maximizes chip stacking density in three dimensions, minimizes overall size, and significantly improves chip speed and power consumption.

[0003] TSV technology differs significantly from conventional packaging techniques in that it can be integrated into various stages of the manufacturing process. Placing TSVs in the packaging production phase, often referred to as via-last, offers the distinct advantage of remaining consistent with existing integrated circuit processes and designs.

[0004] However, the structural performance formed by the existing Via-last through-silicon via technology needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the present invention provides a semiconductor structure comprising: a first wafer, the first wafer including a first surface and a second surface opposite to each other; a first dielectric layer located on the first surface and a first metal interconnection layer located within the first dielectric layer, the first metal interconnection layer including a first welding layer and a first interconnection layer, the first dielectric layer exposing the top surfaces of the first welding layer and the first interconnection layer, the first welding layer having a first projected pattern on the first surface; a second dielectric layer located on the surfaces of the first dielectric layer and the first metal interconnection layer, a second metal interconnection layer located within the second dielectric layer, the second metal interconnection layer including a second welding layer located on the surface of the first welding layer and a plurality of mutually separated first conductive plugs located on the surface of the first interconnection layer, the second welding layer having a second projected pattern on the first surface, the first projected pattern and the second projected pattern having an overlapping region, and an area ratio between the overlapping region and the first projected pattern being greater than a preset value; a second conductive plug extending from the second surface through the first wafer to the surface of the first welding layer; and a second wafer bonded to the first wafer facing the first surface.

[0007] Optionally, it also includes: a third dielectric layer located on the surface of the second dielectric layer and the surface of the second metal interconnection layer, the third dielectric layer having a third metal interconnection layer, the third metal interconnection layer including a third welding layer located on the surface of the second welding layer and a second interconnection layer located on the surfaces of several first conductive plugs.

[0008] Optionally, it also includes: several layers of interconnection structures located on the surface of the third dielectric layer and the third metal interconnection layer, each of the interconnection structures includes a fourth dielectric layer and a fifth dielectric layer located on the surface of the fourth dielectric layer, the fourth dielectric layer has several welding plugs located on the surface of the third welding layer, and several third conductive plugs located on the surface of the second interconnection layer, and the fifth dielectric layer has a fourth welding layer located on the surface of several of the welding plugs and a third interconnection layer located on the surface of several of the third conductive plugs.

[0009] Optionally, it also includes: a sixth dielectric layer located on the first surface, the sixth dielectric layer having a plurality of first bonding metal layers, and the sixth dielectric layer exposing a plurality of the first bonding metal layers; the second wafer includes a substrate wafer, a seventh dielectric layer located on the surface of the substrate wafer, the seventh dielectric layer having a plurality of second bonding metal layers, and the seventh dielectric layer exposing a plurality of the second bonding metal layers, the sixth dielectric layer and the seventh dielectric layer are bonded to each other, and a plurality of the first bonding metal layers and a plurality of the second bonding metal layers are bonded to each other.

[0010] Optionally, the first wafer includes a pad area and a main body area, the main body area has a number of device structures; the several device structures and the first interconnection layer are electrically interconnected; the first welding layer and the second welding layer are located on the pad area; the first interconnection layer and the several first conductive plugs are located on the main body area.

[0011] Accordingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a first wafer and a second wafer, wherein the first wafer includes a first surface and a second surface opposite to each other; forming a first dielectric layer and a first metal interconnection layer located within the first dielectric layer on the first surface, wherein the first metal interconnection layer includes a first welding layer and a first interconnection layer, wherein the first dielectric layer exposes the top surfaces of the first welding layer and the first interconnection layer, and the first welding layer has a first projection pattern on the first surface; forming a second dielectric layer on the surfaces of the first dielectric layer and the first metal interconnection layer, wherein the second dielectric layer has a second metal interconnection layer, and the second metal interconnection layer includes a first welding layer located on the surface of the first welding layer. The invention relates to a method for manufacturing a second metal interconnection layer, wherein the second welding layer has a second projection pattern on the first surface, the first projection pattern and the second projection pattern have an overlapping area, and the area ratio between the overlapping area and the first projection pattern is greater than a preset value; after forming the second metal interconnection layer, the first wafer and the second wafer are bonded with the first surface facing the second wafer; after the first wafer and the second wafer are bonded to each other, the first wafer is etched from the second surface to form a groove in the first wafer, and the bottom of the groove exposes the surface of the first welding layer; and a second conductive plug is formed in the groove.

[0012] Optionally, after forming the second metal interconnection layer and before the bonding process, it also includes: forming a third dielectric layer on the surface of the second dielectric layer and the surface of the second metal interconnection layer, the third dielectric layer having a third metal interconnection layer, the third metal interconnection layer including a third welding layer located on the surface of the second welding layer and a second interconnection layer located on the surfaces of several first conductive plugs.

[0013] Optionally, the formation process of the second metal interconnection layer and the third metal interconnection layer includes a damascene process or a dual damascene process.

[0014] Optionally, the method for forming the second dielectric layer, the third dielectric layer, the second metal interconnection layer, and the third metal interconnection layer includes: forming the third dielectric layer on the surface of the second dielectric layer after forming the second dielectric layer and before forming the second metal interconnection layer; forming a first trench and a plurality of first through-holes in the second dielectric layer, and a second trench and a third trench in the third dielectric layer, wherein the first trench and the second trench are located on the first welding layer and are interconnected, the third trench and the plurality of first through-holes are located on the first interconnection layer and are interconnected, and projections of the plurality of first through-holes on the first surface are within the projection range of the third trench on the first surface; forming a conductive material layer in the first trench, the plurality of first through-holes, the second trench, and the third trench; planarizing the conductive material layer until the third dielectric layer is exposed, forming the second welding layer with the conductive material layer in the first trench, forming the third welding layer with the conductive material layer in the second trench, forming the first conductive plug with the conductive material layer in each of the first through-holes, and forming the second interconnection layer with the conductive material layer in the third trench.

[0015] Optionally, the method for forming the first trench, the second trench, the third trench and the plurality of first through holes comprises: forming a patterned hard mask layer on the surface of the third dielectric layer, the hard mask layer having a first opening and a second opening exposing the surface of the third dielectric layer, the first opening being located on the first welding layer, and the second opening being located on a portion of the first interconnect layer; forming a photoresist layer in the second opening and on the surface of the hard mask layer, the photoresist layer exposing the first opening, and the photoresist layer in the second opening having a plurality of initial through holes, the plurality of the initial through holes exposing a portion of the surface of the third dielectric layer; using the photoresist layer as a mask, etching The third dielectric layer is etched until the second dielectric layer is exposed, and the second trench located on the first welding layer and a plurality of transition through holes located on a portion of the first interconnect layer are formed in the third dielectric layer; after the plurality of transition through holes are formed, the photoresist layer is removed; after the photoresist layer is removed, the third dielectric layer, the bottom of the first trench, and the second dielectric layer at the bottom of the plurality of transition through holes exposed by the hard mask layer are further etched using the hard mask layer as a mask until the first metal interconnect layer is exposed, the first trench and the plurality of through holes are formed in the second dielectric layer, and the second trench and the third trench are formed in the third dielectric layer.

[0016] Optionally, after forming the third metal interconnection layer and before the bonding process, several layers of interconnection structures are formed on the surface of the third dielectric layer and the third metal interconnection layer, each of the interconnection structures includes a fourth dielectric layer and a fifth dielectric layer located on the surface of the fourth dielectric layer, the fourth dielectric layer has several solder plugs located on the surface of the third solder layer, and several third conductive plugs located on the surface of the second interconnection layer, and the fifth dielectric layer has a fourth solder layer located on the surface of several of the solder plugs and a third interconnection layer located on the surface of several of the third conductive plugs.

[0017] Optionally, after forming the second metal interconnect layer and before the bonding process, a sixth dielectric layer is further formed on the first surface, wherein the sixth dielectric layer has a plurality of first bonding metal layers, and the sixth dielectric layer exposes a plurality of the first bonding metal layers; the second wafer includes a substrate wafer and a seventh dielectric layer located on the surface of the substrate wafer, wherein the seventh dielectric layer has a plurality of second bonding metal layers, and the seventh dielectric layer exposes a plurality of the second bonding metal layers.

[0018] Optionally, the bonding process further includes: bonding the sixth dielectric layer and the seventh dielectric layer to each other, and bonding a plurality of the first bonding metal layers and a plurality of the second bonding metal layers to each other.

[0019] Optionally, the first wafer includes a pad area and a main body area, the main body area has a number of device structures; the several device structures and the first interconnection layer are electrically interconnected; the first welding layer and the second welding layer are located on the pad area; the first interconnection layer and the several first conductive plugs are located on the main body area.

[0020] Optionally, after bonding the first wafer and the second wafer to each other and before forming the groove, the method further includes: thinning the first wafer from the second surface.

[0021] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] In the semiconductor structure provided by the technical solution of the present invention, the first solder layer has a first projected pattern on the first surface, the second metal interconnect layer includes a second solder layer located on the surface of the first solder layer and a plurality of first conductive plugs located on the surface of the first interconnect layer. The second solder layer has a second projected pattern on the first surface, the first projected pattern and the second projected pattern have an overlapping area, and the area ratio between the overlapping area and the first projected pattern is greater than a preset value. The first solder layer is used to connect to the second conductive plugs. There is no conductive plug between the first and second solder layers, but they are directly connected together, so that the first and second solder layers form a relatively thick metal layer. Therefore, the probability of warping of the first solder layer can be reduced during the process of forming the groove to expose the surface of the first solder layer. At the same time, the second conductive plugs are electrically connected to the relatively thick metal layer, which helps to improve the current carrying capacity of the second conductive plugs. In addition, only the structures of the first and second solder layers connected to the second conductive plugs are changed, while the structures of other chip areas are not changed, which does not affect the normal chip routing area and has high process compatibility.

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the first solder layer has a first projected pattern on the first surface, the second metal interconnect layer includes a second solder layer located on the surface of the first solder layer and a plurality of first conductive plugs located on the surface of the first interconnect layer. The second solder layer has a second projected pattern on the first surface, the first projected pattern and the second projected pattern have an overlapping area, and the area ratio between the overlapping area and the first projected pattern is greater than a preset value. The first solder layer is used to connect to the second conductive plugs. The first and second solder layers are directly connected together without a conductive plug between them, so that the first and second solder layers form a relatively thick metal layer. Therefore, the probability of warping of the first solder layer can be reduced during the process of forming the groove to expose the surface of the first solder layer. At the same time, the second conductive plugs are electrically connected to the relatively thick metal layer, which helps to improve the current carrying capacity of the second conductive plugs. In addition, only the structures of the first and second solder layers connected to the second conductive plugs are changed, while the structures of other chip areas are not changed, which does not affect the normal chip routing area and has high process compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 3 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0025] Figures 4 to 15 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0027] As the background technology, the structural performance formed by the existing through silicon via technology needs to be further improved. Now, the formation process of the semiconductor structure in a through silicon via process is explained and analyzed.

[0028] Figures 1 to 3 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0029] Please refer to Figure 1 A first wafer structure 100 and a second wafer structure 200 bonded to each other are provided, wherein the first wafer structure includes a first wafer (not shown), a first dielectric layer 101 located on a surface of the first wafer, and a first bonding metal layer 102 located within the first dielectric layer 101, wherein the first dielectric layer 101 exposes a surface of the first bonding metal layer 102, and the second wafer structure 200 includes a second wafer 201, a second dielectric layer 202 located on a surface of the second wafer 201, a plurality of metal interconnect layers located within the second dielectric layer 202, and a second bonding metal layer 203 electrically connected to the plurality of metal interconnect layers. The metal interconnect layers include a first metal layer 204, a plurality of first conductive plugs 205 located on the first metal layer 204, and a second metal layer 206 located on the plurality of first conductive plugs 205. The surface of the second dielectric layer 202 exposes the surface of the second bonding metal layer 203. The second wafer 201 also includes a first surface 201a and a second surface 201b opposite to each other. The second dielectric layer 202 is located on the surface of the first surface 201a. The first dielectric layer 101 and the second dielectric layer 202 are bonded to each other, and the first bonding metal layer 102 and the second bonding metal layer 203 are bonded to each other.

[0030] Please refer to Figure 2 , a mask layer (not shown in the figure) is formed on the surface of the second surface 201b of the second wafer 201; using the mask layer as a mask, the second wafer structure 200 is etched until the surface of the first metal layer 204 is exposed, and TSV through holes 207 are formed in the second wafer structure 200.

[0031] Please refer to Figure 3 , forming a conductive layer 208 in the TSV through hole 207 .

[0032] In the above-mentioned Via-last through silicon via process, after the TSV through hole 207 is formed, as the stress in the formation process of the TSV through hole 207 is released, the first metal layer 204 at the bottom of the TSV through hole 207 is prone to warping (e.g., Figure 2 As shown by the middle dotted line, a break occurs between the first metal layer 204 and the plurality of first conductive plugs 205, resulting in a short circuit, which seriously affects the electrical performance and performance stability of the final chip.

[0033] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein the first welding layer is used to connect the second conductive plug. There is no conductive plug between the first welding layer and the second welding layer, but they are directly connected together, so that the first welding layer and the second welding layer form a metal layer with a larger thickness. Therefore, in the process of forming a groove to expose the surface of the first welding layer, the probability of warping of the first welding layer can be reduced. At the same time, the second conductive plug is electrically connected to the metal layer with a larger thickness, which is beneficial to improving the current carrying capacity of the second conductive plug. In addition, only the structure of the first welding layer and the second welding layer connected to the second conductive plug is changed, without changing the structure of other chip areas, which does not affect the normal chip routing area and has high process compatibility.

[0034] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 4 to 15 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] Please refer to Figure 4 and Figure 5 , providing a first wafer 301 and a second wafer, wherein the first wafer 301 includes a first surface 301 a and a second surface 301 b opposite to each other.

[0037] In this embodiment, the first wafer 301 includes a pad region P and a main body region M. The main body region M has a plurality of device structures 302. The pad region P is used to define the positions of the first and second solder layers to be formed subsequently, while the main body region M is used to define the positions of the first interconnect layer and a plurality of first conductive plugs to be formed subsequently.

[0038] It should be noted that Figure 4 The device structure 302 shown in FIG. 3 is a transistor structure, which is for illustration only. Here, the device structures 302 may include transistors, diodes, triodes, capacitors, inductors, or conductive structures.

[0039] In this embodiment, the first wafer 301 also includes a substrate 300 and an interlayer dielectric layer 303 located on the substrate 300. The transistor includes a gate (not shown in the figure), a source region (not shown in the figure) and a drain region (not shown in the figure). The source region and the drain region are respectively located in the substrate 300 on both sides of the gate. The gate is located on the surface of the substrate 300 and in the interlayer dielectric layer 303. The substrate 300 also has an isolation structure 400, and the isolation structure 400 is located in the pad area P and between adjacent device structures 302.

[0040] In this embodiment, the second wafer includes a substrate wafer (not shown in the figure) and a seventh dielectric layer 401 located on the surface of the substrate wafer. The seventh dielectric layer 401 has a plurality of second bonding metal layers 402 therein, and the seventh dielectric layer 401 exposes a plurality of second bonding metal layers 402 .

[0041] Please refer to Figure 6 A first dielectric layer 304 and a first metal interconnection layer located within the first dielectric layer 304 are formed on the first surface 301a, wherein the first metal interconnection layer includes a first welding layer 305 and a first interconnection layer 306. The first dielectric layer 304 exposes the top surfaces of the first welding layer 305 and the first interconnection layer 306, and the first welding layer 305 has a first projection pattern on the first surface 301a.

[0042] In this embodiment, the plurality of device structures 302 and the first interconnection layer 306 are electrically interconnected.

[0043] In this embodiment, a first etch stop layer (not shown in the figure) is further formed between the first surface 301 a and the first dielectric layer 304 , and the first metal interconnection layer is also located within the first etch stop layer.

[0044] Subsequently, a second dielectric layer is formed on the surface of the first dielectric layer 304 and the first metal interconnection layer. The second dielectric layer has a second metal interconnection layer. The second metal interconnection layer includes a second welding layer located on the surface of the first welding layer 305 and a plurality of mutually separate first conductive plugs located on the surface of the first interconnection layer 306. The second welding layer has a second projected pattern on the first surface 301a. There is an overlapping area between the first projected pattern and the second projected pattern, and the area ratio between the overlapping area and the first projected pattern is greater than a preset value.

[0045] Subsequently, after forming the second metal interconnection layer, the first wafer 301 is bonded to the second wafer with the first surface 301 a facing the second wafer.

[0046] In this embodiment, after forming the second metal interconnection layer and before the bonding process, it also includes: forming a third dielectric layer on the surface of the second dielectric layer and the surface of the second metal interconnection layer, the third dielectric layer having a third metal interconnection layer, the third metal interconnection layer including a third welding layer located on the surface of the second welding layer and a second interconnection layer located on the surfaces of several first conductive plugs.

[0047] In this embodiment, the second metal interconnect layer and the third metal interconnect layer are formed in the same process, that is, the formation process of the second metal interconnect layer and the third metal interconnect layer includes a damascene process or a dual damascene process. In another embodiment, the second metal interconnect layer can be formed first, and then the third metal interconnect layer can be formed.

[0048] In this embodiment, the second metal interconnection layer and the third metal interconnection layer are formed using a dual damascene process.

[0049] In this embodiment, the formation method of the second dielectric layer, the third dielectric layer, the second metal interconnection layer and the third metal interconnection layer can be referred to Figures 7 to 11 .

[0050] Please refer to Figure 7 After forming the second dielectric layer 307 and before forming the second metal interconnection layer, the third dielectric layer 308 is formed on the surface of the second dielectric layer 307 .

[0051] In this embodiment, before forming the second dielectric layer 307 , a second etch stop layer (not shown in the figure) is formed on the surfaces of the first dielectric layer 304 and the first metal interconnection layer.

[0052] Subsequently, a first groove and several first through holes are formed in the second dielectric layer 307, and a second groove and a third groove are formed in the third dielectric layer 308. The first groove and the second groove are located on the first welding layer 305 and are interconnected. The third groove and several first through holes are located on the first interconnection layer 306 and are interconnected. The projections of the several first through holes on the first surface are within the projection range of the third groove on the first surface.

[0053] The first trench, the second trench, the third trench and the first through holes may be formed by a "VIA First Trench Last" method or a "Trench First VIA Last" method.

[0054] In this embodiment, the first trench, the second trench, the third trench and the plurality of first through holes are formed by a method of "trench first, then through hole". For details, please refer to Figures 8 to 10 .

[0055] Please refer to Figure 8 A patterned hard mask layer 309 is formed on the surface of the third dielectric layer 308, and the hard mask layer 309 has a first opening 310 and a second opening (not shown in the figure) that expose the surface of the third dielectric layer 308. The first opening 310 is located on the first welding layer 305, and the second opening is located on a portion of the first interconnection layer 306.

[0056] Please continue to refer to Figure 8 A photoresist layer 311 is formed in the second opening and on the surface of the hard mask layer 309, and the photoresist layer 311 exposes the first opening 310. The photoresist layer 311 in the second opening has a plurality of initial through holes 312, and the plurality of initial through holes 312 expose a portion of the surface of the third dielectric layer 308.

[0057] Please refer to Figure 9 , with the photoresist layer 311 (such as Figure 8 As shown in the figure, the third dielectric layer 308 is etched with a mask until the second dielectric layer 307 is exposed, and the second groove 313 located on the first welding layer 305 and a plurality of transition through holes 314 located on a portion of the first interconnection layer 306 are formed in the third dielectric layer 308; after the plurality of transition through holes 314 are formed, the photoresist layer 311 is removed.

[0058] Please refer to Figure 10 After removing the photoresist layer 311, the hard mask layer 309 is used as a mask to continue etching the third dielectric layer 308, the bottom of the second trench 313, and the second dielectric layer 307 at the bottom of the transition through-holes 314 exposed by the hard mask layer 309 until the first metal interconnection layer is exposed. The first trench 315 and the through-holes 317 are formed in the second dielectric layer 307, and the third trench 318 is formed in the third dielectric layer 308.

[0059] Please refer to Figure 11, forming a conductive material layer (not shown in the figure) in the first trench 315, the plurality of first through holes 317, the second trench 313 and the third trench 318; planarizing the conductive material layer until the third dielectric layer 308 is exposed, forming the second welding layer 319 with the conductive material layer in the first trench 315, forming the third welding layer 320 with the conductive material layer in the second trench 313, forming the first conductive plug 321 with the conductive material layer in each first through hole 317, and forming the second interconnection layer 322 with the conductive material layer in the third trench 318.

[0060] In this embodiment, the first welding layer 305 and the second welding layer 319 are located on the pad area P; the first interconnection layer 306 and the plurality of first conductive plugs 321 are located on the main area M.

[0061] Please refer to Figure 12 After forming the third metal interconnect layer and before the bonding process, several layers of interconnect structures are formed on the surfaces of the third dielectric layer 308 and the third metal interconnect layer. Each of the interconnect structures includes a fourth dielectric layer (not shown in the figure) and a fifth dielectric layer (not shown in the figure) located on the surface of the fourth dielectric layer. The fourth dielectric layer has several solder plugs 326 located on the surface of the third solder layer 320 and several third conductive plugs 327 located on the surface of the second interconnect layer 322. The fifth dielectric layer has a fourth solder layer 328 located on the surface of the several solder plugs 326 and a third interconnect layer 329 located on the surface of the several third conductive plugs 327.

[0062] In this embodiment, the plurality of interconnected layers constitute one layer. In other embodiments, the plurality of interconnected layers may not be formed, or may be configured as multiple layers according to actual needs.

[0063] Please refer to Figure 13 After forming the second metal interconnection layer and before the bonding process, a sixth dielectric layer 330 is further formed on the first surface 301a, wherein the sixth dielectric layer 330 has a plurality of first bonding metal layers 331 therein, and the sixth dielectric layer 330 exposes a plurality of first bonding metal layers 331.

[0064] Several first bonding metal layers 331 are respectively connected to the third welding layer 328 and several layers of interconnection structures.

[0065] Specifically, after forming several layers of interconnection structures, a sixth dielectric layer 330 is further formed on the first surface 301 a .

[0066] Please refer to Figure 14After forming the second metal interconnection layer, the first wafer 301 is bonded to the second wafer with the first surface 301 a facing the second wafer.

[0067] Specifically, after forming the sixth dielectric layer 330 and a plurality of first bonding metal layers 331 , the first surface 301 a is directed toward the surface of the seventh dielectric layer 401 of the second wafer, and the first wafer 301 and the second wafer are bonded.

[0068] In this embodiment, the bonding process further includes: bonding the sixth dielectric layer 330 and the seventh dielectric layer 401 to each other, and bonding a plurality of the first bonding metal layers 331 and a plurality of the second bonding metal layers 402 to each other.

[0069] Please refer to Figure 15 After the first wafer 301 and the second wafer are bonded to each other, the first wafer 301 is etched from the second surface 301b to form a groove (not shown in the figure) in the first wafer 301, and the bottom of the groove exposes the surface of the first welding layer 305; a second conductive plug 403 is formed in the groove.

[0070] At this point, the first welding layer 305 has a first projection pattern on the first surface 301a, the second metal interconnection layer includes a second welding layer 319 located on the surface of the first welding layer 305 and a plurality of mutually separated first conductive plugs 321 located on the surface of the first interconnection layer 306, the second welding layer 319 has a second projection pattern on the first surface 301a, there is an overlapping area between the first projection pattern and the second projection pattern, and the area ratio between the overlapping area and the first projection pattern is greater than a preset value, the first welding layer 305 is used to connect the second conductive plug 403, the first welding layer 305 and the second welding layer 319 are connected. There is no conductive plug, but they are directly connected together, so that the first welding layer 305 and the second welding layer 319 form a metal layer with a larger thickness. Therefore, in the process of forming the groove to expose the surface of the first welding layer 305, the probability of warping of the first welding layer 305 can be reduced. At the same time, the second conductive plug 403 is electrically connected to the metal layer with a larger thickness, which is beneficial to improving the current carrying capacity of the second conductive plug 403. In addition, only the structure of the first welding layer 305 and the second welding layer 319 connected to the second conductive plug 403 is changed, without changing the structure of other chip areas, and does not affect the normal chip routing area, with high process compatibility.

[0071] It should be noted that by limiting the preset value, the area between the overlapping region and the first projected pattern can be increased, thereby forming a thicker metal layer between the first welding layer 305 and the second welding layer 319. In this embodiment, the first projected pattern and the second projected pattern overlap, that is, the first welding layer 305 and the second welding layer 319 have the same size in a direction parallel to the first surface 301a.

[0072] In this embodiment, after the first wafer 301 and the second wafer are bonded to each other and before the grooves are formed, the first wafer 301 is thinned from the second surface 301 b .

[0073] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 15 , comprising: a first wafer 301, the first wafer 301 comprising a first surface 301a and a second surface 301b opposite to each other; a first dielectric layer 304 located on the first surface 301a and a first metal interconnection layer located within the first dielectric layer 304, the first metal interconnection layer comprising a first welding layer 305 and a first interconnection layer 306, the first dielectric layer 304 exposing the top surfaces of the first welding layer 305 and the first interconnection layer 306, the first welding layer 305 having a first projection pattern on the first surface 301a; a second dielectric layer 307 located on the surfaces of the first dielectric layer 304 and the first metal interconnection layer, the second dielectric layer 307 within A second metal interconnection layer, the second metal interconnection layer includes a second welding layer 319 located on the surface of the first welding layer 305 and a plurality of mutually discrete first conductive plugs 321 located on the surface of the first interconnection layer 306, the second welding layer 319 has a second projection pattern on the first surface 301a, there is an overlapping area between the first projection pattern and the second projection pattern, and the area ratio between the overlapping area and the first projection pattern is greater than a preset value; a second conductive plug 403 extending from the second surface 301b through the first wafer 301 to the surface of the first welding layer 305; and a second wafer bonded to the first wafer 301 toward the first surface 301a.

[0074] At this point, the first welding layer 305 has a first projection pattern on the first surface 301a, the second metal interconnection layer includes a second welding layer 319 located on the surface of the first welding layer 305 and a plurality of mutually separated first conductive plugs 321 located on the surface of the first interconnection layer 306, the second welding layer 319 has a second projection pattern on the first surface 301a, there is an overlapping area between the first projection pattern and the second projection pattern, and the area ratio between the overlapping area and the first projection pattern is greater than a preset value, the first welding layer 305 is used to connect the second conductive plug 403, the first welding layer 305 and the second welding layer 319 are connected. There is no conductive plug, but they are directly connected together, so that the first welding layer 305 and the second welding layer 319 form a metal layer with a larger thickness. Therefore, in the process of forming the groove to expose the surface of the first welding layer 305, the probability of warping of the first welding layer 305 can be reduced. At the same time, the second conductive plug 403 is electrically connected to the metal layer with a larger thickness, which is beneficial to improving the current carrying capacity of the second conductive plug 403. In addition, only the structure of the first welding layer 305 and the second welding layer 319 connected to the second conductive plug 403 is changed, without changing the structure of other chip areas, and does not affect the normal chip routing area, with high process compatibility.

[0075] In this embodiment, the semiconductor structure further includes: a third dielectric layer 308 located on the surface of the second dielectric layer 307 and the surface of the second metal interconnection layer, the third dielectric layer 308 having a third metal interconnection layer therein, the third metal interconnection layer including a third welding layer 320 located on the surface of the second welding layer 319 and a second interconnection layer 322 located on the surface of the plurality of first conductive plugs 321.

[0076] In this embodiment, the semiconductor structure further includes: several layers of interconnect structures located on the surfaces of the third dielectric layer 308 and the third metal interconnect layer, each of the interconnect structures including a fourth dielectric layer (not shown in the figure) and a fifth dielectric layer (not shown in the figure) located on the surface of the fourth dielectric layer, the fourth dielectric layer including several solder plugs 326 located on the surface of the third solder layer 320 and several third conductive plugs 327 located on the surface of the second interconnect layer 322, and the fifth dielectric layer including a fourth solder layer 328 located on the surface of the several solder plugs 326 and a third interconnect layer 329 located on the surface of the several third conductive plugs 327.

[0077] In this embodiment, the semiconductor structure further includes a sixth dielectric layer 330 located on the first surface 301 a . The sixth dielectric layer 330 has a plurality of first bonding metal layers 331 therein, and the sixth dielectric layer 330 exposes a plurality of first bonding metal layers 331 .

[0078] In this embodiment, the second wafer includes a substrate wafer (not shown in the figure) and a seventh dielectric layer 401 located on the surface of the substrate wafer. The seventh dielectric layer 401 has a plurality of second bonding metal layers 402, and the seventh dielectric layer 401 exposes a plurality of the second bonding metal layers 402. The sixth dielectric layer 330 and the seventh dielectric layer 401 are bonded to each other, and a plurality of the first bonding metal layers 331 and a plurality of the second bonding metal layers 402 are bonded to each other.

[0079] In this embodiment, the first wafer includes a pad area P and a main area M. The main area M has a plurality of device structures 302 . The plurality of device structures 302 and the first interconnection layer 306 are electrically interconnected.

[0080] In this embodiment, the first welding layer 305 and the second welding layer 319 are located on the pad area P; the first interconnection layer 306 and the plurality of first conductive plugs 321 are located on the main area M.

[0081] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a first wafer comprising a first side and a second side facing each other; a first dielectric layer located on the first surface and a first metal interconnection layer located within the first dielectric layer, the first metal interconnection layer including a first welding layer and a first interconnection layer, the first dielectric layer exposing top surfaces of the first welding layer and the first interconnection layer, the first welding layer having a first projection pattern on the first surface; a second dielectric layer located on the surfaces of the first dielectric layer and the first metal interconnection layer, a second metal interconnection layer within the second dielectric layer, the second metal interconnection layer comprising a second soldering layer located on the surface of the first soldering layer and a plurality of first conductive plugs separated from each other and located on the surface of the first interconnection layer, the second soldering layer having a second projected pattern on the first surface, an overlapping region between the first projected pattern and the second projected pattern, and an area ratio between the overlapping region and the first projected pattern being greater than a preset value; a second conductive plug extending from the second surface through the first wafer to the surface of the first welding layer; A second wafer is bonded to the first wafer facing the first surface.

2. The semiconductor structure according to claim 1, wherein Also includes: A third dielectric layer is located on the surface of the second dielectric layer and the surface of the second metal interconnection layer. The third dielectric layer has a third metal interconnection layer therein. The third metal interconnection layer includes a third welding layer located on the surface of the second welding layer and a second interconnection layer located on the surfaces of the first conductive plugs.

3. The semiconductor structure according to claim 2, wherein: Also includes: Several layers of interconnect structures are located on the surfaces of the third dielectric layer and the third metal interconnect layer, each of the interconnect structures includes a fourth dielectric layer and a fifth dielectric layer located on the surface of the fourth dielectric layer, the fourth dielectric layer has several solder plugs located on the surface of the third solder layer, and several third conductive plugs located on the surface of the second interconnect layer, and the fifth dielectric layer has a fourth solder layer located on the surface of several of the solder plugs and a third interconnect layer located on the surface of several of the third conductive plugs.

4. The semiconductor structure according to claim 1, wherein: Also includes: A sixth dielectric layer is located on the first surface, the sixth dielectric layer has a plurality of first bonding metal layers therein, and the sixth dielectric layer exposes a plurality of the first bonding metal layers; the second wafer includes a substrate wafer and a seventh dielectric layer located on a surface of the substrate wafer, the seventh dielectric layer has a plurality of second bonding metal layers therein, and the seventh dielectric layer exposes a plurality of the second bonding metal layers, the sixth dielectric layer and the seventh dielectric layer are bonded to each other, and the plurality of the first bonding metal layers and the plurality of the second bonding metal layers are bonded to each other.

5. The method for forming a semiconductor structure according to claim 1, wherein: The first wafer includes a pad area and a main body area, and the main body area has a plurality of device structures; the plurality of device structures and the first interconnection layer are electrically interconnected; the first welding layer and the second welding layer are located on the pad area; the first interconnection layer and the plurality of the first conductive plugs are located on the main body area.

6. A method for forming a semiconductor structure, characterized in that: include: Providing a first wafer and a second wafer, wherein the first wafer includes a first side and a second side facing each other; forming a first dielectric layer and a first metal interconnection layer located within the first dielectric layer on the first surface, wherein the first metal interconnection layer includes a first welding layer and a first interconnection layer, the first dielectric layer exposes top surfaces of the first welding layer and the first interconnection layer, and the first welding layer has a first projection pattern on the first surface; A second dielectric layer is formed on the surface of the first dielectric layer and the first metal interconnection layer, wherein the second dielectric layer has a second metal interconnection layer therein, the second metal interconnection layer comprising a second soldering layer located on the surface of the first soldering layer and a plurality of first conductive plugs separated from each other and located on the surface of the first interconnection layer, the second soldering layer having a second projected pattern on the first surface, an overlapping region between the first projected pattern and the second projected pattern, and an area ratio between the overlapping region and the first projected pattern being greater than a preset value; After forming the second metal interconnection layer, bonding the first wafer to the second wafer with the first surface facing the second wafer; After the first wafer and the second wafer are bonded to each other, etching the first wafer from the second surface to form a groove in the first wafer, wherein the bottom of the groove exposes the surface of the first welding layer; A second conductive plug is formed in the trench.

7. The method for forming a semiconductor structure according to claim 6, wherein: After forming the second metal interconnection layer and before the bonding process, the method further includes: forming a third dielectric layer on the surface of the second dielectric layer and the surface of the second metal interconnection layer, wherein the third dielectric layer has a third metal interconnection layer therein, and the third metal interconnection layer includes a third welding layer located on the surface of the second welding layer and a second interconnection layer located on the surfaces of the plurality of first conductive plugs.

8. The method for forming a semiconductor structure according to claim 7, wherein: The second metal interconnection layer and the third metal interconnection layer are formed by a damascene process or a dual damascene process.

9. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the second dielectric layer, the third dielectric layer, the second metal interconnection layer, and the third metal interconnection layer includes: forming the third dielectric layer on the surface of the second dielectric layer after forming the second dielectric layer and before forming the second metal interconnection layer; forming a first trench and a plurality of first through-holes in the second dielectric layer, and a second trench and a third trench in the third dielectric layer, wherein the first trench and the second trench are located on the first soldering layer and are interconnected, the third trench and the plurality of first through-holes are located on the first interconnection layer and are interconnected, and the projections of the plurality of first through-holes on the first surface are within the projection range of the third trench on the first surface; forming a conductive material layer in the first trench, the plurality of first through-holes, the second trench, and the third trench; planarizing the conductive material layer until the third dielectric layer is exposed, forming the second soldering layer with the conductive material layer in the first trench, forming the third soldering layer with the conductive material layer in the second trench, forming the first conductive plug with the conductive material layer in each of the first through-holes, and forming the second interconnection layer with the conductive material layer in the third trench.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the first trench, the second trench, the third trench and the plurality of first through holes comprises: forming a patterned hard mask layer on the surface of the third dielectric layer, wherein the hard mask layer has a first opening and a second opening exposing the surface of the third dielectric layer, the first opening being located on the first welding layer, and the second opening being located on a portion of the first interconnect layer; forming a photoresist layer in the second opening and on the surface of the hard mask layer, wherein the photoresist layer exposes the first opening, and the photoresist layer in the second opening has a plurality of initial through holes, wherein the plurality of initial through holes expose a portion of the surface of the third dielectric layer; etching the first through holes using the photoresist layer as a mask; The method further comprises etching the third dielectric layer until the second dielectric layer is exposed, forming the second trench located on the first welding layer and a plurality of transition through holes located on a portion of the first interconnect layer in the third dielectric layer; removing the photoresist layer after forming the plurality of transition through holes; and after removing the photoresist layer, continuously etching the third dielectric layer, the bottom of the first trench, and the second dielectric layer at the bottom of the plurality of transition through holes exposed by the hard mask layer using the hard mask layer as a mask until the first metal interconnect layer is exposed, forming the first trench and the plurality of through holes in the second dielectric layer, and forming the second trench and the third trench in the third dielectric layer.

11. The method for forming a semiconductor structure according to claim 7, wherein: After forming the third metal interconnect layer and before the bonding process, several layers of interconnect structures are formed on the surfaces of the third dielectric layer and the third metal interconnect layer. Each of the interconnect structures includes a fourth dielectric layer and a fifth dielectric layer located on the surface of the fourth dielectric layer. The fourth dielectric layer has several solder plugs located on the surface of the third solder layer and several third conductive plugs located on the surface of the second interconnect layer. The fifth dielectric layer has a fourth solder layer located on the surfaces of the several solder plugs and a third interconnect layer located on the surfaces of the several third conductive plugs.

12. The method for forming a semiconductor structure according to claim 6, wherein: After forming the second metal interconnect layer and before the bonding process, a sixth dielectric layer is further formed on the first surface, wherein the sixth dielectric layer has a plurality of first bonding metal layers therein, and the sixth dielectric layer exposes a plurality of the first bonding metal layers; the second wafer includes a substrate wafer and a seventh dielectric layer located on a surface of the substrate wafer, wherein the seventh dielectric layer has a plurality of second bonding metal layers therein, and the seventh dielectric layer exposes a plurality of the second bonding metal layers.

13. The method for forming a semiconductor structure according to claim 12, wherein: The bonding process further includes: bonding the sixth dielectric layer and the seventh dielectric layer to each other, and bonding a plurality of the first bonding metal layers and a plurality of the second bonding metal layers to each other.

14. The method for forming a semiconductor structure according to claim 6, wherein: The first wafer includes a pad area and a main body area, and the main body area has a plurality of device structures; the plurality of device structures and the first interconnection layer are electrically interconnected; the first welding layer and the second welding layer are located on the pad area; the first interconnection layer and the plurality of the first conductive plugs are located on the main body area.

15. The method for forming a semiconductor structure according to claim 6, wherein: After bonding the first wafer and the second wafer to each other and before forming the groove, the method further includes: thinning the first wafer from the second surface.

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