Hysteresis comparator with adjustable reference voltage and hysteresis range in multiple bits

Abstract

The application relates to the technical field of integrated circuits, and discloses a hysteresis comparator supporting multiple-bit adjustable reference voltage and hysteresis range. On the basis of a resistance voltage division network of a reference voltage generating unit, a comparator output result is fed back. The feedback signal and a multiple-bit signal used for controlling the hysteresis range jointly control a switch circuit, the voltage division ratio of the resistance network is dynamically changed, and thus the adjustment of the size of the hysteresis window is realized. Meanwhile, a reference voltage adjusting unit can select one from the resistance network as the reference voltage. The scheme has simple control logic, does not need complex additional circuits, can flexibly configure the reference voltage and the hysteresis range through a register, has high multiplexing performance, and is applicable to single-side and double-side window hysteresis comparators.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to hysteresis comparator technology. Background Art

[0002] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of this application.

[0003] In the design of integrated circuits, the comparator is a basic and important analog circuit unit. Its main function is to compare a changing input signal voltage with a fixed reference voltage (Voltage Reference, VREF for short) and output a digital signal of logic high or logic low based on the comparison result.

[0004] However, when the input signal voltage changes slowly around the reference voltage VREF or is subject to noise interference, the output of a traditional comparator may experience undesirable, repeated transitions between logic high and low levels. This phenomenon is known as "false flipping." To address this issue, comparators are often designed with hysteresis. A comparator with hysteresis has a logic-level flip threshold voltage that varies depending on the output state. Specifically, it has two distinct threshold voltages: one for the pull-up threshold when the input signal transitions from low to high, and another for the pull-down threshold when the input signal transitions from high to low. The difference between these two threshold voltages constitutes the hysteresis window, which effectively suppresses noise interference and ensures output logic stability.

[0005] Different integrated circuit application scenarios have different requirements for the comparator's reference voltage VREF and the size of the hysteresis window required for interference prevention. Therefore, the industry expects the hysteresis comparator to have a certain degree of adjustability.

[0006] In the prior art, the reference voltage VREF and hysteresis window size of traditional hysteresis comparators are typically fixed during the circuit design phase. Changing application requirements often require circuit redesign, resulting in a lack of flexibility. To address this issue, several adjustable solutions have emerged. For example, one approach uses the comparator's output signal as feedback to control and switch the resistor connected in series with the source of the comparator's differential input pair, or to change the tail current, thereby adjusting the comparator's upper and lower thresholds and thus adjusting the hysteresis window.

[0007] However, the prior art still has some deficiencies. First, the control logic is relatively complex, and usually requires simultaneous modification of the resistance and current parameters in the circuit, as well as cooperation with the corresponding switch control, to achieve adjustment of the hysteresis window. Second, this adjustment method is not flexible enough, making it difficult to achieve multi-bit synchronous adjustment of the reference voltage and hysteresis window, and unable to conveniently adapt to different application requirements through simple register configuration, resulting in low reusability in different integrated circuit designs. SUMMARY

[0008] One purpose of the present application is to provide a hysteresis comparator that supports multi-bit adjustable reference voltage and hysteresis range, with simple structure, convenient control, and flexible and coordinated adjustment of the reference voltage and hysteresis window.

[0009] The present application discloses a hysteresis comparator that supports multi-bit adjustable reference voltage and hysteresis range, comprising:

[0010] A hysteresis control decoder for generating a multi-bit control signal for controlling hysteresis window adjustment;

[0011] A reference voltage generation unit including a plurality of resistors connected in series between a power supply level and ground, forming a resistance voltage division network, and a plurality of resistance connection nodes between adjacent resistors of the plurality of resistors, at least part of the resistance connection nodes serving as output terminals of a plurality of candidate reference voltages;

[0012] A hysteresis window control unit including a plurality of switch circuits, at least one end of each switch circuit being connected to one of the plurality of resistance connection nodes; the plurality of switch circuits being turned on or off according to the multi-bit control signal and the comparison result of the hysteresis comparator, and when turned on, one or more resistors in the plurality of resistors are short-circuited, thereby changing the voltage division ratio of the resistance voltage division network and dynamically adjusting the plurality of candidate reference voltages;

[0013] A reference voltage adjustment unit including a reference voltage decoder and a multiplexer, the plurality of input terminals of the multiplexer being connected to the output terminals of the plurality of candidate reference voltages respectively, and the multiplexer being configured to select one of the plurality of candidate reference voltages as a final reference voltage output according to the reference voltage selection signal output by the reference voltage decoder;

[0014] A comparator having a first input terminal receiving an input signal and a second input terminal connected to the output terminal of the reference voltage adjustment unit, for comparing the input signal and the final reference voltage and outputting the comparison result of the hysteresis comparator.

[0015] In a preferred embodiment, a hysteresis control logic unit is further included, connected between the output of the comparator and the hysteresis window control unit, for feeding back the comparison result of the comparator output to the hysteresis window control unit.

[0016] In a preferred embodiment, one end of each of the switch circuits is connected to one of the plurality of resistance connection nodes, and the other end is connected to a power supply level or ground.

[0017] In a preferred embodiment, the switch circuit includes a logic gate and a transistor switch, the input of the logic gate receives one bit of the multi-bit control signal and the comparison result of the hysteresis comparator, and the output of the logic gate controls the on or off of the transistor switch.

[0018] In a preferred embodiment, the logic gate is a NAND gate, and the transistor switch is a PMOS transistor; the source of the PMOS transistor is connected to a power supply level, and the drain is connected to one of the plurality of resistance connection nodes, for pulling the potential of the resistance connection node to the power supply level when turned on.

[0019] In a preferred embodiment, the logic gate is an AND gate, and the transistor switch is an NMOS transistor; the drain of the NMOS transistor is connected to one of the plurality of resistance connection nodes, and the source is grounded, for pulling the potential of the resistance connection node to ground when turned on.

[0020] In a preferred embodiment, the hysteresis control decoder generates the multi-bit control signal according to a register configuration signal; and the reference voltage decoder generates a reference voltage selection signal for controlling the multiplexer according to a register configuration signal.

[0021] In a preferred embodiment, the hysteresis control logic unit is a buffer or an inverter.

[0022] The application also discloses a hysteresis comparator supporting multi-bit adjustable reference voltage and up-and-down double-side hysteresis range, comprising:

[0023] a hysteresis control decoder for generating a first multi-bit control signal for controlling the adjustment of the upper hysteresis window, and a second multi-bit control signal for controlling the adjustment of the lower hysteresis window;

[0024] a reference voltage generation unit including a plurality of resistors connected in series between a power supply level and ground, forming a resistance voltage division network, and a plurality of resistance connection nodes are led between adjacent resistors of the plurality of resistors, at least part of the resistance connection nodes serving as output terminals of a plurality of candidate reference voltages;

[0025] a first hysteresis window control unit, comprising a plurality of first switch circuits, one end of each of the first switch circuits being connected to one of the plurality of resistor connection nodes, and the other end being connected to a power supply level; the plurality of first switch circuits being turned on or off according to the first multi-bit control signal and the first comparison result, and shorting one or more of the plurality of resistors to the power supply level when turned on;

[0026] a first reference voltage adjustment unit, comprising a first reference voltage decoder and a first multiplexer, wherein a plurality of input terminals of the first multiplexer are respectively connected to the output terminals of the plurality of candidate reference voltages, and a first reference voltage adjustment unit selects one of the plurality of candidate reference voltages as an upper reference voltage output according to an output signal of the first reference voltage decoder;

[0027] a first comparator, having a first input terminal for receiving an input signal and a second input terminal connected to an output terminal of the first reference voltage adjustment unit, for comparing the input signal with the upper reference voltage and outputting the first comparison result;

[0028] a second hysteresis window control unit, comprising a plurality of second switch circuits, one end of each second switch circuit being connected to one of the plurality of resistor connection nodes, and the other end being connected to ground; the plurality of second switch circuits being turned on or off according to the second multi-bit control signal and the second comparison result, and shorting one or more of the plurality of resistors to ground when turned on;

[0029] a second reference voltage adjustment unit, comprising a second reference voltage decoder and a second multiplexer, wherein a plurality of input terminals of the second multiplexer are respectively connected to the output terminals of the plurality of candidate reference voltages, and a second reference voltage adjustment unit selects one of the plurality of candidate reference voltages as a lower reference voltage output according to an output signal of the second reference voltage decoder;

[0030] The second comparator has a first input terminal for receiving the input signal and a second input terminal connected to the output terminal of the second reference voltage adjustment unit, and is used to compare the input signal with the lower reference voltage and output the second comparison result.

[0031] In a preferred embodiment, it also includes:

[0032] a first hysteresis control logic unit, connected between the output terminal of the first comparator and the first hysteresis window control unit, and configured to feed back the first comparison result output by the first comparator to the first hysteresis window control unit;

[0033] The second hysteresis control logic unit is connected between the output terminal of the second comparator and the second hysteresis window control unit, and is used to feed back the second comparison result output by the second comparator to the second hysteresis window control unit.

[0034] In an embodiment of the present application, by combining a hysteresis control decoder that generates a multi-bit control signal, a resistor divider network that generates a candidate reference voltage, and a switch circuit that is turned on or off according to the comparison result and the multi-bit control signal, and cooperating with a reference voltage adjustment unit to select the final reference voltage, the problem that the reference voltage and hysteresis window of the traditional hysteresis comparator are fixed, difficult to adjust and reuse can be solved. The present invention does not use complex additional circuits, but instead uses a simple switching circuit on the basis of the reference voltage generation unit to directly and dynamically change the voltage divider ratio of the resistor divider network according to the output feedback of the comparator and the external multi-bit configuration signal, thereby moving the reference voltage to form a hysteresis window. This design enables the setting of the reference voltage and the adjustment of the hysteresis window size (i.e., the hysteresis range) to achieve multi-bit collaborative adjustment through simple register configuration. The solution control logic is simple, with high flexibility and reusability, and can be easily adapted to different integrated circuit application scenarios.

[0035] Furthermore, by setting a hysteresis control logic unit to feed back the output result of the comparator to the hysteresis window control unit, a complete closed-loop feedback path can be constructed to ensure that the comparison result can trigger the action of the switching circuit in real time and reliably, thereby realizing dynamic adjustment of the reference voltage and forming a stable hysteresis effect.

[0036] Furthermore, by connecting one end of the switch circuit to a resistor connection node and the other end to a power supply level or ground, the voltage divider ratio can be simply and efficiently changed by directly shorting the resistance between a specific resistor connection node and the power supply (or ground), thereby changing the candidate reference voltage.

[0037] Furthermore, by using logic gates and transistor switches to form a switching circuit, and using multi-bit control signals and comparison results as inputs of the logic gates, standard digital logic units can be used to accurately control the on and off of the transistor switches, making the control logic of the hysteresis window clear, easy to design and implement, and with a fast response speed.

[0038] Furthermore, by using a combination of a NAND gate and a PMOS transistor and connecting the PMOS transistor to a power supply level, a specific implementation method for pulling up the potential of the resistor node can be provided, which is suitable for constructing a pull-up hysteresis window.

[0039] Furthermore, by using a combination of an AND gate and an NMOS transistor and connecting the NMOS transistor to ground, a specific implementation method for pulling down the potential of the resistance node can be provided, which is suitable for constructing a pull-down hysteresis window.

[0040] Furthermore, the control signals of the hysteresis control decoder and the reference voltage decoder can come from register configuration, so that the performance parameters of the hysteresis comparator can be flexibly configured through software or firmware programming, meeting diverse application requirements without any hardware changes, greatly improving the flexibility of chip design and the reuse value of circuit modules.

[0041] By implementing two independent hysteresis window control units, reference voltage adjustment units, and comparators—one for controlling and comparing upper and lower reference voltages—the previously single-sided hysteresis adjustment capability can be expanded to bilateral hysteresis adjustment. This creates a "window comparator" with independently adjustable upper and lower thresholds and bilateral hysteresis windows, suitable for complex applications that require monitoring whether a signal is within a specific voltage range. The hysteresis windows can be optimized based on the varying noise characteristics of rising and falling signals. Larger hysteresis windows can be set for edges with relatively high noise levels (rising or falling). For example, if the rising edge is known to be noisy through experiments, a larger upper hysteresis window can be set; if the falling edge is less noisy, a smaller lower hysteresis window can be set.

[0042] The various technical features disclosed in the above summary of the invention, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings may be freely combined with each other to form various new technical solutions (all of which should be deemed to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, if one example discloses features A+B+C and another example discloses features A+B+D+E, and features C and D are equivalent technical means that perform the same function, only one of them can be used technically, and it is not possible to use them simultaneously. Feature E can be technically combined with feature C. In this case, the solution A+B+C+D should not be deemed to have been described because it is technically infeasible, while the solution A+B+C+E should be deemed to have been described. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 1 is a schematic structural diagram of a hysteresis comparator supporting multi-bit adjustable reference voltage and hysteresis range according to an embodiment of the present application;

[0044] Figure 2 1 is a schematic structural diagram of a hysteresis comparator supporting multi-bit adjustable reference voltage and hysteresis range according to another embodiment of the present application;

[0045] Figure 3 1 is a schematic structural diagram of a hysteresis comparator supporting multi-bit adjustable reference voltage and upper and lower bilateral hysteresis ranges according to an embodiment of the present application;

[0046] Figure 4 yes Figure 1 Schematic diagram of the hysteresis effect of the scheme;

[0047] Figure 5 yes Figure 2 Schematic diagram of the hysteresis effect of the scheme;

[0048] Figure 6 yes Figure 3 Schematic diagram of the hysteresis effect of the scheme. DETAILED DESCRIPTION

[0049] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0050] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0051] The first embodiment of the present application relates to a hysteresis comparator ( Figure 1 FIG. 4 shows a specific embodiment), the hysteresis comparator comprises:

[0052] Hysteresis control decoder, used to generate a multi-bit control signal to control the hysteresis window adjustment ( Figure 1 In the embodiment of Hys_ctrl <n:0>). The hysteresis control decoder is a decoder for decoding a preset code to generate a multi-bit control signal for controlling the size of the hysteresis window.

[0053] The reference voltage generating unit includes a plurality of resistors connected in series between the power supply level VDD and the ground to form a resistor voltage divider network, wherein a plurality of resistor connection nodes are drawn between adjacent resistors of the plurality of resistors, and at least some of the resistor connection nodes serve as output terminals of a plurality of candidate reference voltages. Figure 1 In the embodiment, there are n+2 resistors connected in series between the power supply level VDD and ground, and there is n+1 resistor connection node between these n+2 resistors, which serves as the output terminal of n+1 candidate reference voltages (VREF_0 to VREF_n), where n is a positive integer. The combination of VREF_0 to VREF_n can also be expressed as VREF <n:0>.

[0054] The hysteresis window control unit includes a plurality of switch circuits, and at least one end of each switch circuit is connected to one of a plurality of resistor connection nodes. The plurality of switch circuits are turned on or off according to the comparison result of the multi-bit control signal and the hysteresis comparator. When turned on, one or more of the plurality of resistors are short-circuited, thereby changing the voltage divider ratio of the resistor divider network and dynamically adjusting the plurality of candidate reference voltages. When the switch circuit is turned off, it does not affect the voltage divider ratio of the resistor divider network. The hysteresis window control unit realizes the hysteresis function by changing the voltage divider ratio of the resistor divider network so that the final reference voltage changes dynamically with the comparison result. Optionally, each switch circuit may include a logic gate and a transistor switch, the input end of the logic gate receives one bit of the multi-bit control signal and the comparison result of the hysteresis comparator, and the output of the logic gate controls the conduction or shutdown of the transistor switch. For example, in Figure 1 In an embodiment, each switch circuit includes an AND gate and an NMOS transistor. The drain of the NMOS transistor is connected to one of the n+1 resistance connection nodes, and the source of the NMOS transistor is grounded. When the NMOS transistor is turned on, the potential of the resistance connection node is pulled down to the ground, thereby short-circuiting the resistance between the resistance connection node and the ground. Figure 1 When the NMOS tube with one end connected to the VREF_1 node is turned on, the two resistors between the VREF_1 node and the ground are short-circuited, so that the entire resistor string is missing two resistors, thereby causing the voltages from VREF_1 to VREF_n to change. Figure 1 Explicitly shown are two switch circuits, one end of which is connected to the resistor connection node corresponding to VREF_0 and VREF_1, respectively. Those skilled in the art will appreciate that the number of switch circuits in the hysteresis window control unit can be set as needed and can be any value from 1 to n.

[0055] The reference voltage adjustment unit includes a reference voltage decoder and a multiplexer MUX ( Figure 1 In the embodiment of mux <n:0>). The reference voltage decoder is a decoder for decoding preset control codes to output reference voltage selection signals. The multiple inputs of the multiplexer are respectively connected to the outputs of the multiple candidate reference voltages Figure 1 In an embodiment, VREF <n:0>), the multiplexer is configured to select one of the multiple candidate reference voltages as the final reference voltage output according to the reference voltage selection signal output by the reference voltage decoder ( Figure 1 Alternatively, in one embodiment, the multiplexer may be composed of n transmission gates.

[0056] Comparator ( Figure 1 COMP_P in the figure), whose first input terminal receives the input signal ( Figure 1 SIG in the middle), its second input terminal is connected to the output terminal of the reference voltage adjustment unit ( Figure 1 VREF in the figure is used to compare the input signal with the final reference voltage and output the comparison result of the hysteresis comparator ( Figure 1 COMP_OUT in the example).

[0057] Hysteresis control logic unit, connected to the comparator ( Figure 1 COMP_P) output terminal ( Figure 1 COMP_OUT) and the hysteresis window control unit ( Figure 1 is an input terminal Vctrl of each AND gate, which is used to convert the comparison result output by the comparator into a control signal ( Figure 1 The voltage (Vctrl in the figure) is fed back to the hysteresis window control unit. A hysteresis control logic unit is preferred as it improves the stability of the entire circuit. The hysteresis control logic unit can be implemented using devices such as buffers or inverters. If stability requirements are not high or to save costs, the hysteresis control logic unit can be omitted.

[0058] The function of each switch circuit in the hysteresis window control unit is to short-circuit the resistors in one or more reference voltage generating units when the comparator determines that the reference voltage is exceeded by the input signal. There are many ways to implement this. For example, one end of each switch circuit can be connected to one of the multiple resistor connection nodes and the other end can be connected to ground, such as Figure 1 As another example, one end of each switch circuit can be connected to one of the multiple resistor connection nodes, and the other end can be connected to the power supply level, that is, Figure 2 Alternatively, two ends of at least one switch circuit may be connected to two resistance connection nodes among the plurality of resistance connection nodes. In this case, the switch circuit and one or more resistors between the two resistance connection nodes are connected in parallel, thereby short-circuiting the parallel resistors when the switch circuit is turned on.

[0059] Figure 1 The delayed effect of the program is as follows Figure 4 When the SIG signal breaks through the original reference voltage VREF, the reference voltage will automatically decrease to Figure 1 VREFSHIFT, thus creating a hysteresis effect. Thereafter, when the SIG signal breaks down the adjusted reference voltage VREFSHIFT, the reference voltage will automatically recover to the original VREF, thus creating a hysteresis effect again.

[0060] Figure 2 The circuit of a hysteresis comparator supporting multi-bit adjustable reference voltage and hysteresis range in another embodiment is shown. Figure 2 In the switching circuit of the reference voltage generation unit, the logic gate is an NAND gate, and the transistor switch is a PMOS transistor. The source of the PMOS transistor is connected to the power supply level, and the drain is connected to one of the resistance connection nodes, for pulling the potential of the resistance connection node to the power supply level when turned on, thus shorting the resistance between the resistance connection node and the power supply level in the reference voltage generation unit.

[0061] Figure 2 The hysteresis effect of the scheme is shown in Figure 5 When the SIG signal breaks down the original reference voltage VREF, the reference voltage will automatically adjust to Figure 2 VREFSHIFT, thus creating a hysteresis effect. Thereafter, when the SIG signal breaks down the adjusted reference voltage VREFSHIFT, the reference voltage will automatically recover to the original VREF, thus creating a hysteresis effect again.

[0062] Optionally, in one embodiment, the hysteresis control decoder decodes the hysteresis control signal (an encoding related to the size of the hysteresis window) configured in the register to generate a multi-bit control signal. The reference voltage decoder decodes the reference voltage control signal (an encoding related to the size of the reference voltage) configured in the register to generate a reference voltage selection signal for controlling the multiplexer.

[0063] The second embodiment of the present application relates to a hysteresis comparator supporting multi-bit adjustable reference voltage and up-and-down double-sided hysteresis range, whose circuit is shown in Figure 3

[0064] The hysteresis control decoder is used to generate a first multi-bit control signal Hysl_ctrl for controlling the adjustment of the up hysteresis window. <n:0>, and a second multi-bit control signal Hysh_ctrl for controlling the hysteresis window adjustment <n:0>.

[0065] The reference voltage generating unit includes a plurality of resistors connected in series between the power supply level VDD and the ground to form a resistor voltage divider network. A plurality of resistor connection nodes are drawn between adjacent resistors of the plurality of resistors, and at least some of the resistor connection nodes serve as output terminals of a plurality of candidate reference voltages. Figure 3 In the embodiment, there are n+2 resistors connected in series between the power supply level VDD and ground, and there is n+1 resistor connection node between these n+2 resistors, which serves as the output terminal of n+1 candidate reference voltages (VREF_0 to VREF_n), where n is a positive integer. The combination of VREF_0 to VREF_n can also be expressed as VREF_ <n:0>.

[0066] The first hysteresis window control unit includes a plurality of first switch circuits, one end of each first switch circuit is connected to one of the plurality of resistor connection nodes, and the other end is connected to the power supply level. The plurality of first switch circuits are turned on or off according to the first multi-bit control signal and the first comparison result, and when turned on, one or more resistors in the reference voltage generating unit are short-circuited. Figure 3 In the first hysteresis window control unit, each switch circuit includes a NAND gate and a PMOS transistor. The source of the PMOS transistor is connected to the power supply level, and the drain is connected to one of the resistor connection nodes. When the PMOS transistor is turned on, the potential of the resistor connection node is pulled up to the power supply level, thereby short-circuiting the resistor between the resistor connection node and the power supply level in the reference voltage generating unit. Figure 3 It is clearly shown that the first hysteresis window control unit has two switch circuits, one end of which is connected to the resistor connection node corresponding to VREF_n and VREF_n-1, respectively, and the other end is connected to the power supply level. However, those skilled in the art will understand that the number of switch circuits in the first hysteresis window control unit can be set as needed and can be any value between 1 and n.

[0067] The first reference voltage adjustment unit includes a first reference voltage decoder and a first multiplexer. The multiple input terminals of the first multiplexer are respectively connected to the output terminals of the multiple candidate reference voltages. The multiple candidate reference voltages VREF are selected according to the output signal of the first reference voltage decoder. _ <n:0>Select one as the upper reference voltage VREF1 output.

[0068] The first comparator COMP_N has a first input terminal for receiving an input signal SIG and a second input terminal connected to the output terminal VREF1 of the first reference voltage adjustment unit, and is used to compare the input signal SIG with the upper reference voltage VREF1 and output a first comparison result COMP. _ OUT1.

[0069] The first hysteresis control logic unit is connected to the output terminal COMP of the first comparator COMP_N. _ Between OUT1 and the first hysteresis window control unit, for outputting the first comparison result COMP of the first comparator COMP_N _ OUT1 is converted into a control signal Vctrl1 and fed back to the first hysteresis window control unit.

[0070] The second hysteresis window control unit includes a plurality of second switch circuits, one end of each second switch circuit is connected to one of the plurality of resistor connection nodes, and the other end is connected to the ground. The plurality of second switch circuits are turned on or off according to the second multi-bit control signal and the second comparison result, and when turned on, one or more resistors in the reference voltage generating unit are short-circuited. Figure 3 In the example, each switch circuit includes an AND gate and an NMOS transistor. The drain of the NMOS transistor is connected to one of the resistance connection nodes, and the source of the NMOS transistor is grounded. When the NMOS transistor is turned on, the potential of the resistance connection node is pulled down to the ground, thereby short-circuiting the resistance between the resistance connection node and the ground. Figure 3 The figure clearly shows that the second hysteresis window control unit has two switch circuits, one end of which is connected to the resistor connection node corresponding to VREF_0 and VREF_1, respectively, and the other end is connected to ground. However, those skilled in the art will appreciate that the number of switch circuits in the second hysteresis window control unit can be set as needed and can be any value between 1 and n.

[0071] The second reference voltage adjustment unit includes a second reference voltage decoder and a second multiplexer, wherein the multiple input terminals of the second multiplexer are respectively connected to the output terminals of the multiple candidate reference voltages, and the multiple candidate reference voltages VREF are selected according to the output signal of the second reference voltage decoder. _ <n:0>Select one as the lower reference voltage VREF2 output.

[0072] The second comparator COMP_P has a first input terminal for receiving the input signal SIG and a second input terminal connected to the output terminal of the second reference voltage adjustment unit, and is configured to compare the input signal SIG with the lower reference voltage VREF2 and output a second comparison result COMP_OUT2.

[0073] The second hysteresis control logic unit is connected between the output terminal of the second comparator COMP_P and the second hysteresis window control unit, and is used to convert the second comparison result COMP_OUT2 output by the second comparator COMP_P into a control signal Vctrl2 and feed it back to the second hysteresis window control unit.

[0074] Figure 3 The delayed effect of the program is as follows Figure 6 As shown in the figure. When the SIG signal breaks through the original upper reference voltage VREF1, the upper reference voltage is automatically adjusted down to VREF1SHIFT, thus generating a hysteresis effect. Thereafter, when the SIG signal reverses and breaks through the adjusted reference voltage VREF1SHIFT, the reference voltage automatically returns to the original VREF1, thus generating a hysteresis effect again. When the SIG signal reverses and breaks through the original lower reference voltage VREF2, the lower reference voltage is automatically adjusted up to VREF2SHIFT, thus generating a hysteresis effect. Thereafter, when the SIG signal reverses and breaks through the adjusted reference voltage VREF2SHIFT, the reference voltage automatically returns to the original VREF2, thus generating a hysteresis effect again.

[0075] The comprehensive technical effect of the second embodiment is the realization of a precision window hysteresis comparator with fully independently adjustable parameters. This solution cleverly establishes two parallel comparison and control paths (including their own comparators, reference voltage adjustment units, and hysteresis window control units) and enables them to share the same reference voltage generation unit, thereby achieving a synergistic effect that goes beyond the simple addition of two independent comparators. Specifically, its technical effects are reflected in the following aspects:

[0076] Functionality upgrade: Upgraded from the "single-point level detection" of the first implementation to "voltage range" monitoring. By independently setting the upper and lower reference voltages (VREF1 and VREF2), the circuit can accurately determine whether the input signal is within or outside a specific voltage window. This makes it suitable for more advanced circuit functions such as power supply voltage range monitoring and signal quality verification.

[0077] High Flexibility: This solution's flexibility lies in two dimensions. First, thanks to the two independent reference voltage adjustment units, the upper and lower limits of the window can be independently configured, allowing for arbitrary setting of the window's position and width. Second, through two independent hysteresis window control units, different hysteresis ranges can be configured for the upper and lower limits of the window, respectively, to adapt to asymmetric noise environments and achieve optimal anti-interference performance.

[0078] High Integration and Reusability: Despite its powerful functionality, this design maintains a high level of circuit integration by sharing a core resistor divider network. Furthermore, all key parameters (window upper and lower limits, hysteresis range) are programmable via registers with multiple bits. This allows the same circuit module to be flexibly reused for different design requirements without any hardware modifications, significantly improving design efficiency and chip versatility.

[0079] It should be noted that, in this application, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. Without further restriction, an element defined by the phrase "comprising a" does not preclude the presence of other identical elements in the process, method, article, or device comprising the element. In this application, reference to performing an action according to an element means performing the action at least according to that element, including two scenarios: performing the action only according to that element and performing the action according to that element and other elements. Expressions such as "multiple," "multiple," and "multiple" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0080] This specification includes combinations of the various embodiments described herein. Separate references to an embodiment (e.g., "one embodiment," "some embodiments," or "preferred embodiment") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as such or clear to one skilled in the art. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0081] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the contents of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application. ​

Claims

1. A hysteresis comparator supporting multi-bit adjustable reference voltage and hysteresis range, characterized in that: include: a hysteresis control decoder for generating a multi-bit control signal for controlling adjustment of the hysteresis window; a reference voltage generating unit, comprising a plurality of resistors connected in series between a power supply level and ground to form a resistor voltage divider network, wherein a plurality of resistor connection nodes are drawn between adjacent resistors of the plurality of resistors, and at least some of the resistor connection nodes serve as output terminals of a plurality of candidate reference voltages; a hysteresis window control unit, comprising a plurality of switch circuits, at least one end of each switch circuit being connected to one of the plurality of resistance connection nodes; The multiple switch circuits are turned on or off according to the comparison result between the multi-bit control signal and the hysteresis comparator, and when turned on, one or more resistors among the multiple resistors are short-circuited, thereby changing the voltage division ratio of the resistor voltage divider network and dynamically adjusting the multiple candidate reference voltages; a reference voltage adjustment unit, comprising a reference voltage decoder and a multiplexer, wherein a plurality of input terminals of the multiplexer are respectively connected to output terminals of the plurality of candidate reference voltages, and the multiplexer is configured to select one of the plurality of candidate reference voltages as a final reference voltage output according to a reference voltage selection signal output by the reference voltage decoder; A comparator, whose first input terminal receives an input signal and whose second input terminal is connected to the output terminal of the reference voltage adjustment unit, is used to compare the input signal with the final reference voltage and output the comparison result of the hysteresis comparator.

2. The hysteresis comparator according to claim 1, wherein: It also includes a hysteresis control logic unit connected between the output end of the comparator and the hysteresis window control unit, and is used to feed back the comparison result output by the comparator to the hysteresis window control unit.

3. The hysteresis comparator according to claim 1, wherein: One end of each of the switch circuits is connected to one of the plurality of resistor connection nodes, and the other end is connected to a power supply level or ground.

4. The hysteresis comparator according to claim 3, wherein: The switching circuit includes a logic gate and a transistor switch, the input end of the logic gate receives one bit of the multi-bit control signal and the comparison result of the hysteresis comparator, and the output of the logic gate controls the on or off of the transistor switch.

5. The hysteresis comparator according to claim 4, wherein: The logic gate is a NAND gate, and the transistor switch is a PMOS transistor; the source of the PMOS transistor is connected to the power supply level, and the drain is connected to one of the multiple resistance connection nodes, so as to pull the potential of the resistance connection node to the power supply level when it is turned on.

6. The hysteresis comparator according to claim 4, wherein: The logic gate is an AND gate, and the transistor switch is an NMOS transistor; the drain of the NMOS transistor is connected to one of the multiple resistance connection nodes, and the source is grounded, so as to pull the potential of the resistance connection node down to ground when turned on.

7. The hysteresis comparator according to claim 1, wherein: The hysteresis control decoder generates the multi-bit control signal according to the register configuration signal; the reference voltage decoder generates a reference voltage selection signal for controlling the multiplexer according to the register configuration signal.

8. The hysteresis comparator according to claim 2, wherein: The hysteresis control logic unit is a buffer or an inverter.

9. A hysteresis comparator supporting multi-bit adjustable reference voltage and upper and lower hysteresis ranges, characterized in that: include: a hysteresis control decoder for generating a first multi-bit control signal for controlling adjustment of an upper hysteresis window and a second multi-bit control signal for controlling adjustment of a lower hysteresis window; a reference voltage generating unit, comprising a plurality of resistors connected in series between a power supply level and ground to form a resistor voltage divider network, wherein a plurality of resistor connection nodes are drawn between adjacent resistors of the plurality of resistors, and at least some of the resistor connection nodes serve as output terminals of a plurality of candidate reference voltages; A first hysteresis window control unit includes a plurality of first switch circuits, one end of each first switch circuit is connected to one of the plurality of resistance connection nodes, and the other end is connected to a power supply level; The plurality of first switch circuits are turned on or off according to the first multi-bit control signal and the first comparison result, and when turned on, one or more resistors of the plurality of resistors are shorted to a power supply level; a first reference voltage adjustment unit, comprising a first reference voltage decoder and a first multiplexer, wherein a plurality of input terminals of the first multiplexer are respectively connected to the output terminals of the plurality of candidate reference voltages, and a first reference voltage adjustment unit selects one of the plurality of candidate reference voltages as an upper reference voltage output according to an output signal of the first reference voltage decoder; a first comparator, having a first input terminal for receiving an input signal and a second input terminal connected to an output terminal of the first reference voltage adjustment unit, for comparing the input signal with the upper reference voltage and outputting the first comparison result; A second hysteresis window control unit includes a plurality of second switch circuits, one end of each second switch circuit is connected to one of the plurality of resistance connection nodes, and the other end is connected to ground; The plurality of second switch circuits are turned on or off according to the second multi-bit control signal and the second comparison result, and when turned on, one or more resistors of the plurality of resistors are shorted to ground; a second reference voltage adjustment unit, comprising a second reference voltage decoder and a second multiplexer, wherein a plurality of input terminals of the second multiplexer are respectively connected to the output terminals of the plurality of candidate reference voltages, and a second reference voltage adjustment unit selects one of the plurality of candidate reference voltages as a lower reference voltage output according to an output signal of the second reference voltage decoder; The second comparator has a first input terminal for receiving the input signal and a second input terminal connected to the output terminal of the second reference voltage adjustment unit, and is used to compare the input signal with the lower reference voltage and output the second comparison result.

10. The hysteresis comparator according to claim 9, wherein: Also includes: a first hysteresis control logic unit, connected between the output terminal of the first comparator and the first hysteresis window control unit, and configured to feed back the first comparison result output by the first comparator to the first hysteresis window control unit; The second hysteresis control logic unit is connected between the output terminal of the second comparator and the second hysteresis window control unit, and is used to feed back the second comparison result output by the second comparator to the second hysteresis window control unit.

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