Switching circuit and control circuit for switching circuit

Abstract

The invention discloses a switching circuit and a control circuit used for the switching circuit, the switching circuit comprises a high-side switch and a low-side switch, and the control circuit comprises a first transistor, a second transistor, a capacitor, a third transistor, a fourth transistor and a fifth transistor. Wherein the first end of the first transistor and the first end of the second transistor receive an input voltage, the first end of the third transistor is coupled to a capacitor, the second end of the third transistor is coupled to a reference ground, the capacitor is coupled between the second end of the first transistor and the second end of the second transistor, and the first end of the fourth transistor is coupled to the capacitor. The first end of the fifth transistor is coupled to the fourth transistor and outputs a high-side driving signal to control on and off of the high-side switch, the second end of the fifth transistor is coupled to the capacitor, and the control end of the fifth transistor is coupled to the control end of the fourth transistor. The capacitor is integrated in the switching circuit, so that chip pins of the switching circuit are reduced, the cost is reduced, and the EMI characteristic of the switching circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of control circuits for switching circuits, and in particular to a switching circuit and a control circuit for the switching circuit. Background Art

[0002] Buck converters often use NMOS transistors (NMOS transistors) as the converter's high-side switches to minimize power loss in high-current applications and reduce chip area costs. These transistors, with their lower on-resistance for a given area, require a gate voltage approximately 5V greater than the input voltage when turned on. External bootstrap capacitors are often used to provide this gate drive voltage, but this increases system cost. Furthermore, the bootstrap capacitors require an additional pin (BST) to connect to the chip. For multi-output Buck converters, each pin requires an additional pin. The more pins, the higher the chip cost. These additional pins also introduce parasitic inductance, which degrades EMI performance and increases system noise.

[0003] Therefore, a driving circuit for an NMOS tube with lower cost and better EMI performance is needed. Summary of the Invention

[0004] The present application provides a switching circuit and a control circuit for the switching circuit, aiming to solve the problem of increased pins and system costs caused by providing a driving voltage to the high-side switch of the buck circuit through an off-chip capacitor.

[0005] According to a first aspect of the present application, the present application provides a control circuit for a switching circuit, the switching circuit including a high-side switch and a low-side switch, the control circuit including:

[0006] A first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal receives an input voltage;

[0007] a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal receives an input voltage;

[0008] a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second terminal of the second transistor;

[0009] a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the capacitor, and the second terminal of the third transistor is coupled to the reference ground;

[0010] a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the capacitor; and

[0011] a fifth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the fourth transistor and outputs a high-side drive signal, the second terminal is coupled to the second terminal of the capacitor, and the control terminal of the fifth transistor is coupled to the control terminal of the fourth transistor;

[0012] The high-side switch is an N-type field effect transistor, and the high-side drive signal controls the on and off of the high-side switch.

[0013] According to the second aspect of the present application, the present application provides a switching circuit, comprising: a high-side switch having a source terminal, a drain terminal and a gate terminal, a low-side switch having a source terminal, a drain terminal and a gate terminal, wherein the drain terminal of the low-side switch is coupled to the source terminal of the high-side switch, and a control circuit as described in any one of the above-mentioned first aspects.

[0014] Through one or more of the above embodiments of the present application, at least the following technical effects can be achieved:

[0015] This application integrates the bootstrap capacitor, which is set outside the switch circuit chip, into the chip, reducing the number of pins on the chip. At the same time, the bootstrap capacitor is integrated into the chip, and a unique timing control is used to achieve segmented drive of the high-side switch. It can recycle the gate charge of the high-side switch to speed up the charging speed of the bootstrap capacitor, effectively reducing system costs, improving EMI performance, and increasing the efficiency of the switching circuit under high-frequency and large duty cycle conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A structural diagram of an existing BUCK circuit is given;

[0018] Figure 2 A circuit structure diagram of a control circuit for a switch circuit 200 according to an embodiment of the present application is provided;

[0019] Figure 3 A waveform diagram of the comparison signal Vcs when the voltage VCL at the second terminal of the capacitor C is less than the low-side threshold Vth1 according to an embodiment of the present application is provided;

[0020] Figure 4 A waveform diagram of the comparison signal Vcs when the voltage VCL at the second terminal of the capacitor C is greater than the high-side threshold Vth2 according to an embodiment of the present application is provided;

[0021] Figure 5 A schematic diagram of the circuit structure of a level shift circuit according to an embodiment of the present application is provided;

[0022] Figure 6 A schematic diagram of the on / off states of each transistor of the switch circuit 200 according to an embodiment of the present application is provided in the first conduction stage;

[0023] Figure 7 A schematic diagram of the on / off states of each transistor of the switch circuit 200 according to an embodiment of the present application is provided when the switch circuit 200 is in the second conduction phase;

[0024] Figure 8 The signal waveform diagrams at each stage of the conduction process of the high-side switch MH according to an embodiment of the present application are provided;

[0025] Figure 9 A schematic diagram of the on and off states of each transistor of the switch circuit 200 according to an embodiment of the present application during the first shutdown phase is provided;

[0026] Figure 10 A schematic diagram of the on and off states of each transistor of the switch circuit 200 according to an embodiment of the present application is provided when the second stage of shutdown is in progress;

[0027] Figure 11 The signal waveform diagrams at each stage of the turn-off process of the high-side switch MH according to an embodiment of the present application are provided;

[0028] Figure 12a A schematic diagram of an equivalent charging circuit of capacitor C in an embodiment of the present application is provided;

[0029] Figure 12b Given Figure 1 Schematic diagram of an equivalent charging loop circuit of the bootstrap capacitor CBST in the switching circuit shown;

[0030] Figure 13 A schematic diagram of a circuit for internally generating a switch control signal PWM in an embodiment of the present application is given. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two elements.

[0034] Figure 1 A structural schematic diagram of an existing switch circuit is given. Figure 1 The switching circuit is a buck type switching circuit, in which the internal power generation circuit Voltage regulator is used to convert the input voltage VIN with a large variation range into a stable internal voltage. Generally, a low-dropout linear regulator (LDO) or charge pump (Charge Pump) structure can be used. The charging circuit of the bootstrap capacitor CBST may include a switch or a diode, and the internal voltage is connected to the positive terminal (BST) of the bootstrap capacitor CBST by controlling the conduction of the switch or diode. Figure 1 As shown in the figure, when the high-side switch MH is off and the low-side switch ML is on, the internal power generation circuit, the voltage regulator, charges the bootstrap capacitor CBST through diode D. When the high-side switch MH needs to turn on, the positive charge on the bootstrap capacitor CBST flows from the BST node through the driver circuit to the gate of the high-side switch MH, charging the gate-source capacitance and gate-drain capacitance of the high-side switch MH, thereby turning on the high-side switch MH. This process consumes the charge stored in the bootstrap capacitor CBST.

[0035] In such Figure 1In the bootstrap circuit shown, first, the bootstrap capacitor CBST is an off-chip capacitor, which will bring additional cost to the power supply system. Second, the chip needs to have a BST pin, which introduces parasitic inductance that worsens EMI performance and places high demands on chip packaging in multi-output applications. Figure 1 In the bootstrap circuit shown, when used at a high duty cycle, the charge consumed per cycle exceeds the charge replenished. When the high-side switch MH is turned on, the gate-source voltage of the high-side switch MH gradually decreases, increasing the on-resistance of the high-side switch MH and reducing efficiency. Furthermore, as previously analyzed, the traditional circuit structure also loses gate charge in the high-side switch MH during the switching process, which also reduces system efficiency.

[0036] Figure 2 A schematic diagram of the circuit structure of a control circuit for a switch circuit 200 according to an embodiment of the present application is provided. The switch circuit 200 includes a high-side switch MH, a low-side switch ML, and a control circuit 20. The control circuit 20 includes a first transistor M1, a capacitor C, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The first transistor M1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal receives an input voltage VIN. The second transistor M2 has a first terminal, a second terminal, and a control terminal, wherein the first terminal receives the input voltage VIN. The capacitor C has a first terminal and a second terminal, wherein the first terminal CH of the capacitor is coupled to the second terminal of the first transistor M1, and the second terminal CL of the capacitor is coupled to the second terminal of the second transistor M2, wherein the voltage at the first terminal of the capacitor is VCH, and the voltage at the second terminal of the capacitor is VCL. The third transistor M3 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal CL of the capacitor C, and the second terminal of the third transistor M3 is coupled to the reference ground GND. The fourth transistor M4 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal CH of the capacitor C. The fifth transistor M5 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the fourth transistor M4 and outputs a high-side drive signal HSG, the second terminal is coupled to the second terminal CL of the capacitor C, and the control terminal of the fifth transistor M5 is coupled to the control terminal of the fourth transistor. Figure 2 In the illustrated switch circuit 200 , the high-side switch MH is an N-type field-effect transistor. In some embodiments, the capacitance of the capacitor C is between 0.1 nF and 10 nF. In some embodiments, the capacitance of the capacitor C increases as the width-to-length ratio of the high-side switch MH increases.

[0037] The control circuit 20 also includes a logic circuit that receives a pulse-width modulated signal PWM and generates a first control signal G1, a second control signal G2, and a third control signal G3 based on the pulse-width modulated signal PWM. The first control signal G1, the second control signal G2, and the third control signal G3 control the on / off states of the first transistor M1, the second transistor M2, and the third transistor M3, respectively, to generate a high-side drive signal HSG to control the on / off state of the high-side switch MH. The logic circuit also generates a low-side drive signal LSG based on the pulse-width modulated signal PWM to control the on / off state of the low-side switch ML. In one embodiment, the control circuit 20 generates the pulse-width modulated signal PWM internally. In another embodiment, the control circuit 20 receives an external pulse-width modulated signal PWM via a pin. In one embodiment, when the pulse width modulation signal PWM transitions from a first logic level to a second logic level, the logic circuit accordingly generates a first control signal G1, a second control signal G2, a third control signal G3, and a low-side drive signal LSG. The low-side drive signal LSG controls the low-side switch ML to be turned off. The first control signal G1, the second control signal G2, and the third control signal G3 control the on / off switching of corresponding transistors to generate a high-side drive signal HSG to turn on the high-side switch MH. When the pulse width modulation signal PWM transitions from the second logic level to the first logic level, the logic circuit accordingly generates a first control signal G1, the second control signal G2, the third control signal G3, and the low-side drive signal LSG. The low-side drive signal LSG controls the low-side switch ML to be turned on. The first control signal G1, the second control signal G2, and the third control signal G3 control the on / off switching of corresponding transistors to generate a high-side drive signal HSG to turn off the high-side switch MH. In one embodiment, the first logic level of the pulse width modulation signal PWM is a logic low level, and the second logic level is a logic high level.

[0038] exist Figure 2In the illustrated switch circuit 200, after the pulse width modulation signal PWM transitions from a first logic level to a second logic level, the first control signal G1, the second control signal G2, and the third control signal G3 control the high-side drive signal HSG to increase within a certain period of time to turn on the high-side switch MH. The conduction of the high-side switch MH includes a first conduction phase and a second conduction phase. During the first conduction phase, the first transistor M1, the third transistor M3, and the fourth transistor M4 are turned off, while the second transistor M2 and the fifth transistor M5 are turned on. The input voltage VIN is connected to the second terminal CL of the capacitor C via the second transistor M2. The input voltage VIN charges the gate terminal of the high-side switch MH via the second transistor M2 and the fifth transistor M5, causing the gate voltage of the N-type high-side switch MH to increase from 0V to VIN. During the first conduction phase, the voltage VCL at the second terminal of the capacitor C increases from 0V to VIN, and the corresponding voltage VCH at the first terminal of the capacitor increases from VIN to 2VIN. When the voltage VCL at the second terminal of the capacitor C increases to the high-side threshold Vth2, the first conduction phase ends and the second conduction phase begins. In one embodiment, the high-side threshold Vth2 is between 80%×VIN and 95%×VIN, where VIN is the voltage value of the input voltage.

[0039] In the second conduction phase, the second transistor M2 and the fourth transistor M4 are turned on, the first transistor M1, the third transistor M3, and the fifth transistor M5 are turned off, and the voltage VCH at the second end of the capacitor C is connected to the gate of the N-type high-side switch MH through the fourth transistor M4. Correspondingly, the gate voltage of the high-side switch MH increases from VIN to 2VIN.

[0040] exist Figure 2 In the illustrated switch circuit 200, after the pulse width modulation signal PWM transitions from the second logic level to the first logic level, the first control signal G1, the second control signal G2, and the third control signal G3 control the high-side drive signal HSG to decrease within a certain period of time, thereby turning off the high-side switch MH. Turning off the high-side switch MH includes a first shutdown phase and a second shutdown phase. During the first shutdown phase, the third transistor M3 and the fourth transistor M4 are turned on, while the first transistor M1, the second transistor M2, and the fifth transistor M5 are turned off. The gate charge of the high-side switch MH charges the capacitor C via the fourth transistor M4. When the voltage VCL at the second terminal of the capacitor C decreases to the low-side threshold Vth1, the first shutdown phase ends and the second shutdown phase begins.

[0041] During the second shutdown phase, the first transistor M1, the third transistor M3, and the fifth transistor M5 are turned on, while the second transistor M2 and the fourth transistor M4 are turned off. The gate voltage of the high-side switch MH decreases to zero. In one embodiment, the low-side threshold Vth1 is between 5% × VIN and 20% × VIN, where VIN is the input voltage. In one embodiment, the low-side threshold Vth1 is 0.25V, and the high-side threshold Vth2 is 4.85V. In one embodiment, the input voltage VIN is between 2V and 6V.

[0042] exist Figure 2 In the embodiment shown, the first transistor M1 is an N-type field effect transistor, the second transistor M2 is a P-type field effect transistor, and the third transistor M3 is an N-type field effect transistor. Figure 2 In the illustrated embodiment, the fourth transistor M4 is a P-type field-effect transistor, and the fifth transistor M5 is an N-type field-effect transistor. It should be noted that this application does not limit whether each transistor is N-type or P-type. When the transistor type is changed from N-type to P-type, the logic level of its switch control signal can be designed accordingly. For example, the first transistor M1 can be a P-type field-effect transistor. Compared to an N-type field-effect transistor, it is only necessary to reverse the high and low levels of the first control signal G1.

[0043] exist Figure 2 In the illustrated embodiment, the control circuit 20 further includes a recycling control circuit 110, which includes a trigger circuit 21 and a level shift circuit 23. The trigger circuit 21 has an input and an output. The input is coupled to the second terminal CL of the capacitor C, and the output provides a comparison signal Vcs. When the voltage VCL at the second terminal of the capacitor C is greater than a high-side threshold Vth2, the comparison signal Vcs is at a first logic level. When the voltage VCL at the second terminal of the capacitor C is less than a low-side threshold Vth1, the comparison signal Vcs is at a second logic level. The level shift circuit 23 receives the comparison signal Vcs and generates a recycling control signal G45 based on the comparison signal Vcs to control the on and off states of the fourth transistor M4 and the fifth transistor M5. The first and second logic levels of the comparison signal Vcs are the reference ground GND and the input voltage VIN, respectively. The first and second logic levels of the recycling control signal G45 are the voltage CL at the second terminal of the capacitor and the voltage CH at the first terminal of the capacitor, respectively. In some embodiments, the trigger circuit 21 may be a Schmitt trigger.

[0044] continue Figure 2Description, wherein the recovery control signal G45 has a first logic level and a second logic level, wherein when the comparison signal Vcs is the first logic level, the level shift circuit 23 controls the recovery control signal G45 to be the first logic level, and when the comparison signal Vcs is the second logic level, the level shift circuit 23 controls the recovery control signal G45 to be the second logic level.

[0045] exist Figure 2 In the illustrated embodiment, the switch circuit 200 further includes an inductor L, one end of the inductor is coupled to the common terminal of the high-side switch MH and the low-side switch ML, and the other end of the inductor is coupled to the output capacitor Cout.

[0046] Figure 3 The waveform diagram of the comparison signal Vcs is given when the voltage VCL at the second terminal of the capacitor C is less than the low-side threshold Vth1 according to an embodiment of the present application. Figure 3 It can be seen from FIG. 1 that when the voltage VCL at the second terminal of the capacitor C is less than the low-side threshold Vth1 , the comparison signal Vcs changes from the first logic level (logic low in example) to the second logic level (logic high in example).

[0047] Figure 4 The waveform diagram of the comparison signal Vcs is given when the voltage VCL at the second terminal of the capacitor C is greater than the high-side threshold Vth2 according to an embodiment of the present application. Figure 4 It can be seen from FIG. 1 that when the voltage VCL at the second terminal of the capacitor C is greater than the high-side threshold Vth2 , the comparison signal Vcs changes from the second logic level (VIN) to the first logic level (0V).

[0048] Figure 5 A schematic diagram of the circuit structure of a level shift circuit according to an embodiment of the present application is provided. The level shift circuit includes a sixth transistor M6, a seventh transistor M7, a first resistor R1, a second resistor R2, a first NAND gate AN1, and a second NAND gate AN2. It should be noted that: Figure 5 The level shift circuit shown is only an example. Any level shift circuit that can generate a voltage rail of the comparison signal Vcs from 0 to VIN to a voltage rail of the capacitor second terminal VCL to a voltage rail of the capacitor first terminal VCH is covered by this application.

[0049] Figure 6 A schematic diagram of the on / off states of each transistor in the switching circuit 200 according to an embodiment of the present application is given. Figure 6In the embodiment, the first control signal G1 is coupled to the gate of the first transistor M1 to control the on / off state of the first transistor M1. The second control signal G2 is coupled to the gate of the second transistor M2 to control the on / off state of the second transistor M2. The third control signal G3 is coupled to the gate of the third transistor M3 to control the on / off state of the third transistor M3. The recovery control signal G45 is coupled to the gates of the fourth transistor M4 and the fifth transistor M5 to control the on / off state of the fourth transistor M4 and the fifth transistor M5. Figure 6 In the embodiment, (ON) and (OFF) are used to indicate the on and off states of each transistor, (ON) indicating that the transistor is on, and (OFF) indicating that the transistor is off. The dotted line illustrates the current flow of the gate terminal charging the high-side switch MH when the switch circuit 200 is on in the first stage. In the first stage, the first control signal G1 controls the first transistor M1 to turn off, and the third control signal G3 controls the third transistor M3 to turn off. The second control signal G2 controls the second transistor M2 to turn on. As the second transistor M2 is turned on, the voltage VCL at the second end of the capacitor C increases from 0V. Before the voltage VCL at the second end of the capacitor C reaches the high-side threshold Vth2, the recovery control signal G45 is logic high, the fifth transistor M5 is turned on, and the fourth transistor M4 is turned off. The input voltage VIN charges the gate terminal of the high-side switch MH through the second transistor M2 and the fifth transistor M5.

[0050] exist Figure 6 In the illustrated embodiment, the input voltage VIN can charge the gate terminal of the high-side switch MH to VIN via the second transistor M2 and the fifth transistor M5. The charge required to charge the gate terminal of the high-side switch MH to VIN all comes from the input voltage VIN. This process does not consume the charge of the capacitor C, and therefore the capacitance of the capacitor C can be further reduced to reduce the area of ​​the capacitor C, thereby improving the integration of the switch circuit 200 and reducing the manufacturing cost.

[0051] Figure 7 A schematic diagram of the on and off states of each transistor during the second conduction phase according to an embodiment of the present application is given. Figure 7 In the embodiment, the first control signal G1 is coupled to the gate of the first transistor M1 to control the on / off state of the first transistor M1. The second control signal G2 is coupled to the gate of the second transistor M2 to control the on / off state of the second transistor M2. The third control signal G3 is coupled to the gate of the third transistor M3 to control the on / off state of the third transistor M3. The recovery control signal G45 is coupled to the gates of the fourth transistor M4 and the fifth transistor M5 to control the on / off state of the fourth transistor M4 and the fifth transistor M5. Figure 7In the embodiment, (ON) and (OFF) are used to illustrate the on and off states of each transistor, where (ON) indicates that the transistor is on and (OFF) indicates that the transistor is off. The dotted line illustrates the flow of current charging the gate terminal of the high-side switch MH during the second conduction phase. When the voltage VCL at the second end of the capacitor C increases to the high-side threshold Vth2 of the trigger circuit 21, the first conduction phase ends and the second conduction phase begins. The recovery control signal G45 is at a logic low level, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off. The input voltage VIN is generated by Figure 8 The charging path shown by the middle dotted line continues to charge the gate terminal of the high-side switch MH until the high-side drive signal HSG increases to 2VIN and the high-side switch MH is fully turned on.

[0052] exist Figure 7 In the process shown, when the trigger circuit 21 detects that the voltage VCL at the second end of the capacitor C is greater than the high-side threshold Vth2, the recovery control signal G45 controls the fourth transistor M4 to turn on and the fifth transistor M5 to turn off, thereby changing the gate terminal of the high-side switch MH from being coupled to the second end CL of the capacitor C to being coupled to the first end CH of the capacitor C, thereby achieving the logic high level of the high-side drive signal HSG from the voltage VCL at the second end of the capacitor C (equal to the input voltage VIN) to the voltage VCH at the first end of the capacitor C (equal to 2 times the input voltage 2×VIN).

[0053] Figure 8 The waveform diagram of each signal during the conduction process of the high side switch MH according to an embodiment of the present application is given. Figure 6 and Figure 7 The waveforms of the high-side switch MH during the conduction process, especially the first and second conduction stages, are described. At time t0, the pulse width modulation signal PWM switches from a low level to a high level, and after a first dead time Td, the first control signal G1 and the third control signal G3 jump from a logic high to a logic low to turn off the first transistor M1 and the third transistor M3, respectively. It should be noted that the first dead time Td is set to more reliably turn off the low-side switch ML. In one embodiment, after the pulse width modulation signal PWM jumps from a low level to a high level, the switch circuit 200 is provided with a detection circuit, which detects that the gate terminal voltage of the low-side switch ML is a logic low (for example, 0V) before starting other operations. The period of time during which the gate terminal voltage of the low-side switch ML decreases to a logic low is the first dead time Td. Figure 8After the first dead time Td, at time t1, the switch circuit 200 enters the first conduction phase. During the first conduction phase, the first control signal G1 and the third control signal G3 are logic low, turning off the first transistor M1 and the third transistor M3. The second control signal G2 is logic low, turning off the second transistor M2. The recovery control signal G45 is logic high, turning off the fourth transistor M4 and turning on the fifth transistor M5. During the first conduction phase, the input voltage VIN is connected to the gate of the high-side switch MH through the turned-on second transistor M2 and the turned-on fifth transistor M5, charging the gate of the high-side switch MH. The high-side drive signal HSG increases to the input voltage VIN. During the first conduction phase, the voltage VCL at the second terminal of the capacitor increases from the reference ground GND to VIN, and the voltage VCH at the first terminal of the capacitor increases from VIN to 2×VIN. At time t2, when the voltage VCL at the second terminal of the capacitor increases to the high-side threshold Vth2, the first conduction phase ends and the switch circuit 200 enters the second conduction phase. At this time, because the voltage VCL at the second terminal of the capacitor is greater than the high-side threshold Vth2, the comparison signal Vcs jumps to logic low, the recovery control signal G45 jumps from logic high to logic low, the fourth transistor M4 turns on, and the fifth transistor M5 turns off. The voltage VCH at the first terminal of the capacitor is connected to the gate terminal of the high-side switch MH through the turned-on M4, and the voltage of the high-side drive signal HSG increases to 2×VIN. At time t3, the value of the high-side drive signal HSG increases to 2×VIN, and the high-side switch MH is fully turned on.

[0054] Figure 9 A schematic diagram of the on / off states of each transistor in a switching circuit according to an embodiment of the present application during the first shutdown phase is provided. A first control signal G1 is coupled to the gate of the first transistor M1 to control the on / off state of the first transistor M1. A second control signal G2 is coupled to the gate of the second transistor M2 to control the on / off state of the second transistor M2. A third control signal G3 is coupled to the gate of the third transistor M3 to control the on / off state of the third transistor M3. A recovery control signal G45 is coupled to the gates of the fourth transistor M4 and the fifth transistor M5 to control the on / off state of the fourth transistor M4 and the fifth transistor M5. Figure 9 The on and off states of each transistor are indicated by (ON) and (OFF), wherein (ON) indicates that the transistor is on, and (OFF) indicates that the transistor is off. Figure 9In the figure, the dotted line illustrates the flow of charge at the gate of the high-side switch MH during the first shutdown phase. During the first shutdown phase, the third control signal G3 controls the third transistor M3 to turn on, and the capacitor C discharges to ground through the third transistor M3. The voltage VCL at the second terminal of capacitor C gradually decreases from VIN to 0V, and the voltage VCH at the first terminal of capacitor C correspondingly decreases from 2×VIN. When the voltage VCL at the second terminal of capacitor C is greater than the low-side threshold Vth1, the comparison signal Vcs is at the first logic level, the recovery control signal G45 is at the first logic level, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off. When the voltage VCL at the second terminal of capacitor C drops to the low-side threshold Vth1, the comparison signal Vcs is at the second logic level, the recovery control signal G45 is at the second logic level, the fourth transistor M4 is turned off, and the fifth transistor M5 is turned on. The first shutdown phase ends and the second shutdown phase begins.

[0055] When the high-side switch MH is turned on, the gate voltage of the high-side switch MH is 2×VIN. As the voltage VCH at the first terminal of the capacitor C decreases from 2×VIN to VIN, the gate charge of the high-side switch MH flows to the first terminal CH of the capacitor C through the fourth transistor M4. Positive charge flows from the first terminal CH of the capacitor C (i.e., the positive terminal of the capacitor C), thereby recovering the gate charge of the high-side switch MH.

[0056] Figure 10 A schematic diagram of the on and off states of each transistor in the switching circuit according to an embodiment of the present application is provided when the switching circuit is in the second shutdown phase. Figure 10 In the embodiment, (ON) and (OFF) are used to indicate the on and off states of the transistors, with (ON) indicating on and (OFF) indicating off. The dotted line indicates the current flow at the gate of the high-side switch MH during the second shutdown phase. During the second shutdown phase, the first transistor M1 is turned on, the second transistor M2 is turned off, the third transistor M3 is turned on, the fifth transistor M5 is turned on, and the fourth transistor M4 is turned off. The gate of the high-side switch MH continues to discharge to the reference ground through the fifth transistor M5 and the third transistor M3, completing the second shutdown phase. During the second shutdown phase, the gate charge of the high-side switch MH eventually flows to the reference ground and decreases to 0, that is, the high-side drive signal HSG decreases from 2VIN to the reference ground, and the high-side switch MH is turned off.

[0057] Figure 11 The signal waveforms of each stage during the turn-off process of the high-side switch MH according to an embodiment of the present application are given. Figure 9 and Figure 10 When the switch circuit shown is turned on, the on and off states of each transistor are Figure 9The waveforms of the various signals in the figure are described. At time t0, the pulse width modulation signal PWM jumps from logic high to logic low, and the second control signal G2 jumps from logic low to logic high to turn off the second transistor M2. After the second dead time Ts, the switch circuit 200 enters the first shutdown stage. The second dead time Ts is set here to prevent the second transistor M2 and the third transistor M3 from being turned on at the same time, which causes the input voltage VIN to be penetrated to the reference ground GND. It should be noted that the first dead time Td and the second dead time Ts are set according to the design requirements and can be the same or different. At time t1, the third control signal G3 jumps from logic low to logic high to turn on the third transistor M3. In the first shutdown phase, the first transistor M1 is turned off, the second transistor M2 is turned off, and the third transistor M3 is turned on. At this time, since the voltage VCL at the first terminal of the capacitor is greater than the low-side threshold Vth1, the comparison signal Vcs jumps to logic low, the recovery control signal G45 jumps to logic low, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off. The charge at the gate of the high-side switch MH charges the capacitor C through the turned-on fourth transistor M4. When the voltage VCL at the first terminal of the capacitor decreases to the low-side threshold Vth1, the comparison signal Vcs jumps to logic high, the recovery control signal G45 jumps from logic low to logic high, the fourth transistor M5 is turned on, and the fifth transistor M4 is turned off. The switch circuit 200 enters the second shutdown phase. In the second shutdown phase, the voltage at the gate of the high-side switch MH is reduced to 0, that is, the voltage of the reference ground, through the turned-on third transistor M3, that is, from Figure 11 It can be seen from FIG that at time t3 , the high-side drive signal HSG decreases to 0V, and the high-side switch MH is turned off.

[0058] Figure 12a A schematic diagram of an equivalent charging circuit of capacitor C in an embodiment of the present application is given. Figure 12b Given Figure 1 The equivalent charging circuit diagram of the bootstrap capacitor CBST in the switching circuit shown is shown. The circuit for charging the capacitor C is an RC charging circuit. In the embodiment of the present application, its equivalent capacitance Ceq1 is the series connection of the capacitor C and the gate-source capacitance Cgs and gate-drain capacitance Cgd of the high-side switch MH, which is much smaller than Figure 1 The equivalent capacitance Ceq2 in the switching circuit (i.e., the off-chip bootstrap capacitance CBST). For RC charging, the smaller the equivalent capacitance in the loop, the faster the charging speed. In addition, when the high-side switch MH in the switching circuit 200 of the present application switches to the charging state, the equivalent input voltage switches from the input voltage VIN connected to the second transistor M2 to 0V connected to the third transistor M3, that is, the step of the input voltage VIN is VIN, and for Figure 1For the switch circuit shown, the voltage at the positive terminal of capacitor C switches from the BST node voltage to the input voltage VIN, and the step of the input voltage VIN is less than VIN, which is one reason for the faster charging speed of this application.

[0059] In this application, since the charge recovery process is very fast, the charging process of capacitor C can be completed within a few nanoseconds. Even if the switching frequency is very high and the duty cycle is very large, it can ensure that the voltage across capacitor C is charged to VIN in each switching cycle. And Figure 1 in the switch circuit shown, as the frequency increases and the duty cycle becomes larger, the voltage across it will gradually decrease, which is because Figure 1 the charging speed of the switch circuit shown is slow. This application integrates the bootstrap capacitor CBST originally set outside the switch circuit chip, reducing the number of pins of the chip. At the same time, the bootstrap capacitor CBST is decoupled from the SW terminal, and a unique timing control is adopted to achieve segmented driving of the high-side switch MH. It can achieve the effect of recovering the gate charge of the high-side switch MH to accelerate the charging speed of the bootstrap capacitor CBST, effectively reducing the system cost, improving the EMI performance and increasing the efficiency of the switch circuit under high-frequency and large-duty-cycle conditions.

[0060] In some embodiments, the low-side switch ML is turned on and off under the control of the pulse-width modulation signal PWM, and the pulse-width modulation signal PWM includes a signal received from an external microcontroller MCU or is generated inside the switch circuit.

[0061] Figure 13 shows the circuit schematic diagram of generating the pulse-width modulation signal PWM in the embodiment of this application. The voltage source VDD provides the power supply. The operational amplifier compares the reference voltage VREF with the feedback voltage VS. When the feedback voltage VS is less than the reference voltage VREF, the operational amplifier outputs a high level. When the feedback voltage VS is greater than the reference voltage VREF, the operational amplifier outputs a low level. The output signal of the operational amplifier is coupled to the R terminal of the RS flip-flop. The oscillator OSC generates a periodic pulse signal, which is input to the S terminal of the RS flip-flop to trigger the RS flip-flop periodically. The RS flip-flop changes its output state according to the signals input to the R terminal and the S terminal. When S = 1 and R = 0 (VS < VREF), the Q terminal of the RS flip-flop outputs a high level. When R = 1 (VS > VREF), the Q terminal of the RS flip-flop outputs a low level to generate the pulse-width modulation signal PWM. It should be noted that Figure 13 the circuit for generating the pulse-width modulation signal PWM shown is only a simple schematic illustration. In one embodiment, the feedback voltage VS is generated according to the output of the switch circuit.

[0062] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A control circuit for a switching circuit, the switching circuit comprising a high-side switch and a low-side switch, the control circuit comprising: A first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal receives an input voltage; a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal receives an input voltage; a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second terminal of the second transistor; a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the capacitor, and the second terminal of the third transistor is coupled to the reference ground; a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the capacitor; as well as a fifth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the fourth transistor and outputs a high-side drive signal, the second terminal is coupled to the second terminal of the capacitor, and the control terminal of the fifth transistor is coupled to the control terminal of the fourth transistor; The high-side switch is an N-type field effect transistor, and the high-side drive signal controls the on and off of the high-side switch.

2. The control circuit according to claim 1 , wherein the conduction of the high-side switch includes a first conduction phase and a second conduction phase. In the first conduction stage, the first transistor, the third transistor and the fourth transistor are turned off, the second transistor and the fifth transistor are turned on, and the input voltage is connected to the gate terminal of the high-side switch through the turned-on second transistor; In the second conduction phase, the second transistor and the fourth transistor are turned on, the first transistor, the third transistor and the fifth transistor are turned off, and the gate terminal of the high-side switch is connected to the first terminal of the capacitor through the fourth transistor. 3 . The control circuit according to claim 2 , wherein when the voltage at the second terminal of the capacitor increases to a high-side threshold, the first conduction phase ends and the second conduction phase begins. 4 . The control circuit according to claim 3 , wherein the high-side threshold is between 80%×VIN and 95%×VIN, wherein VIN is a voltage value of the input voltage.

5. The control circuit according to claim 1 , wherein the turning off of the high-side switch comprises a first turning-off stage and a second turning-off stage. In the first shutdown phase, the third transistor and the fourth transistor are turned on, the first transistor, the second transistor, and the fifth transistor are turned off, and the gate charge of the high-side switch charges the capacitor through the fourth transistor; In the second turn-off phase, the first transistor, the third transistor, and the fifth transistor are turned on, the second transistor and the fourth transistor are turned off, and the gate terminal voltage of the high-side switch decreases to zero. 6 . The control circuit according to claim 5 , wherein when the voltage at the second terminal of the capacitor decreases to a low-side threshold, the first shutdown phase ends and the second shutdown phase begins. 7 . The control circuit according to claim 6 , wherein the low-side threshold is between 5%×VIN and 20%×VIN, wherein VIN is a voltage value of the input voltage.

8. The control circuit according to claim 1, wherein the first transistor is an N-type field effect transistor, the second transistor is a P-type field effect transistor, and the third transistor is an N-type field effect transistor.

9. The control circuit according to claim 1, wherein the fourth transistor is a P-type field effect transistor, and the fifth transistor is an N-type field effect transistor.

10. The control circuit according to claim 1, wherein the capacitance of the capacitor is between 0.1nF and 10nF. 11 . The control circuit according to claim 1 , wherein a capacitance of the capacitor increases with an increase in a width-to-length ratio of the high-side switch.

12. The control circuit according to claim 1, further comprising a recycling control circuit, wherein the recycling control circuit comprises: A trigger circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the second terminal of the capacitor, and the output terminal provides a comparison signal, wherein when the voltage at the second terminal of the capacitor is greater than a high-side threshold, the comparison signal is at a first logic level, and when the voltage at the second terminal of the capacitor is less than a low-side threshold, the comparison signal is at a second logic level; as well as The level shift circuit receives the comparison signal and generates a recovery control signal according to the comparison signal to control the on and off of the fourth transistor and the fifth transistor.

13. The control circuit of claim 12 , wherein the recovery control signal has a first logic level and a second logic level, wherein the first logic level of the comparison signal is a reference ground, the second logic level is an input voltage, the first logic level of the recovery control signal is a voltage at the second terminal of the capacitor, and the second logic level is a voltage at the first terminal of the capacitor.

14. The control circuit according to claim 12, wherein the recycling control signal has a first logic level and a second logic level, wherein when the comparison signal is at the first logic level, the recycling control signal is at the first logic level, and when the comparison signal is at the second logic level, the recycling control signal is at the second logic level.

15. The control circuit according to claim 1 further includes a logic circuit, wherein the logic circuit generates a first control signal, a second control signal, and a third control signal according to the pulse width modulation signal to control the on and off of the first transistor, the second transistor, and the third transistor, and calmly generates a high-side drive signal to control the on and off of the high-side switch, and the logic circuit also generates a low-side drive signal according to the pulse width modulation signal to control the on and off of the low-side switch. 16 . The control circuit according to claim 1 , wherein the pulse width modulation signal comprises a signal received from an external source or a signal generated internally.

17. A switching circuit comprising: A high-side switch with a source, a drain, and a gate. A low-side switch having a source terminal, a drain terminal and a gate terminal, wherein the drain terminal of the low-side switch is coupled to the source terminal of the high-side switch, and The control circuit according to any one of claims 1 to 16. 18 . The switch circuit according to claim 17 , further comprising an inductor, one end of the inductor being coupled to a common end of the high-side switch and the low-side switch.

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