A radiation-hardened front-end calibration circuit and device

Abstract

The present invention discloses a radiation-hardened foreground calibration circuit and device. The foreground calibration circuit of the present invention includes a comparator, a first trigger, a counter and accumulator, a digital-to-analog converter, and a radiation-hardened unit. The radiation-hardened unit includes a delay module, a second trigger, an XNOR gate, and an AND gate. The delay module and the second trigger delay the result signal output by the comparator to obtain a second result signal, perform an XNOR operation on the result signal obtained by the first trigger, and then perform an AND operation on the result signal with the clock signal to serve as the response signal of the counter and accumulator. The present invention aims to solve the problem that traditional foreground calibration circuits are easily affected by single particles when operating in a radiation environment, resulting in single particle function interruption and leading to space mission failure, improve the radiation-hardened capability of the foreground calibration circuit when operating in a radiation environment, and realize the radiation-hardened optimized design of the foreground calibration circuit.

Description

Technical Field

[0001] The present invention relates to a comparator foreground calibration technology in the field of analog circuits, and in particular to a foreground calibration circuit and equipment with radiation resistance reinforcement. Background Art

[0002] The front-end calibration circuit is a core submodule in the analog circuit and is generally used in front-end calibration applications such as comparator mismatch calibration, impedance matching calibration, and clock duty cycle calibration. Figure 1 As shown, a traditional front-end calibration circuit includes a comparator, an edge-triggered trigger, a counter and an accumulator (represented as a counter + accumulator in the figure), a buffer BUF, and a digital-to-analog converter. A common-mode voltage VCM is shorted across the comparator input. The output result is synchronized by an edge-triggered trigger and transmitted to the counter along with the response signal ACK from the buffer BUF. The counter counts by 1 per clock cycle. After receiving 32 results, the counter accumulates the results through the accumulator to obtain the final result. This final result is then fed back as a control word code to the digital-to-analog converter to adjust the comparator's compensation voltage CV, ultimately achieving matching across the comparator. However, when operating in a radiation environment, traditional front-end calibration circuits are susceptible to single-event interference and malfunction, leading to space mission failure. Summary of the Invention

[0003] Technical problem to be solved by the present invention: In response to the above-mentioned problems of the prior art, a front-end calibration circuit and equipment with radiation hardening are provided. The present invention aims to solve the problem that the traditional front-end calibration circuit is easily affected by single particles when operating in a radiation environment, resulting in single particle function interruption and leading to space mission failure, improve the radiation hardening capability of the front-end calibration circuit when operating in a radiation environment, and realize the radiation hardening optimization design of the front-end calibration circuit.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A radiation-hardened front-end calibration circuit includes a comparator, a first trigger, a counter and an accumulator, a digital-to-analog converter, and an radiation-hardened unit. The radiation-hardened unit includes a delay module delay, a second trigger, an exclusive-OR gate, and an AND gate. The first trigger is used to synchronize the result signal COMP_OUT output by the comparator to obtain a first result signal result and output it to the counter and the accumulator. The delay module delay and the second trigger are used to delay and synchronize the result signal COMP_OUT output by the comparator to obtain a second result signal result1, and the second result signal result1 and the first result signal result are output to the counter and the accumulator as two inputs of the exclusive-OR gate respectively. The output of the exclusive-OR gate and the clock signal CLK of the second trigger are respectively used as two inputs of the AND gate, and the output of the AND gate is used as a response signal ACK of the counter and the accumulator.

[0006] Optionally, delaying and synchronizing the result signal COMP_OUT output by the comparator to obtain the second result signal result1 means first delaying the result signal COMP_OUT output by the comparator by a delay module and then synchronizing it by a second trigger to obtain the second result signal result1.

[0007] Optionally, the delay module delay is composed of an inverter or a trigger.

[0008] Optionally, a common mode voltage VCM is short-circuited across the input of the comparator.

[0009] Optionally, the feedback control word code and the clock signal CLK0 output by the counter and accumulator are respectively connected to the input end of the digital-to-analog converter, so as to generate the compensation voltage CV and the clock signal CLK for adjusting the comparator through the digital-to-analog converter.

[0010] Optionally, the clock signal input terminal CK of the second flip-flop is connected to the clock signal CLK.

[0011] Optionally, the counter and accumulator include a counter and an accumulator, the counter counts 1 per clock cycle and records the first result result, after receiving 32 clock cycles in total, the 32 recorded first results result are accumulated and calculated by the accumulator to obtain the final result, and the control word code is output to the digital-to-analog converter based on the final result for adjusting the compensation voltage CV of the comparator to match the two ends of the comparator.

[0012] In addition, the present invention also provides an electronic device, including a device body and a circuit module arranged in the device body, wherein the circuit module includes the anti-radiation reinforced foreground calibration circuit.

[0013] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: the anti-radiation reinforcement unit of the present invention includes a delay module delay, a second trigger, an exclusive-OR gate and an AND gate, the first trigger is used to synchronize the result signal COMP_OUT output by the comparator to obtain a first result signal result and output it to the counter and accumulator, the delay module delay and the second trigger are used to delay and synchronize the result signal COMP_OUT output by the comparator to obtain a second result signal result1, and the second result signal result1 and the first result signal result are respectively used as the two inputs of the exclusive-OR gate, the output of the exclusive-OR gate and the clock signal CLK of the second trigger are respectively used as the two inputs of the AND gate, and the output of the AND gate is used as the response signal ACK of the counter and accumulator, so that it can solve the problem that the traditional foreground calibration circuit is easily affected by single particles when operating in a radiation environment, resulting in single particle function interruption and causing space mission failure, improve the anti-radiation reinforcement capability of the foreground calibration circuit when operating in a radiation environment, and realize the anti-radiation reinforcement optimization design of the foreground calibration circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the circuit principle of the traditional front-end calibration circuit.

[0015] Figure 2 2 is a schematic diagram of the circuit principle of the foreground calibration circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0017] like Figure 2As shown, the radiation-hardened foreground calibration circuit in this embodiment includes a comparator, a first trigger, a counter and accumulator, a digital-to-analog converter, and a radiation-hardened unit. The radiation-hardened unit includes a delay module delay, a second trigger, an exclusive-OR gate, and an AND gate. The first trigger is used to synchronize the result signal COMP_OUT output by the comparator to obtain a first result signal result and output it to the counter and accumulator. The delay module delay and the second trigger are used to delay and synchronize the result signal COMP_OUT output by the comparator to obtain a second result signal result1. The second result signal result1 and the first result signal result serve as the two inputs of the exclusive-OR gate respectively. The output of the exclusive-OR gate and the clock signal CLK of the second trigger serve as the two inputs of the AND gate respectively. The output of the AND gate serves as the response signal ACK of the counter and accumulator. The radiation-hardened foreground calibration circuit in this embodiment is designed based on the typical foreground calibration circuit, with a delay module delay, a trigger DFF, an exclusive-OR gate, and an AND gate for radiation-hardened design. In fact, it connects the output of the comparator in parallel with another branch, and designs a delay module on this branch to make the data signals of the two branches have a delay difference. Figure 2 As shown, the outputs of the flip-flops in the two branches, the second result signal (result1) and the first result signal (result), are connected to the two ends of a two-input XNOR gate. If the two inputs differ, the output is a logic "0." The output of the XNOR gate and the synchronous clock CLK serve as the inputs of a two-input AND gate, which outputs the response signal ACK. If either input is a logic "0," the output ACK is a logic "0."

[0018] In this embodiment, delaying and synchronizing the comparator output result signal COMP_OUT to obtain the second result signal result1 means first delaying the comparator output result signal COMP_OUT through a delay module delay, and then synchronizing the delay signal through a second flip-flop to obtain the second result signal result1. In this embodiment, the delay module delay is composed of an inverter or a flip-flop. The delay module delay composed of an inverter or a flip-flop can cause a delay difference between the two branch data signals (the second result signal result1 and the first result signal result).

[0019] like Figure 2As shown, a common-mode voltage VCM is short-circuited across the input terminals of the comparator in this embodiment. The feedback control word code and clock signal CLK0 output by the counter and accumulator in this embodiment are respectively connected to the input terminals of a digital-to-analog converter, for use in generating a compensation voltage CV and a clock signal CLK for adjusting the comparator via the digital-to-analog converter. The clock signal input terminal CK of the second flip-flop in this embodiment is connected to the clock signal CLK. The counter and accumulator in this embodiment include a counter and an accumulator. The counter counts 1 per clock cycle and records a first-path result (result). After accumulating 32 clock cycles, the 32 recorded first-path results (result) are accumulated to obtain a final result. Based on the final result, a control word code is output to the digital-to-analog converter for adjusting the compensation voltage CV of the comparator to achieve matching between the two terminals of the comparator.

[0020] The working principle of the radiation-hardened front-end calibration circuit in this embodiment is as follows: Figure 1 In the traditional front-end calibration circuit shown in the figure, once any module among the comparator, trigger and clock driver is bombarded by a single particle in the radiation environment, the result signal output to the counter will change, and a single particle transient pulse will be output, resulting in calibration errors. Figure 2 The radiation hardened front-end calibration circuit shown in the present embodiment does not. Figure 2 In the illustrated structure, a single-event strike in a radiation environment can cause the comparator to change its result signal COMP_OUT, resulting in a single-event transient pulse output. However, the delay module in the parallel branch delays the result signal COMP_OUT, resulting in a delay difference between the single-event transient pulse generated in the second result signal result1 and the first result signal result. During the duration of this delay difference, the XOR gate detects the logic level discrepancy between the two inputs and outputs a logic "0," causing the ACK signal output by the AND gate to continuously output a logic "0." The counter stops counting and does not record the input result signal, unaffecting the calibration results. After the single-event effect ends, normal calibration function resumes. If either trigger is struck by a single-event strike in a radiation environment, the second result signal result1 or the first result signal result will change. The XOR gate detects the logic level discrepancy between the two inputs and outputs a logic "0," causing the ACK signal output by the AND gate to continuously output a logic "0," causing the counter to stop counting the input result signal and unaffecting the calibration results. After the single-event effect ends, normal calibration function resumes. When an XNOR gate or AND gate is bombarded by a single particle in a radiation environment, the ACK signal will continue to output logic "0". The counter will not count the input result signal and will not affect the calibration result. After the single particle effect ends, the normal calibration function will be restored.

[0021] In addition, this embodiment also provides an electronic device, including a device body and a circuit module provided in the device body, wherein the circuit module includes the radiation-hardened foreground calibration circuit.

[0022] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A radiation-hardened front-end calibration circuit, characterized in that: It includes a comparator, a first trigger, a counter and accumulator, a digital-to-analog converter and an anti-radiation hardening unit, wherein the anti-radiation hardening unit includes a delay module delay, a second trigger, an exclusive-OR gate and an AND gate, wherein the first trigger is used to synchronize the result signal COMP_OUT output by the comparator to obtain a first result signal result and output it to the counter and accumulator, the delay module delay and the second trigger are used to delay and synchronize the result signal COMP_OUT output by the comparator to obtain a second result signal result1, and the second result signal result1 and the first result signal result are respectively used as two inputs of the exclusive-OR gate, the output of the exclusive-OR gate and the clock signal CLK of the second trigger are respectively used as two inputs of the AND gate, and the output of the AND gate is used as a response signal ACK of the counter and accumulator; The delaying and synchronizing the result signal COMP_OUT output by the comparator to obtain the second result signal result1 means that the result signal COMP_OUT output by the comparator is first delayed by the delay module, and then synchronized by the second trigger to obtain the second result signal result1; The two input terminals of the comparator are short-circuited with a common mode voltage VCM; The feedback control word code and the clock signal CLK0 output by the counter and the accumulator are respectively connected to the input end of the digital-to-analog converter, so as to generate the compensation voltage CV and the clock signal CLK for adjusting the comparator through the digital-to-analog converter.

2. The radiation hardened foreground calibration circuit according to claim 1, wherein: The delay module delay is composed of an inverter or a trigger.

3. The radiation hardened foreground calibration circuit according to claim 1, wherein: The clock signal input terminal CK of the second flip-flop is connected to the clock signal CLK.

4. The radiation hardened foreground calibration circuit according to claim 1, wherein: The counter and accumulator include a counter and an accumulator. The counter counts 1 in each clock cycle, and after receiving 32 first-channel result signals, the counter accumulates the results through the accumulator to obtain a final result. According to the final result, the control word code is output to the digital-to-analog converter for adjusting the compensation voltage CV of the comparator to match the two ends of the comparator.

5. An electronic device comprising a device body and a circuit module disposed in the device body, characterized in that: The circuit module includes the radiation-hardened foreground calibration circuit according to any one of claims 1 to 4.

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