Network equipment port isolation circuit
By using multiple port isolation units in network equipment, including common mode filtering and isolation modules, the problems of large space and high cost of port isolation circuits in network equipment are solved, and equipment miniaturization and cost reduction are achieved.
Patent Information
- Application Number
- CN202410216293.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-08-29
AI Technical Summary
The existing network equipment port isolation circuit takes up a lot of space, which makes it difficult to miniaturize the equipment and is costly.
It adopts multiple port isolation units, including the first and second common mode filter modules and isolation modules, and uses conventional devices such as capacitors, resistors and common mode inductors. It has simple design and strong adaptability.
It achieves miniaturization of equipment and reduces costs, adapts to the needs of different application scenarios, has low device prices and is easy to design.
Smart Images
Figure CN120567149A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technology, and in particular to a network equipment port isolation circuit. Background Art
[0002] With the development of communications and IoT technologies, network devices with Ethernet ports are becoming more and more common, and the demand for miniaturized devices is also increasing. In practical applications, the isolation circuits for Ethernet port signals occupy a large space, becoming a bottleneck that urgently needs to be addressed in network device design.
[0003] In some scenarios, network equipment requires long transmission distances. This is especially true when the two devices share a common ground. This can create significant potential differences, potentially damaging the chips. Furthermore, the two devices may experience inconsistent voltage levels. For example, PHY chips offer 1.8V, 2.5V, and 3.3V outputs. Furthermore, some PHY chips use voltage-driven signals, while others use current-driven signals. Directly connecting these signals can easily lead to electrical signal mismatches, resulting in device damage and other anomalies. For these reasons, network equipment signals must be isolated. Signal isolation effectively blocks the effects of DC voltage on the signals and reduces interference from external devices.
[0004] Due to the isolation requirements for network port circuits, most current devices use a 1:1 transformer as an isolation device. Transformers are inherently large due to their magnetic core and shielded casing. Furthermore, due to the need for common-mode suppression, some transformers also feature a center tap and increased common-mode inductance. This results in increasingly larger transformers and a growing number of pins. In hardware design, the network port transformer often occupies the largest space, making device miniaturization challenging. Existing technology integrates the network port transformer and RJ45 port to save space. While this reduces space somewhat, these components are very expensive, making hardware miniaturization expensive.
[0005] This demonstrates the need for a novel network device port isolation circuit to address the issues of traditional solutions, such as large space requirements and difficulty miniaturizing the device. Furthermore, this solution features a simple circuit, is easy to implement, and utilizes conventional passive components, resulting in low cost. This significantly reduces the size and cost of network equipment. Summary of the Invention
[0006] The technical purpose to be achieved by the present invention is to provide a network device port isolation circuit, thereby achieving miniaturization and low cost of the device.
[0007] Based on the above technical objectives, the present invention provides a network device port isolation circuit, which includes a plurality of port isolation units arranged in the channel between the Ethernet interface and the PHY chip, and each port isolation unit corresponds to a channel;
[0008] The port isolation unit includes a first common-mode filtering module, a second common-mode filtering module, and an isolation module, wherein the first common-mode filtering module includes a first common-mode inductor, the first common-mode inductor includes a first coil and a second coil, a first interface and a third interface of the first common-mode inductor are connected to two ends of the first coil, and a second interface and a fourth interface of the first common-mode inductor are connected to two ends of the second coil;
[0009] The second common-mode filtering module includes a second common-mode inductor, which includes a third coil and a fourth coil. The first interface and the third interface of the second common-mode inductor are connected to two ends of the third coil, and the second interface and the fourth interface of the second common-mode inductor are connected to two ends of the fourth coil.
[0010] The isolation module includes a first capacitor, a second capacitor, a first resistor and a second resistor;
[0011] The first interface of the first common-mode choke and the fourth interface of the first common-mode choke are both grounded; the third interface of the first common-mode choke is connected to the first interface of the second common-mode choke, and the second interface of the first common-mode choke is connected to the second interface of the second common-mode choke; the third interface of the first common-mode choke is connected to the first communication port on the Ethernet interface side of the channel, and the second interface of the first common-mode choke is connected to the second communication port on the Ethernet interface side of the channel;
[0012] The first port of the first capacitor in the isolation module is connected to the first port of the first resistor, the first port of the second capacitor is connected to the first port of the second resistor, and the second port of the first resistor is connected to the second port of the second resistor; the second port of the first capacitor is connected to the third port of the second common-mode inductor, and the second port of the second capacitor is connected to the fourth port of the second common-mode inductor;
[0013] The first port of the first capacitor is connected to the first communication port on the PHY chip side of the channel, and the first port of the second capacitor is connected to the second communication port on the PHY chip side of the channel.
[0014] In one embodiment, the isolation module further includes a third capacitor, a first port of the third capacitor is connected to the second port of the first resistor, and a second port of the third capacitor is grounded.
[0015] In one embodiment, the second port of the first resistor in the isolation module is connected to a bias voltage.
[0016] In one embodiment, the network device port isolation circuit also includes an interference unit, which includes a third resistor and a fourth capacitor. A pair of channel interfaces among the multiple pairs of channel interfaces on the Ethernet interface side are short-circuited and connected to the first end of the third resistor, the second end of the third resistor is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the chassis ground of the Ethernet interface.
[0017] In one embodiment, the first capacitor and the second capacitor are 100 nF.
[0018] In one embodiment, the first resistor and the second resistor are 50Ω.
[0019] In one embodiment, the third capacitor is 100nF.
[0020] In one embodiment, the third resistor is 75Ω.
[0021] Compared with the prior art, the inventive points of the present invention described in one or more embodiments include:
[0022] 1. The circuit is simple and easy to implement. Devices with different parameters can be selected according to the application scenario requirements. The design is highly variable and adaptable.
[0023] 2. The main components are conventional components such as capacitors, resistors, and common-mode inductors. These components take up little space, are low-priced, and are easy to design for miniaturization and cost-effectiveness.
[0024] The above-mentioned inventive points are set forth throughout the technical solutions of the present invention. Other features and advantages of the present invention will be set forth in the following description and, in part, will become apparent from the description or learned through practice of the present invention. The objectives and other advantages of the present invention may be achieved and obtained through the structures particularly pointed out in the description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0026] Figure 1 It is a schematic diagram of a voltage-type gigabit network port isolation circuit of the present invention;
[0027] Figure 2 This is a schematic diagram of a voltage-type 100M network port isolation circuit of the present invention;
[0028] Figure 3This is a schematic diagram of a current-mode gigabit network port isolation circuit according to the present invention;
[0029] Figure 4 This is a schematic diagram of the current-type 100M network port isolation circuit of the present invention. DETAILED DESCRIPTION
[0030] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.
[0031] Before proceeding with the detailed description below, it may be beneficial to set forth the definitions of certain words and phrases used throughout the present invention. The terms "coupled," "connected," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate, intertwine, parallel, close to, bound or bound with, having, having an attribute, having a relationship, or having a relationship with, etc. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.
[0032] The description of the first and second ends of a resistor, capacitor, or inductor in this disclosure is intended solely to distinguish the two connection ends of the device, facilitating description of the device's connection relationship with other devices. It does not specifically designate a particular end of the resistor, capacitor, or inductor in actual practice. Those skilled in the art will appreciate that, in actual circuit construction, any end of a resistor, capacitor, or inductor in an actual device can be defined as the first end. When the first end is defined, the other end of the device is automatically designated as the second end.
[0033] When describing various components in this disclosure, the terms "first," "second," "third," and so on are used solely to distinguish the components and to express the distinct relationships between them. These terms themselves do not imply any relationships between the components. For example, the mere mention of "first" and "third" does not imply the existence of a "second" between them. The "first" and "third" terms simply indicate the existence of two distinct, independent components.
[0034] Definitions of other specific words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.
[0035] In the present invention, the application combination of modules and the division level of sub-modules are only used for illustration, and the application combination of modules and the division level of sub-modules may be in different ways without departing from the scope of the present disclosure.
[0036] Example 1
[0037] like Figure 1 The voltage-type gigabit network port isolation circuit of the present invention shown in the figure includes a plurality of port isolation units 100 arranged in the channel between the Ethernet interface and the PHY chip, and each port isolation unit 100 corresponds to a channel, and the port isolation unit 100 includes a first common-mode filtering module 1, a second common-mode filtering module 2 and an isolation module 3, wherein the first common-mode filtering module 1 includes a first common-mode inductor L1, and the first common-mode inductor L1 includes a first coil 10 and a second coil 11, and the first interface and the third interface of the first common-mode inductor L1 are connected to the two ends of the first coil 10, and the second interface and the fourth interface of the first common-mode inductor L1 are connected to the two ends of the second coil 11.
[0038] The second common-mode filtering module 2 includes a second common-mode inductor L2, which includes a third coil 20 and a fourth coil 21. The first interface and the third interface of the second common-mode inductor L2 are connected to the two ends of the third coil 20, and the second interface and the fourth interface of the second common-mode inductor L2 are connected to the two ends of the fourth coil 21.
[0039] The isolation module 3 includes a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , a first resistor R1 , and a second resistor R2 .
[0040] In this embodiment, the first interface of L1 of the first common-mode choke and the fourth interface of L1 of the first common-mode choke are both grounded. The third interface of L1 of the first common-mode choke is connected to the first interface of L2 of the second common-mode choke, and the second interface of L1 of the first common-mode choke is connected to the second interface of L2 of the second common-mode choke. Furthermore, the third interface of L1 of the first common-mode choke is connected to the first communication port on the Ethernet interface side of the channel, and the second interface of L1 of the first common-mode choke is connected to the second communication port on the Ethernet interface side of the channel.
[0041] In this embodiment, the first port of the first capacitor C1 in the isolation module 3 is connected to the first port of the first resistor R1, the first port of the second capacitor C2 is connected to the first port of the second resistor R2, and the second port of the first resistor R1 is connected to the second port of the second resistor R2. The first port of the third capacitor C3 is connected to the second port of the first resistor R1, and the second port of the third capacitor C3 is grounded. The second port of the first capacitor C1 is connected to the third port of the second common-mode inductor L2, and the second port of the second capacitor C2 is connected to the fourth port of the second common-mode inductor L2.
[0042] In this embodiment, the first port of the first capacitor C1 is connected to the first communication port on the PHY chip side of the channel, and the first port of the second capacitor C2 is connected to the second communication port on the PHY chip side of the channel.
[0043] In this embodiment, the gigabit network port has four pairs of differential signals, and the design parameters of each pair of signals are the same, that is, in this embodiment, there are four identical port isolation units 100, and each port isolation unit 100 is arranged between a pair of differential signals.
[0044] For isolation module 3, the signal output by the PHY chip is a differential signal, in which the main components that play an isolation role are the first capacitor C1 and the second capacitor C2. The voltage-type gigabit network port needs to adapt to the communication rate of 1000M / 100M / 10M. According to the principle that capacitors block direct current and pass alternating current, and the low-pass filtering performance of series capacitors. The larger the capacitor, the greater the minimum frequency that can pass. Therefore, in the selection of capacitors, it is necessary to select (10M) according to the lowest communication rate. It is not possible to select too large a capacitor, otherwise it will affect the communication at a low rate. Of course, the capacitor cannot be selected too small, otherwise the performance of the filter will be greatly reduced, so that some interference signals cannot be effectively filtered out or attenuated. According to actual application and testing, C1 and C2 select the best capacitor of 100nF. The capacitor withstand voltage value can be selected according to the actual application scenario. For example, if the device needs to pass a 2000KV surge test, a capacitor of 100nF / 2000V is selected.
[0045] The first resistor R1 and the second resistor R2 are 50Ω resistors, which primarily filter out differential-mode interference from the signal. The third capacitor C3 is a 100nF filter capacitor that complements R1 and R2. The combination of R1 / R2 and C3 forms an RC filter that filters out differential-mode interference from the signal. The parameters for R1 / R2 are 50Ω / 0402, and the parameters for C3 are 100nF / 0402 / 50V.
[0046] The second common-mode inductor L2 is a common-mode filter. Its main function is to filter out common-mode interference on the signal line, enhance signal stability, and increase signal transmission distance. The key selection parameter for the second common-mode inductor L2 is common-mode impedance. Choose one with a common-mode impedance of 800 Ω or higher at 100 MHz. Other parameters, such as DC resistance and rated current, can be determined based on the actual PHY chip. For example, the UTC2012C01 common-mode inductor has a common-mode impedance of 800 Ω or higher at 100 MHz, a DC resistance of 0.9 Ω, and a rated current of 300 mA.
[0047] The first common-mode inductor L1 is a common-mode filter, whose main function is to filter out differential-mode interference introduced from the opposite device and enhance signal stability. And because one end of the inductor is connected to the signal line and the other end is connected to the device GND, this common-mode inductor also has a certain surge resistance capability. It can directly introduce the surge current connected to the signal line of the opposite device directly into the GND, reducing the surge impact on the device. The key selection parameter of L1 is the inductance value. Select a common-mode inductor with an inductance value of 60uH Min.@100KHz / 0.1V. Other parameters such as DC resistance and rated current are also selected according to actual conditions. For example, if you need to pass the surge test, select a common-mode inductor with a maximum current that can withstand the surge current. If there is no such requirement, you can choose the UTD3216C01 common-mode inductor.
[0048] In this embodiment, the Ethernet interface is an RJ45 interface.
[0049] Example 2
[0050] like Figure 2The voltage-type 100M network port isolation circuit of the present invention shown in the figure includes a plurality of port isolation units 100 and an interference unit 200 arranged in the channel between the Ethernet interface and the PHY chip, and each port isolation unit 100 corresponds to a channel, and the port isolation unit 100 includes a first common-mode filtering module 1, a second common-mode filtering module 2 and an isolation module 3, wherein the first common-mode filtering module 1 includes a first common-mode inductor L1, and the first common-mode inductor L1 includes a first coil 10 and a second coil 11, and the first interface and the third interface of the first common-mode inductor L1 are connected to the two ends of the first coil 10, and the second interface and the fourth interface of the first common-mode inductor L1 are connected to the two ends of the second coil 11.
[0051] The second common-mode filtering module 2 includes a second common-mode inductor L2, which includes a third coil 20 and a fourth coil 21. The first interface and the third interface of the second common-mode inductor L2 are connected to the two ends of the third coil 20, and the second interface and the fourth interface of the second common-mode inductor L2 are connected to the two ends of the fourth coil 21.
[0052] The isolation module 3 includes a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , a first resistor R1 , and a second resistor R2 .
[0053] In this embodiment, the first interface of L1 of the first common-mode choke and the fourth interface of L1 of the first common-mode choke are both grounded. The third interface of L1 of the first common-mode choke is connected to the first interface of L2 of the second common-mode choke, and the second interface of L1 of the first common-mode choke is connected to the second interface of L2 of the second common-mode choke. Furthermore, the third interface of L1 of the first common-mode choke is connected to the first communication port on the Ethernet interface side of the channel, and the second interface of L1 of the first common-mode choke is connected to the second communication port on the Ethernet interface side of the channel.
[0054] In this embodiment, the first port of the first capacitor C1 in the isolation module 3 is connected to the first port of the first resistor R1, the first port of the second capacitor C2 is connected to the first port of the second resistor R2, and the second port of the first resistor R1 is connected to the second port of the second resistor R2. The first port of the third capacitor C3 is connected to the second port of the first resistor R1, and the second port of the third capacitor C3 is grounded. The second port of the first capacitor C1 is connected to the third port of the second common-mode inductor L2, and the second port of the second capacitor C2 is connected to the fourth port of the second common-mode inductor L2.
[0055] In this embodiment, the first port of the first capacitor C1 is connected to the first communication port on the PHY chip side of the channel, and the first port of the second capacitor C2 is connected to the second communication port on the PHY chip side of the channel.
[0056] The interference unit 200 includes a third resistor R3 and a fourth capacitor C4. A pair of channel interfaces on the Ethernet interface side are short-circuited and connected to the first end of the third resistor R3. The second end of the third resistor R3 is connected to the first end of the fourth capacitor C4. The second end of the fourth capacitor C4 is connected to the chassis ground of the Ethernet interface.
[0057] In this embodiment, the interference unit 200 further includes a fourth resistor R4. Another pair of channel interfaces on the Ethernet interface side are short-circuited and connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the first end of the fourth capacitor C4.
[0058] In this embodiment, the parameter selection of components in the port isolation unit 100 is the same as that in the aforementioned embodiment 1. In the interference unit 200, R3 / R4 are 75Ω / 0603 resistors, and C4 is a 1nF / 2000V high-voltage capacitor.
[0059] Example 3
[0060] like Figure 3 The current-mode gigabit network port isolation circuit of the present invention shown in the figure includes a plurality of port isolation units 100 arranged in the channel between the Ethernet interface and the PHY chip, and each port isolation unit 100 corresponds to a channel, and the port isolation unit 100 includes a first common-mode filtering module 1, a second common-mode filtering module 2 and an isolation module 3, wherein the first common-mode filtering module 1 includes a first common-mode inductor L1, and the first common-mode inductor L1 includes a first coil 10 and a second coil 11, and the first interface and the third interface of the first common-mode inductor L1 are connected to the two ends of the first coil 10, and the second interface and the fourth interface of the first common-mode inductor L1 are connected to the two ends of the second coil 11.
[0061] The second common-mode filtering module 2 includes a second common-mode inductor L2, which includes a third coil 20 and a fourth coil 21. The first interface and the third interface of the second common-mode inductor L2 are connected to the two ends of the third coil 20, and the second interface and the fourth interface of the second common-mode inductor L2 are connected to the two ends of the fourth coil 21.
[0062] The isolation module 3 includes a first capacitor C1 , a second capacitor C2 , a first resistor R1 , and a second resistor R2 .
[0063] In this embodiment, the first interface of L1 of the first common-mode choke and the fourth interface of L1 of the first common-mode choke are both grounded. The third interface of L1 of the first common-mode choke is connected to the first interface of L2 of the second common-mode choke, and the second interface of L1 of the first common-mode choke is connected to the second interface of L2 of the second common-mode choke. Furthermore, the third interface of L1 of the first common-mode choke is connected to the first communication port on the Ethernet interface side of the channel, and the second interface of L1 of the first common-mode choke is connected to the second communication port on the Ethernet interface side of the channel.
[0064] In this embodiment, the first port of the first capacitor C1 in the isolation module 3 is connected to the first port of the first resistor R1, the first port of the second capacitor C2 is connected to the first port of the second resistor R2, and the second port of the first resistor R1 is connected to the second port of the second resistor R2. Furthermore, the second port of the first resistor R1 is connected to the bias voltage VCC. The second port of the first capacitor C1 is connected to the third port of the second common-mode inductor L2, and the second port of the second capacitor C2 is connected to the fourth port of the second common-mode inductor L2.
[0065] In this embodiment, the first port of the first capacitor C1 is connected to the first communication port on the PHY chip side of the channel, and the first port of the second capacitor C2 is connected to the second communication port on the PHY chip side of the channel.
[0066] In this embodiment, the gigabit network port has four pairs of differential signals, and the design parameters of each pair of signals are the same, that is, in this embodiment, there are four identical port isolation units 100, and each port isolation unit 100 is arranged between a pair of differential signals.
[0067] In this embodiment, the selection of component parameters in the port isolation unit 100 is the same as that in the aforementioned embodiment 1.
[0068] Example 4
[0069] like Figure 4The current-type 100M network port isolation circuit of the present invention shown in the figure includes a plurality of port isolation units 100 and an interference unit 200 arranged in the channel between the Ethernet interface and the PHY chip, and each port isolation unit 100 corresponds to a channel, and the port isolation unit 100 includes a first common-mode filter module 1, a second common-mode filter module 2 and an isolation module 3, wherein the first common-mode filter module 1 includes a first common-mode inductor L1, and the first common-mode inductor L1 includes a first coil 10 and a second coil 11, and the first interface and the third interface of the first common-mode inductor L1 are connected to the two ends of the first coil 10, and the second interface and the fourth interface of the first common-mode inductor L1 are connected to the two ends of the second coil 11.
[0070] The second common-mode filtering module 2 includes a second common-mode inductor L2, which includes a third coil 20 and a fourth coil 21. The first interface and the third interface of the second common-mode inductor L2 are connected to the two ends of the third coil 20, and the second interface and the fourth interface of the second common-mode inductor L2 are connected to the two ends of the fourth coil 21.
[0071] The isolation module 3 includes a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , a first resistor R1 , and a second resistor R2 .
[0072] In this embodiment, the first interface of L1 of the first common-mode choke and the fourth interface of L1 of the first common-mode choke are both grounded. The third interface of L1 of the first common-mode choke is connected to the first interface of L2 of the second common-mode choke, and the second interface of L1 of the first common-mode choke is connected to the second interface of L2 of the second common-mode choke. Furthermore, the third interface of L1 of the first common-mode choke is connected to the first communication port on the Ethernet interface side of the channel, and the second interface of L1 of the first common-mode choke is connected to the second communication port on the Ethernet interface side of the channel.
[0073] In this embodiment, the first port of the first capacitor C1 in the isolation module 3 is connected to the first port of the first resistor R1, the first port of the second capacitor C2 is connected to the first port of the second resistor R2, and the second port of the first resistor R1 is connected to the second port of the second resistor R2. The first port of the third capacitor C3 is connected to the second port of the first resistor R1. Simultaneously, the second port of the first resistor R1 is connected to the bias voltage VCC. The second port of the first capacitor C1 is connected to the third port of the second common-mode inductor L2, and the second port of the second capacitor C2 is connected to the fourth port of the second common-mode inductor L2.
[0074] In this embodiment, the first port of the first capacitor C1 is connected to the first communication port on the PHY chip side of the channel, and the first port of the second capacitor C2 is connected to the second communication port on the PHY chip side of the channel.
[0075] The interference unit 200 includes a third resistor R3 and a third capacitor C3. A pair of channel interfaces on the Ethernet interface side are short-circuited and connected to the first end of the third resistor R3. The second end of the third resistor R3 is connected to the first end of the third capacitor C3. The second end of the third capacitor C3 is connected to the chassis ground of the Ethernet interface.
[0076] In this embodiment, the interference unit 200 further includes a fourth resistor R4. Another pair of channel interfaces on the Ethernet interface side are short-circuited and connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the first end of the third capacitor C3.
[0077] In this embodiment, the parameter selection of components in the port isolation unit 100 is the same as that in the aforementioned embodiment 1. In the interference unit 200, R3 / R4 are 75Ω / 0603 resistors, and C3 is a 1nF / 2000V high-voltage capacitor.
[0078] The above description is only a specific implementation case of the present invention, and the protection scope of the present invention is not limited thereto. Any modification or replacement of the present invention by any technician familiar with this technology within the technical specifications described in the present invention should be within the protection scope of the present invention.
Claims
1. A network device port isolation circuit, characterized in that: The network device port isolation circuit includes a plurality of port isolation units arranged in a channel between the Ethernet interface and the PHY chip, and each port isolation unit corresponds to a channel; The port isolation unit includes a first common-mode filtering module, a second common-mode filtering module, and an isolation module, wherein the first common-mode filtering module includes a first common-mode inductor, the first common-mode inductor includes a first coil and a second coil, a first interface and a third interface of the first common-mode inductor are connected to two ends of the first coil, and a second interface and a fourth interface of the first common-mode inductor are connected to two ends of the second coil; The second common-mode filtering module includes a second common-mode inductor, which includes a third coil and a fourth coil. The first interface and the third interface of the second common-mode inductor are connected to two ends of the third coil, and the second interface and the fourth interface of the second common-mode inductor are connected to two ends of the fourth coil. The isolation module includes a first capacitor, a second capacitor, a first resistor and a second resistor; The first interface of the first common-mode choke and the fourth interface of the first common-mode choke are both grounded; the third interface of the first common-mode choke is connected to the first interface of the second common-mode choke, and the second interface of the first common-mode choke is connected to the second interface of the second common-mode choke; the third interface of the first common-mode choke is connected to the first communication port on the Ethernet interface side of the channel, and the second interface of the first common-mode choke is connected to the second communication port on the Ethernet interface side of the channel; The first port of the first capacitor in the isolation module is connected to the first port of the first resistor, the first port of the second capacitor is connected to the first port of the second resistor, and the second port of the first resistor is connected to the second port of the second resistor; the second port of the first capacitor is connected to the third port of the second common-mode inductor, and the second port of the second capacitor is connected to the fourth port of the second common-mode inductor; The first port of the first capacitor is connected to the first communication port on the PHY chip side of the channel, and the first port of the second capacitor is connected to the second communication port on the PHY chip side of the channel.
2. The network device port isolation circuit according to claim 1, characterized in that: The isolation module further includes a third capacitor, a first port of the third capacitor is connected to the second port of the first resistor, and a second port of the third capacitor is grounded.
3. The network device port isolation circuit according to claim 1, characterized in that: The second port of the first resistor in the isolation module is connected to a bias voltage.
4. The network device port isolation circuit according to any one of claims 1 to 3, characterized in that: The network device port isolation circuit also includes an interference unit, which includes a third resistor and a fourth capacitor. A pair of channel interfaces among the multiple pairs of channel interfaces on the Ethernet interface side are short-circuited and connected to the first end of the third resistor, the second end of the third resistor is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the chassis ground of the Ethernet interface.
5. The network device port isolation circuit according to claim 1, characterized in that: The first capacitor and the second capacitor are 100nF.
6. The network device port isolation circuit according to claim 1, characterized in that: The first resistor and the second resistor are 50Ω.
7. The network device port isolation circuit according to claim 4, characterized in that: The third capacitor is 100nF.
8. The network device port isolation circuit according to claim 4, characterized in that: The third resistor is 75Ω.
9. An integrated circuit structure, comprising the network device port isolation circuit according to any one of claims 1 to 7.