Subnanosecond transmission delay high anti-noise capacitance isolation type level shift circuit
Through capacitive isolation and signal conversion unit, combined with NMOS and PMOS tube design, the transmission delay and isolation problems of the level shift module are solved, sub-nanosecond delay and noise immunity are achieved, and high-frequency and high-speed application needs are met.
Patent Information
- Application Number
- CN202510681398.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-26
- Publication Date
- 2025-08-29
AI Technical Summary
The existing level shift modules have problems such as large transmission delay, poor isolation and insufficient noise immunity, which are difficult to meet the needs of high-frequency and high-speed applications.
Capacitive isolation unit, shift main unit, anti-common mode interference unit and differential mode compensation unit are adopted to replace LDMOS devices through high-voltage capacitors, combined with the design of NMOS tubes and PMOS tubes, voltage domain conversion and signal isolation are realized, common mode and differential mode noise are suppressed, and node potential difference is ensured within the withstand voltage range of low-voltage devices.
It realizes sub-nanosecond transmission delay, excellent isolation performance, suppresses common mode and differential mode noise interference, protects the voltage withstand safety of low-voltage devices, meets the needs of high-frequency and high-speed applications, and reduces power consumption.
Smart Images
Figure CN120567152A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power management, and in particular to a high-noise-resistant capacitor isolation type level shift circuit with sub-nanosecond transmission delay. Background Art
[0002] In modern power electronics, half-bridge driver ICs serve as the core control components of power conversion systems, and their performance directly impacts the efficiency, reliability, and stability of the entire system. Level shift modules, the critical bridge connecting the input stage (low-voltage domain) and the high-side driver stage (high-voltage domain) within a half-bridge driver IC, perform the crucial tasks of voltage domain conversion and signal isolation.
[0003] The level shift module needs to use high-voltage devices to complete the voltage domain conversion. Traditional level shift modules mostly use a combination of high-voltage devices (such as LDMOS, that is, laterally diffused metal oxide semiconductor) and resistors. For the specific structure, please refer to Figure 1 However, this structure has exposed many problems in practical applications: (1) Transmission delay problem: LDMOS has large parasitic capacitance, which will cause significant transmission delay whether it is controlling the gate or source of LDMOS, thereby affecting the operating frequency of the chip and making it difficult to meet the needs of high-frequency and high-speed applications; (2) Insufficient isolation: The structure composed of LDMOS and resistors can only achieve functional isolation. There is a path from the high-voltage power supply to the ground, which cannot effectively isolate the grounding of the low-voltage domain and the high-voltage domain, which may cause signal interference and make the system unstable.
[0004] To address these issues, high-voltage capacitors can be used instead of LDMOS devices. While the use of high-voltage capacitors improves the performance of level-shift circuits to a certain extent, it also brings new challenges. For example, high noise levels pose a pressing technical challenge: how to further improve the level-shift circuit's noise immunity and ensure circuit reliability with sub-nanosecond transmission delays. Summary of the Invention
[0005] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a high-noise-resistant capacitor-isolated level shifter circuit with sub-nanosecond transmission delay that can solve the problems of large transmission delay, poor isolation and insufficient noise resistance of the level shifter circuit.
[0006] To solve the above technical problems, the present invention adopts a technical solution: providing a high-noise-resistant capacitor-isolated level shift circuit with sub-nanosecond transmission delay, comprising:
[0007] a capacitive isolation unit, configured to receive a low-voltage narrow pulse control signal and transmit the low-voltage narrow pulse control signal to nodes P1 and P2, output a narrow pulse signal, and cut off a DC path between the high-voltage domain and the low-voltage domain;
[0008] The shift master unit is used to obtain a narrow pulse signal from the node P1 and the node P2 through the anti-common mode interference unit, and convert the narrow pulse signal into a stable logic level for output, thereby completing the level shift from the low voltage domain to the high voltage domain;
[0009] an anti-common mode interference unit, configured to suppress common mode noise caused by floating of the high-side floating voltage source VS when the high-side floating voltage source VS is transiently pulled high; and
[0010] The differential mode compensation unit is used to compensate the current of node P1 and node P2 through the current mirror and the transmission gate when the high-side floating voltage source VS is transiently pulled high, adjust the potential difference between node P1 and node P2, and suppress differential mode noise.
[0011] Furthermore, the capacitor isolation unit is further configured to maintain the voltage difference between the node P1 and the high-side floating voltage source VS and the voltage difference between the node P2 and the high-side floating voltage source VS within the withstand voltage range of the low-voltage device when the high-side floating voltage source VS drops rapidly;
[0012] The high noise immunity capacitor isolation type level shift circuit with sub-nanosecond transmission delay also includes:
[0013] The ground rail moving unit is used to ensure that the voltage difference between the high-side floating voltage source VS and the high-side floating ground GS2 is stable within a set range to ensure the normal operation of low-voltage devices.
[0014] Furthermore, the capacitor isolation unit includes a first high-voltage capacitor C1, a second high-voltage capacitor C2, a first resistor R1, a second resistor R2, a first Zener diode D1 and a second Zener diode D2; the upper plate of the first high-voltage capacitor C1 is electrically connected to the node P1, and the lower plate of the first high-voltage capacitor C1 is electrically connected to the node N1 to access the low-voltage narrow pulse control signal; the upper plate of the second high-voltage capacitor C2 is electrically connected to the node P2, and the lower plate of the second high-voltage capacitor C2 is electrically connected to the node N2 to access the low-voltage narrow pulse control signal; the first Zener diode D1 is electrically connected to the node P1, and the lower plate of the first high-voltage capacitor C1 is electrically connected to the node N1 to access the low-voltage narrow pulse control signal; the first Zener diode D1 is electrically connected to the node P1, and the lower plate of the second high-voltage capacitor C2 is electrically connected to the node N2 to access the low-voltage narrow pulse control signal. The anode of the first Zener diode D1 is electrically connected to the node P1, and the cathode of the first Zener diode D1 is electrically connected to the high-side floating voltage source VS; the anode of the second Zener diode D2 is electrically connected to the node P2, and the cathode of the second Zener diode D2 is electrically connected to the high-side floating voltage source VS; one end of the first resistor R1 is electrically connected to the high-side floating voltage source VS, and the other end of the first resistor R1 is electrically connected to the node P1; one end of the second resistor R2 is electrically connected to the high-side floating voltage source VS, and the other end of the second resistor R2 is electrically connected to the node P2.
[0015] Furthermore, the anti-common-mode interference unit includes a first NMOS transistor NM1 and a second NMOS transistor NM2; the source of the first NMOS transistor NM1 is electrically connected to the node P1, the gate of the first NMOS transistor NM1 is electrically connected to the node P2, the drain of the first NMOS transistor NM1 is electrically connected to the node F1, the source of the second NMOS transistor NM2 is electrically connected to the node P2, the gate of the second NMOS transistor NM2 is electrically connected to the node P1, and the drain of the second NMOS transistor NM2 is electrically connected to the node F2.
[0016] Furthermore, the shift main unit includes:
[0017] A conversion subunit, configured to obtain narrow pulse signals from nodes P1 and P2 via the anti-common mode interference unit, and convert the input signals into voltage signals recognized by the latch subunit for output, thereby completing level shifting from the low voltage domain to the high voltage domain; and
[0018] The latch subunit is used to receive the voltage signal output by the conversion subunit and convert the voltage signal into a logic level output that is stable relative to the high-side floating voltage source VS, thereby realizing recovery from a narrow pulse to a clock signal.
[0019] Furthermore, the conversion subunit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; the source of the first PMOS transistor PM1 is electrically connected to the high-side floating voltage source VS, and the gate and drain of the first PMOS transistor PM1 are both electrically connected to the node F1; the source of the second PMOS transistor PM2 is electrically connected to the high-side floating voltage source VS. The voltage source VS is electrically connected, the gate and drain of the second PMOS transistor PM2 are both electrically connected to the node F2; the source of the third PMOS transistor PM3 is electrically connected to the high-side floating voltage source VS, the gate of the third PMOS transistor PM3 is electrically connected to the node F1, and the drain of the third PMOS transistor PM3 is electrically connected to the node H1; the source of the fourth PMOS transistor PM4 is electrically connected to the high-side floating voltage source VS, the gate of the fourth PMOS transistor PM4 is electrically connected to the node F2, and the drain of the fourth PMOS transistor PM4 is electrically connected to the node H2; the source of the fifth PMOS transistor PM5 is electrically connected to the high-side floating voltage source VS, and the fifth PMOS transistor PM 5 is electrically connected to the node F1, and the drain of the fifth PMOS transistor PM5 is electrically connected to the node K2; the source of the sixth PMOS transistor PM6 is electrically connected to the high-side floating voltage source VS, the gate of the sixth PMOS transistor PM6 is electrically connected to the node F2, and the drain of the sixth PMOS transistor PM6 is electrically connected to the node K1; the source of the third NMOS transistor NM3 is connected to the high-side floating ground GS2, and the gate and drain of the third NMOS transistor NM3 are both electrically connected to the node H1; the source of the fourth NMOS transistor NM4 is connected to the high-side floating ground GS2, and the gate and drain of the fourth NMOS transistor NM4 are both electrically connected to the node H2; the fifth NMOS transistor NM a source of the fifth NMOS transistor NM5 connected to the high-side floating ground GS2, a gate of the fifth NMOS transistor NM5 electrically connected to the node H1, and a drain of the fifth NMOS transistor NM5 electrically connected to the node K1; a source of the sixth NMOS transistor NM6 connected to the high-side floating ground GS2, a gate of the sixth NMOS transistor NM6 electrically connected to the node H2, and a drain of the sixth NMOS transistor NM6 electrically connected to the node K2; one end of the third resistor R3 electrically connected to the high-side floating voltage source VS, and the other end of the third resistor R3 electrically connected to the node F1; one end of the fourth resistor R4 electrically connected to the high-side floating voltage source VS, and the other end of the fourth resistor R4 electrically connected to the node F2;One end of the fifth resistor R5 is electrically connected to the node H1, and the other end of the fifth resistor R5 is connected to the high-side floating ground GS2. One end of the sixth resistor R6 is electrically connected to the node H2, and the other end of the sixth resistor R6 is connected to the high-side floating ground GS2.
[0020] Further, the latch subunit includes a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV4; the input end of the first inverter INV1 is electrically connected to the node K2, the output end of the first inverter INV1 is electrically connected to the node K1, the input end of the second inverter INV2 is electrically connected to the node K1, the output end of the second inverter INV2 is electrically connected to the node K2, the input end of the third inverter INV3 is electrically connected to the node K1, the output end of the third inverter INV3 is electrically connected to the output node Q, the input end of the fourth inverter INV4 is electrically connected to the node K2, and the output end of the fourth inverter INV4 is electrically connected to the output node QN.
[0021] Furthermore, the differential mode compensation unit includes a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, and a fifth Zener diode D5; the source of the seventh PMOS transistor PM7 is electrically connected to the high-side floating voltage source VS to access the high-side floating voltage source voltage, the gate of the seventh PMOS transistor PM7 is electrically connected to the node J, and the drain of the seventh PMOS transistor PM7 is electrically connected to the node P1; the source of the eighth PMOS transistor PM8 is electrically connected to the high-side floating voltage source VS to access the high-side floating voltage source voltage, the gate of the eighth PMOS transistor PM8 is electrically connected to the node J, and the drain of the eighth PMOS transistor PM8 is electrically connected to the node P2; the source of the ninth PMOS transistor PM9 is electrically connected to the node J, and the gate of the ninth PMOS transistor PM9 is electrically connected to the node P3. The gate of the ninth PMOS transistor PM9 is electrically connected to the output node QN, and the drain of the ninth PMOS transistor PM9 is electrically connected to the node P1; the source of the seventh NMOS transistor NM7 is electrically connected to the node P1, the gate of the seventh NMOS transistor NM7 is electrically connected to the output node Q, and the drain of the seventh NMOS transistor NM7 is electrically connected to the node J; the source of the tenth PMOS transistor PM10 is electrically connected to the node J, the gate of the tenth PMOS transistor PM10 is electrically connected to the output node Q, and the drain of the tenth PMOS transistor PM10 is electrically connected to the node P2; the source of the eighth NMOS transistor NM8 is electrically connected to the node P2, the gate of the eighth NMOS transistor NM8 is electrically connected to the output node QN, and the drain of the eighth NMOS transistor NM8 is electrically connected to the node J; the anode of the fifth Zener diode D5 is electrically connected to the node J, and the cathode of the fifth Zener diode D5 is electrically connected to the high-side floating voltage source VS.
[0022] Furthermore, the differential mode compensation unit also includes an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12, the source of the eleventh PMOS transistor PM11 is electrically connected to the high-side floating voltage source VS, the gate of the eleventh PMOS transistor PM11 is electrically connected to the node J, and the drain of the eleventh PMOS transistor PM11 is electrically connected to the node F1; the source of the twelfth PMOS transistor PM12 is electrically connected to the high-side floating voltage source VS, the gate of the twelfth PMOS transistor PM12 is electrically connected to the node J, and the drain of the twelfth PMOS transistor PM12 is electrically connected to the node F2.
[0023] Furthermore, the ground rail moving unit includes a first medium voltage PMOS transistor HPM1, a seventh resistor R7, a third Zener diode D3, a fourth Zener diode D4, a third capacitor C3 and a fourth capacitor C4; the source of the first medium voltage PMOS transistor HPM1 is connected to the high side floating ground GS2, the gate of the first medium voltage PMOS transistor HPM1 is connected to the node GS1, and the drain of the first medium voltage PMOS transistor HPM1 is connected to the floating ground SW; the anode of the third Zener diode D3 is connected to the high side floating ground GS2, and the cathode of the third Zener diode D3 is connected to the high side floating ground GS2. The anode of the fourth Zener diode D4 is connected to the high-side floating voltage source VS; the anode of the fourth Zener diode D4 is connected to the node GS1, and the cathode of the fourth Zener diode D4 is connected to the high-side floating voltage source VS; the upper plate of the third capacitor C3 is connected to the high-side floating voltage source VS, and the lower plate of the third capacitor C3 is connected to the high-side floating ground GS2; the upper plate of the fourth capacitor C4 is connected to the high-side floating voltage source VS, and the lower plate of the fourth capacitor C4 is connected to the node GS1; one end of the seventh resistor R7 is connected to the node GS1, and the other end of the seventh resistor R7 is connected to the floating ground SW.
[0024] The high-noise-resistant capacitor-isolated level shift circuit with sub-nanosecond transmission delay of the present invention has at least the following beneficial effects: the present invention significantly reduces the influence of parasitic capacitance on signal transmission by replacing traditional LDMOS devices with high-voltage capacitors, achieves sub-nanosecond transmission delay, and meets the requirements of high-frequency and high-speed applications; at the same time, the capacitor isolation unit effectively cuts off the DC path between the high-voltage domain and the low-voltage domain, and has excellent isolation performance; the anti-common-mode interference unit automatically disconnects the noise transmission path during high-voltage transients by dynamically controlling the conduction and cutoff of the NMOS tube, thereby suppressing the interference of common-mode noise on the subsequent circuit; the differential-mode compensation unit automatically cuts off ... The mirror and transmission gate dynamically compensate the current to nodes P1 and P2, which can adjust the potential difference caused by noise and avoid bit errors and logic errors. The ground rail moving unit can limit the voltage difference between the high-side floating voltage source VS and the high-side floating ground GS2, ensuring the voltage safety of the low-voltage devices. At the same time, it realizes the isolation of the floating ground SW and the high-side floating ground GS2, reducing power consumption. The diodes and body diodes in the capacitor isolation unit and the differential mode compensation unit ensure that when the high-side floating voltage source VS drops rapidly, the voltage difference between nodes P1, node P2 and the high-side floating voltage source VS is always lower than the voltage resistance value of the low-voltage devices, thereby protecting the low-voltage devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0026] Figure 1 This is the circuit diagram of a traditional level shifter.
[0027] Figure 2 This is a circuit diagram of a high-noise-resistant capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to the present invention.
[0028] Figure 3 This is a simulation diagram of the voltage waveforms of key nodes of the high-noise-resistant capacitor-isolated level shift circuit with sub-nanosecond transmission delay of the present invention.
[0029] Figure 4 This is a simulation diagram of the anti-interference performance of the high-noise-resistant capacitor-isolated level shift circuit with sub-nanosecond transmission delay under high-voltage transient noise.
[0030] Figure 5 This is a simulation diagram of the signal transmission delay test of the high-noise-resistant capacitor isolation level shift circuit with sub-nanosecond transmission delay of the present invention. DETAILED DESCRIPTION
[0031] The present invention will be further described below with reference to the accompanying drawings.
[0032] See also Figure 2The high-noise-resistant capacitor isolation level shift circuit with sub-nanosecond transmission delay of the present invention includes a capacitor isolation unit 100, a shift main unit 200, an anti-common-mode interference unit 300, and a differential-mode compensation unit 400. The capacitor isolation unit 100 is used to access a low-voltage narrow pulse control signal and transmit the low-voltage narrow pulse control signal to nodes P1 and P2, output a narrow pulse signal, and cut off the DC path between the high-voltage domain and the low-voltage domain. The shift main unit 200 is used to access a narrow pulse signal from nodes P1 and P2 through the anti-common-mode interference unit 300, and convert the narrow pulse signal into a stable logic level for output, thereby completing the level shift from the low-voltage domain to the high-voltage domain. The anti-common-mode interference unit 300 is used to suppress the common-mode noise caused by the floating of the high-side floating voltage source VS when the high-side floating voltage source VS is transiently pulled high. The differential-mode compensation unit 400 is used to compensate the currents at nodes P1 and P2 via a current mirror and transmission gate when the high-side floating voltage source VS is transiently pulled high, adjusting the potential difference between nodes P1 and P2 and suppressing differential-mode noise. The capacitive isolation unit 100 is also used to maintain the voltage differences between nodes P1 and VS, and between nodes P2 and VS, within the withstand voltage range of the low-voltage device when the high-side floating voltage source VS drops rapidly.
[0033] The capacitor isolation unit 100 includes a first high-voltage capacitor C1, a second high-voltage capacitor C2, a first resistor R1, a second resistor R2, a first Zener diode D1, and a second Zener diode D2. The upper plate of the first high-voltage capacitor C1 is electrically connected to node P1, and the lower plate of the first high-voltage capacitor C1 is electrically connected to node N1 to receive a low-voltage narrow pulse control signal. The upper plate of the second high-voltage capacitor C2 is electrically connected to node P2, and the lower plate of the second high-voltage capacitor C2 is electrically connected to node N2 to receive a low-voltage narrow pulse control signal. The anode of the first Zener diode D1 is electrically connected to node P1, and the cathode of the first Zener diode D1 is electrically connected to a high-side floating voltage source VS. The anode of the second Zener diode D2 is electrically connected to node P2, and the cathode of the second Zener diode D2 is electrically connected to the high-side floating voltage source VS. The first Zener diode D1 and the second Zener diode D2 are used to maintain the voltage difference between node P1 and the high-side floating voltage source VS, and between node P2 and the high-side floating voltage source VS, within the withstand voltage range of the low-voltage device when the high-side floating voltage source VS drops rapidly. One end of the first resistor R1 is electrically connected to the high-side floating voltage source VS, and the other end of the first resistor R1 is electrically connected to node P1. One end of the second resistor R2 is electrically connected to the high-side floating voltage source VS, and the other end of the second resistor R2 is electrically connected to node P2. In this embodiment, the low-voltage narrow pulse control signal is a low-level narrow pulse generated by a narrow pulse generation unit. The narrow pulse generation unit converts the clock signal into a narrow pulse signal. The low-level narrow pulse transmitted to node N1 is interleaved with the low-level narrow pulse transmitted to node 2. Therefore, node N1 is electrically connected to the first signal output terminal of the narrow pulse generation unit, and node N2 is electrically connected to the second signal output terminal of the narrow pulse generation unit. The resistance value of the first resistor R1 can be selected so that when a low-level narrow pulse is applied to the node N1, the potential drop at the node P1 is the same as the voltage amplitude of the low-level narrow pulse. Similarly, the resistance value of the second resistor R2 can be selected so that when a low-level narrow pulse is applied to the node N2, the potential drop at the node P2 is the same as the voltage amplitude of the low-level narrow pulse.
[0034] The common-mode interference prevention unit 300 includes a first NMOS transistor NM1 and a second NMOS transistor NM2. The source of the first NMOS transistor NM1 is electrically connected to node P1, the gate of the first NMOS transistor NM1 is electrically connected to node P2, and the drain of the first NMOS transistor NM1 is electrically connected to node F1. The source of the second NMOS transistor NM2 is electrically connected to node P2, the gate of the second NMOS transistor NM2 is electrically connected to node P1, and the drain of the second NMOS transistor NM2 is electrically connected to node F2. When a low-level narrow pulse is applied to node N1, the potential of node P1 is lower than the potential of node P2, and the voltage difference between node P2 and node P1 is greater than the threshold voltage of the first NMOS transistor NM1. At this time, the first NMOS transistor NM1 is turned on, and the second NMOS transistor NM2 is turned off. Similarly, when a narrow low-level pulse is applied to node N2, the potential of node P2 is lower than that of node P1. The voltage difference between nodes P1 and P2 is greater than the threshold voltage of the second NMOS transistor NM2, turning on the second NMOS transistor NM2 and turning off the first NMOS transistor NM1. When the high-side floating power supply is transiently pulled high, the first and second high-voltage capacitors C1 and C2 suppress the sudden change between nodes P1 and P2. Nodes P1 and P2 are clamped by the first and second high-voltage capacitors C1 and C2, and the voltage difference between nodes P1 and P2 is less than the threshold voltage of the first and second NMOS transistors NM1 and NM2, turning off both transistors NM1 and NM2. This prevents noise signals from being transmitted to subsequent circuits, effectively isolating common-mode noise, preventing common-mode noise interference, and ensuring the proper operation of subsequent circuits.
[0035] The shift main unit 200 includes a conversion subunit 210 and a latch subunit 220. The conversion subunit 210 is used to receive a narrow pulse signal from node P1 and node P2 through the anti-common mode interference unit 300 and convert the narrow pulse signal into a voltage signal recognized by the latch subunit for output, thereby completing the level shift from the low voltage domain to the high voltage domain. The latch subunit 220 is used to receive the voltage signal output by the conversion subunit 210 and convert the voltage signal into a logic level output that is stable relative to the high-side floating voltage source VS, thereby realizing recovery from a narrow pulse to a clock signal. The narrow pulse signal described in this embodiment is the amplitude of the change in the potential of node P1 and node P2. When this change is transmitted to the latch subunit 220, it will appear as a voltage change at node F1 and node F2.
[0036] The conversion subunit 210 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The source of the first PMOS transistor PM1 is electrically connected to a high-side floating voltage source VS, and both the gate and drain of the first PMOS transistor PM1 are electrically connected to a node F1. The source of the second PMOS transistor PM2 is electrically connected to the high-side floating voltage source VS, and both the gate and drain of the second PMOS transistor PM2 are electrically connected to a node F2. The source of the third PMOS transistor PM3 is electrically connected to the high-side floating voltage source VS, the gate of the third PMOS transistor PM3 is electrically connected to a node F1, and the drain of the third PMOS transistor PM3 is electrically connected to a node H1. The source of the fourth PMOS transistor PM4 is electrically connected to the high-side floating voltage source VS, the gate of the fourth PMOS transistor PM4 is electrically connected to the node F2, and the drain of the fourth PMOS transistor PM4 is electrically connected to the node H2. The source of the fifth PMOS transistor PM5 is electrically connected to the high-side floating voltage source VS, the gate of the fifth PMOS transistor PM5 is electrically connected to the node F1, and the drain of the fifth PMOS transistor PM5 is electrically connected to the node K2. The source of the sixth PMOS transistor PM6 is electrically connected to the high-side floating voltage source VS, the gate of the sixth PMOS transistor PM6 is electrically connected to the node F2, and the drain of the sixth PMOS transistor PM6 is electrically connected to the node K1. The source of the third NMOS transistor NM3 is connected to the high-side floating ground GS2, and both the gate and drain of the third NMOS transistor NM3 are electrically connected to the node H1. The source of the fourth NMOS transistor NM4 is connected to the high-side floating ground GS2, and both the gate and drain of the fourth NMOS transistor NM4 are electrically connected to the node H2. The source of the fifth NMOS transistor NM5 is connected to the high-side floating ground GS2, the gate of the fifth NMOS transistor NM5 is electrically connected to the node H1, and the drain of the fifth NMOS transistor NM5 is electrically connected to the node K1. The source of the sixth NMOS transistor NM6 is connected to the high-side floating ground GS2, the gate of the sixth NMOS transistor NM6 is electrically connected to the node H2, and the drain of the sixth NMOS transistor NM6 is electrically connected to the node K2. One end of the third resistor R3 is electrically connected to the high-side floating voltage source VS, and the other end of the third resistor R3 is electrically connected to the node F1. One end of the fourth resistor R4 is electrically connected to the high-side floating voltage source VS, and the other end of the fourth resistor R4 is electrically connected to the node F2. One end of the fifth resistor R5 is electrically connected to the node H1, and the other end of the fifth resistor R5 is electrically connected to the high-side floating ground GS2.One end of the sixth resistor R6 is electrically connected to the node H2, and the other end of the sixth resistor R6 is connected to the high-side floating ground GS2.
[0037] When a low-level narrow pulse is applied to node N1, the potential of node F1 decreases as the potential of node P1 decreases. At this point, the current mirror structure formed by the first PMOS transistor PM1 and the third PMOS transistor PM3 converts the voltage change at node F1 into a current. The third PMOS transistor PM3 and the fifth PMOS transistor PM5 are turned on, pulling nodes H1 and K2 high. The fifth NMOS transistor NM5 is turned on, pulling node K1 low, and outputting a low-level voltage signal from node K1 to the latch sub-unit 220. Similarly, when a low-level narrow pulse is applied to node N2, node K2 is pulled low, and outputting a low-level voltage signal from node K2 to the latch sub-unit 220.
[0038] The latch subunit 220 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The input of the first inverter INV1 is electrically connected to node K2, and the output of the first inverter INV1 is electrically connected to node K1. The input of the second inverter INV2 is electrically connected to node K1, and the output of the second inverter INV2 is electrically connected to node K2. The input of the third inverter INV3 is electrically connected to node K1, and the output of the third inverter INV3 is electrically connected to output node Q. The input of the fourth inverter INV4 is electrically connected to node K2, and the output of the fourth inverter INV4 is electrically connected to output node QN. When the latch subunit receives a voltage signal output from node K1, output node Q outputs a high level. When the latch subunit 220 receives a voltage signal output from node K2, output node QN outputs a high level.
[0039] To protect low-voltage components, a preferred embodiment further includes a ground rail transfer unit 500. This unit is used to maintain the voltage differential between the high-side floating voltage source VS and the high-side floating ground GS2 within a set range, thereby ensuring the proper operation of the low-voltage components. The ground rail transfer unit 500 includes a first medium-voltage PMOS transistor HPM1, a seventh resistor R7, a third Zener diode D3, a fourth Zener diode D4, a third capacitor C3, and a fourth capacitor C4. The source of the first medium-voltage PMOS transistor HPM1 is connected to the high-side floating ground GS2, the gate of the first medium-voltage PMOS transistor HPM1 is connected to the node GS1, and the drain of the first medium-voltage PMOS transistor HPM1 is connected to the floating ground SW. The anode of the third Zener diode D3 is connected to the high-side floating ground GS2, and the cathode of the third Zener diode D3 is connected to the high-side floating voltage source VS. The anode of the fourth Zener diode D4 is connected to the node GS1, and the cathode of the fourth Zener diode D4 is connected to the high-side floating voltage source VS. The upper plate of the third capacitor C3 is connected to the high-side floating voltage source VS, and the lower plate of the third capacitor C3 is connected to the high-side floating ground GS2. The upper plate of the fourth capacitor C4 is connected to the high-side floating voltage source VS, and the lower plate of the fourth capacitor C4 is connected to node GS1. One end of the seventh resistor R7 is connected to node GS1, and the other end of the seventh resistor R7 is connected to the floating ground SW. In this embodiment, the high-side and low-side grounds are different. The ground of the low-side narrow pulse generating unit is absolute ground, i.e., 0, while the ground of the signals output by the high-side output nodes Q and QN is the high-side floating ground GS2. Using low-voltage components can reduce transmission delay, achieving an overall transmission delay of sub-nanoseconds. However, to protect the low-voltage components, the voltage difference between the high-side floating voltage source VS and the high-side floating ground GS2 needs to be limited by the third Zener diode D3 and the third capacitor C3. In this embodiment, the voltage difference between the high-side floating voltage source VS and the high-side floating ground GS2 is 5V. Furthermore, the first medium-voltage PMOS transistor HPM1 isolates the high-side floating ground GS2 from the floating ground SW. When the control signal output from node GS1 is low, the first medium-voltage PMOS transistor HPM1 turns on, connecting the floating ground SW to the high-side floating ground GS2. When the control signal output from node GS1 is high, the first medium-voltage PMOS transistor HPM1 turns off, severing the current path between the floating ground SW and the high-side floating ground GS2. This prevents the formation of a continuous current path between the high-side floating ground GS2 and the floating ground SW, reducing power consumption.
[0040] In this embodiment, the floating ground SW serves as the floating ground for the half-bridge circuit, and the high-side floating voltage source VS varies with changes in the floating ground SW. Output node Q controls an externally connected high-side GaN (not shown), while output node QN controls an externally connected low-side GaN (not shown). When output node Q outputs a high level, the high-side GaN conducts, the floating ground SW is 100V, and the high-side floating voltage source VS is transiently pulled high. When output node QN outputs a high level, the low-side GaN conducts, the floating ground SW is 0, and the high-side floating voltage source VS rapidly decreases.
[0041] The differential mode compensation unit 400 includes a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, and a fifth Zener diode D5. The source of the seventh PMOS transistor PM7 is electrically connected to a high-side floating voltage source VS to receive the high-side floating voltage source voltage. The gate of the seventh PMOS transistor PM7 is electrically connected to a node J. The drain of the seventh PMOS transistor PM7 is electrically connected to a node P1. The source of the eighth PMOS transistor PM8 is electrically connected to the high-side floating voltage source VS to receive the high-side floating voltage source voltage. The gate of the eighth PMOS transistor PM8 is electrically connected to a node J. The drain of the eighth PMOS transistor PM8 is electrically connected to a node P2. The source of the ninth PMOS transistor PM9 is electrically connected to a node J. The gate of the ninth PMOS transistor PM9 is electrically connected to an output node QN. The drain of the ninth PMOS transistor PM9 is electrically connected to a node P1. The source of the seventh NMOS transistor NM7 is electrically connected to the node P1, the gate of the seventh NMOS transistor NM7 is electrically connected to the output node Q, and the drain of the seventh NMOS transistor NM7 is electrically connected to the node J. The source of the tenth PMOS transistor PM10 is electrically connected to the node J, the gate of the tenth PMOS transistor PM10 is electrically connected to the output node Q, and the drain of the tenth PMOS transistor PM10 is electrically connected to the node P2. The source of the eighth NMOS transistor NM8 is electrically connected to the node P2, the gate of the eighth NMOS transistor NM8 is electrically connected to the output node QN, and the drain of the eighth NMOS transistor NM8 is electrically connected to the node J. The anode of the fifth Zener diode D5 is electrically connected to the node J, and the cathode of the fifth Zener diode D5 is electrically connected to the high-side floating voltage source VS.
[0042] When the high-side floating voltage source VS is transiently pulled up, the output node Q outputs a high level, turning on the transmission gate formed by the seventh NMOS transistor NM7 and the ninth PMOS transistor PM9, allowing node J to be charged via the seventh PMOS transistor PM7. Since the transmission gate formed by the eighth NMOS transistor NM8 and the tenth PMOS transistor PM10 is not yet turned on, the compensation current received by node P1 is less than the compensation current received by node P2, meaning the potential at node P1 is lower than that at node P2. This ensures that the second NMOS transistor NM2 is non-conductive within a certain range (this range is determined by the current shunting magnitude at node J), providing immunity to differential-mode noise interference and preventing transient noise at node P2 from being transmitted to subsequent stages, potentially causing logic errors and bit errors. Similarly, when the high-side floating voltage source VS rapidly decreases, the output node QN outputs a high level, turning on the transmission gate formed by the eighth NMOS transistor NM8 and the tenth PMOS transistor PM10, allowing node J to be charged via the eighth PMOS transistor PM8. Because the transmission gate formed by the seventh NMOS transistor NM7 and the ninth PMOS transistor PM9 is not yet conductive, the compensation current obtained at node P2 is less than the compensation current obtained at node P1. That is, the potential at node P2 is lower than that at node P1. This ensures that the first NMOS transistor NM1 is non-conductive within a certain range (this range is determined by the shunting magnitude at node J), thereby achieving immunity to differential-mode noise interference and preventing the noise at node P1 from being transmitted to subsequent stages, which could cause logic errors and bit errors.
[0043] To ensure that nodes F1 and F2 maintain stable potentials, as a preferred embodiment, the differential mode compensation unit 400 further includes an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12. The source of the eleventh PMOS transistor PM11 is electrically connected to the high-side floating voltage source VS, the gate of the eleventh PMOS transistor PM11 is electrically connected to the node J, and the drain of the eleventh PMOS transistor PM11 is electrically connected to the node F1. The source of the twelfth PMOS transistor PM12 is electrically connected to the high-side floating voltage source VS, the gate of the twelfth PMOS transistor PM12 is electrically connected to the node J, and the drain of the twelfth PMOS transistor PM12 is electrically connected to the node F2. The pull-up capability provided by the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 further ensures that the high levels of nodes F1 and F2 are not affected.
[0044] The following describes the operation of the high-noise-immune capacitor-isolated level shifter circuit with sub-nanosecond transmission delay using a half-bridge driver chip connected to an external load in continuous conduction mode (CCM) as an example. The circuit includes the following four stages:
[0045] ① In the first phase, a narrow low-level pulse appears at node N1. Due to the design of the resistance value of first resistor R1 and the principle of constant voltage across a capacitor during transient conditions, the potential at node P1 decreases by the same magnitude as the low-level narrow pulse, δ. Simultaneously, first NMOS transistor NM1 turns on, opening the VS-F1-NM1-P1 pathway, causing the potential at node F1 to drop by δ. Third and fifth PMOS transistors PM3 and PM5 turn on, pulling nodes H1 and K2 high. Fifth NMOS transistor NM5 turns on, pulling node K1 low. Latch subunit 220 flips, setting output node Q high.
[0046] ② In the second phase, the output node Q outputs a high level, turning on the external high-side GaN transistor. This causes the floating ground SW to reach a high voltage (e.g., 100V), transiently pulling up the high-side floating voltage source VS. The first and second high-voltage capacitors C1 and C2 suppress the potential jumps at nodes P1 and P2. At this point, the voltage difference between nodes P1 and P2 does not exceed the threshold voltages of the first and second NMOS transistors NM1 and NM2. These two transistors do not conduct, preventing noise signals from being transmitted to subsequent circuits and effectively protecting against common-mode noise. Simultaneously, the output node Q outputs a high level, turning on the transmission gate formed by the seventh NMOS transistor NM7 and the ninth NMOS transistor PM9, and charging node J through the seventh PMOS transistor PM7. Since the transmission gate formed by the eighth NMOS transistor NM8 and the fourth PMOS transistor PM10 is not yet turned on, the compensation current at node P1 is less than the compensation current at node P2. This means that the potential at node P1 is lower than that at node P2. The second NMOS transistor NM2 is kept non-conductive within a certain range (this range is determined by the current shunting at node J), providing immunity to differential-mode noise and preventing transient noise at node P2 from being transmitted to subsequent stages and causing logic errors. The pull-up capability provided by PM11 and PM12 further ensures that the high levels at nodes F1 and F2 are not affected.
[0047] ③ In the third phase, a narrow low-level pulse appears at node N2. Due to the design of the resistance value of second resistor R2 and the principle of constant voltage across a capacitor during transient conditions, the potential drop at node P2 is guaranteed to be the same as the amplitude of the narrow low-level pulse, δ. Simultaneously, second NMOS transistor NM2 turns on, opening the VS-F2-NM2-N2 pathway, causing the potential at node F2 to drop by δ. The specific principles are the same as in the first phase, and output node QN of latch subunit 220 is set to a high level.
[0048] ④ In the fourth phase, the output node QN outputs a high level, turning on the external low-side GaN transistor, causing the floating ground SW to reach a low voltage (e.g., 0V), rapidly reducing the high-side floating voltage source VS. Because the top plates of the first and second high-voltage capacitors C1 and C2 exceeded 100V in the third phase, discharge occurs through the forward-biased first and second Zener diodes D1 and D2, and through the body diodes of the seventh and eighth PMOS transistors PM7 and PM8. This ensures that the voltage difference between nodes P1 and P2 and the high-side floating voltage source VS remains within the withstand voltage range of the low-voltage devices. In this embodiment, the maximum withstand voltage is 0.7V (i.e., P1-VS = P2-VS = 0.7V), preventing breakdown of the low-voltage devices in the discharge branch. In this phase, F1 = F2 = "1," PM1-PM6 are all off, and the latch subunit 220 formed by INV1-INV4 maintains the output of the third phase.
[0049] See also Figure 3 , is a voltage waveform simulation diagram of the key nodes of the high noise-resistant capacitor isolation level shift circuit with sub-nanosecond transmission delay of the present invention. When VS changes, the voltage difference of each node is normal and the output signal does not have error code. Figure 4 , which is a simulation diagram of the anti-interference performance of the high-noise-resistant capacitor-isolated level shift circuit with sub-nanosecond transmission delay under high-voltage transient noise (200V / ns) of the present invention, Figure 4 for Figure 3 The waveforms of nodes H1 and Q with the high-side floating ground GS2 as the ground verify the ability to resist common-mode and differential-mode noise interference and output stability. Figure 5 The transmission delay of the signal from node N1 to output node Q was measured, and the specific delay was 622ps, verifying the sub-nanosecond transmission delay performance of the high-noise-resistant capacitor isolation level shifter circuit of the present invention, which meets the high operating frequency requirements.
[0050] The present invention significantly reduces the impact of parasitic capacitance on signal transmission by replacing traditional LDMOS devices with high-voltage capacitors, achieving sub-nanosecond transmission delay and meeting the requirements of high-frequency and high-speed applications. At the same time, the capacitor isolation unit 100 effectively cuts off the DC path between the high-voltage domain and the low-voltage domain, with excellent isolation performance. The anti-common-mode interference unit 300 automatically disconnects the noise transmission path during high-voltage transients by dynamically controlling the conduction and cutoff of the NMOS tube, thereby suppressing the interference of common-mode noise on the subsequent circuit. The differential-mode compensation unit 400 compensates the currents of nodes P1 and P2 through current mirrors and transmission gates, thereby adjusting the potential difference caused by noise and avoiding bit errors and logical errors. The ground rail moving unit 500 can limit the voltage difference between the high-side floating voltage source VS and the high-side floating ground GS2. The voltage resistance of the low-voltage device is ensured, and the floating ground SW is isolated from the high-side floating ground GS2, thereby reducing power consumption. The eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 ensure that the high levels of the nodes F1 and F2 are not affected by noise, thereby avoiding logical misjudgment caused by level drops. Combined with the bistable design of the latch sub-unit 220, the signals output by the output nodes Q and QN have strong anti-interference properties and stable waveforms. The body diodes of the first Zener diode D1, the second Zener diode D2, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 ensure that when the high-side floating voltage source VS drops rapidly, the voltage difference between the nodes P1, the node P2 and the high-side floating voltage source VS is always lower than the voltage resistance value of the low-voltage device, thereby protecting the low-voltage device.
[0051] The above description merely expresses the preferred embodiments of the present invention, and its description is relatively specific and detailed, but it should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art may make a number of variations and improvements without departing from the concept of the present invention, and these variations and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent of the present invention shall be based on the appended claims.
Claims
1. A high-noise-resistance capacitor-isolated level shift circuit with sub-nanosecond transmission delay, characterized in that: include: a capacitive isolation unit, configured to receive a low-voltage narrow pulse control signal and transmit the low-voltage narrow pulse control signal to nodes P1 and P2, output a narrow pulse signal, and cut off a DC path between the high-voltage domain and the low-voltage domain; The shift master unit is used to obtain narrow pulse signals from nodes P1 and P2 through the anti-common mode interference unit, and convert the narrow pulse signals into stable logic levels for output, thereby completing level shifting from the low-voltage domain to the high-voltage domain; An anti-common mode interference unit is used to suppress the common mode noise caused by the floating of the high-side floating voltage source VS when the high-side floating voltage source VS is transiently pulled high; as well as The differential mode compensation unit is used to compensate the current of node P1 and node P2 through the current mirror and the transmission gate when the high-side floating voltage source VS is transiently pulled high, adjust the potential difference between node P1 and node P2, and suppress differential mode noise.
2. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 1, characterized in that: The capacitor isolation unit is further configured to maintain the voltage difference between the node P1 and the high-side floating voltage source VS and the voltage difference between the node P2 and the high-side floating voltage source VS within the withstand voltage range of the low-voltage device when the high-side floating voltage source VS drops rapidly; The high noise immunity capacitor isolation type level shift circuit with sub-nanosecond transmission delay also includes: The ground rail moving unit is used to ensure that the voltage difference between the high-side floating voltage source VS and the high-side floating ground GS2 is stable within a set range.
3. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 1, characterized in that: The capacitor isolation unit includes a first high-voltage capacitor C1, a second high-voltage capacitor C2, a first resistor R1, a second resistor R2, a first Zener diode D1 and a second Zener diode D2; the upper plate of the first high-voltage capacitor C1 is electrically connected to the node P1, and the lower plate of the first high-voltage capacitor C1 is electrically connected to the node N1 to access the low-voltage narrow pulse control signal; the upper plate of the second high-voltage capacitor C2 is electrically connected to the node P2, and the lower plate of the second high-voltage capacitor C2 is electrically connected to the node N2 to access the low-voltage narrow pulse control signal; the first Zener diode An anode of the first Zener diode D1 is electrically connected to a node P1, and a cathode of the first Zener diode D1 is electrically connected to a high-side floating voltage source VS; an anode of the second Zener diode D2 is electrically connected to a node P2, and a cathode of the second Zener diode D2 is electrically connected to the high-side floating voltage source VS; one end of the first resistor R1 is electrically connected to the high-side floating voltage source VS, and the other end of the first resistor R1 is electrically connected to the node P1; one end of the second resistor R2 is electrically connected to the high-side floating voltage source VS, and the other end of the second resistor R2 is electrically connected to the node P2.
4. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 1, characterized in that: The anti-common-mode interference unit includes a first NMOS transistor NM1 and a second NMOS transistor NM2; the source of the first NMOS transistor NM1 is electrically connected to the node P1, the gate of the first NMOS transistor NM1 is electrically connected to the node P2, the drain of the first NMOS transistor NM1 is electrically connected to the node F1, the source of the second NMOS transistor NM2 is electrically connected to the node P2, the gate of the second NMOS transistor NM2 is electrically connected to the node P1, and the drain of the second NMOS transistor NM2 is electrically connected to the node F2.
5. The high noise immunity capacitor isolation type level shift circuit with sub-nanosecond transmission delay according to claim 4, characterized in that: The shift master unit comprises: A conversion subunit, configured to obtain narrow pulse signals from nodes P1 and P2 via the anti-common mode interference unit, and convert the input signals into voltage signals recognized by the latch subunit for output, thereby completing level shifting from the low voltage domain to the high voltage domain; and The latch subunit is used to receive the voltage signal output by the conversion subunit and convert the voltage signal into a logic level output that is stable relative to the high-side floating voltage source VS, thereby realizing recovery from a narrow pulse to a clock signal.
6. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 5, characterized in that: The conversion subunit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; the source of the first PMOS transistor PM1 is electrically connected to the high-side floating voltage source VS, and the gate and drain of the first PMOS transistor PM1 are both electrically connected to the node F1; the source of the second PMOS transistor PM2 is electrically connected to the high-side floating voltage source V S is electrically connected, the gate and drain of the second PMOS transistor PM2 are both electrically connected to the node F2; the source of the third PMOS transistor PM3 is electrically connected to the high-side floating voltage source VS, the gate of the third PMOS transistor PM3 is electrically connected to the node F1, and the drain of the third PMOS transistor PM3 is electrically connected to the node H1; the source of the fourth PMOS transistor PM4 is electrically connected to the high-side floating voltage source VS, the gate of the fourth PMOS transistor PM4 is electrically connected to the node F2, and the drain of the fourth PMOS transistor PM4 is electrically connected to the node H2; the source of the fifth PMOS transistor PM5 is electrically connected to the high-side floating voltage source VS, the gate of the fifth PMOS transistor PM5 is electrically connected to the node H1. The gate of the sixth PMOS transistor PM6 is electrically connected to the high-side floating voltage source VS, the gate of the sixth PMOS transistor PM6 is electrically connected to the node F2, and the drain of the sixth PMOS transistor PM6 is electrically connected to the node K1; the source of the third NMOS transistor NM3 is connected to the high-side floating ground GS2, and the gate and drain of the third NMOS transistor NM3 are both electrically connected to the node H1; the source of the fourth NMOS transistor NM4 is connected to the high-side floating ground GS2, and the gate and drain of the fourth NMOS transistor NM4 are both electrically connected to the node H2; the fifth NMOS transistor NM5 is electrically connected to the high-side floating ground GS2. The source of the fifth NMOS transistor NM5 is connected to the high-side floating ground GS2, the gate of the fifth NMOS transistor NM5 is electrically connected to the node H1, and the drain of the fifth NMOS transistor NM5 is electrically connected to the node K1; the source of the sixth NMOS transistor NM6 is connected to the high-side floating ground GS2, the gate of the sixth NMOS transistor NM6 is electrically connected to the node H2, and the drain of the sixth NMOS transistor NM6 is electrically connected to the node K2; one end of the third resistor R3 is electrically connected to the high-side floating voltage source VS, and the other end of the third resistor R3 is electrically connected to the node F1; one end of the fourth resistor R4 is electrically connected to the high-side floating voltage source VS, and the other end of the fourth resistor R4 is electrically connected to the node F2;One end of the fifth resistor R5 is electrically connected to the node H1, and the other end of the fifth resistor R5 is connected to the high-side floating ground GS2. One end of the sixth resistor R6 is electrically connected to the node H2, and the other end of the sixth resistor R6 is connected to the high-side floating ground GS2.
7. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 6, characterized in that: The latch subunit includes a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV4; the input end of the first inverter INV1 is electrically connected to the node K2, the output end of the first inverter INV1 is electrically connected to the node K1, the input end of the second inverter INV2 is electrically connected to the node K1, the output end of the second inverter INV2 is electrically connected to the node K2, the input end of the third inverter INV3 is electrically connected to the node K1, the output end of the third inverter INV3 is electrically connected to the output node Q, the input end of the fourth inverter INV4 is electrically connected to the node K2, and the output end of the fourth inverter INV4 is electrically connected to the output node QN.
8. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 7, characterized in that: The differential mode compensation unit includes a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, and a fifth Zener diode D5; the source of the seventh PMOS transistor PM7 is electrically connected to the high-side floating voltage source VS to access the high-side floating voltage source voltage, the gate of the seventh PMOS transistor PM7 is electrically connected to the node J, and the drain of the seventh PMOS transistor PM7 is electrically connected to the node P1; the source of the eighth PMOS transistor PM8 is electrically connected to the high-side floating voltage source VS to access the high-side floating voltage source voltage, the gate of the eighth PMOS transistor PM8 is electrically connected to the node J, and the drain of the eighth PMOS transistor PM8 is electrically connected to the node P2; the source of the ninth PMOS transistor PM9 is electrically connected to the node J, and the gate of the ninth PMOS transistor PM9 is electrically connected to the node P1. The output node QN is electrically connected, the drain of the ninth PMOS transistor PM9 is electrically connected to the node P1; the source of the seventh NMOS transistor NM7 is electrically connected to the node P1, the gate of the seventh NMOS transistor NM7 is electrically connected to the output node Q, and the drain of the seventh NMOS transistor NM7 is electrically connected to the node J; the source of the tenth PMOS transistor PM10 is electrically connected to the node J, the gate of the tenth PMOS transistor PM10 is electrically connected to the output node Q, and the drain of the tenth PMOS transistor PM10 is electrically connected to the node P2; the source of the eighth NMOS transistor NM8 is electrically connected to the node P2, the gate of the eighth NMOS transistor NM8 is electrically connected to the output node QN, and the drain of the eighth NMOS transistor NM8 is electrically connected to the node J; the anode of the fifth Zener diode D5 is electrically connected to the node J, and the cathode of the fifth Zener diode D5 is electrically connected to the high-side floating voltage source VS.
9. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 8, characterized in that: The differential mode compensation unit also includes an eleventh PMOS transistor PM11 and a twelfth PMOS transistor PM12. The source of the eleventh PMOS transistor PM11 is electrically connected to the high-side floating voltage source VS, the gate of the eleventh PMOS transistor PM11 is electrically connected to the node J, and the drain of the eleventh PMOS transistor PM11 is electrically connected to the node F1; the source of the twelfth PMOS transistor PM12 is electrically connected to the high-side floating voltage source VS, the gate of the twelfth PMOS transistor PM12 is electrically connected to the node J, and the drain of the twelfth PMOS transistor PM12 is electrically connected to the node F2.
10. The high noise immunity capacitor-isolated level shift circuit with sub-nanosecond transmission delay according to claim 2, characterized in that: The ground rail moving unit includes a first medium voltage PMOS transistor HPM1, a seventh resistor R7, a third Zener diode D3, a fourth Zener diode D4, a third capacitor C3 and a fourth capacitor C4; the source of the first medium voltage PMOS transistor HPM1 is connected to the high side floating ground GS2, the gate of the first medium voltage PMOS transistor HPM1 is connected to the node GS1, and the drain of the first medium voltage PMOS transistor HPM1 is connected to the floating ground SW; the anode of the third Zener diode D3 is connected to the high side floating ground GS2, and the cathode of the third Zener diode D3 is connected to the high side floating ground GS2. into the high-side floating voltage source VS; the anode of the fourth Zener diode D4 is connected to the node GS1, and the cathode of the fourth Zener diode D4 is connected to the high-side floating voltage source VS; the upper plate of the third capacitor C3 is connected to the high-side floating voltage source VS, and the lower plate of the third capacitor C3 is connected to the high-side floating ground GS2; the upper plate of the fourth capacitor C4 is connected to the high-side floating voltage source VS, and the lower plate of the fourth capacitor C4 is connected to the node GS1; one end of the seventh resistor R7 is connected to the node GS1, and the other end of the seventh resistor R7 is connected to the floating ground SW.