Global dynamic self-biased low-noise phase-locked loop circuit and electronic device

Abstract

The application discloses a kind of global dynamic self-bias low-noise phase-locked loop circuit and electronic equipment, the global dynamic self-bias low-noise phase-locked loop circuit of the present application includes frequency discriminator, charge pump, current-voltage module, comparison operational amplifier, bias current mirror module, voltage conversion current module, current control oscillator, feedback frequency division circuit and low-dropout linear regulator circuit, frequency discriminator, charge pump, current-voltage module, comparison operational amplifier, bias current mirror module, voltage conversion current module, current control oscillator are sequentially connected to generate output clock by current control oscillator.The present application aims to solve the problem of serious phase noise of traditional phase-locked loop circuit in high-speed high-precision application scene, especially the current mismatch of charge pump, so that the phase-locked loop circuit bias has the characteristics of low noise and fast speed.

Description

TECHNICAL FIELD

[0001] The present application relates to a phase-locked loop circuit in an electronic circuit, in particular to a globally dynamic self-biased low-noise phase-locked loop circuit and an electronic device. BACKGROUND

[0002] The phase-locked loop (PLL) circuit is widely used in communication systems, and the circuit structure of the traditional phase-locked loop circuit is as shown in Figure 1 The phase-locked loop (PLL) circuit is widely used in communication systems, and the circuit structure of the traditional phase-locked loop circuit is as shown in SUMMARY

[0003] The technical problem to be solved by the present application: In view of the above problems of the prior art, the present application provides a globally dynamic self-biased low-noise phase-locked loop circuit and an electronic device, and the present application aims to solve the problem of serious phase noise of the traditional phase-locked loop circuit in the high-speed high-precision application scenario, especially the current mismatch of the charge pump, so that the phase-locked loop circuit has the characteristics of low noise and fast speed.

[0004] In order to solve the above technical problems, the technical scheme adopted by the present application is:

[0005] A global dynamic self-biased low noise phase-locked loop circuit, comprising a frequency discriminator phase detector, a charge pump cp, a current to voltage module I2V, a comparison operational amplifier A1, a bias current mirror module bias, a voltage to current module V2I, a current controlled oscillator CCO, a feedback frequency divider circuit and a low dropout linear regulator circuit LDO, the frequency discriminator phase detector, the charge pump cp, the current to voltage module I2V, the comparison operational amplifier A1, the bias current mirror module bias, the voltage to current module V2I and the current controlled oscillator CCO are connected in sequence to generate an output clock Clk_out through the current controlled oscillator CCO, the input of the feedback frequency divider circuit is connected to the output of the current controlled oscillator CCO to generate a feedback clock Fb_clk required by the frequency discriminator phase detector by frequency dividing the output clock Clk_out, the bias voltage Vpsf of the charge pump cp, the current to voltage module I2V, the bias current mirror module bias and the voltage to current module V2I are commonly from the low dropout linear regulator circuit LDO, and the reference voltage Vreg of the low dropout linear regulator circuit LDO is the same as the reference voltage Vreg of the comparison operational amplifier A1 to form a self-biased loop.

[0006] Optionally, the bias current mirror module bias includes pmos transistors Mp1-Mp10 and nmos transistors Mn1-Mn7, the pmos transistor Mp1 and the nmos transistor Mn1 are arranged in series between the bias voltage Vpsf and the ground, the pmos transistor Mp2, the pmos transistor Mp3 and the nmos transistor Mn2 are arranged in series between the bias voltage Vpsf and the ground, the gate of the pmos transistor Mp2 is connected to the frequency selection signal Freq_sel, the gate of the pmos transistor Mp1 is connected to the amplified signal Vbias output by the comparison operational amplifier A1, the gates of the nmos transistors Mn1 and Mn2 are connected to form a current mirror to generate the bias current Vb and output to the current-to-voltage module I2V; the pmos transistor Mp4 and the pmos transistor Mp7 are connected in series and one end is connected to the bias voltage Vpsf and the other end outputs the bias current Icp1 to the charge pump cp, the pmos transistor Mp5 and the pmos transistor Mp5 are connected in series and one end is connected to the bias voltage Vpsf and the other end outputs the bias current Icp2 to the charge pump cp, the pmos transistor Mp6 and the nmos transistor Mn3 are arranged in series between the bias voltage Vpsf and the ground, the pmos transistor Mp9 and the nmos transistor Mn4 are arranged in series between the bias voltage Vpsf and the ground, the gates of the nmos transistors Mn3 and Mn4 are connected to form a current mirror to generate a control signal for controlling the gate of the pmos transistor Mp10, the source of the pmos transistor Mp10 is connected to the bias voltage Vpsf and the drain generates the bias current icas through a plurality of parallel units and outputs to the voltage-to-current module V2I; the parallel units include nmos transistors Mn5, Mn6 and Mn7, the drain of the pmos transistor Mp10 is connected to the ground through one or more groups of nmos transistors Mn5, Mn6 and Mn7 in sequence, and the gate of the nmos transistor Mn7 is connected to the power voltage Vp_cp.

[0007] Optionally, the circuit part for generating the bias voltage Vpsf in the low dropout linear regulator circuit LDO includes an nmos transistor Mn8, pmos transistors Mp11-Mp12, an operational amplifier A4 and a plurality of serially connected nmos transistors, the pmos transistor Mp11 and the nmos transistor Mn8 are arranged in series between the voltage Vph and the ground, the gate of the nmos transistor Mn8 is connected to the output voltage Vreg of the pmos transistor Mp6 in the bias current mirror module bias, the drain of the pmos transistor Mp11 is connected to the gate of the pmos transistor Mp12, the pmos transistor Mp12 and the plurality of serially connected nmos transistors are arranged in series between the voltage Vph and the ground, and the drain of the pmos transistor Mp12 is connected to the input end of the operational amplifier A4 to output the bias voltage Vpsf through the output end of the operational amplifier A4.

[0008] Optionally, the circuit portion of the low-dropout linear regulator (LDO) circuit that generates the power supply voltage Vp_cp includes a capacitor, an operational amplifier A5, and multiple PMOS transistors connected in series. The multiple PMOS transistors and the capacitor are connected in series between the voltage Vph and ground, and the intermediate node between the capacitor and the multiple PMOS transistors is connected to the input terminal of the operational amplifier A5 so that the power supply voltage Vp_cp is output through the output terminal of the operational amplifier A5.

[0009] Optionally, the charge pump cp includes operational amplifiers A2-A3, PMOS transistors Mp13-Mp20, and NMOS transistors Mn9-Mn16. The input signals of the charge pump cp are the up signal UP, the inverted up signal UPb, the down signal DN, and the inverted down signal DN generated by the frequency and phase detector PFD after frequency and phase discrimination; the reference voltage signal Vref generated by the current-to-voltage module I2V; the bias voltage signal Vb generated by the bias current mirror module bias after biasing; and a pair of opposite power-on signals Pon and ponb. The output signals of the charge pump cp include the control voltage signal Vctr. The control voltage signal Vctrl is fed back to the voltage-to-current conversion module V2I to control its pull-down network, which is also the input of the comparator operational amplifier A1; the control voltage signal Vint is fed back to the gate of the NMOS transistor Mn20 in the current-to-voltage conversion module I2V to control the generation of the control voltage signal Vctrl; the pull-up networks for generating the control voltage signals Vctrl and Vint in the charge pump cp are controlled by PMOS transistors Mp13 and Mp17, respectively; the pull-down networks for generating the control voltage signals Vctrl and Vint are controlled by NMOS transistors Mp13 and Mp17, respectively. The NMOS transistors Mn12 and Mn16 control the charge pump's pull-down network. The up signal UP is input to the gates of NMOS transistors Mn10 and Mp19, the inverted up signal UPb is input to the gates of NMOS transistors Mn9 and Mp20, the down signal DN is input to the gates of Mp15 and Mn14, and the inverted down signal DN is input to the gates of NMOS transistors Mn13 and Mp16. The reference voltage signal Vref is input to the gates of NMOS transistors Mn11 and Mn15, controlling the pull-down network of the charge pump CP. The bias voltage signal Vb is input to the PMOS transistor Mn11. The gates of p14 and Mp18 control the pull-up network of the charge pump cp; an operational amplifier A3 is clamped at the control terminal Vctrl_dump between the control voltage signal Vctrl and the drain of the pMOS transistor Mp15 and the NMOS transistor Mn9, and an identical operational amplifier A2 is clamped at the control terminal Vint_dump between the control voltage signal Vint and the drain of the pMOS transistor Mp20 and the NMOS transistor Mn14. There are a total of 24 groups of charge pump cp that generate the control voltage signal Vctrl, and a total of 8 groups of charge pump cp that generate the control voltage signal Vint.

[0010] Optionally, the current-to-voltage module I2V includes PMOS transistors Mp21-Mp26 and NMOS transistors Mn17-Mn25. The input signal is the bias voltage signal Vb generated after biasing by the bias current mirror module bias, a pair of opposite power-on signals Pon and ponb, and a control signal Pon_stop. The output signals are the control voltage signal Vctrl and the reference voltage signal Vref. The reference voltage signal Vref is fed back to the charge pump cp to control the pull-down network of the charge pump cp. The control voltage signal Vctrl is fed back to the voltage-to-current module V2I to control its pull-down network, and is also the input terminal of the comparator operational amplifier A1. The power-on signal Ponb is connected to the gates of PMOS transistors Mp24 and Mp21, the power-on signal Pon is connected to the gates of NMOS transistors Mn17-Mn18, Mn21-Mn22, and Mn23-Mn25, and the control signal Pon_stop is connected to the gates of PMOS transistors Mp23 and Mp26.

[0011] Optionally, the voltage-to-current conversion module V2I includes a pmos transistor Mp27 and nmos transistors Mn26-Mn28. The input signal is the amplified signal Vbias output by the comparator operational amplifier A1, the bias signal icas generated after biasing by the bias current mirror module bias, and the control voltage signal Vctrl jointly adjusted and generated by the current-to-voltage conversion module I2V and the CP module. The output signal is the input signal ivco of the current-controlled oscillator CCO, which controls the oscillation frequency of the current-controlled oscillator CCO. The amplified signal Vbias is connected to the gate of the pmos transistor Mp27 and controls the pull-up network that generates the input signal ivco of the current-controlled oscillator CCO. The bias signal icas and the control voltage signal Vctrl are respectively connected to the gates of nmos transistors Mn26 and Mn27 and jointly control the pull-down network that generates the input signal ivco of the current-controlled oscillator CCO.

[0012] Optionally, the output of the comparator operational amplifier A1 is also grounded through a MOS capacitor X501.

[0013] In addition, the present invention also provides an electronic device, including a device body and a circuit module disposed in the device body, wherein the circuit module includes the global dynamic self-biased low-noise phase-locked loop circuit described above.

[0014] Compared with the prior art, the present invention mainly achieves the following beneficial effects: The present invention includes a frequency and phase detector, a charge pump cp, a current-to-voltage module I2V, a comparator operational amplifier A1, a bias current mirror module bias, a voltage-to-current module V2I, a current-controlled oscillator CCO, a feedback frequency divider circuit, and a low-dropout linear regulator circuit LDO. The frequency and phase detector, charge pump cp, current-to-voltage module I2V, comparator operational amplifier A1, bias current mirror module bias, voltage-to-current module V2I, and current-controlled oscillator CCO are sequentially connected to generate an output clock Clk_out through the current-controlled oscillator CCO, achieving global dynamic self-biasing and low noise. In the acoustic phase-locked loop (PLL) circuit, the bias voltage of all modules is provided by the internal low-dropout linear regulator (LDO) circuit. At the same time, the reference current of the LDO circuit is provided by the comparator operational amplifier A1 in the loop, forming a self-biased loop. The modules self-biased in the self-biased loop include the comparator operational amplifier A1, the current-to-voltage module I2V, the voltage-to-current module V2I, the charge pump cp, the LDO circuit, and the bias current mirror module bias. This can solve the serious phase noise problem of traditional PLL circuits in high-speed and high-precision applications, especially the current mismatch of the charge pump, so that the PLL circuit bias has the characteristics of low noise and high speed. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit structure of a traditional phase-locked loop circuit.

[0016] Figure 2 This is a schematic diagram of the circuit framework structure of the phase-locked loop circuit in an embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram of the phase-locked loop circuit in an embodiment of the present invention.

[0018] Figure 4 The diagram shows the circuit schematics of two parts of the low dropout linear regulator (LDO) circuit in this embodiment of the invention, where (a) is the circuit part used to generate the bias voltage Vpsf, and (b) is the circuit part used to generate the power supply voltage Vp_cp.

[0019] Figure 5 This is a schematic diagram of the feedback loop of the charge pump cp in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] like Figure 2 and Figure 3As shown, the global dynamic self-biased low-noise phase-locked loop circuit in this embodiment includes a frequency and phase detector, a charge pump cp, a current-to-voltage module I2V, a comparator operational amplifier A1, a bias current mirror module bias, a voltage-to-current module V2I, a current-controlled oscillator CCO, a feedback frequency divider circuit, and a low-dropout linear regulator circuit LDO. The frequency and phase detector, charge pump cp, current-to-voltage module I2V, comparator operational amplifier A1, bias current mirror module bias, voltage-to-current module V2I, and current-controlled oscillator CCO are connected in sequence to generate voltage through the current-controlled oscillator CCO. The output clock Clk_out is generated. The input terminal of the feedback frequency divider circuit is connected to the output terminal of the current-controlled oscillator CCO to divide the output clock Clk_out to generate the feedback clock Fb_clk required by the frequency and phase detector. The bias voltage Vpsf of the charge pump cp, the current-to-voltage module I2V, the bias current mirror module bias, and the voltage-to-current module V2I all come from the low dropout linear regulator circuit LDO. The reference voltage Vreg of the low dropout linear regulator circuit LDO is the same as the reference voltage Vreg of the comparator operational amplifier A1 to form a self-biased loop. The circuit consists of a low-dropout linear regulator (LDO) circuit to provide the voltage required by each module; a charge pump (CP) to convert the phase information of the frequency and phase detector into current; a current-to-voltage (I2V) module to convert the current output by the charge pump (CP) into a voltage value; a comparator operational amplifier (CPA) module to output the voltage difference between the control voltage signal (Vtrl) and the reference voltage signal (Vref) of the current-to-voltage (I2V) module to the bias current mirror module (bias); the bias current mirror module (bias) to convert the output voltage value of the CPA into the dynamic bias current required globally; and a voltage-to-current (V2I) module to convert the voltage value generated by the bias current mirror module (bias) into a current value to drive the current-controlled oscillator (CCO), thereby generating the required clock signal through the current-controlled oscillator (CCO).

[0022] After the bias current mirror module bias is biased by the comparator operational amplifier A1, it generates a reference current. This reference current is then mirrored by a transistor to generate the bias current of the unity-gain amplifier in the charge pump CP. This biases the two CP modules CP1 and CP2 in the charge pump CP, respectively. CP1 and CP2 refer to X24 and X8 units that generate the control voltage signals Vctrl and Vint, respectively, where X24 and X8 represent the number of groups in CP modules CP1 and CP2. Figure 3As shown, the bias current mirror module bias in this embodiment includes PMOS transistors Mp1-Mp10 and NMOS transistors Mn1-Mn7. PMOS transistors Mp1 and Mn1 are connected in series between the bias voltage Vpsf and ground. PMOS transistors Mp2, Mp3, and Mn2 are connected in series between the bias voltage Vpsf and ground. The gate of PMOS transistor Mp2 is connected to the frequency selection signal Freq_sel. The gate of PMOS transistor Mp1 is connected to the amplified signal Vbias output by the comparator operational amplifier A1. The gates of NMOS transistors Mn1 and Mn2 are connected to form a current mirror to generate a bias current Vb and output it to the current-to-voltage module I2V. PMOS transistors Mp4 and Mp7 are connected in series, with one end connected to the bias voltage Vpsf and the other end outputting a bias current Icp1 to the charge pump cp. PMOS transistors Mp5, Mp1, Mp10 ... The PMOS transistor Mp5 is connected in series, with one end connected to the bias voltage Vpsf and the other end outputting a bias current Icp2 to the charge pump cp. PMOS transistors Mp6 and Mn3 are connected in series between the bias voltage Vpsf and ground. PMOS transistors Mp9 and Mn4 are connected in series between the bias voltage Vpsf and ground. The gates of Mn3 and Mn4 are connected to form a current mirror to generate a control signal for controlling the gate of PMOS transistor Mp10. The source of PMOS transistor Mp10 is connected to the bias voltage Vpsf, and its drain generates a bias current icas through multiple parallel units and outputs it to the voltage-to-current conversion module V2I. The parallel units include NMOS transistors Mn5, Mn6, and Mn7. The drain of PMOS transistor Mp10 is grounded sequentially through one or more sets of NMOS transistors Mn5, Mn6, and Mn7. The gate of NMOS transistor Mn7 is connected to the power supply voltage Vp_cp.

[0023] In this embodiment, the low-dropout linear regulator (LDO) circuit includes two parts: a circuit for generating the bias voltage Vpsf and a circuit for generating the power supply voltage Vp_cp. These provide the voltage required by each module and control the comparator operational amplifier A1, the current-to-voltage module I2V, the voltage-to-current module V2I, the bias current mirror module bias, and the charge pump cp. Figure 4As shown in (a), the circuit portion of the low-dropout linear regulator (LDO) circuit that generates the bias voltage Vpsf includes an nmos transistor Mn8, pmoos transistors Mp11-Mp12, an operational amplifier A4, and multiple nmos transistors connected in series. Pmoos transistors Mp11 and Mn8 are connected in series between voltage Vph and ground. The gate of nmos transistor Mn8 is connected to the output voltage Vreg of pmoos transistor Mp6 in the bias current mirror module (bias). The drain of pmoos transistor Mp11 is connected to the gate of pmoos transistor Mp12. Pmoos transistor Mp12 and the multiple connected nmos transistors are connected in series between voltage Vph and ground, and the drain of pmoos transistor Mp12 is connected to the input terminal of operational amplifier A4 to output the bias voltage Vpsf through the output terminal of operational amplifier A4. Figure 4 As shown in (b), the circuit part of the low dropout linear regulator (LDO) circuit that generates the power supply voltage Vp_cp includes a capacitor, an operational amplifier A5, and multiple PMOS transistors connected in series. The multiple PMOS transistors and the capacitor are connected in series between the voltage Vph and ground, and the intermediate node between the capacitor and the multiple PMOS transistors is connected to the input terminal of the operational amplifier A5 so that the power supply voltage Vp_cp is output through the output terminal of the operational amplifier A5.

[0024] The charge pump cp includes two matched current source structures, in which the current source structures use two unity-gain operational amplifiers to convert the frequency and phase discrimination information of the up signal UP and the down signal DN into current information and feed it into the current-to-voltage module I2V.

[0025] Two pairs of transistor-matched charge pumps (cp) control the current-to-voltage module I2V and simultaneously send the control voltage signal Vctrl to the voltage-to-current module V2I, which in turn controls the current injected into the current-controlled oscillator CCO by the voltage-to-current module V2I. For example... Figure 3 and Figure 5As shown, the charge pump cp in this embodiment includes operational amplifiers A2-A3, PMOS transistors Mp13-Mp20, and NMOS transistors Mn9-Mn16. The input signals of the charge pump cp are the up signal UP, the inverted up signal UPb, the down signal DN, and the inverted down signal DN generated by the frequency and phase detector PFD after frequency and phase discrimination; the reference voltage signal Vref generated by the current-to-voltage module I2V; the bias voltage signal Vb generated by the bias current mirror module bias after biasing; and a pair of opposite power-on signals Pon and ponb. The output signals of the charge pump cp include the control voltage signal Vc. The control voltage signal Vctrl is fed back to the voltage-to-current conversion module V2I to control its pull-down network, which is also the input of the comparator operational amplifier A1. The control voltage signal Vint is fed back to the gate of the NMOS transistor Mn20 in the current-to-voltage conversion module I2V to control the generation of the control voltage signal Vctrl. The pull-up networks that generate the control voltage signals Vctrl and Vint in the charge pump cp are controlled by PMOS transistors Mp13 and Mp17, respectively. The pull-down networks that generate the control voltage signals Vctrl and Vint are controlled by NMOS transistors Mp13 and Mp17, respectively. The NMOS transistors Mn12 and Mn16 control the charge pump's pull-down network. The up signal UP is input to the gates of NMOS transistors Mn10 and Mp19, the inverted up signal UPb is input to the gates of NMOS transistors Mn9 and Mp20, the down signal DN is input to the gates of Mp15 and Mn14, and the inverted down signal DN is input to the gates of NMOS transistors Mn13 and Mp16. The reference voltage signal Vref is input to the gates of NMOS transistors Mn11 and Mn15, controlling the pull-down network of the charge pump CP. The bias voltage signal Vb is input to the PMOS transistor. The gates of Mp14 and Mp18 control the pull-up network of the charge pump cp; an operational amplifier A3 is clamped at the control terminal Vctrl_dump between the control voltage signal Vctrl and the drain of the PMOS transistor Mp15 and the NMOS transistor Mn9, and an identical operational amplifier A2 is clamped at the control terminal Vint_dump between the control voltage signal Vint and the drain of the PMOS transistor Mp20 and the NMOS transistor Mn14. There are a total of 24 groups of charge pump cp that generate the control voltage signal Vctrl, and a total of 8 groups of charge pump cp that generate the control voltage signal Vint.

[0026] The current-to-voltage (I2V) module is divided into two paths, ensuring that the transistor sizes are matched. One path generates a reference voltage signal Vref, which serves as the input reference voltage for the comparator operational amplifier A1. The other path is controlled by the control voltage signals Vctrl and Vint generated by the charge pump cp. The generated control voltage signal Vctrl is also used as another input signal for the comparator operational amplifier A1. The comparator operational amplifier A1 compares the control voltage signal Vctrl with the reference voltage signal Vref, determines the difference between them, and then uses the output as the reference voltage Vbias for the bias current mirror module bias. Figure 3 and Figure 5 As shown, the current-to-voltage module I2V in this embodiment includes PMOS transistors Mp21-Mp26 and NMOS transistors Mn17-Mn25. The input signal is the bias voltage signal Vb generated after biasing by the bias current mirror module bias, a pair of opposite power-on signals Pon and ponb, and a control signal Pon_stop. The output signals are the control voltage signal Vctrl and the reference voltage signal Vref. The reference voltage signal Vref is fed back to the charge pump cp to control the pull-down network of the charge pump cp. The control voltage signal Vctrl is fed back to the voltage-to-current module V2I to control its pull-down network, and is also the input terminal of the comparator operational amplifier A1. The power-on signal Ponb is connected to the gates of PMOS transistors Mp24 and Mp21, the power-on signal Pon is connected to the gates of NMOS transistors Mn17-Mn18, Mn21-Mn22, and Mn23-Mn25, and the control signal Pon_stop is connected to the gates of PMOS transistors Mp23 and Mp26.

[0027] like Figure 3 and Figure 5 As shown, the voltage-to-current conversion module V2I in this embodiment includes a pmos transistor Mp27 and NMOS transistors Mn26-Mn28. The input signal is the amplified signal Vbias output by the comparator operational amplifier A1, the bias signal icas generated after biasing by the bias current mirror module bias, and the control voltage signal Vctrl jointly generated by the current-to-voltage conversion module I2V and the charge pump cp. The output signal is the input signal ivco of the current-controlled oscillator CCO, which controls the oscillation frequency of the current-controlled oscillator CCO. The amplified signal Vbias is connected to the gate of the pmos transistor Mp27, controlling the pull-up network that generates the input signal ivco of the current-controlled oscillator CCO. The bias signal icas and the control voltage signal Vctrl are respectively connected to the gates of the NMOS transistors Mn26 and Mn27, jointly controlling the pull-down network that generates the input signal ivco of the current-controlled oscillator CCO.

[0028] In this embodiment, the bias voltage of all modules in the globally dynamic self-biased low-noise phase-locked loop circuit is provided by the internal low-dropout linear regulator (LDO) circuit. Simultaneously, the reference current of the LDO circuit is provided by the comparator operational amplifier A1 in the loop, forming a self-biased loop. The self-biased modules in the self-biased loop include the comparator operational amplifier A1, the current-to-voltage module I2V, the voltage-to-current module V2I, the charge pump cp, the LDO circuit, and the bias current mirror module bias. Figure 5 As shown, a feedback loop is formed from the charge pump cp output current (Icp) – comparator operational amplifier A1 (inputs: Vtrl voltage and Vref voltage, output: Vbias voltage) – bias current mirror module bias (outputs reference currents Icp1, Icp2, Icas, reference voltage Vreg) – charge pump cp. It also includes two feedback loops, as shown below. Figure 5 The red and green bold lines in the image indicate the bias current mirror module. Figure 5The blue line loop controls the overall current magnitude of the charge pump CP, forming a loop from charge pump CP to charge pump CP, controlling the overall bias current of the circuit, and forming a global dynamic self-biasing circuit structure. The output voltage of the comparator operational amplifier A1 not only biases the bias current mirror module bias in the phase-locked loop circuit, but also serves as the bias for the PMOS transistor in the voltage-to-current conversion module V2I. Simultaneously, the NMOS transistor in the voltage-to-current conversion module V2I is biased by the control voltage signal Vctrl generated by the charge pump CP and the current-to-voltage conversion module I2V, forming a loop. While ensuring that the transistor sizes of the two CP modules (CP1 and CP2) are matched, and that the upper and lower X4 units in the two current-to-voltage conversion modules I2V, which generate the control voltage signal Vctrl and the reference voltage signal Vref respectively, also maintain transistor size matching, it is also necessary to ensure that the charge pump CP and the current-to-voltage conversion module I2V maintain transistor size matching. When the bias current mirror module bias mirrors the current to the voltage-to-current conversion module V2I, it is also necessary to ensure that the transistor sizes of the bias module and the voltage-to-current conversion module V2I are matched. In this embodiment, all reference currents in the phase-locked loop (PLL) circuit originate from the bias current mirror module (bias), and the reference voltage of the bias current mirror module (bias) is derived from the output of the comparator operational amplifier A1. The difference between the input control voltage signal Vctrl and the reference voltage signal Vref is determined, thus forming a global dynamic self-biasing structure. The characteristic of this structure is that when the PLL is operating, even with significant adjustments to the charge pump cp, the current of the charge pump cp and the current-to-voltage converter I2V will not experience large mismatches. Simultaneously, the current in the bias loop is replicated and, together with the current-to-voltage converter I2V, serves as the input current for the current-controlled oscillator (CCO), enabling faster frequency adjustment of the CCO. Compared to traditional bias structures, this circuit architecture features low noise and high speed.

[0029] like Figure 3 As shown, in this embodiment, the output terminal of the comparator operational amplifier A1 is also grounded through a MOS capacitor X501.

[0030] In addition, this embodiment also provides an electronic device, including a device body and a circuit module disposed in the device body, wherein the circuit module includes the global dynamic self-biased low-noise phase-locked loop circuit described above in this embodiment.

[0031] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A globally dynamic self-biased low-noise phase-locked loop circuit, characterized in that, The circuit includes a frequency and phase detector, a charge pump (cp), a current-to-voltage module (I2V), a comparator operational amplifier (A1), a bias current mirror module (bias), a voltage-to-current module (V2I), a current-controlled oscillator (CCO), a feedback divider circuit, and a low-dropout linear regulator (LDO). These components are sequentially connected to generate an output clock (Clk_out) through the current-controlled oscillator (CCO). The input of the feedback divider circuit is connected to the output of the current-controlled oscillator (CCO) to divide the output clock Clk_out, generating the feedback clock Fb_clk required by the frequency and phase detector. The bias voltage (Vpsf) of the bias current mirror module (bias) and the voltage-to-current module (V2I) both originate from the LDO. Furthermore, the reference voltage (Vreg) of the LDO is the same as the reference voltage (Vreg) of the comparator operational amplifier (A1), forming a self-biasing loop.

2. The global dynamic self-biased low-noise phase-locked loop circuit according to claim 1, characterized in that, The bias current mirror module bias includes PMOS transistors Mp1-Mp10 and NMOS transistors Mn1-Mn7. PMOS transistors Mp1 and Mn1 are connected in series between the bias voltage Vpsf and ground. PMOS transistors Mp2, Mp3, and Mn2 are connected in series between the bias voltage Vpsf and ground. The gate of PMOS transistor Mp2 is connected to the frequency selection signal Freq_sel. The gate of PMOS transistor Mp1 is connected to the amplified signal Vbias output by the comparator operational amplifier A1. The gates of NMOS transistors Mn1 and Mn2 are connected to form a current mirror to generate a bias current Vb and output it to the current-to-voltage module I2V. PMOS transistors Mp4 and Mp7 are connected in series, with one end connected to the bias voltage Vpsf and the other end outputting a bias current Icp1 to the charge pump cp. PMOS transistors Mp5 and Mp7 are connected in series, with one end connected to the bias voltage Vpsf and the other end outputting a bias current Icp1 to the charge pump cp. p5 is connected in series, with one end connected to the bias voltage Vpsf and the other end outputting a bias current Icp2 to the charge pump cp. PMOS transistors Mp6 and Mn3 are connected in series between the bias voltage Vpsf and ground. PMOS transistors Mp9 and Mn4 are connected in series between the bias voltage Vpsf and ground. The gates of Mn3 and Mn4 are connected to form a current mirror to generate a control signal to control the gate of PMOS transistor Mp10. The source of PMOS transistor Mp10 is connected to the bias voltage Vpsf, and its drain generates a bias current icas through multiple parallel units and outputs it to the voltage-to-current conversion module V2I. The parallel units include NMOS transistors Mn5, Mn6, and Mn7. The drain of PMOS transistor Mp10 is grounded sequentially through one or more sets of NMOS transistors Mn5, Mn6, and Mn7. The gate of NMOS transistor Mn7 is connected to the power supply voltage Vp_cp.

3. The global dynamic self-biased low-noise phase-locked loop circuit according to claim 2, characterized in that, The circuit portion of the low-dropout linear regulator (LDO) circuit that generates the bias voltage Vpsf includes an NMOS transistor Mn8, PMOS transistors Mp11-Mp12, an operational amplifier A4, and multiple NMOS transistors connected in series. PMOS transistors Mp11 and Mn8 are connected in series between voltage Vph and ground. The gate of NMOS transistor Mn8 is connected to the output voltage Vreg of PMOS transistor Mp6 in the bias current mirror module bias. The drain of PMOS transistor Mp11 is connected to the gate of PMOS transistor Mp12. PMOS transistor Mp12 and the multiple NMOS transistors connected in series are connected in series between voltage Vph and ground. The drain of PMOS transistor Mp12 is connected to the input terminal of operational amplifier A4 to output the bias voltage Vpsf through the output terminal of operational amplifier A4.

4. The global dynamic self-biased low-noise phase-locked loop circuit according to claim 3, characterized in that, The circuit portion of the low-dropout linear regulator (LDO) circuit that generates the power supply voltage Vp_cp includes a capacitor, an operational amplifier A5, and multiple PMOS transistors connected in series. These multiple PMOS transistors and the capacitor are connected in series between the voltage Vph and ground. The intermediate node between the capacitor and the multiple PMOS transistors is connected to the input terminal of the operational amplifier A5, so that the power supply voltage Vp_cp is output through the output terminal of the operational amplifier A5.

5. The global dynamic self-biased low-noise phase-locked loop circuit according to claim 1, characterized in that, The charge pump CP includes operational amplifiers A2-A3, PMOS transistors Mp13-Mp20, and NMOS transistors Mn9-Mn16. The input signals of the charge pump CP are: an up signal UP, an inverted up signal UPb, a down signal DN, and an inverted down signal DN generated by the frequency and phase detector PFD after frequency and phase discrimination; a reference voltage signal Vref generated by the current-to-voltage module I2V; a bias voltage signal Vb generated by the bias current mirror module bias after biasing; and a pair of opposite power-on signals Pon and ponb. The output signals of the charge pump CP include control voltage signals Vctrl and V... The control voltage signal Vctrl is fed back to the voltage-to-current conversion module V2I to control its pull-down network, which is also the input of the comparator operational amplifier A1; the control voltage signal Vint is fed back to the gate of the NMOS transistor Mn20 in the current-to-voltage conversion module I2V to control the generation of the control voltage signal Vctrl; the pull-up networks that generate the control voltage signals Vctrl and Vint in the charge pump cp are controlled by PMOS transistors Mp13 and Mp17, respectively; the pull-down networks that generate the control voltage signals Vctrl and Vint are controlled by NMOS transistors Mn20, respectively. The NMOS transistors Mn12 and Mn16 control the charge pump's pull-down network. The up signal (UP) is input to the gates of NMOS transistors Mn10 and Mp19, the inverted up signal (UPb) is input to the gates of NMOS transistors Mn9 and Mp20, the down signal (DN) is input to the gates of Mp15 and Mn14, and the inverted down signal (DN) is input to the gates of NMOS transistors Mn13 and Mp16. The reference voltage signal (Vref) is input to the gates of NMOS transistors Mn11 and Mn15, controlling the pull-down network of the charge pump (CP). The bias voltage signal (Vb) is input to the PMOS transistor Mp10. The gates of Mp14 and Mp18 control the pull-up network of the charge pump cp; an operational amplifier A3 is clamped at the control terminal Vctrl_dump between the control voltage signal Vctrl and the drain of the PMOS transistor Mp15 and the NMOS transistor Mn9, and an identical operational amplifier A2 is also clamped at the control terminal Vint_dump between the control voltage signal Vint and the drain of the PMOS transistor Mp20 and the NMOS transistor Mn14. There are a total of 24 groups of charge pump cp that generate the control voltage signal Vctrl, and a total of 8 groups of charge pump cp that generate the control voltage signal Vint.

6. The global dynamic self-biased low-noise phase-locked loop circuit according to claim 1, characterized in that, The current-to-voltage module I2V includes PMOS transistors Mp21-Mp26 and NMOS transistors Mn17-Mn25. Its input signals are the bias voltage signal Vb generated by the bias current mirror module bias, a pair of opposite power-on signals Pon and ponb, and a control signal Pon_stop. The output signals are the control voltage signal Vctrl and the reference voltage signal Vref. The reference voltage signal Vref is fed back to the charge pump cp, controlling its pull-down network. The control voltage signal Vctrl is fed back to the voltage-to-current module V2I, controlling its pull-down network and also serving as the input to the comparator operational amplifier A1. The power-on signal Ponb is connected to the gates of PMOS transistors Mp24 and Mp21, the power-on signal Pon is connected to the gates of NMOS transistors Mn17-Mn18, Mn21-Mn22, and Mn23-Mn25, and the control signal Pon_stop is connected to the gates of PMOS transistors Mp23 and Mp26.

7. The global dynamic self-biased low-noise phase-locked loop circuit according to claim 1, characterized in that, The voltage-to-current conversion module V2I includes a pmos transistor Mp27 and NMOS transistors Mn26-Mn28. Its input signals are the amplified signal Vbias output from the comparator operational amplifier A1, the bias signal icas generated by the bias current mirror module bias, and the control voltage signal Vctrl jointly generated by the current-to-voltage conversion module I2V and the CP module. The output signal is the input signal ivco of the current-controlled oscillator (CCO), which controls the oscillation frequency of the CCO. The amplified signal Vbias is connected to the gate of the pmos transistor Mp27, controlling the pull-up network that generates the input signal ivco of the CCO. The bias signal icas and the control voltage signal Vctrl are connected to the gates of the NMOS transistors Mn26 and Mn27, respectively, jointly controlling the pull-down network that generates the input signal ivco of the CCO.

8. The global dynamic self-biased low-noise phase-locked loop circuit according to claim 1, characterized in that, The output of the comparator operational amplifier A1 is also grounded through a MOS capacitor X501.

9. An electronic device, comprising a device body and a circuit module disposed within the device body, characterized in that, The circuit module includes the global dynamic self-biased low-noise phase-locked loop circuit as described in any one of claims 1 to 8.

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