High speed comparator and applications thereof

Abstract

In order to improve the comparison speed of the comparator, the application provides a high-speed comparator and application thereof, which adopts a two-stage structure, a first stage is a pre-amplification stage, and a second stage is an amplification and latching stage; a differential input signal is connected to the pre-amplification stage, and a differential output end of the pre-amplification stage is connected to a differential input end of the amplification and latching stage; two clock signals are used to perform timing control on the pre-amplification stage and the amplification and latching stage, the two clock signals are respectively a first clock signal CLKB and a second clock signal CLK, the phase of the first clock signal CLKB is ahead of the phase of the second clock signal CLK by a certain phase, and each clock cycle is divided into a reset stage, a reset pre-amplification stage, an amplification stage and a pre-reset stage. The application increases the pre-amplification of the reset stage and the pre-reset of the comparison stage in the timing through clock control, forms multiplexing in time, and relieves the tense timing margin.

Description

Technical Field

[0001] The present invention mainly relates to the field of electronic information technology, in particular to a high-speed comparator and application thereof. Background Art

[0002] Analog-to-digital converters (ADCs) are core components of modern electronic information systems and are widely used in fields with stringent requirements for high-speed data conversion, such as wireless communications, image processing, radar systems, and precision measurement. The Successive Approximation Register ADC (SAR ADC) is a medium-to-high-precision analog-to-digital conversion technology based on the successive approximation algorithm. As a key functional unit of a SAR ADC, the comparator performs real-time comparisons of the input analog signal with a reference voltage and outputs the corresponding digital level. Its performance directly determines the ADC's conversion speed, resolution, and overall power consumption. As ADC sampling rates continue to increase, the comparator's time margin decreases. Improving comparison speed and achieving fast and accurate comparisons are key challenges for high-speed ADCs.

[0003] In a clock cycle, the traditional two-stage structure is in working state only half of the time. Coupled with the influence of parasitic capacitance, the traditional two-stage structure comparator circuit must complete pre-amplification, amplification and latching operations in far less than half of the clock cycle. At high data rates, it will face strict timing margins. Summary of the Invention

[0004] In view of the technical problems existing in the prior art and in order to improve the comparison speed of the comparator, the present invention proposes a high-speed comparator and applications thereof.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] On the one hand, the present invention provides a high-speed comparator, which adopts a two-stage structure, wherein the first stage is a pre-amplifier stage and the second stage is an amplifying latch stage; a differential input signal is connected to the pre-amplifier stage, and a differential output terminal of the pre-amplifier stage is connected to a differential input terminal of the amplifying latch stage;

[0007] Two clock signals are used to perform timing control on the pre-amplifier stage and the amplification latch stage. The two clock signals are the first clock signal CLKB and the second clock signal CLK. The phase of the first clock signal CLKB is a certain phase ahead of the phase of the second clock signal CLK. Each clock cycle is divided into a reset phase, a reset pre-amplifier phase, an amplification phase and a pre-reset phase.

[0008] Preferably, the clock periods of the first clock signal CLKB and the second clock signal CLK are equal, and the duty cycles of both are 50%.

[0009] Preferably, the pre-amplifier stage includes a pre-amplifier stage tail current tube, a pre-amplifier stage differential input pair tube, a pre-amplifier stage latch pair tube, and two pre-amplifier stage pull-up tubes connected between the differential output terminal of the pre-amplifier stage and the VDD terminal;

[0010] The pre-amplifier tail current tube is connected between the pre-amplifier differential input pair tube and the ground, and the first clock signal CLKB is input into the pre-amplifier stage via the pre-amplifier tail current tube;

[0011] The differential input signal is input to the pre-amplifier stage via the pre-amplifier stage differential input pair tube, and the pre-amplifier stage differential input pair tube is connected between the pre-amplifier stage tail current tube and the differential output end of the pre-amplifier stage;

[0012] The pre-amplifier stage latch pair is connected to the differential output terminal of the pre-amplifier stage and the VDD terminal. The pre-amplifier stage latch pair is a cross-coupled structure, forming a positive feedback latch amplifier.

[0013] The pull-up tube of the pre-amplifier stage is connected between the differential output terminal of the pre-amplifier stage and the VDD terminal, and the second clock signal CLK is input into the pre-amplifier stage via the pull-up tube of the pre-amplifier stage.

[0014] Preferably, the amplifying and latching stage includes an amplifying and latching stage tail current tube, an amplifying and latching stage differential input pair tube, an amplifying and latching stage latch pair tube and an amplifying and latching stage pull-up tube;

[0015] The tail current tube of the amplifying latch stage is connected between the differential input pair of the amplifying latch stage and the ground, and the second clock signal CLK is input into the amplifying latch stage via the tail current tube of the pre-amplifying stage;

[0016] The differential output signal of the pre-amplifier stage is input into the amplifier latch stage via the differential input pair of the amplifier latch stage, and the differential input pair of the amplifier latch stage is connected between the tail current tube of the amplifier latch stage and the differential output end of the amplifier latch stage;

[0017] The latch pair of the amplifying latch stage is connected to the differential output terminal of the amplifying latch stage and the VDD terminal. The latch pair of the amplifying latch stage is a cross-coupled structure, forming a positive feedback latch amplifier.

[0018] The pull-up tube of the amplifying latch stage is connected between the differential output terminal of the amplifying latch stage and the VDD terminal. The second clock signal CLK is input into the amplifying latch stage via the pull-up tube of the pre-amplifying latch stage.

[0019] On the other hand, the high-speed comparator can be applied in a successive approximation analog-to-digital converter. That is, a successive approximation analog-to-digital converter is provided, which includes any of the high-speed comparators described above.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] Compared to traditional two-stage comparator architectures, the present invention uses two clock signals for timing control of the pre-amplifier stage and the amplification latch stage. These two clock signals are a first clock signal, CLKB, and a second clock signal, CLK. The phase of the first clock signal, CLKB, is a certain phase ahead of the phase of the second clock signal, CLK. Each clock cycle is divided into a reset phase, a reset pre-amplification phase, an amplification phase, and a pre-reset phase. This has the advantage of alleviating timing margins. Specifically, the reset and comparison phases overlap, improving time utilization and reducing the requirements for circuit response speed. Compared to the pre-amplifier stage in traditional two-stage comparator architectures, the present invention further incorporates positive feedback amplification into the dynamic comparator, improving output response speed.

[0022] Compared with the traditional two-stage comparator architecture, the present invention has the advantage of low kickback noise, which is specifically reflected in the following aspects: since the output of the pre-amplifier stage is limited in the pre-reset stage, and the pre-amplifier stage adjusts the pull-up level in the reset stage to VDD-|Vds|, the signal change amplitude at dn / dp is reduced and the kickback noise is weakened.

[0023] Compared to traditional two-stage comparator architectures, this invention offers the advantages of high resolution and low offset noise. Specifically, the addition of a cross-coupled positive feedback structure in the pre-amplifier stage increases the gain of the first-stage circuit, making it easier to detect small signal differences. Furthermore, the greater the first-stage gain, the smaller the contribution of the offset voltage of subsequent stages to the overall offset. Increasing the gain of the first-stage circuit reduces the offset voltage of the entire circuit.

[0024] Compared with the traditional two-stage comparator architecture, the present invention has the advantage of breaking through the constraints of gain and bandwidth. Specifically, it adopts a dynamic comparator combined with a cross-coupled positive feedback structure in the pre-amplifier stage to improve the gain while avoiding the problem of narrowing the bandwidth and extending the signal settling time due to the increase in gain in the static circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0026] Figure 1 Schematic diagram of the structure of a high-speed comparator in one embodiment, wherein Figure 1(a) is a pre-amplifier stage diagram, Figure 1 (b) is an amplification latch stage diagram;

[0027] Figure 2 is a high-speed comparator timing control diagram in an embodiment;

[0028] Figure 3 is a dn / dp transient curve diagram in an embodiment;

[0029] Figure 4 is a reset stage diagram of a high-speed comparator in an embodiment, wherein Figure 4 (a) is a reset stage diagram of a pre-amplifier, Figure 4 (b) is a reset stage diagram of an amplification latch;

[0030] Figure 5 is a reset pre-amplification stage diagram of a high-speed comparator in an embodiment, wherein Figure 5 (a) is a reset pre-amplification stage diagram of a pre-amplifier, Figure 5 (b) is a reset pre-amplification stage diagram of an amplification latch;

[0031] Figure 6 is an amplification stage diagram of a high-speed comparator in an embodiment, wherein Figure 6 (a) is an amplification stage diagram of a pre-amplifier, Figure 6 (b) is an amplification stage diagram of an amplification latch;

[0032] Figure 7 is a pre-reset stage diagram of a high-speed comparator in an embodiment, wherein Figure 7 (a) is a pre-reset stage diagram of a pre-amplifier, Figure 7 (b) is a pre-reset stage diagram of an amplification latch. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0034] In order to improve the comparison speed of the comparator, in an embodiment, a high-speed comparator is provided, which adopts a two-stage structure, the first stage is a pre-amplifier stage, and the second stage is an amplification latch stage; a differential input signal is connected to the pre-amplifier stage, and the differential output end of the pre-amplifier stage is connected to the differential input end of the amplification latch stage.

[0035] The pre-amplification stage and the amplification and latching stage are controlled by two clock signals, the first clock signal CLKB and the second clock signal CLK, the phase of the first clock signal CLKB is ahead of the phase of the second clock signal CLK by a certain phase, and each clock cycle is divided into a reset stage, a reset pre-amplification stage, an amplification stage and a pre-reset stage. In this way, through clock control, the pre-amplification of the reset stage and the pre-reset of the comparison stage are added in the timing, forming multiplexing in time and relieving the tense timing margin.

[0036] Preferably, the clock periods of the first clock signal CLKB and the second clock signal CLK are equal, and the duty cycles are both 50%.

[0037] In an embodiment, a design scheme of the pre-amplification stage is provided: the pre-amplification stage includes a pre-amplification stage tail current tube, a pre-amplification stage differential input pair tube, a pre-amplification stage latching pair tube and two pre-amplification stage pull-up tubes connected between the differential output end of the pre-amplification stage and the VDD end.

[0038] The pre-amplification stage tail current tube is connected between the pre-amplification stage differential input pair tube and the ground, and the first clock signal CLKB is input into the pre-amplification stage through the pre-amplification stage tail current tube.

[0039] The differential input signal is input into the pre-amplification stage through the pre-amplification stage differential input pair tube, and the pre-amplification stage differential input pair tube is connected between the pre-amplification stage tail current tube and the differential output end of the pre-amplification stage.

[0040] The pre-amplification stage latching pair tube is connected between the differential output end of the pre-amplification stage and the VDD end, and the pre-amplification stage latching pair tube is of a cross-coupled structure and constitutes a positive feedback latching amplifier.

[0041] The pre-amplification stage pull-up tube is connected between the differential output end of the pre-amplification stage and the VDD end, and the second clock signal CLK is input into the pre-amplification stage through the pre-amplification stage pull-up tube.

[0042] The cross-coupled positive feedback structure is added in the pre-amplification stage, the gain of the first stage circuit is improved, and the tiny signal difference is more easily detected. In addition, the greater the first stage gain is, the smaller the contribution of the subsequent stage to the total offset voltage is, and the offset voltage of the overall circuit is reduced. The dynamic comparator is combined with the cross-coupled positive feedback structure in the pre-amplification stage, the gain is improved, and the problem of narrow bandwidth and long signal establishment time caused by the increase of the gain of the static circuit is avoided.

[0043] In an embodiment, a design scheme of the amplification and latching stage is provided: the amplification and latching stage includes an amplification and latching stage tail current tube, an amplification and latching stage differential input pair tube, an amplification and latching stage latching pair tube and an amplification and latching stage pull-up tube.

[0044] The amplification latch stage tail current tube is connected between the amplification latch stage differential input pair tube and the ground, and the second clock signal CLK is input into the amplification latch stage through the pre-amplification stage tail current tube.

[0045] The differential output signal of the pre-amplification stage is input into the amplification latch stage through the amplification latch stage differential input pair tube, and the amplification latch stage differential input pair tube is connected between the amplification latch stage tail current tube and the differential output end of the amplification latch stage.

[0046] The amplification latch stage latch pair tube is connected between the differential output end of the amplification latch stage and the VDD end, and the amplification latch stage latch pair tube is in a cross-coupled structure, forming a positive feedback latch amplifier.

[0047] The amplification latch stage pull-up tube is connected between the differential output end of the amplification latch stage and the VDD end, and the second clock signal CLK is input into the amplification latch stage through the pre-amplification latch stage pull-up tube.

[0048] In an embodiment, with reference to Figure 1 , a high-speed comparator is provided, which adopts a two-stage structure, the first stage is a pre-amplification stage, and the second stage is an amplification latch stage, wherein Figure 1 (a) is a structure diagram of the pre-amplification stage, Figure 1 (b) is a structure diagram of the amplification latch stage. The input end of the pre-amplification stage is connected with a first input signal Vip and a second input signal Vin, and the output end of the pre-amplification stage is connected with the input end of the amplification latch stage.

[0049] The pre-amplification stage includes a pre-amplification stage tail current tube M0, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, and a sixth MOS tube M6, wherein the pre-amplification stage tail current tube M0, the first MOS tube M1, and the second MOS tube M2 are NMOS tubes, and the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, and the sixth MOS tube M6 are PMOS tubes.

[0050] The gate of the pre-amplification stage tail current tube M0 is connected with a first clock signal CLKB, and tail current is provided under the control of the first clock signal CLKB; the source of the pre-amplification stage tail current tube M0 is grounded, and the drain of the pre-amplification stage tail current tube M0 is connected with a first node;

[0051] The first MOS tube M1 and the second MOS tube M2 form a pre-amplification stage differential input pair tube, the gate of the first MOS tube M1 is connected with a first input signal input end Vip, the gate of the second MOS tube M2 is connected with a second input signal input end Vin, the source of the first MOS tube M1 and the source of the second MOS tube M2 are commonly connected with the first node, the drain of the first MOS tube M1 is connected with a second node, and the drain of the second MOS tube M3 is connected with a third node;

[0052] The fourth MOS transistor M4 and the fifth MOS transistor M5 constitute a pre-amplification stage latch pair transistor, are in a cross-coupling structure, and constitute a positive feedback latch amplifier, wherein sources of the fourth MOS transistor M4 and the fifth MOS transistor M5 are connected to the VDD terminal, a drain of the fourth MOS transistor M4 and a gate of the fifth MOS transistor M5 are connected to the second node, and a gate of the fourth MOS transistor M4 and a drain of the fifth MOS transistor M5 are connected to the third node.

[0053] The third MOS transistor M3 and the sixth MOS transistor M6 are pre-amplification stage pull-up transistors, gates of the third MOS transistor M3 and the sixth MOS transistor M6 are connected to the second clock signal CLK, sources of the third MOS transistor M3 and the sixth MOS transistor M6 are connected to the VDD terminal, a drain of the third MOS transistor M3 is connected to the second node, a drain of the sixth MOS transistor M6 is connected to the third node, the second node is a first output terminal dp of the pre-amplification stage, and the third node is a second output terminal dn of the pre-amplification stage.

[0054] The amplification latch stage includes a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, and a thirteenth MOS transistor M13, wherein the seventh MOS transistor M7, the eighth MOS transistor M8, and the ninth MOS transistor M9 are NMOS transistors, and the tenth MOS transistor M10, the eleventh MOS transistor M11, the twelfth MOS transistor M12, and the thirteenth MOS transistor M13 are PMOS transistors.

[0055] The seventh MOS transistor M7 is a tail current transistor of the amplification latch stage, provides a tail current under the control of the second clock signal CLK, a gate of the seventh MOS transistor M7 is connected to the second clock signal CLK, a source of the seventh MOS transistor M7 is grounded, and a drain of the seventh MOS transistor M7 is connected to the fourth node.

[0056] The eighth MOS transistor M8 and the ninth MOS transistor M9 constitute a differential input pair transistor of the amplification latch stage, a gate of the eighth MOS transistor M8 is connected to the first output terminal dp of the pre-amplification stage, a gate of the ninth MOS transistor M9 is connected to the second output terminal dn of the pre-amplification stage, sources of the eighth MOS transistor M8 and the ninth MOS transistor M9 are commonly connected to the fourth node, a drain of the eighth MOS transistor M8 is connected to the fifth node, and a drain of the ninth MOS transistor M9 is connected to the sixth node.

[0057] The eleventh MOS transistor M11 and the twelfth MOS transistor M12 constitute a latch pair transistor of the amplification latch stage, are in a cross-coupling structure, and constitute a positive feedback latch amplifier, wherein sources of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are connected to the VDD terminal, a drain of the eleventh MOS transistor M11 and a gate of the twelfth MOS transistor M12 are connected to the fifth node, a gate of the eleventh MOS transistor M11 and a drain of the twelfth MOS transistor M12 are connected to the sixth node.

[0058] The tenth MOS transistor M10 and the thirteenth MOS transistor M13 are pull-up transistors of the amplifying latch stage. The gates of the tenth MOS transistor M10 and the thirteenth MOS transistor M13 are both connected to the second clock signal CLK. The sources of the tenth MOS transistor M10 and the thirteenth MOS transistor M13 are both connected to the VDD terminal. The drain of the tenth MOS transistor M10 is connected to the fifth node, and the drain of the thirteenth MOS transistor M13 is connected to the sixth node. The fifth node serves as the first output terminal Vop of the amplifying latch stage, and the sixth node serves as the second output terminal Von of the amplifying latch stage.

[0059] like Figure 2 As shown in the figure, it is a timing control diagram of a high-speed comparator, in which the clock periods of the first clock signal CLKB and the second clock signal CLK are equal, the duty cycles are both 50%, the phase of the first clock signal CLKB is ahead of the phase of the second clock signal CLK by a certain phase, and each clock period is divided into a reset phase, a reset pre-amplification phase, an amplification phase and a pre-reset phase; in the reset phase, the first clock signal CLKB and the second clock signal CLK are both low; in the reset pre-amplification phase, the first clock signal CLKB is high and the second clock signal CLK is low; in the amplification phase, the first clock signal CLKB is high and the second clock signal CLK is high; in the pre-reset phase, the first clock signal CLKB is low and the second clock signal CLK is high.

[0060] Reference Figure 3 , is a dn / dp transient curve diagram, wherein Vdsh is the larger drain-source voltage between the drain-source voltage of the third MOS transistor and the drain-source voltage of the sixth MOS transistor in the reset pre-amplification stage, and Vdsl is the smaller drain-source voltage between the drain-source voltage of the third MOS transistor and the drain-source voltage of the sixth MOS transistor.

[0061] In the reset phase, the first output terminal dp and the second output terminal dn of the preamplifier stage are both reset to VDD. The time when the first output terminal dp and the second output terminal dn of the preamplifier stage are both reset is t3.

[0062] In the reset pre-amplification stage, the first output terminal dp of the pre-amplification stage and the second output terminal dn of the pre-amplification stage are amplified to VDD-Vdsl and VDD-Vdsh respectively. The time when the first output terminal dp of the pre-amplification stage and the second output terminal dn of the pre-amplification stage are fully amplified is t1.

[0063] During the amplification stage, the first output terminal dp of the pre-amplifier stage and the second output terminal dn of the pre-amplifier stage continue to amplify under the action of positive feedback. The time when the first output terminal dp of the pre-amplifier stage and the second output terminal dn of the pre-amplifier stage are amplified to the point where they can just be read by the next stage is t2.

[0064] In the pre-reset stage, the first output end dp of the pre-amplification stage and the second output end dn of the pre-amplification stage stop amplification.

[0065] The clock period of the first clock signal CLKB and the second clock signal CLK is T. The first clock signal CLKB is ahead of the second clock signal CLK by a phase x, which is defined in the range of t1 < x < max(T / 2-t2, T / 2-t3). Under the premise of normal operation of the circuit, the greater the x, the faster the circuit speed, but due to the influence of PVT, x generally will not take the limit value, but within a certain range according to the circuit requirements.

[0066] Preferably, the phase of the first clock signal CLKB ahead of the second clock signal CLK is less than 1 / 4 clock period.

[0067] As shown in Figure 4 , wherein Figure 4 (a) is a schematic diagram of the pre-amplification stage in the reset stage, Figure 4 (b) is a schematic diagram of the amplification latch stage in the reset stage, in the reset stage, the second clock signal CLK is low, the first clock signal CLKB is low, the third MOS tube M3, the sixth MOS tube M6, the tenth MOS tube M10, the thirteenth MOS tube M13 are turned on, the pre-amplification stage tail current tube M0, the seventh MOS tube M7 are cut off, the fourth MOS tube M4, the fifth MOS tube M5, the eleventh MOS tube M11, the twelfth MOS tube M12 are cut off, the first output end dp of the pre-amplification stage, the second output end dn of the pre-amplification stage, the first output end Vop of the amplification latch stage, the second output end Von of the amplification latch stage are pulled up to VDD.

[0068] As shown in Figure 5 , wherein Figure 5 (a) is a schematic diagram of the pre-amplification stage in the reset pre-amplification stage, Figure 5(b) is a schematic diagram of the reset pre-amplification phase of the amplifying latch stage. During the reset pre-amplification phase, the second clock signal CLK is at a low level, the first clock signal CLKB is at a high level, the third MOS transistor M3, the sixth MOS transistor M6, the tenth MOS transistor M10, and the thirteenth MOS transistor M13 are turned on, the seventh MOS transistor M7 is turned off, the fourth MOS transistor M4, the fifth MOS transistor M5, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 are turned off, and the first output terminal Vop and the second output terminal Von of the amplifying latch stage are pulled up to VDD. The pre-amplifying stage constitutes a static amplifying circuit. The first output terminal dp and the second output terminal dn of the pre-amplifying stage are pulled up to VDD-|Vds|, where Vds is the source-drain voltage of the third MOS transistor M3 and the sixth MOS transistor M6 during the reset pre-amplification phase. Assuming Vip>Vin (the input voltage Vip of the first input signal input terminal is greater than the input voltage Vin of the second input signal input terminal), the current flowing through the first MOS tube M1 is greater than the second MOS tube M2, |Vds3|>|Vds6|, then the voltage of the first output terminal dp of the pre-amplifier stage is less than the power supply Vdp of the second output terminal of the pre-amplifier stage. <Vdn,其中Vds3为复位预放大阶段,第三MOS管M3的源漏电压。Vds6为复位预放大阶段,第六MOS管M6的源漏电压。复位预放大阶段完成第一次预放大。

[0069] like Figure 6 As shown, Figure 6 (a) is a schematic diagram of the amplification stage of the pre-amplification stage. Figure 6 (b) is a schematic diagram of the amplification phase of the amplification latch stage. In the amplification phase, the second clock signal CLK is at a high level, the first clock signal CLKB is at a high level, the third MOS transistor M3, the sixth MOS transistor M6, the tenth MOS transistor M10, and the thirteenth MOS transistor M13 are turned off, and the pre-amplification stage tail current transistor M0 and the seventh MOS transistor M7 are turned on.

[0070] The preamplifier stage now forms a positive feedback dynamic amplifier. Assuming Vip > Vin, the current flowing through the first MOS transistor M1 is greater than the current flowing through the second MOS transistor M2. The voltage Vdp at the first output terminal dp of the preamplifier stage drops faster than the voltage Vdn at the second output terminal dn of the preamplifier stage. Vdn - Vdp is the amplified value of Vip - Vin, representing the second preamplification step. The first preamplification step during the reset preamplification phase and the second preamplification step during the reset phase have the same amplification direction. After preamplification, the feedback structure formed by the fourth and fifth MOS transistors M4 and M5 of the preamplifier stage continues to amplify the value of Vdn - Vdp, providing a larger input voltage difference for the subsequent stage and accelerating comparison.

[0071] In the amplification latch stage, the eighth and ninth MOS transistors M8 and M9 receive the amplification result Vdn-Vdp from the pre-amplification stage. Assuming Vip > Vin, then Vdn > Vdp. Consequently, the current flowing through the ninth MOS transistor M9 is greater than the current flowing through the eighth MOS transistor M8, and the voltage at the Von terminal drops faster than that at the Vop terminal. As the voltage at the Von terminal drops, the eleventh MOS transistor M11 gradually turns on. Once the eleventh MOS transistor M11 turns on, the feedback loop formed by the eleventh MOS transistor M11 and the twelfth MOS transistor M12 causes the voltage at the Vop terminal to stop dropping and quickly increase, while continuing to pull down the voltage at the Von terminal, thus performing voltage amplification.

[0072] like Figure 7 As shown, Figure 7 (a) is a schematic diagram of the pre-reset stage of the pre-amplifier stage. Figure 7 (b) is a schematic diagram of the pre-reset phase of the amplifier latch stage. During this phase, the second clock signal CLK is high, the first clock signal CLKB is low, the third MOS transistor M3, the sixth MOS transistor M6, the tenth MOS transistor M10, and the thirteenth MOS transistor M13 are off, the pre-amplifier stage tail current transistor M0 is off, and the seventh MOS transistor M7 is on. At this point, because the amplifier latch stage has entered a positive feedback latching state, Vop and Von are pushed to VDD and GND, respectively, by the feedback network of the eleventh MOS transistor M11 and the twelfth MOS transistor M12. Therefore, the resolution speed is primarily dependent on the eleventh MOS transistor M11 and the twelfth MOS transistor M12, and has nothing to do with the pre-amplifier stage. For the pre-amplifier stage, after the pre-amplifier stage tail current transistor M0 is turned off, the feedback network cannot discharge to ground, interrupting the pre-amplifier stage's feedback amplification, limiting the dn / dp swing, and accelerating the reset speed of the next reset phase.

[0073] Finally, Vop is pulled up to VDD and Von is pulled down to ground, completing the latch.<Vin,最终Vop将被下拉至地,Von被上拉至VDD。可见当输入Vip> When Vin, output Vop>Von, when Vip <Vin时,输出Vop<Von,实现了正确的电平判决。

[0074] Unlike traditional two-stage comparator structures, which complete pre-amplification, amplification, and latching operations within the same half-cycle, the present invention uses clock control to add pre-amplification during the reset phase and pre-reset during the comparison phase to the timing, creating time multiplexing. This circuit extends the sum of the actual comparison and reset times to more than one clock cycle, alleviating tight timing margins.

[0075] Matters not covered by the present invention are known technologies.

[0076] Any technical features in the above-described embodiments can be combined in any manner, and for the sake of brevity, not all possible combinations are described, however, any combination of the technical features is considered to be within the scope of the present specification.

[0077] The above-described embodiments are merely illustrative for the present application and are not used to limit the present application. It should be pointed out that, for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these should be included in the protection scope of the present application.

[0078] The above-described embodiments are merely illustrative for the present application and are not used to limit the present application. It should be pointed out that, for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these should be included in the protection scope of the present application. The above-described embodiments are merely illustrative for the present application and are not used to limit the present application. It should be pointed out that, for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these should be included in the protection scope of the present application.

Claims

1. High-speed comparator, adopting a two-stage structure, characterized by: The first stage is the pre-amplification stage, and the second stage is the amplification latch stage; The preamplifier stage includes a preamplifier tail current tube, a preamplifier differential input pair tube, a preamplifier latch pair tube, and two preamplifier pull-up tubes connected between the differential output terminal of the preamplifier stage and the VDD terminal; the preamplifier tail current tube is connected between the preamplifier differential input pair tube and ground, and the first clock signal CLKB is input into the preamplifier stage via the preamplifier tail current tube; the differential input signal is input into the preamplifier stage via the preamplifier differential input pair tube, and the preamplifier differential input pair tube is connected between the preamplifier tail current tube and the differential output terminal of the preamplifier stage; the preamplifier latch pair tube is connected between the differential output terminal of the preamplifier stage and the VDD terminal, and the preamplifier latch pair tube is a cross-coupling structure, forming a positive feedback latch amplifier; the preamplifier pull-up tube is connected between the differential output terminal of the preamplifier stage and the VDD terminal, and the second clock signal CLK is input into the preamplifier stage via the preamplifier pull-up tube; The amplifying latch stage includes an amplifying latch stage tail current tube, an amplifying latch stage differential input pair tube, an amplifying latch stage latch pair tube, and an amplifying latch stage pull-up tube; the amplifying latch stage tail current tube is connected between the amplifying latch stage differential input pair tube and ground, and the second clock signal CLK is input into the amplifying latch stage via the pre-amplifying stage tail current tube; the differential output signal of the pre-amplifying stage is input into the amplifying latch stage via the amplifying latch stage differential input pair tube, and the amplifying latch stage differential input pair tube is connected between the amplifying latch stage tail current tube and the differential output terminal of the amplifying latch stage; the amplifying latch stage latch pair tube is connected between the differential output terminal of the amplifying latch stage and the VDD terminal, and the amplifying latch stage latch pair tube is a cross-coupling structure, forming a positive feedback latch amplifier; the amplifying latch stage pull-up tube is connected between the differential output terminal of the amplifying latch stage and the VDD terminal, and the second clock signal CLK is input into the amplifying latch stage via the pre-amplifying latch stage pull-up tube; Two clock signals are used to control the timing of the pre-amplification stage and the amplification latch stage. The phase of the first clock signal CLKB is a certain phase ahead of the phase of the second clock signal CLK. Each clock cycle is divided into a reset phase, a reset pre-amplification phase, an amplification phase, and a pre-reset phase. In the reset phase, the first output terminal dp and the second output terminal dn of the differential output terminal of the pre-amplifier stage are both reset to VDD, and the time when the first output terminal dp and the second output terminal dn of the pre-amplifier stage are both reset is recorded as t3; in the reset pre-amplification phase, the time when the first output terminal dp and the second output terminal dn of the differential output terminal of the pre-amplifier stage are both amplified is recorded as t1; In the amplification stage, the first output terminal dp and the second output terminal dn of the differential output terminal of the pre-amplifier stage continue to amplify under the action of positive feedback. The time when the first output terminal dp and the second output terminal dn of the pre-amplifier stage are amplified to the point where they can just be read by the next stage is t2. The clock periods of the first clock signal CLKB and the second clock signal CLK are equal, and the duty cycles are both 50%. The clock periods of the first clock signal CLKB and the second clock signal CLK are denoted as T. The first clock signal CLKB is ahead of the second clock signal CLK by a certain phase x, and the phase is defined as t1. <x<min(T / 2-t2,T / 2-t3)。 2. The high-speed comparator according to claim 1, wherein: The pre-amplifier stage includes a pre-amplifier tail current tube, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, and a sixth MOS tube, wherein the pre-amplifier tail current tube, the first MOS tube, and the second MOS tube are all NMOS tubes, and the third MOS tube, the fourth MOS tube, the fifth MOS tube, and the sixth MOS tube are all PMOS tubes; The gate of the pre-amplifier stage tail current tube is connected to the first clock signal CLKB, and provides a tail current under the control of the first clock signal CLKB; the source of the pre-amplifier stage tail current tube is grounded, and the drain of the pre-amplifier stage tail current tube is connected to the first node; The first MOS transistor and the second MOS transistor constitute a pre-amplifier differential input pair, the gate of the first MOS transistor is connected to the first input signal Vip, the gate of the second MOS transistor is connected to the second input signal Vin, the source of the first MOS transistor and the source of the second MOS transistor are commonly connected to the first node, the drain of the first MOS transistor is connected to the second node, and the drain of the second MOS transistor is connected to the third node; The fourth MOS transistor and the fifth MOS transistor constitute a pre-amplifier stage latch pair, which is a cross-coupled structure and constitutes a positive feedback latch amplifier, wherein the sources of the fourth MOS transistor and the fifth MOS transistor are both connected to the VDD terminal, the drain of the fourth MOS transistor and the gate of the fifth MOS transistor are connected to the second node, and the gate of the fourth MOS transistor and the drain of the fifth MOS transistor are connected to the third node; The third MOS transistor and the sixth MOS transistor are pull-up transistors of the pre-amplifier stage. The gates of the third MOS transistor and the sixth MOS transistor are both connected to the second clock signal CLK. The sources of the third MOS transistor and the sixth MOS transistor are both connected to the VDD terminal. The drain of the third MOS transistor is connected to the second node, and the drain of the sixth MOS transistor is connected to the third node. The second node and the third node are differential output terminals of the pre-amplifier stage, wherein the second node serves as the first output terminal dp of the pre-amplifier stage, and the third node serves as the second output terminal dn of the pre-amplifier stage.

3. The high-speed comparator according to claim 2, wherein: The amplifying latch stage includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor and a thirteenth MOS transistor, wherein the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are all NMOS transistors, and the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor and the thirteenth MOS transistor are all PMOS transistors; The seventh MOS transistor serves as a tail current transistor of the amplifying latch stage, and provides a tail current under the control of the second clock signal CLK. The gate of the seventh MOS transistor is connected to the second clock signal CLK, the source of the seventh MOS transistor is grounded, and the drain of the seventh MOS transistor is connected to the fourth node. The eighth MOS transistor and the ninth MOS transistor constitute a differential input pair of transistors of the amplifying latch stage. The gate of the eighth MOS transistor is connected to the first output terminal dp of the pre-amplifying stage, the gate of the ninth MOS transistor is connected to the second output terminal dn of the pre-amplifying stage, the source of the eighth MOS transistor and the source of the ninth MOS transistor are commonly connected to the fourth node, the drain of the eighth MOS transistor is connected to the fifth node, and the drain of the ninth MOS transistor is connected to the sixth node. The eleventh MOS transistor and the twelfth MOS transistor constitute an amplifying latch stage latch pair, which is a cross-coupled structure and constitutes a positive feedback latch amplifier, wherein the source of the eleventh MOS transistor and the twelfth MOS transistor are both connected to the VDD terminal, the drain of the eleventh MOS transistor and the gate of the twelfth MOS transistor are connected to the fifth node, and the gate of the eleventh MOS transistor and the drain of the twelfth MOS transistor are connected to the sixth node; The tenth MOS transistor and the thirteenth MOS transistor are pull-up transistors of the amplifying latch stage. The gates of the tenth MOS transistor and the thirteenth MOS transistor are both connected to the second clock signal CLK. The sources of the tenth MOS transistor and the thirteenth MOS transistor are both connected to the VDD terminal. The drain of the tenth MOS transistor is connected to the fifth node, and the drain of the thirteenth MOS transistor is connected to the sixth node. The fifth node and the sixth node serve as differential output terminals of the amplifying latch stage, wherein the fifth node serves as the first output terminal Vop of the amplifying latch stage, and the sixth node serves as the second output terminal Von of the amplifying latch stage.

4. The high-speed comparator according to claim 3, wherein: During the reset phase, the first clock signal CLKB and the second clock signal CLK are both at a low level; during the reset pre-amplification phase, the first clock signal CLKB is at a high level and the second clock signal CLK is at a low level; during the amplification phase, the first clock signal CLKB is at a high level and the second clock signal CLK is at a high level; during the pre-reset phase, the first clock signal CLKB is at a low level and the second clock signal CLK is at a high level.

5. The high-speed comparator according to claim 4, wherein: In the reset phase, the first output terminal dp of the pre-amplifier stage and the second output terminal dn of the pre-amplifier stage are both reset to VDD. The time when the first output terminal dp of the pre-amplifier stage and the second output terminal dn of the pre-amplifier stage are both reset is t3. In the reset pre-amplification stage, the first output terminal dp of the pre-amplification stage and the second output terminal dn of the pre-amplification stage are amplified to VDD-Vdsl and VDD-Vdsh, respectively. The time when the first output terminal dp of the pre-amplification stage and the second output terminal dn of the pre-amplification stage are fully amplified is t1, where Vdsh is the larger drain-source voltage between the drain-source voltage of the third MOS transistor and the drain-source voltage of the sixth MOS transistor in the reset pre-amplification stage, and Vdsl is the smaller drain-source voltage between the drain-source voltage of the third MOS transistor and the drain-source voltage of the sixth MOS transistor. In the pre-reset stage, the first output terminal dp of the pre-amplifier stage and the second output terminal dn of the pre-amplifier stage stop amplifying.

6. The high-speed comparator according to claim 1, 2, 3, 4 or 5, wherein: The phase of the first clock signal CLKB is ahead of the second clock signal CLK by less than 1 / 4 clock period.

7. A successive approximation analog-to-digital converter, comprising the high-speed comparator according to claim 1, 2, 3, 4 or 5.

8. The successive approximation analog-to-digital converter according to claim 7, wherein: In the high-speed comparator, the phase of the first clock signal CLKB is less than 1 / 4 of a clock cycle ahead of the second clock signal CLK.

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