Optical receiving component and optical module

Abstract

The invention discloses an optical receiving component and an optical module. The optical receiving component comprises a photoelectric detector, an amplitude detector, a compensation controller and an equalizer. The photodetector is configured to convert the signal light into an electrical signal. The amplitude detector is configured to detect an amplitude value according to the amplified electrical signal. The compensation controller can output different equalization compensation values to the control equalizer according to the amplitude value, so that the equalizer compensates the electric signal according to the equalization compensation values. The amplitude detector can output amplitude values according to different intensities of the optical power, and the compensation controller can output different equalization compensation values to the control equalizer according to the amplitude values, so that the equalizer can carry out equalization compensation on the electric signals according to the intensities of the optical power, the bit error rate is reduced, and the communication quality is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an optical receiving component and an optical module. Background Art

[0002] Passive Optical Network (PON) is a fiber-optic access technology that distributes fiber signals to multiple users via passive optical splitters, achieving fiber-to-the-home (FTTH). With its high transmission rates, wide coverage, low cost, and energy-saving and environmentally friendly advantages, PON has become a mainstream technology for broadband access. PON is an optical distribution network between the optical transmission line (OLT) and optical network units (ONUs) without any active electronic devices. It includes ATM-based passive optical networks (APON) and IP-based passive optical networks (E / GPON).

[0003] A passive optical network consists of an optical line terminal (OLT) installed in a central control station and a number of supporting optical network units (ONUs) installed in user locations.

[0004] The OLT faces uplink optical signals sent from multiple ONU optical modules at different distances. The light intensities of multiple uplink optical signals reaching the OLT optical module are inconsistent. The same optical receiving component faces different light intensities, and the quality of the electrical signals output through photoelectric conversion varies greatly. Summary of the Invention

[0005] The present application provides an optical receiving component and an optical module to improve the quality of electrical signals received in the optical module.

[0006] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0007] In a first aspect, embodiments of the present application disclose a light receiving component, comprising: a photodetector configured to convert signal light into an electrical signal;

[0008] an amplitude detector, whose input terminal is connected to the output terminal of the transimpedance amplifier, and the amplitude detector is configured to detect the amplitude value of the amplified electrical signal;

[0009] a compensation controller, whose input terminal is connected to the first output terminal of the amplitude detector, the compensation controller being configured to calculate a current voltage amplitude value according to the amplitude value, and output a balanced compensation value according to the current voltage amplitude value, the previous voltage amplitude value, the first compensation table, and the second compensation table;

[0010] an equalizer, wherein a first input terminal is connected to the second output terminal of the amplitude detector, a second input terminal is connected to the output terminal of the compensation controller, and the equalizer is configured to perform equalization compensation on the electrical signal according to the equalization compensation value;

[0011] The compensation controller is configured to: when the current voltage amplitude value is greater than or equal to the previous voltage amplitude value, output a balanced compensation value according to the first compensation table;

[0012] When the current voltage amplitude value is smaller than the previous voltage amplitude value, the equalization compensation value is output according to the second compensation table.

[0013] In a second aspect, an embodiment of the present application discloses a light receiving component, comprising: a photodetector configured to convert signal light into an electrical signal;

[0014] an amplitude detector, an input terminal of which is connected to the output terminal of the photodetector, and the amplitude detector is configured to detect an amplitude value of the electrical signal;

[0015] a compensation controller, an input end of which is connected to the first output end of the amplitude detector, the compensation controller being configured to output an equalization compensation value according to the amplitude value and a preset compensation table;

[0016] An equalizer, wherein a first input terminal is connected to the second output terminal of the amplitude detector, and a second input terminal is connected to the output terminal of the compensation controller. The equalizer is configured to perform equalization compensation on the electrical signal according to the equalization compensation value.

[0017] In a third aspect, an embodiment of the present application discloses an optical module, comprising the above-mentioned light receiving component.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] The present application discloses an optical receiving component and an optical module, wherein the optical receiving component includes: a photodetector, an amplitude detector, a compensation controller, and an equalizer. The photodetector is configured to convert the signal light into an electrical signal. The amplitude detector is configured to detect the amplitude value of the amplified electrical signal. The compensation controller can output different equalization compensation values ​​to the control equalizer according to the amplitude value, so that the equalizer compensates the electrical signal according to the equalization compensation value. The amplitude detector can output amplitude values ​​according to different intensities of optical power, and the compensation controller can output different equalization compensation values ​​to the control equalizer according to the amplitude value, so that the equalizer can perform equalization compensation on the electrical signal according to the intensity of the optical power, which is beneficial to reducing the bit error rate and improving the communication quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0021] Figure 1 A partial architecture diagram of an optical communication system provided according to some embodiments of the present disclosure;

[0022] Figure 2 A partial structural diagram of a host computer provided according to some embodiments of the present disclosure;

[0023] Figure 3 A structural diagram of an optical module provided according to some embodiments of the present disclosure;

[0024] Figure 4 An exploded view of an optical module provided according to some embodiments of the present disclosure;

[0025] Figure 5 A schematic diagram of the structure of a light receiving component provided according to some embodiments of the present disclosure Figure 1 ;

[0026] Figure 6 Schematic diagram of the optical power and bit error rate curve of the optical receiving component in the OLT in the prior art;

[0027] Figure 7 A schematic diagram of the structure of a light receiving component provided according to some embodiments of the present disclosure Figure 2 ;

[0028] Figure 8 Schematic diagram of a first compensation table provided according to some embodiments Figure 1 ;

[0029] Figure 9 Schematic diagram of a first compensation table provided according to some embodiments Figure 2 ;

[0030] Figure 10 Schematic diagram of a second compensation table provided according to some embodiments Figure 1 . DETAILED DESCRIPTION

[0031] Some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described are only some of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present disclosure are within the scope of protection of the present disclosure.

[0032] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be interpreted as open and inclusive, meaning "including, but not limited to." The terms "first" and "second" are not to be understood as indicating or implying relative importance or an upper limit on quantity. The term "plurality" means two or more. The term "connected" is to be interpreted broadly, for example, "connected" can mean fixed, detachable, or integrated, directly connected, or indirectly connected through an intermediary. The use of the terms "suitable for" or "configured to" is intended to be open and inclusive, and does not exclude devices that are suitable for or configured to perform additional tasks or steps. Terms such as "parallel," "perpendicular," "same," "consistent," and "aligned" are not to be limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, as well as differences arising from manufacturing based on the same design concept. Without further limitation, the phrase "comprising a..." does not preclude the presence of additional identical elements in the circuit structure, article, or device that includes the element.

[0033] Optical communication technology enables information transmission between information processing devices. It loads information onto light and uses the propagation of light to achieve this transmission. Light loaded with information is an optical signal. The propagation of optical signals within information transmission equipment reduces optical power loss, enabling high-speed, long-distance, and low-cost information transmission. The information processed by information processing equipment exists in the form of electrical signals. Optical network terminals / gateways, routers, switches, mobile phones, computers, servers, tablets, and televisions are common information processing devices, and optical fibers and optical waveguides are common information transmission devices.

[0034] The conversion of optical and electrical signals between information processing equipment and information transmission equipment is achieved through optical modules. For example, an optical fiber is connected to the optical signal input and / or optical signal output of the optical module, and an optical network terminal is connected to the electrical signal input and / or electrical signal output of the optical module. A first optical signal from the optical fiber is transmitted into the optical module, which converts the first optical signal into a first electrical signal, which is then transmitted into the optical network terminal. Since information processing devices can be connected to each other via an electrical signal network, at least one type of information processing device needs to be directly connected to the optical module. It is not necessary for all types of information processing devices to be directly connected to the optical module. The information processing device directly connected to the optical module is called the host computer of the optical module.

[0035] Figure 1 FIG. 1 is a partial architecture diagram of an optical communication system provided according to some embodiments of the present disclosure. Figure 1 As shown, a part of the optical communication system is presented as a remote information processing device 1000 , a local information processing device 2000 , a host computer 100 , an optical module 200 , an optical fiber 101 and a network cable 103 .

[0036] One end of optical fiber 101 extends toward remote information processing device 1000, and the other end connects to the optical interface of optical module 200. Optical signals can undergo total internal reflection within optical fiber 101, maintaining nearly their original optical power as they propagate in the direction of total internal reflection. Multiple total internal reflections within optical fiber 101 transmit optical signals from the direction of remote information processing device 1000 into optical module 200, or transmit light from optical module 200 toward remote information processing device 1000, enabling long-distance, low-power information transmission.

[0037] The number of optical fibers 101 may be one or more (two or more); the optical fiber 101 and the optical module 200 may be connected in a pluggable movable manner or in a fixed manner.

[0038] The host computer 100 has an optical module interface 102, which is configured to connect to the optical module 200, so that the host computer 100 establishes a unidirectional / bidirectional electrical signal connection with the optical module 200; the host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor and control the working status of the optical module 200.

[0039] The host computer 100 has an external electrical interface, such as a Universal Serial Bus (USB) interface and a network cable interface 104, which can be connected to an electrical signal network. For example, the network cable interface 104 is configured to connect to a network cable 103, thereby establishing a unidirectional / bidirectional electrical signal connection between the host computer 100 and the network cable 103.

[0040] Optical Network Unit (ONU), Optical Line Terminal (OLT), Optical Network Equipment (ONT) and data center servers are common host computers.

[0041] One end of the network cable 103 is connected to the local information processing device 2000 , and the other end is connected to the host computer 100 . The network cable 103 establishes an electrical signal connection between the local information processing device 2000 and the host computer 100 .

[0042] For example, the third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted into the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal. The optical module 200 transmits the second optical signal into the optical fiber 101. The second optical signal is transmitted to the remote information processing device 1000 in the optical fiber 101.

[0043] For example, a first optical signal from the direction of the remote information processing device 1000 propagates through the optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted into the optical module 200. The optical module 200 converts the first optical signal into a first electrical signal. The optical module 200 transmits the first electrical signal into the host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal, and the host computer 100 transmits the fourth electrical signal to the local information processing device 2000.

[0044] Optical modules are tools for converting optical signals into electrical signals. During this conversion process, the information remains unchanged, but the encoding and decoding methods of the information can change.

[0045] Figure 2 This is a partial structural diagram of a host computer provided according to some embodiments of the present disclosure. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structures related to the host computer 100 and the optical module 200 are shown. Figure 2 As shown, the host computer 100 also includes a PCB circuit board 105 arranged in the shell, a cage 106 arranged on the surface of the PCB circuit board 105, a heat sink 107 arranged on the cage 106, and an electrical connector (not shown in the figure) arranged inside the cage 106. The heat sink 107 has a protruding structure that increases the heat dissipation area, and a fin-shaped structure is a common protruding structure.

[0046] Optical module 200 is inserted into cage 106 of host computer 100. Cage 106 secures optical module 200, and heat generated by optical module 200 is transferred to cage 106 and then dissipated through heat sink 107. After optical module 200 is inserted into cage 106, the electrical interface of optical module 200 connects to the electrical connector inside cage 106.

[0047] Figure 3 is a structural diagram of an optical module provided according to some embodiments of the present disclosure, Figure 4 FIG1 is an exploded view of an optical module provided according to some embodiments of the present disclosure. Figure 3 and Figure 4 As shown, the optical module 200 includes a housing, a circuit board 300 disposed in the housing, a light emitting component 400, and a light receiving component 500. However, the present disclosure is not limited thereto. In some embodiments, the optical module 200 includes one of the light emitting component 400 and the light receiving component 500.

[0048] The housing includes an upper housing 201 and a lower housing 202 . The upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 . The outer contour of the housing is generally a square.

[0049] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicular to the base plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0050] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicularly to the base plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and arranged perpendicularly to the cover plate 2011. The two upper side plates are combined with the two lower side plates 2022 to achieve the upper shell 201 covering the lower shell 202.

[0051] The direction of the line connecting the two openings 204 and 205 may be consistent with the length direction of the optical module 200, or may be inconsistent with the length direction of the optical module 200. For example, the opening 204 is located at the end of the optical module 200 ( Figure 3 The opening 205 is also located at the end of the optical module 200 ( Figure 3Alternatively, opening 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200. Opening 204 is an electrical interface, through which the gold finger 301 of circuit board 300 extends and is inserted into the electrical connector of the host computer; opening 205 is an optical port, configured to receive optical fiber 101, thereby connecting optical fiber 101 to the optical emitting component 400 and / or optical receiving component 500 in optical module 200.

[0052] The combined assembly of the upper and lower housings 201 and 202 facilitates the installation of components such as the circuit board 300, light emitting component 400, and light receiving component 500 within the housings. These components are encapsulated and protected by the upper and lower housings 201 and 202. Furthermore, during assembly of the circuit board 300, light emitting component 400, and light receiving component 500, positioning components, heat dissipation components, and electromagnetic shielding components are easily positioned, facilitating automated production.

[0053] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0054] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0055] For example, the unlocking member 600 is located on the outside of the two lower side panels 2022 of the lower housing 202 and includes engaging components that mate with the cage 106 of the host computer. When the optical module 200 is inserted into the cage 106, the engaging components of the unlocking member 600 secure the optical module 200 within the cage 106. When the unlocking member 600 is pulled, the engaging components of the unlocking member 600 move accordingly, thereby changing the connection between the engaging components and the host computer, thereby releasing the fixed engagement between the optical module 200 and the host computer, allowing the optical module 200 to be removed from the cage 106.

[0056] The circuit board 300 includes circuit traces, electronic components, and chips. The circuit traces connect the electronic components and chips together according to the circuit design to achieve functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include, for example, a microcontroller unit (MCU), a laser driver chip, a transimpedance amplifier (TIA), a limiting amplifier, a clock and data recovery chip 310 (CDR), a power management chip, and a digital signal processing (DSP) chip.

[0057] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board is also easy to insert into the electrical connector in the upper computer cage.

[0058] The circuit board 300 further includes a gold finger 301 formed on its end surface. The gold finger 301 is composed of a plurality of independent pins. The circuit board 300 is inserted into the cage 106, and the gold finger 301 is connected to the electrical connector in the cage 106. The gold finger 301 can be provided on only one side of the circuit board 300 (for example, Figure 4 The gold finger 301 is configured to establish an electrical connection with the host computer to achieve power supply, grounding, I2C signal transmission, data signal transmission, etc.

[0059] Of course, flexible circuit boards are also used in some optical modules. Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement rigid circuit boards.

[0060] The light emitting component 400 and / or the light receiving component 500 are located on the side of the circuit board 300 away from the gold finger 301; in some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors; in some embodiments, the light emitting component and / or the light receiving component can be directly set on the circuit board 300, can be set on the surface of the circuit board, and can also be set on the side of the circuit board.

[0061] The first optical signal from the direction of the remote information processing device 1000 propagates through the optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted into the optical module 200. The optical module 200 converts the first optical signal into a first electrical signal. The optical module 200 transmits the first electrical signal into the host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal, and the host computer 100 transmits the fourth electrical signal to the local information processing device 2000.

[0062] In some embodiments, during a first time period, the optical receiving component 500 may receive a first optical signal and convert the first optical signal into a first electrical signal. During a second time period, the optical receiving component 500 may receive a second optical signal and convert the second optical signal into a second electrical signal. The optical power corresponding to the first optical signal is the first optical power; the optical power corresponding to the second optical signal is the second optical power. The first optical power and the second optical power are different.

[0063] In some embodiments, the first optical signal comes from a first optical network unit, and the second optical signal comes from a second optical network unit. A distance between the first optical network unit and the optical receiving component is different from a distance between the second optical network unit and the optical receiving component, resulting in the first optical power being different from the second optical power.

[0064] Figure 5 Schematic diagram of a light receiving component and circuit board structure provided according to some embodiments of the present disclosure. Figure 5 As shown, in some embodiments, the light receiving component may include: a photodetector 510, which converts the received light signal into an electrical signal.

[0065] The photodetector 510 may convert the first optical signal into a first electrical signal. The photodetector 510 may convert the second optical signal into a second electrical signal.

[0066] The light receiving component may include a first amplifier that amplifies the electrical signal output by the photodetector 510 , and the output signal is an amplified electrical signal.

[0067] The first amplifier may be a transimpedance amplifier, which amplifies the electrical signal output by the photodetector 510. The output signal is an amplified electrical signal. Due to the distance between the OLT and the ONU, signal loss may occur during the transmission of the optical signal from the ONU to the OLT, resulting in a bit error rate in the optical signal received by the OLT.

[0068] The optical receiving component may include an equalizer 530 , which may perform equalization compensation on the amplified electrical signal to reduce the bit error rate of the compensated electrical signal.

[0069] In some embodiments, the electrical signal output by the photodetector 510 may be a differential signal or a single-ended signal.

[0070] The optical receiving component may include a clock data recovery chip 310. The output end of the equalizer 530 may be connected to the input end of the clock data recovery chip 310. The output end of the clock data recovery chip 310 may be connected to a host computer.

[0071] The optical signal is converted into an electrical signal by the photodetector 510. The first amplifier amplifies the electrical signal and then outputs it to the clock data recovery chip 310 after equalization compensation by the equalizer 530. The equalizer 530 can equalize the electrical signal to reduce the bit error rate of the electrical signal and improve the communication quality.

[0072] Figure 6 This is a schematic diagram of the optical power and bit error rate curve of the optical receiving component in the OLT in the prior art. Figure 7 A schematic diagram of the structure of a light receiving component provided according to some embodiments of the present disclosure Figure 2 .like Figure 6 and Figure 7 As shown in FIG, when the optical power is different, the bit error rate of the optical receiving component is different.

[0073] The distance between the first optical network unit and the optical receiving component is different from the distance between the second optical network unit and the optical receiving component, the first optical power is different from the second optical power, and the bit error rate of the electrical signal converted from the optical signal is different. To optimize the signal-to-noise ratio of the electrical signal of the optical receiving component and improve signal stability, the optical receiving component may include an amplitude detector 540. Amplitude detector 540 is located between the equalizer 530 and the limiting amplifier and detects the amplitude of the amplified electrical signal output by the first amplifier.

[0074] In some embodiments, the input end of the amplitude detector 540 may be connected to the output end of the first amplifier, and the amplitude value of the amplified electrical signal output by the first amplifier is detected by the amplitude detector 540 .

[0075] The first output terminal of the amplitude detector 540 can be connected to the input terminal of the compensation controller 550 , and the first output terminal outputs the amplitude value of the amplified electrical signal.

[0076] The second output terminal of the amplitude detector 540 can be connected to the input terminal of the equalizer 530, and the second output terminal outputs the amplified electrical signal.

[0077] The output terminal of the compensation controller 550 may be connected to the equalizer 530, and the compensation controller 550 may output a control signal to the equalizer 530. In some embodiments, the equalizer 530 may receive the control signal output by the compensation controller 550 and perform equalization compensation on the electrical signal according to the control signal.

[0078] In some embodiments, the first input end of the equalizer 530 can be connected to the output end of the compensation controller 550, the second input end of the equalizer 530 can be connected to the second output end of the amplitude detector 540, and the output end of the equalizer 530 can be connected to the input end of the clock data recovery chip.

[0079] In some embodiments, the compensation controller 550 may output different equalization compensation values ​​to the equalizer 530 according to the amplitude value output by the amplitude detector 540 .

[0080] Figure 8 Schematic diagram of a first compensation table provided according to some embodiments Figure 1 .like Figure 8 As shown, a first compensation table may be set in the compensation controller 550, wherein the first compensation table is a correspondence table between voltage amplitude values ​​and equalization compensation values.

[0081] The voltage amplitude value may include a first lower limit value. The equalization compensation value may include: a first compensation value and a second compensation value. The first compensation value and the second compensation value are different. The first compensation table can be interpreted as follows: when the voltage amplitude value is less than the first lower limit value, the equalization compensation value output by the compensation controller 550 is the first compensation value; when the voltage amplitude value is greater than or equal to the first lower limit value, the equalization compensation value output by the compensation controller 550 is the second compensation value.

[0082] In some embodiments, the voltage amplitude value may include a first lower limit value and a first upper limit value. The equalization compensation value may include: a first compensation value, a second compensation value, and a third compensation value. The first compensation value, the second compensation value, and the third compensation value are different.

[0083] In some embodiments, the voltage amplitude value is calculated by applying the amplitude value output by the amplitude detector 540 to a preset algorithm. The compensation controller 550 pre-stores a first amplitude limit value and a second amplitude limit value.

[0084] In some embodiments of the present application, the amplitude detector may be an operational amplifier.

[0085] In some embodiments the first amplitude limit is greater than the second amplitude limit.

[0086] For ease of description, the voltage amplitude value can be denoted as V; the first amplitude limit value can be denoted as V1; and the second amplitude limit value can be denoted as V2. The first amplitude limit value is the amplitude value corresponding to the amplitude detector 540 when the optical power input to the photodetector 510 is at the limit optical power. The limit optical power can be +1 dB of the overload optical power. The second amplitude limit value is the amplitude value corresponding to the amplitude detector 540 when the optical power input to the photodetector 510 is at an extremely low optical power. The limit optical power can be -2 dB of the sensitivity of the photodetector 510.

[0087] The default algorithm for voltage limit is: V = 10*log(V1-V2)(1)

[0088] In formula (1), the voltage limit can be recorded as V; the first amplitude limit can be recorded as V1; and the second amplitude limit can be recorded as V2.

[0089] In some embodiments, the preset algorithm for the preset voltage amplitude value may be: V = 10*log(V1) (2)

[0090] In formula (2), the voltage limit can be recorded as V, the first amplitude limit can be recorded as V1, and the ratio of the current amplitude value to the voltage limit can be recorded as the voltage amplitude value.

[0091] like Figure 8 As shown, the first compensation table can be interpreted as follows: when the voltage amplitude is less than the first lower limit, the equalization compensation value output by compensation controller 550 is the first compensation value EQ1; when the voltage amplitude is greater than or equal to the first lower limit and less than the first upper limit, the equalization compensation value output by compensation controller 550 is the second compensation value EQ2; and when the voltage amplitude is greater than or equal to the first upper limit, the equalization compensation value output by compensation controller 550 is the third compensation value EQ3. The equalization compensation values ​​output by compensation controller 550 vary depending on the voltage amplitude, facilitating adjustment of the equalizer based on the bit error rate of the electrical signal, improving equalization performance, and enhancing communication quality.

[0092] Figure 9 Schematic diagram of a first compensation table provided according to some embodiments Figure 2 .like Figure 9 As shown, the first amplitude limit may be 0.4 and the second amplitude limit may be 0.7. In some embodiments, the first amplitude limit may be 0.3 and the second amplitude limit may be 0.8; or in some embodiments, the first amplitude limit may be 0.4 and the second amplitude limit may be 0.8.

[0093] When the optical receiving component receives an optical signal sent by an ONU at the same location, the signal amplitude will also vary. For example, if the data carried in the optical signal is a CID pattern, with 72 consecutive zeros, the amplitude value will be reduced. In other words, the optical signal of a data packet sent by an ONU at the same location will also cause the voltage amplitude value output by amplitude detector 540 to vary. If this voltage amplitude value fluctuates around the first amplitude limit, the control signal output by compensation controller 550 will continue to vary.

[0094] For example, the first lower limit is 0.4. When the voltage amplitude changes from 0.41 to 0.38, the control signal output by compensation controller 550 changes from the second compensation value to the first compensation value. When the data returns to a non-zero bit, the voltage amplitude may return to 0.41. According to the first compensation table, the control signal output by compensation controller 550 changes from the first compensation value to the second compensation value. If the control signal output by compensation controller 550 continuously jumps during the transmission of a data packet from an ONU at the same location, this may cause signal fluctuations.

[0095] Figure 10 Schematic diagram of a second compensation table provided according to some embodiments Figure 1 .like Figure 10 As shown, the compensation controller 550 may include a second compensation table and a first compensation table. The second compensation table is a table that maps voltage amplitude values ​​to equalization compensation values. The voltage amplitude values ​​in the second compensation table may include a second lower limit value. The equalization compensation values ​​may include a first compensation value and a second compensation value. The first compensation value and the second compensation value are different. The first lower limit value is greater than the second lower limit value.

[0096] The compensation controller 550 can be configured to obtain a current voltage amplitude value and a previous voltage amplitude value. When the current voltage amplitude value is greater than or equal to the previous voltage amplitude value (low light in front, high light in the back), the control signal is output according to the current voltage amplitude value and the first compensation table. When the current voltage amplitude value is less than the previous voltage amplitude value (high light in front, low light in the back), the control signal is output according to the current voltage amplitude value and the second compensation table. The first lower limit value is greater than the second lower limit value.

[0097] The compensation controller 550 may be configured such that: when the current voltage amplitude value is greater than or equal to the previous voltage amplitude value (small light in front, large light in the back), and the current voltage amplitude value is less than the first lower limit value, the compensation controller 550 outputs a first compensation value as the equalization compensation value;

[0098] The current voltage amplitude value is greater than or equal to the previous voltage amplitude value (small light in front, large light in the back), and when the current voltage amplitude value is greater than or equal to the first lower limit value, the equalization compensation value output by the compensation controller 550 is the second compensation value.

[0099] The current voltage amplitude value is smaller than the previous voltage amplitude value (large light is in front, small light is in the back), and when the current voltage amplitude value is smaller than the second lower limit value, the compensation controller 550 outputs the equalization compensation value as the first compensation value;

[0100] When the current voltage amplitude value is smaller than the previous voltage amplitude value (large light in front, small light in the back) and the current voltage amplitude value is greater than or equal to the second lower limit value, the equalization compensation value output by the compensation controller 550 is the second compensation value.

[0101] In some embodiments, the first lower limit value is greater than the second lower limit value. When the voltage amplitude value output by the amplitude detector 540 changes from less than the first lower limit value to greater than or equal to the first lower limit value, according to the first compensation table, the current voltage amplitude value is greater than or equal to the first lower limit value, and the control signal output by the compensation controller 550 is converted from the first compensation value to the second compensation value; when the voltage amplitude value output by the amplitude detector 540 changes from greater than or equal to the first lower limit value to less than the first lower limit value, but the current voltage amplitude value is greater than or equal to the second lower limit value, according to the second compensation table, the current voltage amplitude value is not less than the second lower limit value, and the control signal output by the compensation controller 550 maintains the second compensation value unchanged, thereby increasing the hysteresis space and avoiding signal fluctuations caused by frequent switching.

[0102] For example, when the first lower limit value is 0.4 and the second lower limit value is 0.3, when the voltage amplitude value output by the amplitude detector 540 changes from 0.38 to 0.41, according to the first compensation table, the current voltage amplitude value is greater than the first lower limit value, and the control signal output by the compensation controller 550 is converted from the first compensation value to the second compensation value; when the voltage amplitude value output by the amplitude detector 540 changes from 0.41 to 0.3, according to the second compensation table, the current voltage amplitude value is not less than the second lower limit value, and the control signal output by the compensation controller 550 maintains the second compensation value unchanged, thereby increasing the hysteresis space and avoiding frequent switching of the optical receiving component when receiving the ONU signal at the same position, resulting in signal fluctuations.

[0103] In some embodiments, the voltage amplitude values ​​in the second compensation table may include a second lower limit value; the voltage amplitude values ​​in the second compensation table may include a second upper limit value. The equalization compensation values ​​may include: a first compensation value, a second compensation value, and a third compensation value. The first compensation value, the second compensation value, and the third compensation value are different. The second lower limit value may be less than the first upper limit value, and the second upper limit value may be less than the first upper limit value.

[0104] In some embodiments, the second lower limit value is smaller than the first upper limit value, and the second upper limit value is larger than the first lower limit value.

[0105] For example, when the first upper limit value is 0.8 and the second upper limit value is 0.7, when the voltage amplitude value output by the amplitude detector 540 changes from 0.78 to 0.81, according to the first compensation table, the current voltage amplitude value is greater than the first upper limit value, and the control signal output by the compensation controller 550 is changed from the second compensation value to the third compensation value; when the voltage amplitude value output by the amplitude detector 540 changes from 0.81 to 0.78, according to the second compensation table, the current voltage amplitude value is not less than the second upper limit value, and the control signal output by the compensation controller 550 maintains the third compensation value unchanged, thereby increasing the hysteresis space and avoiding frequent switching of the optical receiving component when receiving the ONU signal at the same position, resulting in signal fluctuations.

[0106] By setting the first compensation table and the second compensation table, the present application can avoid signal fluctuations caused by frequent switching of the optical receiving component when receiving ONU signals at the same position, thereby improving communication stability.

[0107] In some embodiments of the present application, the first compensation table can be set to a 2-stage type; the first compensation table can be set to a 3-stage type, and the first compensation table can be set to a multi-stage type. The specific settings can be made according to actual needs and will not be repeated here.

[0108] In some embodiments of the present application, the second compensation table can be set to a 2-stage type; the second compensation table can be set to a 3-stage type, and the second compensation table can be set to a multi-stage type. The specific settings can be made according to actual needs and will not be repeated here.

[0109] In some embodiments, the photodetector 510 converts the received optical signal into an electrical signal, which is then amplified by a transimpedance amplifier. The equalizer 530 can be configured to perform equalization compensation on the amplified electrical signal based on the equalization compensation value output by the compensation controller 550. The amplitude detector 540 detects the amplitude of the amplified electrical signal and outputs the amplitude value to the compensation controller 550. The compensation controller 550 outputs the equalization compensation value to the control equalizer 530 based on a preset compensation table, thereby controlling the equalizer 530 to perform equalization compensation on the amplified electrical signal and reduce the bit error rate of the signal. The compensation controller 550 is configured to calculate a voltage amplitude value based on the amplitude value. A first compensation table and a second compensation table are preset. When the current voltage amplitude value is greater than or equal to the previous voltage amplitude value, the control signal is output based on the current voltage amplitude value and the first compensation table. When the current voltage amplitude value is less than the previous voltage amplitude value, the control signal is output based on the current voltage amplitude value and the second compensation table. The first lower limit value is greater than the second lower limit value. This configuration increases the hysteresis margin of the amplitude switching point, preventing signal fluctuations caused by frequent switching.

[0110] In some embodiments, the first compensation table may include: the voltage amplitude value may include a first lower limit value; the equalization compensation value may include: a first compensation value and a second compensation value; wherein the first compensation value and the second compensation value are different. The compensation controller 550 is configured such that: when the current voltage amplitude value is less than the first lower limit value, the equalization compensation value output by the compensation controller 550 is the first compensation value; when the voltage amplitude value is greater than or equal to the first lower limit value, the equalization compensation value output by the compensation controller 550 is the second compensation value.

[0111] The voltage amplitude values ​​in the second compensation table may include a second lower limit value. The equalization compensation values ​​may include: a first compensation value and a second compensation value. The first compensation value and the second compensation value are different. The first lower limit value is greater than the second lower limit value.

[0112] The compensation controller 550 may be configured such that: when the current voltage amplitude value is greater than or equal to the previous voltage amplitude value (small light in front, large light in the back), and the current voltage amplitude value is less than the first lower limit value, the compensation controller 550 outputs a first compensation value as the equalization compensation value;

[0113] The current voltage amplitude value is greater than or equal to the previous voltage amplitude value (small light in front, large light in the back), and when the current voltage amplitude value is greater than or equal to the first lower limit value, the equalization compensation value output by the compensation controller 550 is the second compensation value.

[0114] The current voltage amplitude value is smaller than the previous voltage amplitude value (large light is in front, small light is in the back), and when the current voltage amplitude value is smaller than the second lower limit value, the compensation controller 550 outputs the equalization compensation value as the first compensation value;

[0115] When the current voltage amplitude value is smaller than the voltage amplitude value (large light in front, small light in the back) and the current voltage amplitude value is greater than or equal to the second lower limit value, the equalization compensation value output by the compensation controller 550 is the second compensation value.

[0116] In some embodiments, the compensation controller may include a preset compensation table, which may be a correspondence table between voltage amplitude values ​​and equalization compensation values; or a correspondence table between amplitude values ​​and equalization compensation values.

[0117] In some embodiments, the preset compensation table may include: a first voltage value, a first compensation value, and a second compensation value. When the current amplitude value is less than the first voltage value, the equalization compensation value output by the compensation controller 550 is the first compensation value; when the current amplitude value is greater than the first voltage value, the equalization compensation value output by the compensation controller 550 is the second compensation value.

[0118] In some embodiments, the preset compensation table may be a first compensation table. The preset compensation table may be a second compensation table. The preset compensation table may be a first compensation table and a second compensation table.

[0119] In some embodiments, the optical module may include a clock data recovery chip, and the transimpedance amplifier may be disposed between the equalizer and the clock data recovery chip.

[0120] In some embodiments, the optical module may include a limiting amplifier, and the limiting amplifier may be located between the equalizer and the clock data recovery chip.

[0121] Since the above embodiments are all described by reference in combination with other embodiments, different embodiments have the same parts, and the same and similar parts between the various embodiments in this specification can be referred to each other. No further detailed explanation is given here.

Claims

1. A light receiving component, characterized in that include: a photodetector configured to convert signal light into an electrical signal; an amplitude detector, whose input end is connected to the output end of the photodetector, and the amplitude detector is configured to detect the amplitude value of the amplified electrical signal; a compensation controller, whose input terminal is connected to the first output terminal of the amplitude detector, the compensation controller being configured to calculate a current voltage amplitude value according to the amplitude value, and output a balanced compensation value according to the current voltage amplitude value, the previous voltage amplitude value, the first compensation table, and the second compensation table; an equalizer, wherein a first input terminal is connected to the second output terminal of the amplitude detector, a second input terminal is connected to the output terminal of the compensation controller, and the equalizer is configured to perform equalization compensation on the electrical signal according to the equalization compensation value; The compensation controller is configured to: when the current voltage amplitude value is greater than or equal to the previous voltage amplitude value, output a balanced compensation value according to the first compensation table; When the current voltage amplitude value is smaller than the previous voltage amplitude value, the equalization compensation value is output according to the second compensation table.

2. The light receiving element according to claim 1, wherein The first compensation table includes: a first lower limit value, a first compensation value, and a second compensation value; The second compensation table includes: a second lower limit value, a first compensation value, and a second compensation value; wherein the first lower limit value is greater than the second lower limit value; The compensation controller is configured to: when the current voltage amplitude value is greater than or equal to the previous voltage amplitude value and the current voltage amplitude value is less than a first lower limit value, the output of the compensation controller is a first compensation value; When the current voltage amplitude value is greater than or equal to the previous voltage amplitude value and the current voltage amplitude value is greater than or equal to the first lower limit value, the output of the compensation controller is the second compensation value; When the current voltage amplitude value is smaller than the previous voltage amplitude value and the current voltage amplitude value is smaller than the second lower limit value, the output of the compensation controller is the first compensation value; When the current voltage amplitude value is smaller than the previous voltage amplitude value and the voltage amplitude value is greater than or equal to a second lower limit value, the output of the compensation controller is a second compensation value.

3. The light receiving element according to claim 1, wherein include: A transimpedance amplifier is located between the amplitude detector and the photodetector.

4. The light receiving element according to claim 1, wherein The calculating of the current voltage amplitude value according to the amplitude value includes: recording the ratio of the current amplitude value to the voltage limit value as the voltage amplitude value; The voltage limit is a preset value.

5. A light receiving component, characterized in that include: a photodetector configured to convert signal light into an electrical signal; an amplitude detector, an input terminal of which is connected to the output terminal of the photodetector, and the amplitude detector is configured to detect an amplitude value of the electrical signal; a compensation controller, an input end of which is connected to the first output end of the amplitude detector, the compensation controller being configured to output an equalization compensation value according to the amplitude value and a preset compensation table; An equalizer, wherein a first input terminal is connected to the second output terminal of the amplitude detector, and a second input terminal is connected to the output terminal of the compensation controller. The equalizer is configured to perform equalization compensation on the electrical signal according to the equalization compensation value.

6. The light receiving element according to claim 5, wherein include: A transimpedance amplifier is located between the amplitude detector and the photodetector.

7. The light receiving element according to claim 5 or 6, characterized in that The compensation controller is configured to: Calculating a voltage limit value according to the first amplitude limit value and the second amplitude limit value; Calculate the ratio of the amplitude value to the voltage limit value, and record it as the voltage amplitude value; outputting a balanced compensation value according to the voltage amplitude value and a first compensation table; The first compensation table is a correspondence table between voltage amplitude values ​​and equalization compensation values.

8. The light receiving element according to claim 7, wherein The first compensation table includes: a first lower limit value, a first compensation value, and a second compensation value; The compensation controller is configured to: when the voltage amplitude value is less than a first lower limit value, the output of the compensation controller is a first compensation value; When the voltage amplitude value is greater than the first lower limit value, the output of the compensation controller is a second compensation value.

9. An optical module, characterized in that: The light receiving component comprises the light receiving component according to any one of claims 1 to 8.

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