Shared network card, shared network card control method, device and electronic equipment

Abstract

The present application discloses a shared network card and a control method, device and electronic device for the shared network card, and relates to the field of computer technology. Through the present application, an integrated processing unit chip is connected to multiple storage controllers to form a joint architecture, so that multiple storage controllers can realize data interaction and load distribution through a direct memory access engine inside a unified integrated processing unit. Therefore, it can solve the problems of high load bottlenecks of some controllers and low overall resource utilization caused by the independent configuration of physical network cards and lack of coordination of each storage controller in the existing multi-controller storage system, thereby achieving the technical effect of improving the load balancing capability and resource utilization of the storage system.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a shared network card system, control method, device and electronic equipment. Background Art

[0002] In modern storage systems, multi-controller architectures have become mainstream to enhance system redundancy and availability. Currently, storage controllers typically provide Network Attached Storage (NAS) services through independent network adapters (NICs). Their technology encompasses the entire process, from data transmission and I / O scheduling to failover.

[0003] However, in existing multi-controller storage systems, each storage controller is usually configured with an independent physical network card without a load balancing strategy. Some storage controllers may become performance bottlenecks due to high load, while other storage controllers are in an inefficient operating state, affecting overall resource utilization. Summary of the Invention

[0004] The present application provides a shared network card and a control method, device and electronic device for the shared network card, so as to at least solve the problem in the related art that some storage controllers may become performance bottlenecks due to high load, while other storage controllers are in an inefficient operating state, affecting the overall resource utilization.

[0005] The present application provides a shared network card, comprising: an integrated processing unit chip, the integrated processing unit chip including a first Ethernet controller, a plurality of peripheral component interconnect express ports, and a direct memory access engine, the first Ethernet controller being connected to the direct memory access engine; the direct memory access engine being linked to a plurality of storage controllers via the peripheral component interconnect express ports and a high-density connector, wherein one peripheral component interconnect express port is connected to one storage controller via one high-density connector; a pluggable module, the pluggable module being connected to the first Ethernet controller;

[0006] The pluggable module is configured to send the data to be stored from the external server to the first Ethernet controller;

[0007] The first Ethernet controller is configured to send the data to be stored to the direct memory access engine;

[0008] The direct memory access engine is configured to perform load balancing on the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller.

[0009] Optionally, the shared network card further includes a double data rate memory;

[0010] The first Ethernet controller is connected to the direct memory access engine through the double data rate memory.

[0011] Optionally, the integrated processing unit chip further includes a second Ethernet controller; the second Ethernet controller is connected to the plurality of storage controllers by heartbeat via the peripheral component interconnect express port;

[0012] The second Ethernet controller is configured to synchronize status information of each storage controller in real time.

[0013] Optionally, the integrated processing unit chip further includes a control module; the control module is connected to the second Ethernet controller;

[0014] The control module is configured to detect whether the storage controller is faulty based on the status information, and when a fault is detected in any of the storage controllers, automatically direct the data packets corresponding to the faulty controller to the remaining normal target storage controllers.

[0015] Optionally, detecting whether the storage controller is faulty according to the status information includes:

[0016] The control module periodically receives a heartbeat message sent by the storage controller through the second Ethernet controller;

[0017] If no heartbeat message is received for a predetermined number of consecutive times, it is determined that the storage controller is faulty.

[0018] Optionally, automatically redirecting data packets corresponding to the faulty controller to other normal storage controllers includes:

[0019] The control module updates the physical address mapping of the target storage controller through a hardware routing table inside the integrated processing unit chip.

[0020] Optionally, the control module is further configured to send the data unloaded from the integrated processing unit chip to the double data rate memory to the corresponding storage controller through the direct memory access engine.

[0021] Optionally, the shared network card further includes:

[0022] a pluggable module configured to send data to be stored from an external server to the first Ethernet controller;

[0023] The first Ethernet controller is configured to send the data to be stored to the double data rate memory;

[0024] The double data rate memory is configured to send the data to be stored to a direct memory access engine;

[0025] The direct memory access engine is configured to perform load balancing on the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller.

[0026] The present application provides a method for controlling a shared network card, which is applied to the shared network card described in the above aspect, including:

[0027] Get the data to be stored sent by the external server;

[0028] According to the current load conditions of each storage controller, the data to be stored is load balanced and distributed, and the data to be stored is migrated to the corresponding storage controller.

[0029] Optionally, after migrating the data to be stored to the corresponding storage controller, the method further includes:

[0030] Regularly receiving heartbeat messages sent by the storage controller;

[0031] If no heartbeat message is received for a predetermined number of consecutive times, it is determined that the storage controller is faulty;

[0032] When a failure of any of the storage controllers is detected, the to-be-stored data corresponding to the failed controller is automatically directed to the remaining normal target storage controllers.

[0033] Optionally, the load balancing distribution of the data to be stored according to the current load of each storage controller and migrating the data to be stored to the corresponding storage controller includes:

[0034] The direct memory access engine manages the address, length and transmission status of data transmission based on the symbol ring.

[0035] The present application further provides a control device for a shared network card, which is applied to the shared network card described in the above aspect, including:

[0036] An acquisition unit, used for acquiring data to be stored sent by an external server;

[0037] The migration unit is used to perform load balancing on the data to be stored according to the current load conditions of each storage controller, and migrate the data to be stored to the corresponding storage controller.

[0038] Optionally, the device further includes:

[0039] a receiving unit, configured to periodically receive a heartbeat message sent by the storage controller after the migration unit migrates the data to be stored to the corresponding storage controller;

[0040] a determining unit, configured to determine that the storage controller is faulty when no heartbeat message is received for a predetermined number of consecutive times;

[0041] The migration unit is further configured to automatically direct the to-be-stored data corresponding to the failed controller to the remaining normal target storage controllers when a failure of any of the storage controllers is detected.

[0042] Optionally, the migration unit performs load balancing on the data to be stored according to the current load of each storage controller, and migrates the data to be stored to the corresponding storage controller, and is further configured to:

[0043] The direct memory access engine manages the address, length and transmission status of data transmission based on the symbol ring.

[0044] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned methods for controlling a shared network card when executing the computer program.

[0045] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for controlling a shared network card are implemented.

[0046] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned shared network card control methods when executed by a processor.

[0047] Through this application, since the integrated processing unit chip is connected to multiple storage controllers to form a joint architecture, multiple storage controllers can realize data interaction and load distribution through the direct memory access engine inside the unified integrated processing unit. Therefore, it can solve the problems of high load bottlenecks and low overall resource utilization of some controllers caused by the independent configuration of physical network cards and lack of coordination of each storage controller in the existing multi-controller storage system, and achieve the technical effect of improving the load balancing capability and resource utilization of the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0049] Figure 1 A schematic diagram of a shared network card structure provided in an embodiment of the present application;

[0050] Figure 2A schematic diagram of another shared network card structure provided in an embodiment of the present application;

[0051] Figure 3 A flow chart of a method for controlling a shared network card provided by an embodiment of the present disclosure;

[0052] Figure 4 A schematic diagram of a management service flow of a shared network card provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of the structure of a control device for a shared network card provided in an embodiment of the present application;

[0054] Figure 6 A schematic structural diagram of another shared network card control device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0057] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0058] The embodiment of the present application provides a shared network card, and the shared network card is described in detail in conjunction with the structural diagram of the shared network card. Figure 1 , Figure 1 A schematic diagram of a shared network card structure provided in an embodiment of the present application is shown as follows: Figure 1As shown, it includes: an integrated processing unit chip, the integrated processing unit chip includes a first Ethernet controller, multiple peripheral component interconnect express ports and a direct memory access engine (Direct Memory Access, DMA), the first Ethernet controller is connected to the direct memory access engine; the direct memory access engine is linked to multiple memory controllers through the peripheral component interconnect express ports and high-density connectors, one peripheral component interconnect express port is connected to one memory controller through one high-density connector; a pluggable module, the pluggable module is connected to the first Ethernet controller;

[0059] The pluggable module is configured to send the data to be stored from the external server to the first Ethernet controller;

[0060] The first Ethernet controller is configured to send the data to be stored to the direct memory access engine;

[0061] The direct memory access engine is configured to perform load balancing on the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller.

[0062] The Integrated Processing Unit (IPU) is an infrastructure processing unit, a programmable network device that can intelligently manage data center system-level infrastructure resources through security acceleration functions, support fully virtualized storage and network architectures, and maintain high performance, predictability, and a high degree of control. As the core processing unit, the IPU chip integrates the first Ethernet controller, multiple Peripheral Component Interconnect Express (PCIe) ports (a high-speed computer expansion bus standard that supports high throughput and low latency, is compatible with multiple versions such as PCIe 3.0 / 4.0 / 5.0, and can achieve a single-channel transmission rate of over 32GT / s), and a direct memory access engine (DMA engine). It can directly move data through a multi-channel zero-copy transmission mechanism, bypassing the CPU and system memory bottleneck. The first Ethernet controller and the DMA engine are connected to ensure efficient data transmission between the two.

[0063] Please continue reading Figure 1The direct memory access engine ensures the reliability of the physical connection between the PCIe port and the storage controller through the Peripheral Component Interconnect Express port and a high-density connector, establishing links with multiple storage controllers. Each Peripheral Component Interconnect Express port is connected to a corresponding storage controller through a high-density connector. This one-to-one connection method ensures the independence and stability of data transmission between each storage controller and the IPU, avoiding mutual interference. A pluggable module (such as a Quad Small Form-factor Pluggable (QSFP), a high-density pluggable optical module connector that supports high-speed data transmission and adapts to data center network environments) is connected to the first Ethernet controller, which is configured to receive data to be stored sent by an external server and pass the data to the first Ethernet controller. The first Ethernet controller, as a hardware module responsible for data link layer and physical layer functions, sends the data to be stored to the direct memory access engine after receiving it.

[0064] The direct memory access engine is configured to balance the load distribution and migration of data. It monitors the current load of each storage controller in real time through hardware-accelerated traffic classification and dynamic scheduling algorithms (such as the minimum connection number algorithm), and then intelligently allocates the received data to be stored, ensuring that the data can be reasonably migrated to the corresponding storage controller based on the load capacity of each storage controller, thereby optimizing resource utilization and improving the performance and data transmission efficiency of the entire storage system.

[0065] In some embodiments, the shared network card further comprises a double data rate memory;

[0066] The first Ethernet controller is connected to the direct memory access engine through the double data rate memory.

[0067] Double Data Rate (DDR) is a high-performance synchronous dynamic random access memory technology that achieves double the bandwidth of traditional SDRAM by transmitting data on both the rising and falling edges of each clock cycle. It has higher storage density, lower power consumption, and better channel efficiency.

[0068] The first Ethernet controller transfers data between the two through the double data rate memory. That is, after receiving the data to be stored transmitted by the pluggable module, the first Ethernet controller temporarily stores the data in the double data rate memory. Then, the direct memory access engine reads the data to be stored from the double data rate memory, and performs load balancing distribution according to the current load of each storage controller, and finally migrates the data to the corresponding storage controller.

[0069] This connection method using double data rate memory can utilize the high bandwidth and low latency characteristics of DDR as a data buffer, effectively alleviating the data transmission pressure between the first Ethernet controller and the direct memory access engine, avoiding transmission congestion caused by excessive instantaneous data traffic, and at the same time providing sufficient time windows for the load balancing distribution process of the direct memory access engine, ensuring the rationality and accuracy of data distribution, thereby improving the data processing efficiency and stability of the entire shared network card solution.

[0070] In some embodiments, the integrated processing unit chip further includes a second Ethernet controller; the second Ethernet controller is connected to the plurality of storage controllers via the PCI Express port by heartbeat;

[0071] The second Ethernet controller is configured to synchronize status information of each storage controller in real time.

[0072] See also Figure 2 , Figure 2 Schematic diagram of another shared network card structure provided in an embodiment of the present application; the second Ethernet controller corresponds to the Management Ethernet Controller (MEC), which is an independent Ethernet control module dedicated to device management and monitoring, and is usually separated from the business data network where the first Ethernet controller responsible for data transmission is located to improve the reliability and security of the system.

[0073] The second Ethernet controller establishes a heartbeat connection with multiple storage controllers via the PCIe port on the integrated processing unit chip. This heartbeat connection is a continuous, low-frequency communication mechanism that periodically sends and receives heartbeat messages to enable status exchange between the second Ethernet controller and each storage controller.

[0074] The core function of the second Ethernet controller is to synchronize the status of each storage controller in real time, including operational status, load, and fault conditions. This real-time status information is transmitted to relevant modules within the IPU, providing accurate status information for subsequent operations such as controller fault handling and load balancing, ensuring efficient and stable operation and management of the entire storage system based on the real-time status of each controller.

[0075] In some embodiments, the integrated processing unit chip further includes a control module; the control module is connected to the second Ethernet controller;

[0076] The control module is configured to detect whether the storage controller is faulty based on the status information, and when a fault is detected in any of the storage controllers, automatically direct the data packets corresponding to the faulty controller to the remaining normal target storage controllers.

[0077] The control module is the core functional module responsible for fault detection and service migration within the IPU. It establishes a heartbeat connection with the second Ethernet controller and the storage controller through the PCIe port, so that it can directly obtain the status information of each storage controller synchronized in real time by the second Ethernet controller.

[0078] The core function of the control module is configured to detect whether the storage controller has failed based on the above status information, and its detection basis is mainly based on the response of the heartbeat message transmitted by the second Ethernet controller; when the second Ethernet controller and the storage controller periodically exchange heartbeat messages through the heartbeat connection, if the control module detects that a storage controller has no heartbeat message response for a long time, it is determined that the storage controller has failed.

[0079] When a storage controller failure is detected, the control module will activate the preset fault handling mechanism and automatically redirect the data packets that should have been sent to the faulty controller to the remaining normally operating target storage controllers. The entire process achieves seamless business migration at the millisecond level, and the failover process is completely transparent to external servers. The server does not need to be aware of the failure and switching operations, thereby ensuring the continuity and stability of the storage service and avoiding business interruptions caused by a single controller failure.

[0080] In some embodiments, detecting whether the storage controller is faulty according to the status information includes:

[0081] The control module periodically receives a heartbeat message sent by the storage controller through the second Ethernet controller;

[0082] If no heartbeat message is received for a predetermined number of consecutive times, it is determined that the storage controller is faulty.

[0083] Periodic reception refers to the interaction of heartbeat messages at preset time intervals, such as a cycle of two seconds, to ensure that the control module can grasp the operating status of each storage controller in real time; the heartbeat message is a periodic signal that the storage controller feeds back to the IPU to indicate its normal operation, containing key status data such as the controller's current load and health status.

[0084] To avoid misjudgments caused by occasional network fluctuations, message loss, and other occasional events, a predetermined number of consecutive reception cycles is set as the detection condition. If a storage controller fails to receive heartbeat messages within multiple, periodic reception cycles (e.g., three or five consecutive times, the specific number can be preset based on system stability requirements), the control module will determine that the storage controller has failed. This judgment mechanism based on multiple consecutive message failures effectively filters out interference factors, improves fault detection accuracy, and provides a reliable basis for automatically redirecting data packets corresponding to the faulty controller to other healthy target storage controllers, ensuring the stable operation of storage services.

[0085] In some embodiments, automatically redirecting data packets corresponding to the failed controller to other normal storage controllers includes:

[0086] The control module updates the physical address mapping of the target storage controller through a hardware routing table inside the integrated processing unit chip.

[0087] The hardware routing table is a hardware-level data structure inside the IPU used to store and manage the correspondence between network addresses and physical devices. It has high-speed search and update capabilities and can support microsecond-level address mapping adjustments. The physical addresses it stores include key identification information such as the MAC address of the storage controller and the PCIe port address, which are used to accurately locate the receiving target of the data packet.

[0088] When the control module determines that a storage controller has failed, it will immediately trigger the update operation of the hardware routing table, and modify the physical address mapping entry originally pointing to the failed controller to point to the physical address of the remaining normally operating target storage controller. In this way, subsequent data packets that should have been sent to the failed controller can be automatically matched to the correct target storage controller according to the updated hardware routing table when passing through the IPU internal data processing flow, thereby realizing seamless redirection of data packets. The entire process relies on the hardware acceleration characteristics of the IPU to ensure that the redirection operation is efficient and does not affect the overall data transmission performance, thereby ensuring the continuity of storage services.

[0089] In some embodiments, the control module is further configured to send the data offloaded from the integrated processing unit chip to the double data rate memory to the corresponding memory controller through the direct memory access engine.

[0090] After receiving external data, the IPU will temporarily store the data in the DDR through the hardware offload function. At this time, the control module will send instructions to the DMA engine based on the real-time status of each storage controller, such as load conditions and whether it is operating normally, instructing it to read the corresponding data from the DDR and accurately transmit the data to the corresponding storage controller through the PCIe port connected to the target storage controller.

[0091] During this process, the control module is responsible for coordinating the data distribution logic. The DMA engine, with its zero-copy feature and independent channel design, ensures efficient data transmission without occupying CPU resources. DDR acts as a data buffer pool to ensure the stability of data storage. The three work together to achieve efficient and accurate data transmission from the IPU to the storage controller, further improving the data processing efficiency and system response speed of the entire shared network card solution.

[0092] Optionally, the shared network card further includes:

[0093] a pluggable module configured to send data to be stored from an external server to the first Ethernet controller;

[0094] The first Ethernet controller is configured to send the data to be stored to the double data rate memory;

[0095] The double data rate memory is configured to send the data to be stored to a direct memory access engine;

[0096] The direct memory access engine is configured to perform load balancing on the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller.

[0097] For the specific implementation method, please refer to the description of the above-mentioned application embodiment, and the present application embodiment will not go into details about it.

[0098] An embodiment of the present application provides a method for controlling a shared network card. The method is described in detail in conjunction with the execution flow of the method for controlling a shared network card. Figure 3 A flow chart of a control method for a shared network card provided in an embodiment of the present application is applied to the shared network card described in the aforementioned aspect, such as Figure 3 As shown, the method comprises the following steps:

[0099] Step 101: Acquire data to be stored sent by an external server.

[0100] Please continue reading Figure 2 , the external server establishes a connection with the QSFP of the shared network card through the network. As a high-speed data interface, QSFP supports high-bandwidth data transmission and can transmit the data to be stored sent by the server to the first Ethernet controller inside the shared network card.

[0101] The first Ethernet controller, the core module responsible for data flow processing in the shared network card, operates in target-side mode, primarily receiving and processing external network data. When data to be stored is transmitted to the first Ethernet controller via the QSFP module, it processes the data, including frame decapsulation, CRC check, MAC address identification, and flow control.

[0102] Step 102 : load-balance the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller.

[0103] The data to be stored after being processed by the first Ethernet controller will be transmitted to the DMA engine through a preset internal data path. The data will be temporarily stored in the DDR and then read from the DDR by the DMA engine to match the rhythm of data processing and transmission and avoid data blocking.

[0104] The Direct Memory Access Engine, the core module for direct data transfer between the controller and the network card, determines the transmission strategy based on the current load of each storage controller. This process relies on the IPU's real-time perception of the storage controller status and hardware-accelerated scheduling capabilities. Specifically, the IPU synchronizes the status information of each storage controller in real time through the management network, including but not limited to the current workload, data processing rate, idle resource ratio, and other load data of each controller. This information is then passed to the DMA engine as the basis for determining the transmission strategy.

[0105] Based on the load of each storage controller, the DMA engine makes decisions with the help of dynamic scheduling algorithms such as the minimum connection number algorithm and the consistent hashing algorithm: when a storage controller has a low load, such as when there are sufficient free resources, the DMA engine will prioritize allocating the data to be stored to the DMA channel corresponding to the controller; if some controllers have a high load, such as a long task queue, the transmission order will be adjusted to direct the data to the controller with a more balanced load, so as to avoid data processing delays caused by overload of a single controller. At the same time, the priority scheduler of the DMA engine will dynamically adjust the transmission order based on load balancing, combining the priority of the data to be stored, such as high-priority I / O requests, to ensure that critical data is transmitted first. In addition, if Figure 2 As shown in the figure, the four independent channels of the DMA engine are bound to different storage controllers respectively, supporting concurrent transmission. After determining the transmission strategy, the engine will efficiently transfer the data to be stored to the target storage controller through the corresponding channel. The entire process bypasses the CPU and system memory bottlenecks, improves data transmission efficiency through the zero-copy mechanism, and realizes the optimal utilization of storage resources.

[0106] After the transmission strategy is determined, the DMA engine calls the corresponding independent DMA channel according to the target storage controller determined in the strategy. Each DMA channel is pre-bound to a storage controller and migrates to different storage controllers.

[0107] If the policy specifies migrating data to a less-loaded storage controller, the DMA engine prioritizes data transfer by binding that controller's DMA channels, corresponding PCIe ports, and high-density connectors. If the policy requires balanced distribution across multiple controllers, multiple DMA channels are activated simultaneously, transferring data in parallel through their corresponding hardware links, preventing a single storage controller from being overloaded by a concentrated influx of data. This hardware-accelerated migration approach dynamically adapts to the overall storage system load.

[0108] In some embodiments, after migrating the data to be stored to the corresponding storage controller, the method further includes:

[0109] Regularly receiving heartbeat messages sent by the storage controller;

[0110] If no heartbeat message is received for a predetermined number of consecutive times, it is determined that the storage controller is faulty;

[0111] When a failure of any of the storage controllers is detected, the to-be-stored data corresponding to the failed controller is automatically directed to the remaining normal target storage controllers.

[0112] See also Figure 4 , Figure 4 A schematic diagram of a management service flow of a shared network card provided in an embodiment of the present application is shown as follows: Figure 4 As shown, monitoring the status of each storage controller is mainly completed through the management network and heartbeat detection module inside the IPU. Specifically, the IPU establishes an independent heartbeat connection with each storage controller through the second Ethernet controller. The second Ethernet controller will regularly send heartbeat messages to each storage controller through the management network and wait for a response; if the storage controller is operating normally, it will return a response message in time to confirm that it is in a normal state; if no response is received from a certain storage controller within the preset time (such as no heartbeat message feedback), it is determined that the storage controller is in an abnormal state. At this time, the IPU will record the abnormal information in real time to provide a basis for subsequent data migration.

[0113] When a storage controller is detected as abnormal, the direct memory access engine migrates data from the abnormal storage controller to a normal storage controller. The DMA engine, a core component supporting multi-channel zero-copy transfers, has four independent channels bound to four storage controllers, enabling concurrent data transfer. Specifically, if a storage controller is identified as abnormal, the DMA engine dynamically adjusts the transfer strategy based on the load status of each normal storage controller. The DMA channel originally bound to the abnormal controller is released, and data to be transferred or cached on that channel, such as data temporarily stored in DDR memory, is reallocated to the DMA channel bound to the normal controller. The DMA engine's priority scheduler prioritizes this migrated data, and the entire process uses a zero-copy mechanism to bypass CPU and system memory bottlenecks, avoiding additional performance losses. During the migration process, data is transferred via the PCIe ports and high-density connectors corresponding to the normal storage controller, ultimately being securely migrated to the normal storage controller. External servers are unaware of the entire process, ensuring storage service continuity and data security.

[0114] In some embodiments, load balancing the data to be stored and migrating the data to be stored to the corresponding storage controller according to the current load of each storage controller includes:

[0115] The direct memory access engine manages the address, length and transmission status of data transmission based on the symbol ring.

[0116] The symbol ring is a circular data structure used within the DMA engine to record and manage data transfer metadata. It consists of multiple descriptor items, each corresponding to a specific data transfer task. For address management, the symbol ring records the source address of the data to be stored in the DDR, where the data is temporarily stored, and the memory address of the target storage controller, where the data needs to be transferred. These addresses are written by the first Ethernet controller after data processing, ensuring that the DMA engine can accurately locate the source and destination of the data, providing the basis for direct data transfer.

[0117] For length management, each descriptor item in the symbol ring records the byte length of the corresponding data block. This information is generated by the first Ethernet controller based on the data frame parsing results. The DMA engine can accurately control the scale of data transmission by reading the length information to avoid transmission errors caused by data volume mismatch. It also provides a basis for judging the load of the storage controller. For example, if the cumulative data length in the symbol ring corresponding to a certain storage controller is small, it means that the amount of data it is currently processing is small and the load is low.

[0118] To manage transfer status, the symbol ring uses status bits to provide real-time feedback on data transfer progress, such as not started, transferring, completed, or transfer errors. The DMA engine continuously scans these status bits to monitor the execution status of each transfer task. If a descriptor item is in the completed status, indicating that the corresponding data has been successfully transferred to the target storage controller, the DMA engine can release the descriptor item for use by a new task. If the status is a transfer error, a retry mechanism is triggered or switching to another channel is triggered.

[0119] Based on the current load of each storage controller, the DMA engine determines the transmission strategy by analyzing the address distribution, total data length, and transfer status update frequency of each storage controller in the symbol ring. If the symbol ring corresponding to a storage controller has few descriptor items in the transfer state, a small total data length, and fast status updates, it indicates that its load is low. The DMA engine will prioritize allocating new data to be stored to its channel through the descriptor items corresponding to that controller. If the symbol ring corresponding to a storage controller has a long duration of transfer state and a large data backlog, it indicates that its load is high. In this case, less data will be allocated to that channel. Through the symbol ring's precise management of addresses, lengths, and transfer status, the DMA engine achieves traceability and dynamic scheduling of data transmission, ensuring that data to be stored is evenly distributed according to the storage controller load, improving overall transmission efficiency.

[0120] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0121] The embodiment of the present application also provides a control device for a shared network card. Figure 5 A schematic diagram of a control device for a shared network card provided in an embodiment of the present application is shown in FIG. Figure 5 Shown, including:

[0122] An acquiring unit 21 is configured to acquire data to be stored sent by an external server;

[0123] The migration unit 22 is configured to perform load balancing on the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller.

[0124] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 6 As shown, the device also includes:

[0125] The receiving unit 23 is configured to periodically receive a heartbeat message sent by the storage controller after the migration unit 22 migrates the data to be stored to the corresponding storage controller;

[0126] a determining unit 24 configured to determine that the storage controller is faulty when no heartbeat message is received for a predetermined number of consecutive times;

[0127] The migration unit 22 is further configured to automatically direct the to-be-stored data corresponding to the failed controller to the remaining normal target storage controllers when a failure of any of the storage controllers is detected.

[0128] Furthermore, in a possible implementation of the embodiment of the present disclosure, the migration unit 22 performs load balancing on the data to be stored according to the current load of each storage controller, and migrates the data to be stored to the corresponding storage controller, and is further configured to:

[0129] The direct memory access engine manages the address, length and transmission status of data transmission based on the symbol ring. The description of the features of the embodiment corresponding to the control device of the shared network card can be found in the relevant description of the embodiment corresponding to the control method of the shared network card, which will not be repeated here.

[0130] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the control method for sharing a network card.

[0131] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned shared network card control method embodiments when running.

[0132] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0133] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned shared network card control method embodiments are implemented.

[0134] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned shared network card control method embodiments.

[0135] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0136] The above is a detailed introduction to a shared network card and a control method, device and electronic device for a shared network card provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A shared network card, characterized in that: include: An integrated processing unit chip, the integrated processing unit chip comprising a first Ethernet controller, a plurality of PCI Express ports, and a direct memory access engine, wherein the first Ethernet controller is connected to the direct memory access engine; the direct memory access engine is connected to a plurality of memory controllers via the PCI Express ports and a high-density connector, wherein one PCI Express port is connected to one memory controller via one high-density connector; A pluggable module, wherein the pluggable module is connected to the first Ethernet controller; The pluggable module is configured to send the data to be stored from the external server to the first Ethernet controller; The first Ethernet controller is configured to send the data to be stored to the direct memory access engine; The direct memory access engine is configured to perform load balancing on the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller; Wherein, the integrated processing unit chip further includes a second Ethernet controller; the second Ethernet controller is connected to the plurality of storage controllers through the peripheral component interconnect express port by heartbeat; The second Ethernet controller is configured to synchronize status information of each storage controller in real time.

2. The shared network card according to claim 1, wherein: The shared network card also includes a double data rate memory; The first Ethernet controller is connected to the direct memory access engine through the double data rate memory.

3. The shared network card according to claim 1, wherein: The integrated processing unit chip further includes a control module; the control module is connected to the second Ethernet controller; The control module is configured to detect whether the storage controller is faulty based on the status information, and when a fault is detected in any of the storage controllers, automatically direct the data packets corresponding to the faulty controller to the remaining normal target storage controllers.

4. The shared network card according to claim 3, wherein: Detecting whether the storage controller is faulty according to the status information includes: The control module periodically receives a heartbeat message sent by the storage controller through the second Ethernet controller; If no heartbeat message is received for a predetermined number of consecutive times, it is determined that the storage controller is faulty.

5. The shared network card according to claim 3, wherein: The automatically redirecting data packets corresponding to the failed controller to other normal storage controllers includes: The control module updates the physical address mapping of the target storage controller through a hardware routing table inside the integrated processing unit chip.

6. The shared network card according to claim 3, wherein: The control module is further configured to send the data offloaded from the integrated processing unit chip to the double data rate memory to the corresponding storage controller through the direct memory access engine.

7. The shared network card according to any one of claims 1 to 6, characterized in that: The shared network card also includes: a pluggable module configured to send data to be stored from an external server to the first Ethernet controller; The first Ethernet controller is configured to send the data to be stored to the double data rate memory; The double data rate memory is configured to send the data to be stored to a direct memory access engine; The direct memory access engine is configured to perform load balancing on the data to be stored according to the current load of each storage controller, and migrate the data to be stored to the corresponding storage controller.

8. A method for controlling a shared network card, characterized in that: The shared network card according to any one of claims 1 to 7 comprises: Get the data to be stored sent by the external server; According to the current load conditions of each storage controller, the data to be stored is load balanced and distributed, and the data to be stored is migrated to the corresponding storage controller.

9. The method for controlling a shared network card according to claim 8, wherein: After migrating the data to be stored to the corresponding storage controller, the method further includes: Regularly receiving heartbeat messages sent by the storage controller; If no heartbeat message is received for a predetermined number of consecutive times, it is determined that the storage controller is faulty; When a failure of any of the storage controllers is detected, the to-be-stored data corresponding to the failed controller is automatically directed to the remaining normal target storage controllers.

10. The method for controlling a shared network card according to claim 8, wherein: The step of load balancing the data to be stored according to the current load of each storage controller and migrating the data to be stored to the corresponding storage controller includes: The direct memory access engine manages the address, length and transmission status of data transmission based on the symbol ring.

11. A control device for a shared network card, characterized in that: The shared network card according to any one of claims 1 to 7 comprises: An acquisition unit, used for acquiring data to be stored sent by an external server; The migration unit is used to perform load balancing on the data to be stored according to the current load conditions of each storage controller, and migrate the data to be stored to the corresponding storage controller.

12. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for controlling a shared network card according to any one of claims 8 to 10 when executing the computer program.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for controlling a shared network card according to any one of claims 8 to 10 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for controlling a shared network card according to any one of claims 8 to 10 are implemented.

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