Trench IGBT chip active region edge structure

Abstract

The application relates to the technical field of IGBT chip, and discloses a trench type IGBT chip active region edge structure, which comprises a substrate body, the surface of the substrate body is provided with a plurality of groups of active region trenches and virtual region trenches, the plurality of groups of virtual region trenches are respectively located between adjacent active region trenches, and the substrate body is provided with a redundant region trench near the active region trenches, in the application, the current transmission path can be rapidly switched to the redundant region polycrystalline silicon by means of the connecting assembly, the redundant region polycrystalline silicon is like a standby conductive channel, timely replaces the failed active region polycrystalline silicon, and continues to maintain the normal work of the chip, the design greatly enhances the fault tolerance of the chip, effectively reduces the risk that the whole chip cannot normally operate due to the failure of individual active region polycrystalline silicon, and remarkably improves the reliability and stability of the chip, thereby providing a powerful guarantee for the efficient operation of the chip in various complex working environments.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of IGBT chip, in particular to a trench IGBT chip active region edge structure. BACKGROUND

[0002] Trench IGBT chip is an important type of power semiconductor device, which etches a trench on a silicon wafer and places the gate in the trench. Compared with the traditional planar structure, it greatly increases the effective area and current density of the chip and reduces the on-state voltage drop. The active region is the core of realizing electrical function, and the edge structure guarantees the performance and reliability of the device. The chip is composed of a gate, a collector and an emitter, and the conduction and turn-off are realized by controlling the gate voltage. The chip has high input impedance, fast switching characteristics of MOSFET, and large current handling capacity of bipolar transistor, and is widely used in industrial frequency converters, new energy power generation, new energy vehicles, smart grids, rail transit and other fields, which can improve power conversion efficiency and reduce energy consumption.

[0003] The prior art such as the patent with publication number CN111916495A discloses a trench IGBT chip active region edge structure, which comprises a substrate, at least one active trench and at least two virtual region trenches are alternately and parallelly arranged on the upper surface of the substrate; a gate bus polycrystalline silicon is arranged at one end of the upper surface of the substrate; a polycrystalline silicon bridge is arranged on the upper surface of the substrate; a dielectric layer covers the entire upper surface of the substrate and the upper surfaces of the gate bus polycrystalline silicon and the polycrystalline silicon bridge; a contact window is arranged in the dielectric layer on the upper surface of the polycrystalline silicon bridge; the distance L2 between the end of the contact window away from the gate bus polycrystalline silicon and the end of the virtual region trench close to the gate bus polycrystalline silicon is greater than 0; since the upper surface of the polycrystalline silicon bridge is relatively flat, the etching of the contact window in the dielectric layer on its upper surface will not be affected by the uneven virtual region trench polycrystalline silicon, and a complete contact window can be etched. In addition, the contact window avoids the end of the virtual region trench, so that the etching of the contact window will not damage the structure of the virtual region trench, and the problem of incomplete etching of the contact window due to unevenness is solved.

[0004] In the prior art, a plurality of active area polysilicon and gate polysilicon are connected in parallel in the chip, when any of the active area polysilicon is damaged due to overvoltage breakdown, thermal stress damage or manufacturing process defects, the failure point will cause the entire parallel circuit to malfunction, and the chip loses normal working ability. At the same time, due to the complex integrated structure and parallel connection mode inside the chip, fault location and repair are extremely difficult, and it is difficult to realize precise replacement or repair of the damaged polysilicon, and the chip often needs to be replaced as a whole. A single oxide layer is arranged in the active area trench and the virtual area trench, which cannot well adjust the electric field distribution. When the IGBT is working, especially in the case of high voltage and large current, the electric field is easily concentrated in some areas, so that these areas bear a high electric field strength, thereby reducing the voltage resistance of the chip, and even may cause breakdown phenomenon, affecting the reliability and service life of the chip.

[0005] To this end, we propose a trench IGBT chip active area edge structure. SUMMARY

[0006] (I) Technical problems solved

[0007] In view of the shortcomings of the prior art, the present application provides a trench IGBT chip active area edge structure, which solves the problem that there is no standby conduction path once damaged in the prior art, and the single oxide layer in the trench cannot well adjust the electric field distribution.

[0008] (II) Technical solutions

[0009] To achieve the above object, the present application is implemented by the following technical solutions: A trench type IGBT chip active area edge structure, comprising a substrate body, a plurality of groups of active area trenches and virtual area trenches are arranged on the surface of the substrate body, a plurality of groups of the virtual area trenches are respectively arranged between adjacent active area trenches, a redundancy area trench is arranged near the active area trench of the substrate body, the size and the number of the redundancy area trench are the same as those of the active area trench, active area polysilicon, redundancy area polysilicon and virtual area polysilicon are respectively arranged in the active area trench, the redundancy area trench and the virtual area trench, a composite dielectric layer is arranged on the inner wall of the active area trench, the redundancy area trench and the virtual area trench, an anchoring part is arranged on the composite dielectric layer, and the anchoring part is connected with the active area trench, the redundancy area trench and the virtual area trench respectively, the surface of the substrate body is fixedly connected with a contact sheet one and a contact sheet two, a groove for the contact sheet two to pass through is arranged on the surface of the contact sheet one, a plurality of groups of the active area polysilicon are in contact with the contact sheet one, a plurality of groups of the redundancy area polysilicon are in contact with the contact sheet two, a polysilicon bridge in contact with the virtual area polysilicon is arranged on the surface of the substrate body, a contact window is arranged on the polysilicon bridge, an insulating layer is arranged on the substrate body, the contact sheet one and the contact sheet two, a gate polysilicon, a dielectric layer and an emitter metal layer are sequentially arranged on the insulating layer, and a connecting assembly is arranged between the contact sheet one, the contact sheet two and the gate polysilicon.

[0010] Preferably, the connecting assembly comprises a pin one and a pin two fixedly connected on the surfaces of the contact sheet one and the contact sheet two respectively, a pin three and a pin four are respectively arranged on the gate polysilicon, the connecting assembly further comprises a connecting module for connecting the pin one, the pin three or the pin two and the pin four, through the above-mentioned components, the connecting module can be connected with the pin one and the pin three, at this time, the active area polysilicon is in communication with the gate polysilicon, after the connecting module is connected with the pin two and the pin four, the redundancy area polysilicon is in communication with the gate polysilicon, thereby facilitating subsequent maintenance.

[0011] Preferably, the connecting module comprises a module body and a conductive body, the conductive body is fixed in the module body, a groove is arranged on the conductive body, the width of the groove is slightly smaller than the width of the pin one, the pin two, the pin three and the pin four, through the above-mentioned components, when communication is performed, the pin one and the pin two or the pin three and the pin four are only inserted in the groove on the surface of the conductive body, and since the size is slightly smaller, clamping operation can be realized.

[0012] Preferably, the conductive body is made of silver-plated copper material.

[0013] Preferably, the anchoring part comprises a plurality of dovetail blocks fixed on the outer surface of the composite dielectric layer, the inner walls of the active area groove, the redundant area groove and the virtual area groove are provided with dovetail grooves, and the dovetail blocks are inserted with the inner walls of the dovetail grooves, so that the anchoring force of the composite dielectric layer can be improved by cooperation of the dovetail blocks and the dovetail grooves.

[0014] Preferably, the recess in one surface of the contact sheet is fixedly connected with an isolation pad, the contact sheet one and the contact sheet two are separated, and the isolation pad is made of insulating material.

[0015] Preferably, the composite dielectric layer comprises, from inside to outside, an ultrathin charge trapping layer, an inner layer of high dielectric constant material, a stress buffer layer and an outer layer of low dielectric constant material.

[0016] Preferably, the ultrathin charge trapping layer is silicon oxynitride (SiON), the inner layer of high dielectric constant material is HfO2 or Al2O3, the stress buffer layer is silicon nitride Si3N4 or a polymer film, and the outer layer of low dielectric constant material is SiO2, so that the ultrathin charge trapping layer of silicon oxynitride can optimize the interface with polysilicon, reduce the interface state density, improve the carrier migration efficiency and inhibit charge injection, the inner layer of high dielectric constant material of HfO2 or Al2O3 can effectively adjust the electric field, reduce the electric field concentration and improve the chip voltage resistance, the stress buffer layer of silicon nitride or polymer film can relieve the stress in chip manufacturing and working and avoid dielectric layer rupture, the outer layer of low dielectric constant material of SiO2 provides good insulation and chemical protection, reduces the leakage and external erosion, and can also reduce the parasitic capacitance, and the layers work together to comprehensively improve the chip performance, reliability and stability.

[0017] Preferably, the lower surface of the substrate body is provided with a plurality of groove bodies, and the inner walls of the plurality of groove bodies are fixedly connected with heat conducting sheets, so that the heat conducting sheets in the grooves under the substrate body can realize heat conduction.

[0018] Preferably, the heat conducting sheet is made of copper material.

[0019] In summary, the technical effects and advantages of the present application are as follows:

[0020] 1、In the present application, by setting the redundant area groove and the redundant area polysilicon on the substrate body, and by contacting the first contact piece with the active area polysilicon and the second contact piece with the redundant area polysilicon, and then by connecting the first contact piece and the active area polysilicon to the gate polysilicon or the second contact piece and the redundant area polysilicon to the gate polysilicon through the connecting assembly, when a certain active area polysilicon fails due to reasons such as electromigration, thermal stress or defects generated during the manufacturing process, the current transmission path can be quickly switched to the redundant area polysilicon through the connecting assembly, and the redundant area polysilicon can timely replace the failed active area polysilicon and continue to maintain the normal operation of the chip, which greatly enhances the fault tolerance of the chip, effectively reduces the risk of the entire chip unable to operate normally due to the failure of individual active area polysilicon, and significantly improves the reliability and stability of the chip, providing a strong guarantee for its efficient operation in various complex working environments.

[0021] 2、In the present application, the anchor part adopts dovetail blocks and dovetail grooves to enhance the anchoring force of the composite dielectric layer on the inner walls of the active area groove, the redundant area groove and the virtual area groove, reduce the peeling or displacement of the dielectric layer, ensure the stability of the chip structure and guarantee long-term reliable operation.

[0022] 3、In the present application, the composite dielectric layer has a synergistic effect of each layer, the ultra-thin charge trapping layer improves the interface properties and enhances the carrier migration efficiency, the high dielectric constant inner layer optimizes the electric field distribution and enhances the voltage resistance, the stress buffer layer relieves stress and protects the dielectric layer structure, and the low dielectric constant outer layer provides insulation protection and reduces parasitic capacitance, which comprehensively improves the performance of the chip.

[0023] 4、In the present application, the lower surface of the substrate body is provided with a copper heat sink to increase the heat dissipation path, accelerate heat conduction and dissipation, effectively reduce the working temperature of the chip, reduce the performance degradation or damage caused by overheating, prolong the service life of the chip and improve the operation stability. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a schematic diagram of the overall structure of the active area edge structure of the trench type IGBT chip of the present application;

[0025] Figure 2 It is a schematic diagram of the side view structure of the active area edge structure of the trench type IGBT chip of the present application;

[0026] Figure 3 It is a schematic diagram of the active area edge structure of the trench type IGBT chip of the present application; Figure 2 partial structure;

[0027] Figure 4 It is a schematic diagram of the active area edge structure of the trench type IGBT chip of the present application;

[0028] Figure 5 Part of the schematic diagram of the bottom view structure of the active region edge structure of the trench type IGBT chip of the present application;

[0029] Figure 6 Part of the schematic diagram of the structure of the active region edge structure of the trench type IGBT chip of the present application;

[0030] Figure 7 Part of the schematic diagram of the structure of the active region edge structure of the trench type IGBT chip of the present application; Figure 6 Part of the schematic diagram of the structure of the active region edge structure of the trench type IGBT chip of the present application;

[0031] Figure 8 Part of the schematic diagram of the structure of the active region edge structure of the trench type IGBT chip of the present application; Figure 6 Part of the schematic diagram of the structure of the active region edge structure of the trench type IGBT chip of the present application;

[0032] Figure 9 Part of the schematic diagram of the structure of the active region edge structure of the trench type IGBT chip of the present application;

[0033] Figure 10 Part of the schematic diagram of the structure of the active region edge structure of the trench type IGBT chip of the present application.

[0034] In the figure: 1, substrate body; 2, active region trench; 3, redundancy region trench; 4, virtual region trench; 5, active region polysilicon; 6, redundancy region polysilicon; 7, virtual region polysilicon; 8, composite dielectric layer; 81, ultra-thin charge trapping layer; 82, high dielectric constant material inner layer; 83, stress buffer layer; 84, low dielectric constant material outer layer; 9, polysilicon bridge; 10, contact window; 11, contact piece one; 12, contact piece two; 13, isolation pad; 14, pin one; 15, pin two; 16, insulating layer; 17, gate polysilicon; 18, dielectric layer; 19, emitter metal layer; 20, pin three; 21, pin four; 22, connection module; 221, module body; 222, conductive body; 23, groove body; 24, heat conduction piece; 25, anchoring part; 251, dovetail block; 252, dovetail groove. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] REFERENCE Figure 1 - Figure 10The trench type IGBT chip active region edge structure shown includes a substrate body 1, a plurality of active region trenches 2 and virtual region trenches 4 are formed on the surface of the substrate body 1, the plurality of virtual region trenches 4 are respectively located between adjacent active region trenches 2, a redundant region trench 3 is arranged near the active region trench 2 of the substrate body 1, the size and number of the redundant region trench 3 are the same as those of the active region trench 2, and active region polysilicon 5, redundant region polysilicon 6 and virtual region polysilicon 7 are respectively arranged in the active region trench 2, the redundant region trench 3 and the virtual region trench 4;

[0037] The inner walls of the active region trench 2, the redundant region trench 3 and the virtual region trench 4 are provided with a composite dielectric layer 8, the composite dielectric layer 8 is provided with an anchoring part 25, and the anchoring part 25 is connected with the active region trench 2, the redundant region trench 3 and the virtual region trench 4, respectively, the surface of the substrate body 1 is fixedly connected with a contact sheet one 11 and a contact sheet two 12, the surface of the contact sheet one 11 is provided with a groove for the contact sheet two 12 to pass through, a plurality of active region polysilicon 5 is in contact with the contact sheet one 11, a plurality of redundant region polysilicon 6 is in contact with the contact sheet two 12, the surface of the substrate body 1 is provided with a polysilicon bridge 9 in contact with the virtual region polysilicon 7, the polysilicon bridge 9 is provided with a contact window 10, the substrate body 1, the contact sheet one 11 and the contact sheet two 12 are provided with an insulating layer 16, the insulating layer 16 is sequentially provided with a gate polysilicon 17, a dielectric layer 18 and an emitter metal layer 19, and the contact sheet one 11 and the contact sheet two 12 are provided with a connecting assembly between the gate polysilicon 17;

[0038] In the embodiment, by arranging the redundant region trench 3 and the redundant region polysilicon 6 on the substrate body 1, and by the contact of the contact sheet one 11 with the plurality of active region polysilicon 5 and the contact of the contact sheet two 12 with the redundant region polysilicon 6, and then by the connecting assembly, the contact of the contact sheet one 11 with the active region polysilicon 5 and the gate polysilicon 17 is realized or the contact of the contact sheet two 12 with the redundant region polysilicon 6 and the gate polysilicon 17 is realized, when a certain active region polysilicon 5 fails due to reasons such as electromigration, thermal stress or defects generated in the manufacturing process, the connecting assembly can quickly switch the current transmission path to the redundant region polysilicon 6, and the redundant region polysilicon 6 can timely replace the failed active region polysilicon 5 and continue to maintain the normal work of the chip.

[0039] The connecting assembly includes the pin one 14 and the pin two 15 fixedly connected on the surfaces of the contact sheet one 11 and the contact sheet two 12 respectively, the pin three 20 and the pin four 21 arranged on the gate polysilicon 17 respectively, and the connecting module 22 for connecting the pin one 14, the pin three 20 or the pin two 15 and the pin four 21. The connecting module 22 includes a module body 221 and a conductive body 222. The conductive body 222 is fixed in the module body 221. The conductive body 222 is provided with a groove. The width of the groove is slightly smaller than the width of the pin one 14, the pin two 15, the pin three 20 and the pin four 21. The conductive body 222 is made of silver-plated copper.

[0040] In the embodiment, the connecting module 22 can be connected with the pin one 14 and the pin three 20. At this time, the active area polysilicon 5 is connected with the gate polysilicon 17. After the connecting module 22 is connected with the pin two 15 and the pin four 21, the redundant area polysilicon 6 is connected with the gate polysilicon 17. Thus, it is convenient for subsequent maintenance. Meanwhile, the pin one 14 and the pin two 15 or the pin three 20 and the pin four 21 are inserted into the groove on the surface of the conductive body 222. Since the size is slightly smaller, the clamping operation can be realized.

[0041] The anchoring part 25 includes a plurality of dovetail blocks 251 fixed on the outer surface of the composite dielectric layer 8. The inner walls of the active area groove 2, the redundant area groove 3 and the virtual area groove 4 are all provided with dovetail grooves 252. The dovetail blocks 251 are inserted into the inner walls of the dovetail grooves 252. The recess on the surface of the contact sheet one 11 is fixedly connected with the isolation pad 13. The contact sheet one 11 and the contact sheet two 12 are separated by the isolation pad 13. The isolation pad 13 is made of insulating material.

[0042] In the embodiment, the dovetail blocks 251 and the dovetail grooves 252 are matched. Thus, the anchoring force of the composite dielectric layer 8 can be improved.

[0043] The composite dielectric layer 8 includes, from inside to outside, an ultrathin charge trapping layer 81, a high dielectric constant material inner layer 82, a stress buffer layer 83 and a low dielectric constant material outer layer 84. The ultrathin charge trapping layer 81 is silicon oxynitride SiON. The high dielectric constant material inner layer 82 is HfO2 or Al2O3. The stress buffer layer 83 is silicon nitride Si3N4 or a polymer film. The low dielectric constant material outer layer 84 is SiO2.

[0044] In the embodiment: the silicon oxynitride ultra-thin charge capture layer 81 can optimize the interface with the polysilicon, reduce the interface state density, improve the carrier migration efficiency, and inhibit the charge injection; the HfO2 or Al2O3 high dielectric constant inner layer can effectively adjust the electric field, reduce the electric field concentration, and improve the chip voltage resistance capacity; the silicon nitride or polymer thin film stress buffer layer 83 can relieve the stress in the chip manufacturing and working, and avoid the dielectric layer rupture; the SiO2 low dielectric constant outer layer provides good insulation and chemical protection, reduces the leakage and external erosion, and can also reduce the parasitic capacitance. The layers work together to comprehensively improve the chip performance, reliability and stability.

[0045] The lower surface of the substrate body 1 is provided with a plurality of groove bodies 23, and the inner walls of the plurality of groove bodies 23 are fixedly connected with heat conduction sheets 24 made of copper material.

[0046] The working principle of the present application is as follows: in the working process, the plurality of active area polysilicon 5 are connected together through the contact sheet one 11, and the plurality of redundant area polysilicon 6 are connected together through the contact sheet two 12; in the normal working process, the connecting module 22 is connected with the pin one 14 and the pin three 20, the pin one 14 and the pin three 20 can be inserted into the groove on the surface of the conductor 222, and the groove is slightly smaller in size, so that the clamping effect is achieved; then the active area polysilicon 5 can be in communication with the gate polysilicon 17 for normal work; once the active area polysilicon 5 is damaged, the connecting module 22 is removed, and the connecting module 22 or a new connecting module 22 is connected with the pin two 15 and the pin four 21; the pin two 15 and the pin four 21 can be inserted into the groove on the surface of the conductor 222, and the groove is slightly smaller in size, so that the clamping effect is achieved; then the redundant area polysilicon 6 can be in communication with the gate polysilicon 17 to realize the standby conductive channel, and the maintenance is convenient.

[0047] Meanwhile, the inner wall of the active area trench 2, the redundant area trench 3 and the virtual area trench 4 is provided with a composite dielectric layer 8, and the dovetail block 251 cooperates with the dovetail groove 252 to realize anchoring effect. The ultra-thin charge capture layer 81, such as silicon oxynitride SiON, can significantly improve the interface quality between the dielectric layer and the polysilicon. It can effectively reduce the interface state density, reduce the scattering of carriers at the interface, improve the mobility and transmission efficiency of the carriers, and further improve the switching speed and reduce the on-resistance of the device. The layer can capture a small amount of charge injected from the polysilicon, reduce the further diffusion of these charges into other dielectric layers, reduce the distortion of the electric field distribution and the degradation of the device performance caused by charge accumulation, and help to maintain the stability of the chip performance. The high dielectric constant material inner layer 82 is HfO2 or Al2O3, which can make the electric field more uniformly distributed in the active area, reduce the electric field concentration phenomenon, improve the voltage resistance of the chip, reduce the risk of breakdown caused by electric field concentration, and thus enhance the reliability of the chip. The stress buffer layer 83 such as silicon nitride Si3N4 or polymer film can effectively relieve these stresses, reduce the problems such as dielectric layer cracking and delamination caused by stress, and improve the stability and reliability of the dielectric layer. The low dielectric constant material outer layer 84 such as SiO2 has good insulation performance, can provide reliable electrical isolation, reduce the occurrence of leakage phenomenon, and ensure the normal work of the chip.

[0048] The electrical components in the text are all connected with the main controller and 220V mains, and the main controller can be a conventional known device such as a computer.

[0049] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent replacements to some technical features, as long as they are within the spirit and principles of the present application. Any modification, equivalent replacement, improvement, etc. made within the scope of the present application shall be included in the protection scope of the present application.

Claims

1. A trench IGBT chip active region edge structure, comprising a substrate body (1), characterized in that: The surface of the substrate body (1) is provided with a plurality of groups of active area grooves (2) and virtual area grooves (4), the substrate body (1) is provided with a redundant area groove (3) near the active area groove (2), the active area groove (2), the redundant area groove (3) and the virtual area groove (4) are respectively provided with active area polysilicon (5), redundant area polysilicon (6) and virtual area polysilicon (7), the inner walls of the active area groove (2), the redundant area groove (3) and the virtual area groove (4) are provided with a composite dielectric layer (8), the composite dielectric layer (8) is provided with an anchoring part (25), and the active area groove (2), the redundant area groove (3) and the virtual area groove (4) are connected through the anchoring part (25), the surface of the substrate body (1) is fixedly connected with a contact sheet one (11) and a contact sheet two (12), the surface of the contact sheet one (11) is provided with a groove for the contact sheet two (12) to pass through, a plurality of groups of the active area polysilicon (5) and the redundant area polysilicon (6) are in contact with the contact sheet one (11) and the contact sheet two (12), the surface of the substrate body (1) is provided with a polysilicon bridge (9) in contact with the virtual area polysilicon (7), the polysilicon bridge (9) is provided with a contact window (10), the substrate body (1), the contact sheet one (11) and the contact sheet two (12) are provided with an insulating layer (16), the insulating layer (16) is sequentially provided with a gate polysilicon (17), a dielectric layer (18) and an emitter metal layer (19), and the contact sheet one (11) and the contact sheet two (12) are provided with a connecting assembly between the gate polysilicon (17).

2. The trench IGBT chip active region edge structure of claim 1, wherein: The connecting assembly comprises pins one (14) and pins two (15) fixedly connected on the surfaces of the contact sheet one (11) and the contact sheet two (12) respectively, the gate polysilicon (17) is respectively provided with pins three (20) and pins four (21), and the connecting assembly further comprises a connecting module (22) for connecting the pins one (14), the pins three (20) or the pins two (15) and the pins four (21).

3. The trench IGBT chip active region edge structure of claim 2, wherein: The connecting module (22) comprises a module body (221) and a conductive body (222), the conductive body (222) is fixed in the module body (221), the conductive body (222) is provided with a groove, and the width of the groove is slightly smaller than the width of the pins one (14), the pins two (15), the pins three (20) and the pins four (21).

4. The trench IGBT chip active region edge structure of claim 3, wherein: The conductive body (222) is made of silver-plated copper material.

5. The trench IGBT chip active region edge structure of claim 1, wherein: The anchoring part (25) comprises a plurality of dovetail blocks (251) fixed on the outer surface of the composite dielectric layer (8), the inner walls of the active area groove (2), the redundant area groove (3) and the virtual area groove (4) are provided with dovetail grooves (252), and the dovetail blocks (251) are inserted with the inner walls of the dovetail grooves (252).

6. The trench IGBT chip active region edge structure of claim 1, wherein: The groove in the surface of the contact sheet one (11) is fixedly connected with an isolation pad (13) for separating the contact sheet one (11) and the contact sheet two (12), and the isolation pad (13) is made of insulating material.

7. The trench IGBT chip active region edge structure of claim 1, wherein: The composite dielectric layer (8) comprises, from inside to outside, an ultrathin charge trapping layer (81), a high dielectric constant material inner layer (82), a stress buffer layer (83) and a low dielectric constant material outer layer (84).

8. The trench IGBT chip active region edge structure of claim 7, wherein: The ultrathin charge trapping layer (81) is silicon oxynitride (SiON), the high dielectric constant material inner layer (82) is HfO2 or Al2O3, the stress buffer layer (83) is silicon nitride Si3N4 or a polymer film, and the low dielectric constant material outer layer (84) is SiO2.

9. The trench IGBT chip active region edge structure of claim 1, wherein: The lower surface of the substrate body (1) is provided with a plurality of groove bodies (23), and the inner walls of the plurality of groove bodies (23) are fixedly connected with heat conduction sheets (24).

10. The trench IGBT chip active region edge structure of claim 9, wherein: The heat conduction sheets (24) are made of copper.

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