Semiconductor devices and chips

Abstract

Embodiments of the present disclosure provide a semiconductor device and a chip, relating to the technical field of semiconductor technology, for realizing monolithic integration of enhancement mode and depletion mode; the semiconductor device comprises a substrate, a channel layer, a barrier layer, a gate layer, a first cap layer and a second cap layer; the channel layer and the barrier layer are stacked on the substrate, and the barrier layer is farther away from the substrate than the channel layer; the gate layer is arranged on the side of the barrier layer away from the channel layer; the gate layer comprises a first gate and a second gate arranged at intervals; the first cap layer is arranged between the first gate and the barrier layer; the second cap layer is arranged between the second gate and the barrier layer; wherein the thickness of the barrier layer between the first cap layer and the channel layer is less than the thickness of the barrier layer between the second cap layer and the channel layer. The above semiconductor device is applied to a chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and chip. Background Technology

[0002] In semiconductor devices, enhancement-mode and depletion-mode devices are widely used in power electronics, radio frequency circuits, and mixed-signal systems due to their different conduction characteristics. In traditional designs, enhancement-mode devices typically require a gate voltage to turn on, making them suitable for control circuits with high safety requirements; while depletion-mode devices turn on naturally at zero gate voltage, exhibiting low on-resistance and high current drive capability, making them suitable for power switching and high-frequency amplification.

[0003] However, in the prior art, enhancement-mode and depletion-mode devices are usually designed in discrete form or integrated with external circuitry, which not only leads to high complexity but also increases packaging costs. Summary of the Invention

[0004] The purpose of embodiments of this disclosure is to provide a semiconductor device and chip for achieving enhancement-mode and depletion-mode monolithic integration.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate layer, a first cap layer, and a second cap layer; the channel layer and the barrier layer are stacked on the substrate, with the barrier layer being farther from the substrate than the channel layer; the gate layer is disposed on the side of the barrier layer away from the channel layer; the gate layer includes a first gate and a second gate disposed at a distance; the first cap layer is disposed between the first gate and the barrier layer; the second cap layer is disposed between the second gate and the barrier layer; wherein the thickness of the barrier layer between the first cap layer and the channel layer is less than the thickness of the barrier layer between the second cap layer and the channel layer.

[0007] In the aforementioned semiconductor device, a channel layer and a barrier layer are stacked on a substrate. Because the materials of the channel layer and the barrier layer have different band gaps, a heterojunction is formed between them. The spontaneous polarization and piezoelectric polarization effects of the heterojunction induce a two-dimensional electron gas at the interface between the channel layer and the barrier layer. Furthermore, the thickness of the barrier layer between the first cap layer and the channel layer is less than the thickness between the second cap layer and the channel layer; that is, the barrier layer between the first cap layer and the channel layer is thinner, and the barrier layer between the second cap layer and the channel layer is thicker. Thus, the first cap layer... The high work function of the first cap layer can fully deplete the two-dimensional electron gas between the channel layer and the barrier layer at the bottom of the first cap layer, achieving normally-off operation, i.e., enhancement-mode. However, due to the thickness of the barrier layer between the second cap layer and the channel layer, the depletion effect of the second cap layer is weakened due to its greater distance from the channel layer, resulting in the two-dimensional electron gas between the barrier layer and the channel layer at the bottom of the second cap layer not being completely depleted, achieving normally-on operation, i.e., depletion-mode. A thin barrier layer ensures fast switching and provides safe turn-off capability, while a thick barrier layer maintains high electron mobility and low on-resistance. Therefore, the semiconductor device provided in this embodiment can achieve functional differentiation on the same substrate simply by modulating the thickness of the barrier layer, thereby balancing high-frequency response and high current drive capability, achieving monolithic integration of enhancement-mode and depletion-mode.

[0008] In some embodiments, the thickness of the barrier layer between the first cap layer and the channel layer is a first thickness, the thickness of the barrier layer between the second cap layer and the channel layer is a second thickness, and the difference between the second thickness and the first thickness ranges from 5 nm to 20 nm.

[0009] In some embodiments, a first groove is formed on the surface of the barrier layer away from the channel layer, and the first cap layer includes a first portion and a second portion connected together, the first portion being disposed in the first groove, and the second portion being disposed on the side of the first portion away from the barrier layer.

[0010] In some embodiments, the dimension of the first portion along a first direction is smaller than the dimension of the second portion along the first direction, the first direction being perpendicular to the thickness direction of the semiconductor device.

[0011] In some embodiments, along the first direction, the first portion has a first boundary and a second boundary, the second portion has a third boundary and a fourth boundary, and the third boundary and the first boundary are disposed on one side of the first cap layer along the first direction, and the fourth boundary and the second boundary are disposed on the other side of the first cap layer along the first direction; wherein, along the first direction, the third boundary is farther from the center of the first cap layer than the first boundary, and the fourth boundary is farther from the center of the first cap layer than the second boundary; or, the third boundary overlaps with the first boundary along a second direction, the second direction being the thickness direction of the semiconductor device; along the first direction, the fourth boundary is farther from the center of the first cap layer than the second boundary.

[0012] In some embodiments, the dimension of the first portion along a first direction is equal to the dimension of the second portion along the first direction, wherein the first direction is perpendicular to the thickness direction of the semiconductor device.

[0013] In some embodiments, the first cap layer includes: a first surface and a second surface disposed opposite to each other along a second direction, the second direction being the thickness direction of the semiconductor device; at least one side surface connecting the first surface and the second surface; wherein the at least one side surface is in contact with the groove wall of the first groove; or, along a first direction, at least a portion of at least one of the side surfaces has a gap between it and the groove wall of the first groove, the first direction being perpendicular to the second direction.

[0014] In some embodiments, the first cap layer includes a first portion and a second portion connected together, the first portion being disposed within the first groove, and the second portion being disposed on the side of the first portion away from the barrier layer; the at least one side surface includes a first sub-surface and a second sub-surface arranged circumferentially along the first cap layer; the first sub-surface is in contact with the groove wall of the first groove; the second sub-surface and the groove wall of the first groove are spaced apart in the first direction; the first sub-surface is stepped, and the stepped surface of the first sub-surface overlaps the surface of the barrier layer away from the channel layer; the second sub-surface is a surface perpendicular to the first direction.

[0015] In some embodiments, the barrier layer includes: a main body portion and a protruding portion stacked and connected along a second direction, the protruding portion being farther away from the channel layer than the main body portion, the second direction being the thickness direction of the semiconductor device; a second cap layer disposed on the side of the protruding portion away from the main body portion, and a first cap layer disposed on the side of the main body portion away from the channel layer.

[0016] In some embodiments, the dimension of the first cap layer in the second direction is greater than the dimension of the second cap layer in the second direction, where the second direction is the thickness direction of the semiconductor device.

[0017] In some embodiments, the semiconductor device includes a first region and a second region arranged along a first direction, the first direction being perpendicular to a second direction, the second direction being the thickness direction of the semiconductor device; a first cap layer and a first gate are located in the first region, and a second cap layer and a second gate are located in the second region; the semiconductor device further includes: a first source and a first drain located in the first region, disposed on the barrier layer and respectively located on opposite sides of the first cap layer in the first direction; a second source and a second drain located in the second region, disposed on the barrier layer and respectively located on opposite sides of the second cap layer in the first direction; and an isolation structure disposed between the first region and the second region, penetrating at least a portion of the barrier layer along the second direction.

[0018] In some embodiments, a second groove is formed on the surface of the barrier layer away from the channel layer, and the isolation structure is disposed within the second groove; wherein, the bottom surface of the second groove is closer to the substrate than the surface of the channel layer away from the substrate; or, the bottom surface of the second groove is further away from the substrate than the surface of the channel layer away from the substrate; the first cap layer includes a first portion embedded in the barrier layer; the isolation structure and the first portion of the first cap layer have the same dimensions in the second direction; the isolation structure and the first cap layer are made of the same material.

[0019] On the other hand, a chip is provided, including a semiconductor device as described in any of the above embodiments; and a packaging substrate, the packaging substrate being coupled to the semiconductor device.

[0020] The chip described above has the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0022] Figure 1A structural diagram of an electronic device provided for some embodiments of this disclosure;

[0023] Figure 2 A structural diagram of a semiconductor device provided for some embodiments of this disclosure;

[0024] Figure 3 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0025] Figure 4 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0026] Figure 5 for Figure 4 A magnified view of a portion of the semiconductor device;

[0027] Figure 6 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0028] Figure 7 for Figure 6 A magnified view of a portion of the semiconductor device;

[0029] Figure 8 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0030] Figure 9 for Figure 8 A magnified view of a portion of the semiconductor device;

[0031] Figure 10 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0032] Figure 11 for Figure 10 A magnified view of a portion of the semiconductor device;

[0033] Figure 12 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0034] Figure 13 for Figure 12 A magnified view of a portion of the semiconductor device;

[0035] Figure 14 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0036] Figure 15 for Figure 14 A magnified view of a portion of the semiconductor device;

[0037] Figure 16A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0038] Figure 17 for Figure 16 A magnified view of a portion of the semiconductor device;

[0039] Figure 18 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0040] Figure 19 A schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0041] Figures 20-25 This is a schematic diagram illustrating a method for manufacturing a display panel according to some embodiments of the present disclosure. Detailed Implementation

[0042] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0043] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0045] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0046] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0047] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0048] The use of "applies to" or "configured to" in this document implies open and inclusive language, which does not exclude, as used herein, the inclusion of "parallel," "perpendicular," and "equal" situations as described, as well as those approximating the described situation, within an acceptable range of deviations, which are determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism could be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity could also be, for example, within 5°; "equal" includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality could be, for example, a difference between the two equals less than or equal to 5% of either one.

[0049] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0050] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] like Figure 1 As shown, this disclosure provides an electronic device 1000. The electronic device 1000 can be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic devices.

[0052] Continue to refer to Figure 1 The electronic device 1000 includes a chip 1001 and a circuit board 1002. The chip 1001 and the circuit board 1002 are electrically connected. The circuit board 1002 converts the external power supply into the voltage or current required for the chip 1001 to operate.

[0053] For example, circuit board 1002 may include a printed circuit board (PCB) or the like.

[0054] For example, circuit board 1002 may include multiple conductive layers. The multiple conductive layers within circuit board 1002 may be separated from each other by dielectric layers.

[0055] The aforementioned chip 1001 includes a semiconductor device and a packaging substrate, with the packaging substrate coupled to the semiconductor device. The packaging substrate provides mechanical support, electrical connection, and heat dissipation for the chip 1001.

[0056] In some embodiments, chip 1001 further includes a resistor, a capacitor, and a diode. The resistor can limit current and divide voltage; the capacitor can store energy and filter; and the diode can conduct electricity in one direction and regulate voltage.

[0057] The above-mentioned semiconductor devices will be described in detail below.

[0058] refer to Figure 2The semiconductor device 100 includes a substrate 10, a channel layer 20, a barrier layer 30, a gate layer 40, a first cap layer 51, and a second cap layer 52. The channel layer 20 and the barrier layer 30 are stacked on the substrate 10, with the barrier layer 30 being farther from the substrate 10 than the channel layer 20. The gate layer 40 is disposed on the side of the barrier layer 30 away from the channel layer 20. The gate layer 40 includes a first gate 41 and a second gate 42 disposed at intervals. The first cap layer 51 is disposed between the first gate 41 and the barrier layer 30. The second cap layer 52 is disposed between the second gate 42 and the barrier layer 30. The thickness of the barrier layer 30 between the first cap layer 51 and the channel layer 20 is less than the thickness of the barrier layer 30 between the second cap layer 52 and the channel layer 20.

[0059] In the aforementioned semiconductor device 100, a channel layer 20 and a barrier layer 30 are stacked on a substrate 10. Since the materials of the channel layer 20 and the barrier layer 30 have different band gaps, a heterojunction is formed between them. The spontaneous polarization and piezoelectric polarization effects of the heterojunction induce a two-dimensional electron gas (2DEG) at the interface between the channel layer 20 and the barrier layer 30. Furthermore, the thickness of the barrier layer 30 between the first cap layer 51 and the channel layer 20 is less than the thickness between the second cap layer 52 and the channel layer 20. That is, the barrier layer 30 between the first cap layer 51 and the channel layer 20 is thinner, while the barrier layer 30 between the second cap layer 52 and the channel layer 20 is thicker. This allows the high work function of the first cap layer 51 to fully deplete the two-dimensional electron gas between the channel layer 20 and the barrier layer 30 located at the bottom of the first cap layer 51, achieving normal-off operation. Normally on operation, also known as depletion mode; however, due to the thickness of the barrier layer 30 between the second cap layer 52 and the channel layer 20, the depletion effect of the second cap layer 52 is weakened because it is farther away from the channel layer 20. This results in the two-dimensional electron gas between the channel layer 20 and the barrier layer 30 at the bottom of the second cap layer 52 not being completely depleted, achieving normally on operation, also known as depletion mode; a thin barrier layer 30 can ensure fast switching and provide safe turn-off capability, while a thick barrier layer 30 can maintain high electron mobility and low on-resistance. Therefore, the semiconductor device provided in this embodiment can achieve functional differentiation on the same substrate 10 by simply modulating the thickness of the barrier layer 30, thereby balancing high-frequency response and high current drive capability, and realizing monolithic integration of enhancement mode and depletion mode.

[0060] In some embodiments, the substrate 10 material includes silicon, silicon carbide, silicon nitride, sapphire, diamond, or SOI (Silicon-on-Insulator).

[0061] In some embodiments, the channel layer 20 material includes gallium nitride (GaN).

[0062] In some embodiments, the barrier layer 30 material includes one or a combination of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN).

[0063] In some embodiments, the first cap layer 51 and the second cap layer 52 are made of the same material. This eliminates the need to switch epitaxial growth or deposition processes when fabricating the semiconductor device 100, thus avoiding multiple changes to the gas source or reaction chamber. This simplifies the fabrication process and improves the manufacturing efficiency of the semiconductor device 100. Furthermore, the identical material of the first cap layer 51 and the second cap layer 52 ensures consistent interface defect density and bandgap between the first cap layer 51, the second cap layer 52, and the channel layer 20, thereby reducing performance fluctuations between semiconductor devices 100.

[0064] For example, the materials of the first cap layer 51 and the second cap layer 52 both include gallium nitride (GaN) and are both P-type doped, with the doping element including magnesium (Mg).

[0065] In other embodiments, the materials of the first cap layer 51 and the second cap layer 52 may also be other p-type semiconductor materials capable of raising the energy band and having a depletion effect on the two-dimensional electron gas. For example, a p-type aluminum gallium nitride monolayer structure, or a composite stacked structure of p-type gallium nitride and p-type aluminum gallium nitride.

[0066] In some embodiments, the concentration of doped elements in both the first cap layer 51 and the second cap layer 52 is greater than 1 × 10⁻⁶. 19 cm -3 For example, 1.2 × 10 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 Or 4×10 19 cm -3 .

[0067] In some embodiments, the materials of the first gate 41 and the second gate 42 both include one or more combinations of palladium (Pd), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), titanium (Ti), and titanium nitride (TiN). The first cap layer 51 and the first gate 41 can form a Schottky contact or an ohmic contact. Similarly, the second cap layer 52 and the second gate 42 can form a Schottky contact or an ohmic contact.

[0068] In some embodiments, continue to refer to Figure 2The semiconductor device 100 includes a first region Q1 and a second region Q2 arranged along a first direction X, the first direction X being perpendicular to a second direction Y, the second direction Y being the thickness direction of the semiconductor device 100; a first cap layer 51 and a first gate 41 are located in the first region Q1, and a second cap layer 52 and a second gate 42 are located in the second region Q2; the semiconductor device 100 further includes: a first source 61 and a first drain 62, a second source 71 and a second drain 72, and an isolation structure G; the first source 61 and the first drain 62 are located in the first region Q1 and are disposed on the barrier layer 30, and are respectively located on opposite sides of the first cap layer 51 in the first direction X; the second source 71 and the second drain 72 are located in the second region Q2 and are disposed on the barrier layer 30, and are respectively located on opposite sides of the second cap layer 52 in the first direction X; the isolation structure G is disposed between the first region Q1 and the second region Q2, and penetrates at least a portion of the barrier layer 30 along the second direction Y.

[0069] The first source 61, the first drain 62, the second source 71, and the second drain 72 each include one or more combinations of titanium (Ti), aluminum (Al), titanium nitride (TiN), silicon (Si), and gold (Au).

[0070] Since the first cap layer 51, the first gate 41, the first source 61, and the first drain 62 are located in the first region Q1, and the second cap layer 52, the second gate 42, the second source 71, and the second drain 72 are located in the second region Q2, the isolation structure G is disposed between the first region Q1 and the second region Q2 and penetrates at least part of the barrier layer 30 along the second direction Y. In this way, the first region Q1 and the second region Q2 are physically separated by the isolation structure, that is, the enhancement-mode device and the depletion-mode device are physically separated by the isolation structure G. This can cut off the two-dimensional electron gas path between the first region Q1 and the second region Q2 at the interface between the channel layer 20 and the barrier layer 30, ensuring that the enhancement-mode device and the depletion-mode device work independently.

[0071] For example, continue to refer to Figure 2 A second groove C2 is formed on the surface of the barrier layer 30 away from the channel layer 20, and an isolation structure G is disposed within the second groove C2. The bottom surface of the second groove C2 is closer to the substrate 10 than the surface of the channel layer 20 away from the substrate 10. That is, the second groove C2 penetrates the barrier layer 30 and at least a portion of the channel layer 20. In this case, the second groove C2 blocks the pathway of the two-dimensional electron gas at the interface between the channel layer 20 and the barrier layer 30 between the first region Q1 and the second region Q2, ensuring that the enhancement-type device located in the first region Q1 and the depletion-type device located in the second region Q2 can achieve electrical isolation on the same substrate 10, avoiding mutual interference between the enhancement-type device and the depletion-type device during operation.

[0072] Wherein, the second groove C2 penetrating at least part of the channel layer 20 means that the second groove C2 needs to at least isolate the heterojunction formed between the channel layer 20 and the barrier layer 30.

[0073] For example, see reference. Figure 3 The bottom surface of the second groove C2 is further away from the surface of the channel layer 20 than the surface of the substrate 10; the isolation structure G and the first cap layer 51 have the same dimensions in the second direction Y; the isolation structure G and the first cap layer 51 are made of the same material.

[0074] Since the isolation structure G and the first cap layer 51 are made of the same material (such as p-type GaN), their high work function characteristics can form sufficient band bending, causing the conduction band at the interface between the barrier layer 30 and the channel layer 20 to rise above the Fermi level, thus achieving complete depletion of the two-dimensional electron gas. The first part 511 of the isolation structure G and the first cap layer 51 has the same dimension in the second direction Y, which can ensure that the depletion region covers the entire target area and avoid leakage caused by local two-dimensional electron gas residue.

[0075] As another example, the isolation structure G includes an ion implantation isolation structure, which can disrupt the conductivity of the barrier layer 30 to form a high-resistivity region to block the transport of two-dimensional electron gas.

[0076] The ion implantation isolation structure includes fluoride ions, boron ions, or phosphorus ions.

[0077] In some embodiments, you may continue to refer to Figure 2 The semiconductor device 100 also includes a nucleation layer 80 and a buffer layer 90. The nucleation layer 80 is disposed between the buffer layer 90 and the substrate 10, and the buffer layer 90 is disposed between the nucleation layer 80 and the channel layer 20.

[0078] The nucleation layer 80 can avoid lattice mismatch caused by contact between the substrate 10 and the buffer layer 90, which is beneficial to reduce interface dislocations and can also alleviate warping or cracking caused by the difference in thermal expansion coefficients between the substrate 10 and the buffer layer 90.

[0079] The buffer layer 90 can trap dislocations (such as through-dislocations) extending from the nucleation layer 80, reducing the defect density of the channel layer 20. The buffer layer 90 can also form a high-resistivity region to prevent longitudinal leakage of the semiconductor device 100.

[0080] For example, the material of the nucleation layer 80 includes one or more combinations of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN).

[0081] For example, the material of the buffer layer 90 includes carbon (C)-doped gallium nitride, wherein the carbon doping concentration is between 1 × 10⁻⁶. 19 cm -3~1×10 20 cm -3 Between, for example, 1×10 19 cm -3 1.5×10 20 cm -3 Or 1×10 20 cm -3 In other embodiments, the material of the buffer layer 90 may also be a superlattice structure composed of one or more of aluminum nitride, aluminum gallium nitride, and gallium nitride.

[0082] Continue to refer to Figure 2 The thickness of the barrier layer 30 between the first cap layer 51 and the channel layer 20 is the first thickness H1, and the thickness of the barrier layer 30 between the second cap layer 52 and the channel layer 20 is the second thickness H2. The difference between the second thickness H2 and the first thickness H1 is in the range of 5nm to 20nm.

[0083] Because the first thickness H1 of the barrier layer 30 between the first cap layer 51 and the channel layer 20 is thin, the high work function of the first cap layer 51 can fully deplete the two-dimensional electron gas between the channel layer 20 and the barrier layer 30 located at the bottom of the first cap layer 51. The second thickness H2 of the barrier layer 30 between the second cap layer 52 and the channel layer 20 is thick, and the depletion effect of the second cap layer 52 is weakened due to its greater distance from the channel layer 20, resulting in the two-dimensional electron gas between the barrier layer 30 and the channel layer 20 located at the bottom of the second cap layer 52 not being completely depleted. Therefore, the difference between the second thickness H2 and the first thickness H1 is within this range, which can make the thickness difference between the portion of the barrier layer 30 located between the first cap layer 51 and the channel layer 20 and the portion of the barrier layer 30 located between the second cap layer 52 and the channel layer 20 large. This can ensure that the two-dimensional electron gas density between the first cap layer 51 and the channel layer 20 and the two-dimensional electron gas density between the second cap layer 52 and the channel layer 20 are significantly different, so as to achieve enhancement-mode and depletion-mode monolithic integration.

[0084] For example, the difference between the second thickness H2 and the first thickness H1 can be 5nm, 10nm, 15nm, 18nm, or 20nm.

[0085] For example, the second thickness H2 is greater than or equal to 20nm, and the second thickness H2 can be 20nm, 25nm, 30nm or 35nm.

[0086] When the difference between the second thickness H2 and the first thickness H1 is within the range of 10 nm, the first thickness H1 can be 10 nm, 12 nm, 14 nm or 15 nm.

[0087] In other embodiments, the second thickness H2 and the first thickness H1 can be other parameters, as long as they satisfy the condition that the two-dimensional electron gas between the first cap layer 51 and the channel layer 20 is exhausted at zero gate voltage, and the two-dimensional electron gas between the second cap layer 52 and the channel layer 20 is naturally formed at zero gate voltage, thus providing a high two-dimensional electron gas density.

[0088] In some embodiments, reference Figure 2 The dimension of the first cap layer 51 in the second direction Y is larger than the dimension of the second cap layer 52 in the second direction Y, where the second direction Y is the thickness direction of the semiconductor device 100. The larger dimension of the first cap layer 51 in the second direction Y not only facilitates strong electric field penetration through the first gate 41, improving the channel carrier control efficiency, but also helps reduce the leakage current of the first gate 41 and improve the stability of the threshold voltage. The smaller dimension of the second cap layer 52 in the second direction Y reduces carrier scattering, lowers on-resistance, and also facilitates the continuous distribution of the two-dimensional electron gas in the depletion-type device, thus maintaining high current.

[0089] In some embodiments, reference Figure 2 A first groove C1 is formed on the surface of the barrier layer 30 away from the channel layer 20, and at least a portion of the first cap layer 51 is disposed within the first groove C1. Since at least a portion of the first cap layer 51 is disposed within the first groove C1, the thickness of the barrier layer 30 between the first cap layer 51 and the channel layer 20 is reduced, so that the high work function of the first cap layer 51 can fully deplete the two-dimensional electron gas between the channel layer 20 and the barrier layer 30 located at the bottom of the first cap layer 51.

[0090] For example, continue to refer to Figure 3 The first cap layer 51 includes a first portion 511 and a second portion 512 connected together. The first portion 511 is disposed in the first groove C1, and the second portion 512 is disposed on the side of the first portion 511 away from the barrier layer 30. In this way, the first portion 511 occupies the thickness of the barrier layer 30 between the first cap layer 51 and the channel layer 20, thereby making the thickness of the barrier layer 30 between the first cap layer 51 and the channel layer 20 small. The high work function of the first cap layer 51 can fully deplete the two-dimensional electron gas between the channel layer 20 and the barrier layer 30 located at the bottom of the first cap layer 51, so that the two-dimensional electron gas in the channel layer 20 opposite to the first cap layer 51 is depleted at zero gate voltage.

[0091] In some embodiments, in conjunction with reference Figure 4 and Figure 5The dimension L1 of the first portion 511 along the first direction X is smaller than the dimension L2 of the second portion 512 along the first direction X, where the first direction X is perpendicular to the thickness direction of the semiconductor device 100. That is, along the first direction X, the second portion 512 extends outward relative to the first portion 511. This outward extension of the second portion 512 not only acts as a gate field plate, optimizing the electric field distribution and dispersing the electric field peak to improve the breakdown voltage, but also helps to adjust the distribution density of the two-dimensional electron gas along the first direction X, thereby modulating the channel resistance, suppressing the interference of the drain electric field on the channel, and making the threshold voltage more stable and easier to adjust. The smaller dimension L1 of the first portion 511 along the first direction X helps to precisely control the electric field distribution of the channel layer 20.

[0092] Continue to refer to Figure 5 Along the first direction X, the first part 511 has a first boundary J1 and a second boundary J2, the second part 512 has a third boundary J3 and a fourth boundary J4, and the third boundary J3 and the first boundary J1 are located on one side of the first cap layer 51 along the first direction X, and the fourth boundary J4 and the second boundary J2 are located on the other side of the first cap layer 51 along the first direction X.

[0093] In some embodiments, reference Figure 5 Along the first direction X, the third boundary J3 is farther from the center of the first cap layer 51 than the first boundary J1, and the fourth boundary J4 is farther from the center of the first cap layer 51 than the second boundary J2. That is, along one side of the first direction X, the second part 512 has an outwardly extending portion relative to the first part 511, and along the other side of the first direction X, the second part 512 also has an outwardly extending portion relative to the first part 511. Thus, the second part 512 has at least two outwardly extending portions relative to the first part 511, which is more conducive to dispersing the peak electric field, achieving the effect of improving the breakdown voltage, and is also more conducive to modulating the resistance of the channel.

[0094] In some embodiments, in conjunction with reference Figure 6 and Figure 7 Or, in conjunction with references Figure 8 and Figure 9The third boundary J3 overlaps with the first boundary J1 along the second direction Y, which is the thickness direction of the semiconductor device 100. Along the first direction X, the fourth boundary J4 is farther from the center of the first cap layer 51 than the second boundary J2. That is, the fourth boundary J4 of the second part 512 extends outward compared to the second boundary J2 of the first part 511. The outward extension of the second part 512 relative to the first part 511 can not only disperse the peak electric field and achieve the effect of improving the breakdown voltage, but also help to adjust the distribution density of the two-dimensional electron gas along the first direction X, thereby modulating the resistance of the channel, suppressing the interference of the drain electric field on the channel, and making the threshold voltage more stable and easier to adjust. The first part 511 has a small size along the first direction, which helps to accurately control the electric field distribution of the channel layer 20.

[0095] For example, in conjunction with reference Figure 6 and Figure 7 The third boundary J3 and the first boundary J1 are located on the side closer to the first source 61, and the fourth boundary J4 and the second boundary J2 are located on the side closer to the first drain 62.

[0096] For example, in conjunction with reference Figure 8 and Figure 9 The third boundary J3 and the first boundary J1 are located on the side closer to the first drain 62, and the fourth boundary J4 and the second boundary J2 are located on the side closer to the first source 61.

[0097] In some embodiments, reference Figure 2 or Figure 3 The dimensions of the first portion 511 along the first direction X are equal to the dimensions of the second portion 512 along the first direction X, which is perpendicular to the thickness direction of the semiconductor device 100. Thus, when current flows through the first cap layer 51, since the cross-sectional area of ​​the conductive path in the first portion 511 is the same as that in the second portion 512, the current is more evenly distributed between the two portions, thus avoiding localized overheating. Secondly, it also helps to ensure that the depletion effect of the first cap layer 51 on the underlying two-dimensional electron gas is consistent, thereby making the depletion effect of the first cap layer 51 on the two-dimensional electron gas more balanced.

[0098] In some embodiments, in conjunction with reference Figure 10 and Figure 11The first cap layer 51 includes: a first surface m1 and a second surface m2 disposed opposite to each other along a second direction Y; at least one side surface m3 connecting the first surface m1 and the second surface m2; the second surface m2 contacting the bottom surface of the first groove C1; and the second direction Y being the thickness direction of the semiconductor device; wherein at least one side surface m3 is in contact with the groove wall of the first groove C1. That is, at least one side surface m3 of the first cap layer 51 is in direct contact with the barrier layer 30, which avoids the need for additional etching steps, thereby preventing damage to the sidewalls of the barrier layer 30 and improving the crystal quality of the barrier layer 30.

[0099] In this case, at least one side surface m3 is in contact with the groove wall of the first groove C1, including the case where a portion of a side surface of the first cap layer 51 near the barrier layer 30 is in contact with the groove wall of the first groove C1, such as... Figure 9 As shown, the side surface m3 of the first portion 511 of the first cap layer 51 is in contact with the groove wall of the first groove C1.

[0100] In other embodiments, in conjunction with reference to Figure 10 and Figure 11 Along the first direction X, at least a portion of at least one side surface m3 is spaced from the wall of the first groove C1, and the first direction X is perpendicular to the second direction Y. That is, at least one side surface m3 of the first cap layer 51 is spaced from the side wall of the first groove C1 of the barrier layer 30. Since the first cap layer 51 and the side wall of the first groove C1 of the barrier layer 30 form a physical isolation, when a voltage is applied to the first gate 41, the electric field can be prevented from extending directly to the drain region through the first cap layer 51, forming an electric field coupling path, which would lead to an increase in switching losses.

[0101] For example, in conjunction with reference Figure 10 and Figure 11 Or, in conjunction with references Figure 12 and Figure 13 Along the first direction X, there is a gap between a side surface m3 of the first cap layer 51 and the sidewall of the first groove C1 of the barrier layer 30.

[0102] For example, in conjunction with reference Figure 10 and Figure 11 The distance between the side surface m3 and the side wall of the first groove C1 of the barrier layer 30 is set on the side of the first groove C1 near the first drain electrode 62.

[0103] For example, in conjunction with reference Figure 12 and Figure 13 The distance between the side surface m3 and the side wall of the first groove C1 of the barrier layer 30 is set on the side of the first groove C1 near the first source electrode 61.

[0104] For example, in conjunction with reference Figure 14 and Figure 15 Along the first direction X, there is a gap between the two side surfaces m3 of the first cap layer 51 and the sidewall of the first groove C1 of the barrier layer 30.

[0105] For example, in conjunction with reference Figure 16 and Figure 17 The first cap layer 51 includes a first portion 511 and a second portion 512 connected to each other. The first portion 511 is disposed in the first groove C1, and the second portion 512 is disposed on the side of the first portion 511 away from the barrier layer 30. At least one side surface m3 includes a first sub-surface m31 and a second sub-surface m32 arranged circumferentially along the first cap layer 51. The first sub-surface m31 is in contact with the groove wall of the first groove C1. The second sub-surface m32 has a distance from the groove wall of the first groove C1 in the first direction X.

[0106] The first sub-surface m31 is stepped, and the stepped surface of the first sub-surface m31 overlaps with the surface of the barrier layer 30 away from the channel layer 20; the second sub-surface m32 is a surface perpendicular to the first direction X. Since the stepped surface of the first sub-surface m31 overlaps with the surface of the barrier layer 30 away from the channel layer 20, that is, along the first direction X, the first cap layer 51 has an extension relative to the first groove C1. The extension can gate the two-dimensional electron gas channel and directly modulate the channel resistance through the voltage of the first gate 41. In addition, since the edge of the first gate 41 is a region of concentrated electric field, the high concentration of two-dimensional electron gas will aggravate the electric field peak. By making the second sub-surface m32 and the groove wall of the first groove C1 have a gap in the first direction X, the concentration of two-dimensional electron gas at the edge of the first gate 41 can be reduced, thereby reducing the electric field peak at the edge of the first gate 41, smoothing the electric field distribution, avoiding leakage or breakdown of the first gate 41, and improving the reliability of the first gate 41.

[0107] The above-mentioned "at least one side surface m3 includes a first sub-surface m31 and a second sub-surface m32 arranged circumferentially along the first cap layer 51" means that the first sub-surface m31 and the second sub-surface m32 can be interconnected sub-surfaces or unconnected sub-surfaces, for example, the first sub-surface m31 and the second sub-surface m32 are opposite sub-surfaces.

[0108] In other embodiments, reference is made to... Figure 18 The barrier layer 30 includes a main body portion 31 and a protrusion portion 32 stacked and connected along a second direction Y, wherein the protrusion portion 32 is farther away from the channel layer 20 than the main body portion 31, and the second direction Y is the thickness direction of the semiconductor device 100; a second cap layer 52 is disposed on the side of the protrusion portion 32 away from the main body portion 31, and a first cap layer 51 is disposed on the side of the main body portion 31 away from the channel layer 20.

[0109] Since the thickness of the barrier layer 30 between the first cap layer 51 and the channel layer 20 is equal to the thickness of the main body 31, and the thickness of the barrier layer 30 between the second cap layer 52 and the channel layer 20 is equal to the sum of the thicknesses of the main body 31 and the protruding portion 32, the thickness of the portion of the barrier layer 30 between the first cap layer 51 and the channel layer 20 is less than the thickness of the portion of the barrier layer 30 between the second cap layer 52 and the channel layer 20. This allows the high work function of the first cap layer 51 to fully deplete the two-dimensional electron gas between the first cap layer 51 and the channel layer 20, achieving… Enhancement mode; however, due to the thickness of the barrier layer 30 between the second cap layer 52 and the channel layer 20, the depletion effect of the second cap layer 52 is weakened due to its distance from the channel layer 20, resulting in the two-dimensional electron gas between the barrier layer 30 at the bottom of the second cap layer 52 and the channel layer 20 not being completely depleted, thus achieving depletion mode; therefore, the semiconductor device provided in this embodiment can achieve functional differentiation on the same substrate 10 by simply modulating the thickness of the barrier layer 30, thereby taking into account both high frequency response and high current drive capability, and realizing monolithic integration of enhancement mode and depletion mode.

[0110] Embodiments of this disclosure also provide a method for fabricating a semiconductor device, referencing... Figure 19 This includes the following steps:

[0111] Step S1: Refer to the reference Figure 20 and Figure 21 A nucleation layer 80, a buffer layer 90, a channel layer 20, and a barrier layer 30 are sequentially formed on the substrate 10.

[0112] Step S1 includes steps S11 and S12.

[0113] Step S11: Refer to Figure 20 A nucleation layer 80, a buffer layer 90, a channel layer 20, and an initial barrier layer 300 are sequentially formed on the substrate 10.

[0114] Here, the process for forming the nucleation layer 80, buffer layer 90, channel layer 20 and initial barrier layer 300 includes metal-organic chemical vapor deposition (MOCVD).

[0115] Step S12: Reference Figure 21 A first groove C1 is formed on the surface of the initial barrier layer 300 away from the channel layer 20, so that the initial barrier layer 30 forms a barrier layer 30, and the first groove C1 is located in the first region Q1.

[0116] The semiconductor device 100 includes a first region Q1 and a second region Q2 arranged in a first direction X, the first direction X being perpendicular to the second direction Y, and the second direction Y being the thickness direction of the semiconductor device.

[0117] Step S2: Refer to the reference Figure 22 and Figure 23 A first cap layer 51 and a second cap layer 52 are formed on the side of the barrier layer 30 away from the channel layer 20.

[0118] Here, at least a portion of the first cap layer 51 is disposed within the first groove C1, and the first cap layer 51 is located in the first region Q1, while the second cap layer 52 is located in the second region Q2.

[0119] Step S2 includes: Step S21 and Step S22.

[0120] Step S21: Reference Figure 22 An initial cap layer 50 is formed on the side of the barrier layer 30 away from the channel layer 20. The initial cap layer 50 fills the first groove C1 and covers the surface of the barrier layer 30 away from the channel layer 20.

[0121] Step S22: Reference Figure 23 A portion of the initial cap layer 50 is removed to form a first cap layer 51 and a second cap layer 52 spaced apart.

[0122] In some embodiments, reference Figure 23 The first cap layer 51 includes a first part 511 and a second part 512 connected to each other. The first part 511 is disposed in the first groove C1, and the second part 512 is disposed on the side of the first part 511 away from the barrier layer 30.

[0123] In other embodiments, reference is made to... Figure 23 The second part 512 also extends to the side surface of the barrier layer 30 away from the channel layer.

[0124] In some embodiments, step S2 further includes:

[0125] Step S23: Reference Figure 24 At least one sidewall of the first cap layer 51 is etched so that at least a portion of at least one side surface of the first cap layer 51 has a gap with the groove wall of the first groove C1.

[0126] Step S3: Reference Figure 25 A gate layer 40 is formed; the gate layer 40 includes a first gate 41 and a second gate 42 disposed at intervals; the first gate 41 is disposed on the side of the first cap layer 51 away from the barrier layer 30, and the second gate 42 is disposed on the side of the second cap layer 52 away from the barrier layer 30; wherein, the thickness of the portion of the barrier layer 30 located between the first cap layer 51 and the channel layer 20 is less than the thickness of the portion of the barrier layer 30 located between the second cap layer 52 and the channel layer 20.

[0127] Step S4: Reference Figure 25This forms the first source 61, the first drain 62, the second source 71, and the second drain 72.

[0128] The first source 61 and the first drain 62 are located in the first region Q1 and are disposed on the barrier layer 30, and are respectively located on opposite sides of the first cap layer 51 in the first direction X; the second source 71 and the second drain 72 are located in the second region Q2 and are disposed on the barrier layer 30, and are respectively located on opposite sides of the second cap layer 52 in the first direction X.

[0129] Step S5: Reference Figure 25 This forms an isolation structure G.

[0130] The isolation structure G is located between the first region Q1 and the second region Q2 to block the transmission of two-dimensional electron gas between the first region Q1 and the second region Q2.

[0131] In some embodiments, the process for forming the isolation structure G includes an etching process. The isolation structure G penetrates at least a portion of the barrier layer 30 along the second direction Y.

[0132] For example, such as Figure 25 As shown, the isolation structure G penetrates the barrier layer 30 and part of the channel layer 20 along the second direction Y.

[0133] In other embodiments, the process of forming the isolation structure G includes an ion implantation process, which can disrupt the conductivity of the barrier layer 30 to form a high-resistivity region to block the transport of two-dimensional electron gas between the first region Q1 and the second region Q2.

[0134] In other embodiments, during the formation of the first cap layer 51 and the second cap layer 52 on the side of the barrier layer 30 away from the channel layer 20, the channel structure G is formed simultaneously, and the isolation structure G is made of the same material as the first cap layer 51.

[0135] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer and a barrier layer are stacked on the substrate, wherein the barrier layer is farther away from the substrate than the channel layer; A gate layer is disposed on the side of the barrier layer away from the channel layer; the gate layer includes a first gate and a second gate disposed at a distance from each other. A first cap layer is disposed between the first gate and the barrier layer; The second cap layer is disposed between the second gate and the barrier layer; Wherein, the thickness of the barrier layer between the first cap layer and the channel layer is less than the thickness of the barrier layer between the second cap layer and the channel layer; A first groove is formed on the surface of the barrier layer away from the channel layer. The first cap layer includes a first part and a second part connected to each other. The first part is disposed in the first groove, and the second part is disposed on the side of the first part away from the barrier layer. The dimension of the first part along the first direction is smaller than the dimension of the second part along the first direction, and the first direction is perpendicular to the thickness direction of the semiconductor device. The first cap layer includes: a first surface and a second surface disposed opposite to each other along a second direction, the second direction being the thickness direction of the semiconductor device; the first cap layer further includes: at least one side surface connecting the first surface and the second surface; The at least one side surface includes a first sub-surface and a second sub-surface arranged circumferentially along the first cap layer; the first sub-surface is in contact with the groove wall of the first groove; the second sub-surface and the groove wall of the first groove are spaced apart in the first direction; The first sub-surface is stepped, and the stepped surface of the first sub-surface overlaps the surface of the barrier layer away from the channel layer; the second sub-surface is a surface perpendicular to the first direction.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the barrier layer between the first cap layer and the channel layer is a first thickness, and the thickness of the barrier layer between the second cap layer and the channel layer is a second thickness, wherein the difference between the second thickness and the first thickness ranges from 5 nm to 20 nm.

3. The semiconductor device according to claim 1, characterized in that, Along the first direction, the first part has a first boundary and a second boundary, the second part has a third boundary and a fourth boundary, and the third boundary and the first boundary are located on one side of the first cap layer along the first direction, and the fourth boundary and the second boundary are located on the other side of the first cap layer along the first direction. Wherein, along the first direction, the third boundary is farther from the center of the first cap layer than the first boundary, and the fourth boundary is farther from the center of the first cap layer than the second boundary; or, the third boundary overlaps with the first boundary along a second direction, the second direction being the thickness direction of the semiconductor device, and along the first direction, the fourth boundary is farther from the center of the first cap layer than the second boundary.

4. The semiconductor device according to claim 1, characterized in that, The barrier layer includes: a main body portion and a protruding portion stacked and connected along a second direction, wherein the protruding portion is farther away from the channel layer than the main body portion, and the second direction is the thickness direction of the semiconductor device; The second cap layer is disposed on the side of the protrusion away from the main body, and the first cap layer is disposed on the side of the main body away from the channel layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The dimension of the first cap layer in the second direction is greater than the dimension of the second cap layer in the second direction, where the second direction is the thickness direction of the semiconductor device.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device includes a first region and a second region arranged along a first direction, the first direction being perpendicular to the second direction, and the second direction being the thickness direction of the semiconductor device. The first cap layer and the first gate are located in the first region, and the second cap layer and the second gate are located in the second region; The semiconductor device further includes: The first source and the first drain, located in the first region, are disposed on the barrier layer and are respectively located on opposite sides of the first cap layer in the first direction; The second source and the second drain, located in the second region, are disposed on the barrier layer and are respectively located on opposite sides of the second cap layer in the first direction; An isolation structure is disposed between the first region and the second region, and extends through at least a portion of the barrier layer along the second direction.

7. The semiconductor device according to claim 6, characterized in that, A second groove is formed on the surface of the barrier layer away from the channel layer, and the isolation structure is disposed in the second groove; Wherein, the bottom surface of the second groove is closer to the substrate than the surface of the channel layer that is farther from the substrate; or... The bottom surface of the second groove is further away from the substrate than the surface of the channel layer that is further away from the substrate; the isolation structure has the same dimensions as the first cap layer in the second direction; the isolation structure is made of the same material as the first cap layer.

8. A chip, characterized in that, include: The semiconductor device as described in any one of claims 1 to 7; A packaging substrate, wherein the packaging substrate is coupled to the semiconductor device.

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