Apparatus and method for multiplication and accumulation of multi-tacked and real tacked data elements

Abstract

An apparatus and method for multiplication and addition of complex packed data and real packed data are disclosed. An example method includes multiplying a selected virtual data element in a first source register by a selected real data element in a second source register, and multiplying the selected real data element in the first source register by a selected virtual data element in the second source register to generate a plurality of virtual products; adding a first subset of the plurality of virtual products to generate a first temporary result, and adding a second subset of the plurality of virtual products to generate a second temporary result; performing negation on the first and second temporary results to generate third and fourth temporary results, respectively; accumulating the third temporary result with the first data from the destination register to generate a first final result, and accumulating the fourth temporary result with the second data from the destination register to generate a second final result; and storing the first and second final results back in the destination register.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 29, 2018, the priority date of September 29, 2017, the application number 201810996655.7, and the title “Device and method for multiplication and accumulation of complex packed data elements and real packed data elements”. Technical Field

[0002] Embodiments of the present invention generally relate to the field of computer processors. More particularly, these embodiments relate to apparatus and methods for multiplication and accumulation of imaginary packed data values ​​and real packed data values. Background Art

[0003] The instruction set or instruction set architecture (ISA) is the part of the computer architecture that involves programming, including native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O). It should be noted that the term "instruction" in this article generally refers to macroinstructions - that is, instructions provided to the processor for execution - rather than microinstructions or microoperations - that is, the microinstructions or microoperations are the result of the processor's decoder decoding the macroinstructions. Microinstructions or microoperations can be configured to instruct the execution units on the processor to perform operations to implement the logic associated with the macroinstructions.

[0004] ISA is different from microarchitecture, which is a collection of processor design technologies used to implement an instruction set. Processors with different microarchitectures can share a common instruction set. For example, Pentium 4 processor, Core TM (Core TM) processors, and multiple processors from Advanced Micro Devices, Inc. of Sunnyvale, California, implement nearly identical versions of the x86 instruction set (with some extensions added with newer versions), but have different internal designs. For example, the same register architecture of the ISA can be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a retirement register file). Unless otherwise specified, the phrases "register architecture," "register file," and "registers" are used herein to refer to the register architecture, register file, and registers that are visible to software / programmers and to how instructions specify registers. Where a distinction is needed, the adjectives "logical," "architectural," or "software-visible" will be used to refer to registers / register files in a register architecture, while different adjectives will be used to specify registers (e.g., physical registers, reorder buffers, retirement registers, register pools) in a given microarchitecture.

[0005] Multiply-accumulate is a common digital signal processing operation that computes the product of two numbers and adds the product to an accumulated value. Existing single-instruction, multiple-data (SIMD) microarchitectures implement multiply-accumulate operations by executing a sequence of instructions. For example, a multiply-accumulate can be performed using a multiply instruction, followed by a 4-way add, and then an accumulate using the destination quadword data to generate two 64-bit saturated results. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A better understanding of the present invention may be obtained from the following detailed description in conjunction with the following drawings, in which:

[0007] Figure 1A and Figure 1B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention;

[0008] Figure 2A-2C is a block diagram illustrating an exemplary VEX instruction format according to an embodiment of the present invention;

[0009] Figure 3 is a block diagram of a register architecture according to one embodiment of the present invention; and

[0010] Figure 4A is a block diagram illustrating both an exemplary in-order fetch, decode, and retirement pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0011] Figure 4B is a block diagram illustrating an exemplary embodiment of an in-order fetch, decode, retirement core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to an embodiment of the present invention;

[0012] Figure 5A is a block diagram of a single processor core and its connection to the on-die interconnect network;

[0013] Figure 5B FIG. 1 shows an embodiment of the present invention Figure 5A An expanded view of the processor core portion;

[0014] Figure 6 is a block diagram of a single-core processor and a multi-core processor with an integrated memory controller and graphics device according to an embodiment of the present invention;

[0015] Figure 7 FIG. 1 shows a block diagram of a system according to an embodiment of the present invention;

[0016] Figure 8 FIG. 1 shows a block diagram of a second system according to an embodiment of the present invention;

[0017] Figure 9 FIG. 1 shows a block diagram of a third system according to an embodiment of the present invention;

[0018] Figure 10 FIGURE 1 illustrates a block diagram of a system on a chip (SoC) according to an embodiment of the present invention;

[0019] Figure 11 Figure illustrates a block diagram comparing the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention;

[0020] Figure 12 illustrates a processor architecture upon which embodiments of the present invention may be implemented;

[0021] Figure 13 Figure illustrates a plurality of packed data elements containing real and complex values ​​according to one embodiment;

[0022] Figures 14A-14B Illustrated is one embodiment of an architecture for multiplying and accumulating the real and imaginary parts of complex numbers;

[0023] Figure 15 illustrates a method according to one embodiment of the present invention; and

[0024] Figure 16 The figure shows a method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0025] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention described below. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the present invention.

[0026] Exemplary processor architectures, instruction formats, and data types

[0027] An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, bit positions) to specify the operation to be performed (opcode) and the operand(s) on which the operation is to be performed. Some instruction formats are further broken down by the definition of instruction templates (or subformats). For example, instruction templates for a given instruction format can be defined to have different subsets of the fields of that instruction format (the included fields are generally in the same order, but at least some fields have different bit positions because fewer fields are included), and / or to have given fields interpreted differently. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, according to a given one of the instruction templates for that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD (addition) instruction has a specific opcode and instruction format, including an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2). The occurrence of this ADD instruction in an instruction stream will cause the operand field to have specific content that selects a specific operand.

[0028] The embodiments of the instruction(s) described herein can be embodied in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. The embodiments of the instruction(s) can be executed on such systems, architectures, and pipelines, but are not limited to those described in detail.

[0029] Generic vector-friendly instruction format

[0030] The vector friendly instruction format is an instruction format suitable for vector instructions (e.g., there are specific fields dedicated to vector operations). Although embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations through the vector friendly instruction format.

[0031] Figure 1A-1B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention. Figure 1Ais a block diagram illustrating a general vector friendly instruction format and its class A instruction template according to an embodiment of the present invention; and Figure 1B 1 is a block diagram illustrating a generic vector friendly instruction format and its class B instruction templates according to an embodiment of the present invention. Specifically, class A and class B instruction templates are defined for the generic vector friendly instruction format 100, both of which include instruction templates without memory access 105 and instruction templates with memory access 120. The term "generic" in the context of the vector friendly instruction format refers to an instruction format that is not tied to any particular instruction set.

[0032] Although embodiments of the present invention will be described in which the vector friendly instruction format supports: 64-byte vector operand length (or size) with 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, a 64-byte vector consists of 16 doubleword-sized elements, or alternatively, 8 quadword-sized elements); 64-byte vector operand length (or size) with 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); 32-byte vector operand length (or size) with 32-bit (4-byte) or 64-bit (8-byte) data element width (or size); byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); and 16-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); however, alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., 256-byte vector operands) and larger, smaller, or different data element widths (e.g., 128-bit (16-byte) data element width).

[0033] Figure 1A The Class A instruction templates include: 1) within the instruction templates without memory access 105, there are shown instruction templates for full rounding control type operations 110 without memory access and instruction templates for data transformation type operations 115 without memory access; and 2) within the instruction templates with memory access 120, there are shown instruction templates for temporal memory access 125 and instruction templates for non-temporal memory access 130. Figure 1B The Class B instruction templates include: 1) within the instruction template without memory access 105, an instruction template for a partial rounding control type operation 112 with write mask control without memory access and an instruction template for a vsize type operation 117 with write mask control without memory access; and 2) within the instruction template without memory access 120, an instruction template for a write mask control 127 with memory access.

[0034] The generic vector friendly instruction format 100 includes the following listed in accordance with Figures 1A-1B The following fields are in the order shown in the figure.

[0035] Format field 140 - The specific value in this field (the instruction format identifier value) uniquely identifies the vector friendly instruction format, and thus identifies that the instruction appears in the vector friendly instruction format in the instruction stream. Thus, this field is optional in the sense that it is not required for instruction sets that only have the general vector friendly instruction format.

[0036] Basic operation field 142 - its content distinguishes different basic operations.

[0037] Register index field 144 - its contents specify the location of the source or destination operand in a register or in memory, either directly or through address generation. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N may be up to three source registers and one destination register, alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources may be supported, one of which may also serve as a destination; up to three sources may be supported, one of which may also serve as a destination; up to two sources and one destination may be supported).

[0038] Modifier field 146 - its content distinguishes instructions appearing in the generic vector instruction format that specify memory access from instructions appearing in the generic vector instruction format that do not specify memory access; that is, between instruction templates with no memory access 105 and instruction templates with memory access 120. Memory access operations read and / or write to the memory hierarchy (in some cases, using values ​​in registers to specify source and destination addresses), while non-memory access operations do not (e.g., the source and / or destination are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, fewer, or different ways to perform memory address calculations.

[0039] Extended Operation Field 150 - Its contents distinguish which of various operations are to be performed in addition to the base operation. This field is context-specific. In one embodiment of the present invention, this field is divided into a class field 168, an alpha field 152, and a beta field 154. Extended Operation Field 150 allows for common groups of operations to be performed in a single instruction rather than two, three, or four instructions.

[0040] Scale field 160 - its content allows for memory address generation (e.g., for use with (2 比例 * The address of (index + base address) is generated by scaling the contents of the index field.

[0041] Displacement field 162A - its contents are used as part of memory address generation (e.g., for use with (2 比例 *Address generation of (index + base address + displacement).

[0042] Displacement Factor field 162B (note that the concatenation of displacement field 162A directly over displacement factor field 162B indicates that one or the other is used) - its contents are used as part of address generation; it specifies the displacement factor by which the size (N) of the memory access will be scaled - where N is the number of bytes in the memory access (e.g., for use with (2 比例 * index + base address + scaled displacement). Redundant low-order bits are ignored, and therefore the contents of the displacement factor field are multiplied by the total size of the memory operand (N) to generate the final displacement to be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 174 (described later herein) and the data manipulation field 154C. The displacement field 162A and the displacement factor field 162B are optional in the sense that they are not used in instruction templates without memory access 105 and / or different embodiments may implement only one or neither of the two.

[0043] Data element width field 164 - its contents distinguish which of multiple data element widths will be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or some aspect of the opcode is used to support the data element width.

[0044] Writemask field 170—its contents control, on a per-data-element-position basis, whether the data element positions in the destination vector operand reflect the results of the base and augmented operations. Class A instruction templates support merge-writemasking, while class B instruction templates support both merge-writemasking and zero-writemasking. When merged, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base and augmented operations); in another embodiment, the old value of each element of the destination where the corresponding mask bit has a 0 is preserved. Conversely, when zeroed, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and augmented operations); in one embodiment, elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified); however, the modified elements do not necessarily have to be contiguous. Thus, writemask field 170 allows for partial vector operations, including loads, stores, arithmetic, logical, and more. Although embodiments of the present invention are described in which the contents of write mask field 170 select one of a plurality of write mask registers that contains a write mask to be used (and thereby, the contents of write mask field 170 indirectly identify the masking to be performed), alternative embodiments alternatively or additionally allow the contents of mask write field 170 to directly specify the masking to be performed.

[0045] Immediate field 172 - its contents allow specification of an immediate value. This field is optional in the sense that it is not present in implementations that do not support the generic vector friendly format for immediate values ​​and is not present in instructions that do not use immediate values.

[0046] Class field 168 - its content distinguishes between instructions of different classes. Figure 1A-1B , the content of this field selects between class A and class B instructions. Figure 1A-1B In , a rounded square is used to indicate that a specific value exists in a field (for example, in Figure 1A-1B 168A and B, respectively, for class field 168).

[0047] Class A instruction template

[0048] In the case of the class A non-memory access 105 instruction templates, the α field 152 is interpreted as an RS field 152A whose content distinguishes which of the different augmented operation types is to be performed (e.g., round 152A.1 and data transform 152A.2 are specified for the instruction templates for the no-memory access round operation 110 and the no-memory access data transform operation 115, respectively), while the β field 154 distinguishes which of the specified types of operations is to be performed. In the no-memory access 105 instruction templates, the scale field 160, the displacement field 162A, and the displacement scale field 162B are not present.

[0049] Instruction templates with no memory access – fully rounded control type operations

[0050] In the instruction templates for the no-memory-access, fully round-controlled operation 110, the beta field 154 is interpreted as a round control field 154A that provides static rounding for its contents. Although in the described embodiment of the invention the round control field 154A includes a suppress all floating-point exceptions (SAE) field 156 and a round operation control field 158, alternative embodiments may support both concepts, may encode both concepts into the same field, or may have only one or the other of these concepts / fields (e.g., may have only the round operation control field 158).

[0051] SAE field 156 - its content distinguishes whether exception event reporting is disabled; when the content of SAE field 156 indicates that suppression is enabled, the given instruction does not report any kind of floating point exception flags and does not invoke any floating point exception handler.

[0052] Round operation control field 158 - its contents distinguish which of a set of rounding operations is to be performed (e.g., round up, round down, round toward zero, and round to nearest). Thus, round operation control field 158 allows the rounding mode to be changed on an instruction-by-instruction basis. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the contents of round operation control field 150 override the register value.

[0053] Instruction templates without memory access - data transformation operations

[0054] In instruction templates for data transform type operations 115 without memory access, the beta field 154 is interpreted as a data transform field 154B, the contents of which distinguish which of multiple data transforms is to be performed (eg, no data transform, blend, broadcast).

[0055] In the case of an instruction template of type A memory access 120, the alpha field 152 is interpreted as an eviction hint field 152B, the contents of which distinguish which of the eviction hints is to be used (in Figure 1A In the example, the instruction templates for memory access temporal 125 and memory access non-temporal 130 specify temporal 152B.1 and non-temporal 152B.2, respectively, while the beta field 154 is interpreted as a data manipulation field 154C, the contents of which distinguish which of a plurality of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation, broadcast, upcast of the source, and downcast of the destination). The instruction templates for memory access 120 include a scale field 160 and optionally a displacement field 162A or a displacement scale field 162B.

[0056] Vector memory instructions use the translation support to perform vector loads from memory and vector stores to memory. Like normal vector instructions, vector memory instructions transfer data to and from memory in an element-wise manner, where the actual elements transferred are specified by the contents of the vector mask selected as the writemask.

[0057] Memory access instruction templates - time-sensitive

[0058] Temporal data is data that is likely to be reused quickly enough to benefit from cache operations. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0059] Memory access instruction templates - non-temporal

[0060] Non-temporal data is data that is unlikely to be reused quickly enough to benefit from cache operations in the first level cache and should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0061] Class B instruction template

[0062] In the case of class B instruction templates, the alpha field 152 is interpreted as a writemask control (Z) field 152C, the contents of which distinguish whether the writemask controlled by the writemask field 170 should be merge or zero.

[0063] In the case of the class B non-memory access 105 instruction templates, a portion of the β field 154 is interpreted as the RL field 157A, the contents of which distinguish which of the different augmented operation types is to be performed (e.g., the instruction templates for the no-memory-access write mask control partial rounding control type operation 112 and the instruction templates for the no-memory-access write mask control VSIZE type operation 117 specify rounding 157A.1 and vector length (VSIZE) 157A.2, respectively), while the remainder of the β field 154 distinguishes which of the specified types of operations is to be performed. In the no-memory-access 105 instruction templates, the scale field 160, the displacement field 162A, and the displacement scale field 162B are not present.

[0064] In the instruction template for the write mask control partial round control type operation 110 without memory access, the remainder of the beta field 154 is interpreted as the round operation field 159A, and exception event reporting is disabled (the given instruction does not report any kind of floating point exception flag and does not invoke any floating point exception handler).

[0065] Round Operation Control Field 159A - As with round operation control field 158, its contents distinguish which of a set of rounding operations (e.g., round up, round down, round toward zero, and round to nearest) is to be performed. Thus, round operation control field 159A allows the rounding mode to be changed on an instruction-by-instruction basis. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the contents of round operation control field 159A override the register value.

[0066] In the instruction template for the write mask control VSIZE type operation 117 without memory access, the remainder of the β field 154 is interpreted as a vector length field 159B, the contents of which distinguish which of multiple data vector lengths is to be performed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0067] In the case of a class B memory access 120 instruction template, a portion of the beta field 154 is interpreted as a broadcast field 157B, the contents of which distinguish whether a broadcast-type data manipulation operation is to be performed, while the remainder of the beta field 154 is interpreted as a vector length field 159B. The memory access 120 instruction template includes a scale field 160 and optionally includes a displacement field 162A or a displacement scale field 162B.

[0068] For the generic vector friendly instruction format 100, the full opcode field 174 is shown to include the format field 140, the base operation field 142, and the data element width field 164. Although one embodiment is shown in which the full opcode field 174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 174 includes less than all of these fields. The full opcode field 174 provides an operation code (opcode).

[0069] The augment operation field 150, the data element width field 164, and the write mask field 170 allow these features to be specified on an instruction-by-instruction basis in the generic vector friendly instruction format.

[0070] The combination of the write mask field and the data element width field creates various types of instructions because these instructions allow the mask to be applied based on different data element widths.

[0071] The various instruction templates found within classes A and B are beneficial in different situations. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both general-purpose computing and graphics and / or scientific (throughput) computing may support both classes A and B (of course, cores with some mix of templates and instructions from both classes, but not all templates and instructions from both classes, are within the scope of the present invention). Similarly, a single processor may include multiple cores, all of which support the same class, or where different cores support different classes. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more of the general-purpose cores may be a high-performance general-purpose core with out-of-order execution and register renaming intended for general-purpose computing that supports only class B. Another processor that does not have a separate graphics core may include one or more general-purpose in-order or out-of-order cores that support both Class A and Class B. Of course, in different embodiments of the invention, features from one class may also be implemented in the other class. A program written in a high-level language will be made (e.g., just-in-time or statically compiled) into a variety of different executable forms, including: 1) a form with only instructions of the class(es) supported by the target processor for execution; or 2) a form with alternative routines written using different combinations of instructions from all classes and with control flow code that selects these routines to execute based on the instructions supported by the processor currently executing the code.

[0072] VEX instruction format

[0073] VEX encoding allows instructions with more than two operands and allows SIMD vector registers to be longer than 28 bits. The use of the VEX prefix provides a three-operand (or more operand) syntax. For example, previous two-operand instructions performed operations such as A=A+B that overwrote the source operand. The use of the VEX prefix enables non-destructive operations such as A=B+C.

[0074] Figure 2A An exemplary AVX instruction format is shown, including a VEX prefix 202 , a real opcode field 230 , a Mod R / M byte 240 , a SIB byte 250 , a displacement field 262 , and an IMM8 272 . Figure 2B The diagram shows the Figure 2A Which fields constitute the complete operation code field 274 and the basic operation field 241. Figure 2C The diagram shows the Figure 2A Which fields of constitute the register index field 244.

[0075] The VEX prefix (bytes 0-2) 202 is encoded in three bytes. The first byte is the format field 290 (VEX byte 0, bits [7:0]), which contains the explicit C4 byte value (a unique value used to distinguish the C4 instruction format). The second and third bytes (VEX bytes 1-2) include several bit fields that provide special capabilities. Specifically, the REX field 205 (VEX byte 1, bits [7-5]) consists of the VEX.R bit field (VEX byte 1, bits [7]-R), the VEX.X bit field (VEX byte 1, bits [6]-X), and the VEX.B bit field (VEX byte 1, bits [5]-B). The other fields of these instructions encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, so that Rrrr, Xxxx, and Bbbb can be formed by adding VEX.R, VEX.X, and VEX.B. The opcode map field 215 (VEX byte 1, bits [4:0]–mmmmm) includes content for encoding the implied leading opcode byte. The W field 264 (VEX byte 2, bits [7]–W) is represented by the notation VEX.W and provides different functionality depending on the instruction. The effects of VEX.vvvv 220 (VEX byte 2, bits [6:3]–vvvv) may include the following: 1) VEX.vvvv encodes the first source register operand specified in inverted (1's complement) form and is valid for instructions with two or more source operands; 2) VEX.vvvv encodes the destination register operand specified in 1's complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand and is reserved and should contain 1111b. If the VEX.L 268 size field (VEX byte 2, bit [2]-L) = 0, it indicates a 28-bit vector; if VEX.L = 1, it indicates a 256-bit vector. The prefix encoding field 225 (VEX byte 2, bits [1:0]-pp) provides additional bits for the base operation field 241.

[0076] The real opcode field 230 (byte 3) is also called the opcode byte. A portion of the opcode is specified in this field.

[0077] The MOD R / M field 240 (byte 4) includes a MOD field 242 (bits [7-6]), a Reg field 244 (bits [5-3]), and an R / M field 246 (bits [2-0]). The Reg field 244 may be used to encode a destination register operand or a source register operand (Rrrr's rrr), or it may be treated as an opcode extension and not used to encode any instruction operand. The R / M field 246 may be used to encode an instruction operand that references a memory address, or it may be used to encode a destination register operand or a source register operand.

[0078] Scale, Index, Base (SIB) - The contents of the scale field 250 (byte 5) include SS 252 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 254 (bits [5-3]) and SIB.bbb 256 (bits [2-0]) have been previously mentioned for register indexes Xxxx and Bbbb.

[0079] The displacement field 262 and the immediate field (IMM8) 272 contain data.

[0080] Exemplary Register Architecture

[0081] Figure 3 is a block diagram of a register architecture 300 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 512-bit wide vector registers 310; these registers are referenced as zmm0 through zmm31. The lower-order 256 bits of the lower six zmm registers are overlaid on registers ymm0-15. The lower-order 128 bits of the lower six zmm registers (the lower-order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

[0082] General purpose registers 325 - In the embodiment shown, there are sixteen 64-bit general purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0083] A scalar floating-point stack register file (x87 stack) 345 on which an MMX packed integer flat register file 350 is overlaid—in the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension; while MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between MMX and XMM registers.

[0084] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0085] Exemplary Core Architectures, Processors, and Computer Architectures

[0086] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic or as dedicated cores, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip, which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture. Circuits (units) including example cores, processors, etc. are described in detail herein.

[0087] Exemplary Core Architecture

[0088] Figure 4A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register-renaming out-of-order issue / execution pipeline according to various embodiments of the present invention. Figure 4B is a block diagram illustrating an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention. Figure 4A-4B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optional addition of dashed line boxes illustrates the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0089] exist Figure 4A, processor pipeline 400 includes a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a rename stage 410, a schedule (also known as a dispatch or issue) stage 412, a register read / memory read stage 414, an execute stage 416, a write back / memory write stage 418, an exception handling stage 422, and a commit stage 424.

[0090] Figure 4B A processor core 490 is shown that includes a front end unit 430 coupled to an execution engine unit 450, and both the front end unit 430 and the execution engine unit 450 are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 490 can be a special-purpose core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0091] The front end unit 430 includes a branch prediction unit 432, which is coupled to an instruction cache unit 434, which is coupled to an instruction translation lookaside buffer (TLB) 436, which is coupled to an instruction fetch unit 438, which is coupled to a decode unit 440. The decode unit 440 (or decoder) can decode an instruction and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, or otherwise reflect, or are derived from, the original instruction. The decode unit 440 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, the core 490 includes a microcode ROM or other medium (e.g., in the decode unit 440 or otherwise within the front end unit 430) that stores microcode for certain macroinstructions. Decode unit 440 is coupled to rename / allocator unit 452 in execution engine unit 450 .

[0092] The execution engine unit 450 includes a rename / allocator unit 452 coupled to a retirement unit 454 and a set of one or more scheduler units 456. The scheduler unit(s) 456 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. The scheduler unit(s) 456 are coupled to physical register file(s) units 458. Each of the physical register file(s) units 458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating point, packed integers, packed floating point, vector integers, vector floating point, state (e.g., an instruction pointer, which is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file(s) units 458 include a vector register unit and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. Physical register file(s) unit(s) 458 are overlapped by retirement unit(s) 454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using reorder buffer(s) and retirement register file(s); using future file(s), history buffer(s), retirement register file(s); using register maps and register pools, etc.). Retirement unit(s) 454 and physical register file(s) unit(s) 458 are coupled to execution cluster(s) 460. Execution cluster(s) 460 include a set of one or more execution units 462 and a set of one or more memory access units 464. Execution units 462 can perform various operations (e.g., shifts, additions, subtractions, multiplications) and can operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scheduler unit(s) 456, physical register file(s) 458, and execution cluster(s) 460 are shown as potentially multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each with its own scheduler unit(s), physical register file(s) units, and / or execution cluster—and in the case of separate memory access pipelines, certain embodiments are implemented in which only the execution cluster of that pipeline has memory access unit(s) 464). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order.

[0093] A set of memory access units 464 is coupled to a memory unit 470, which includes a data TLB unit 472, which is coupled to a data cache unit 474, which is coupled to a level 2 (L2) cache unit 476. In one exemplary embodiment, the memory access unit 464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 472 in the memory unit 470. The instruction cache unit 434 is also coupled to a level 2 (L2) cache unit 476 in the memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and ultimately to main memory.

[0094] As an example, the exemplary register renaming out-of-order issue / execution core architecture may implement the pipeline 400 as follows: 1) instruction fetch 438 executes fetch stage 402 and length decode stage 404; 2) decode unit 440 executes decode stage 406; 3) rename / allocator unit 452 executes allocate stage 408 and rename stage 410; 4) (multiple) scheduler units 456 execute schedule stage 412; 5) (multiple) physical register file units 458 and memory units 470 execute register read / memory read stage 414; execution cluster 460 executes execute stage 416; 6) memory unit 470 and (multiple) physical register file units 458 execute write back / memory write stage 418; 7) various units may be involved in exception handling stage 422; and 8) retirement unit 454 and (multiple) physical register file units 458 execute commit stage 424.

[0095] Core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set from MIPS Technologies, Inc. of Sunnyvale, California; the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, California (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, core 490 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0096] It should be understood that a core may support multithreading (executing two or more sets of operations or threads in parallel) and that this multithreading may be accomplished in a variety of ways, including time-shared multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-shared fetch and decode and subsequent operations such as Hyper-Threading (Simultaneous Multithreading).

[0097] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiment of the processor also includes separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a first level (L1) internal cache or multiple levels of internal cache. In some embodiments, the system may include a combination of internal caches and external caches external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0098] Specific exemplary in-order core architecture

[0099] Figure 5A-5B A block diagram illustrating a more specific exemplary in-order core architecture is shown, which would be one logic block among several logic blocks in a chip (including other cores of the same and / or different types). Depending on the application, the logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0100] Figure 5A 5 is a block diagram of a single processor core and its connection to the on-die interconnect network 502 and its local subset 504 of the second level (L2) cache according to an embodiment of the present invention. In one embodiment, the instruction decoder 500 supports the x86 instruction set with the packed data instruction set extension. The L1 cache 506 allows low latency access to cache memory in the scalar and vector units. Although in one embodiment (to simplify the design), the scalar unit 508 and the vector unit 510 use separate register sets (scalar registers 512 and vector registers 514, respectively), and data transferred between these registers is written to memory and then read back from the first level (L1) cache 506, alternative embodiments of the present invention may use different approaches (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0101] The local subset 504 of the L2 cache is part of the global L2 cache, which is divided into multiple separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 504 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 504 and flushed from other subsets when necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. In some embodiments, each ring data path is 1024 bits wide in each direction.

[0102] Figure 5B According to an embodiment of the present invention Figure 5A An expanded view of a portion of a processor core in FIG. Figure 5B The L1 data cache 506A portion of the L1 cache 504 is included, as well as more details about the vector unit 510 and vector registers 514. Specifically, the vector unit 510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports blending of register inputs through blending unit 520, numerical conversion through numerical conversion units 522A-B, and copying of memory inputs through copy unit 524.

[0103] Processor with integrated memory controller and graphics device

[0104] Figure 6 is a block diagram of a processor 600 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present invention. Figure 6 The solid line box in the figure illustrates a processor 600 having a single core 602A, a system agent 610, a set 616 of one or more bus controller units, while the optional addition of the dashed line box illustrates an alternative processor 600 having multiple cores 602A-N, a set 614 of one or more integrated memory controller units in the system agent unit 610, and dedicated logic 608.

[0105] Thus, different implementations of processor 600 may include: 1) a CPU where specialized logic 608 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and cores 602A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor where cores 602A-N are a large number of specialized cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor where cores 602A-N are a large number of general-purpose in-order cores. Thus, processor 600 may be a general-purpose processor, a coprocessor, or a specialized processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-in-one (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. Processor 600 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0106] The memory hierarchy includes one or more cache levels within the cores 602A-N, a set of one or more shared cache units 606, and external memory (not shown) coupled to a set of integrated memory controller units 614. The set of shared cache units 606 may include one or more intermediate levels of cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 612 interconnects the integrated graphics logic 608, the set of shared cache units 606, and the system agent unit 610 / integrated memory controller unit(s) 614, alternative embodiments may use any number of well-known techniques to interconnect such units. In one embodiment, coherency is maintained between the one or more cache units 606 and the cores 602A-N.

[0107] In some embodiments, one or more cores 602A-N may be multithreaded. System agent 610 includes components that coordinate and operate cores 602A-N. System agent unit 610 may include, for example, a power control unit (PCU) and a display unit. The PCU may include or include the logic and components required to regulate the power state of cores 602A-N and integrated graphics logic 608. The display unit is used to drive one or more externally connected displays.

[0108] The cores 602A-N may be homogeneous or heterogeneous with respect to architectural instruction sets; that is, two or more of the cores 602A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0109] Exemplary Computer Architecture

[0110] Figure 7-10 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network appliances, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can include a processor and / or other execution logic as disclosed herein are generally suitable.

[0111] Now refer to Figure 7 , shown is a block diagram of a system 700 according to one embodiment of the present invention. System 700 may include one or more processors 710, 715 coupled to a controller hub 720. In one embodiment, controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input / output hub (IOH) 750 (which may be on separate chips); GMCH 790 includes memory and a graphics controller to which memory 740 and coprocessor 745 are coupled; and IOH 750 couples input / output (I / O) devices 760 to GMCH 790. Alternatively, one or both of the memory and graphics controller are integrated within the processor (as described herein), with memory 740 and coprocessor 745 coupled directly to processor 710, and controller hub 720 and IOH 750 being on a single chip.

[0112] The optional addition of processor 715 is Figure 7 Each processor 710 , 715 may include one or more of the processing cores described herein and may be a version of processor 600 .

[0113] The memory 740 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 720 communicates with the processor(s) 710, 715 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface, or similar connection 795.

[0114] In one embodiment, coprocessor 745 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 720 may include an integrated graphics accelerator.

[0115] There may be various differences between the physical resources 710 , 715 in terms of a range of quality metrics including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0116] In one embodiment, processor 710 executes instructions that control general types of data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 710 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 745. Accordingly, processor 710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 745 over a coprocessor bus or other interconnect. Coprocessor(s) 745 accept and execute the received coprocessor instructions.

[0117] Now see Figure 8 , shown is a block diagram of a first more specific exemplary system 800 according to an embodiment of the present invention. Figure 8 As shown in FIG, multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each of processors 870 and 880 may be a version of processor 600. In one embodiment of the present invention, processors 870 and 880 are processors 710 and 715, respectively, and coprocessor 838 is coprocessor 745. In another embodiment, processors 870 and 880 are processor 710 and coprocessor 745, respectively.

[0118] Processors 870 and 880 are shown as including integrated memory controller (IMC) units 872 and 882, respectively. Processor 870 also includes point-to-point (PP) interfaces 876 and 878 as part of its bus controller unit; similarly, second processor 880 includes PP interfaces 886 and 888. Processors 870, 880 can exchange information via PP interface 850 using point-to-point (PP) interface circuits 878, 888. Figure 8 As shown in FIG, IMCs 872 and 882 couple the processors to respective memories, namely, memory 832 and memory 834, which may be portions of main memory locally attached to the respective processors.

[0119] Processors 870, 880 may each exchange information with a chipset 890 via respective PP interfaces 852, 854 using point-to-point interface circuits 876, 894, 886, 898. Chipset 890 may optionally exchange information with a coprocessor 838 via a high-performance interface 892. In one embodiment, coprocessor 838 is a special-purpose processor such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

[0120] A shared cache (not shown) may be included in either processor, or external to both processors but connected to the processors via the PP interconnect, such that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0121] Chipset 890 may be coupled to first bus 816 via interface 896. In one embodiment, first bus 816 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or another I / O interconnect bus, although the scope of the invention is not limited in this regard.

[0122] like Figure 8 As shown in , various I / O devices 814 may be coupled to the first bus 816, along with a bus bridge 818 that couples the first bus 816 to a second bus 820. In one embodiment, one or more additional processors 815, such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 816. In one embodiment, the second bus 820 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 820, including, for example, a keyboard and / or mouse 822, communication devices 827, and a storage unit 828, such as a disk drive or other mass storage device, which may include instructions / code and data 830. Additionally, an audio I / O 824 may be coupled to the second bus 820. Note that other architectures are possible. For example, instead of Figure 8 Instead of a point-to-point architecture, the system can implement a multi-drop bus or other such architecture.

[0123] Now refer to Figure 9 , shown is a block diagram of a second more specific exemplary system 900 according to an embodiment of the present invention. Figure 8 and 9 Similar elements in the same reference numerals are used, and Figure 9 Omitted Figure 8Some aspects of Figure 9 other aspects.

[0124] Figure 9 The illustrated processors 870, 880 may include integrated memory and I / O control logic ("CL") 971 and 982, respectively. Thus, the CL 972, 982 includes an integrated memory controller unit and includes I / O control logic. Figure 9 The illustration shows not only memories 832, 834 coupled to CL 972, 982, but also I / O devices 914 coupled to control logic 972, 982. Legacy I / O devices 915 are coupled to chipset 890.

[0125] Now refer to Figure 10 , which shows a block diagram of a SoC 1000 according to an embodiment of the present invention. Figure 6 Similar elements in the FIGURE 1 use similar reference numerals. In addition, the dashed boxes are optional features on more advanced SoCs. Figure 10 , interconnect unit(s) 1002 are coupled to: an application processor 1010, which includes a set of one or more cores 602A-N, cache units 604A-N, and shared cache unit(s) 606; a system agent unit 610; bus controller unit(s) 616; integrated memory controller unit(s) 614; a set of one or more coprocessors 1020, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In one embodiment, coprocessor(s) 1020 include specialized processors such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor, among others.

[0126] The various embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0127] Program code (such as Figure 8The code 830 illustrated in FIG. 8 is applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0128] The program code can be implemented in a high-level process-oriented programming language or an object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented in assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0129] One or more aspects of at least one embodiment may be implemented as representative instructions stored on a machine-readable medium that represent various logic within a processor, which, when read by a machine, causes the machine to fabricate logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into fabrication machines that actually manufacture the logic or processor.

[0130] Such machine-readable storage media may include, but are not limited to, a non-transitory, tangible arrangement of an article of manufacture manufactured or formed by a machine or apparatus, including storage media such as a hard disk; any other type of disk, including a floppy disk, an optical disk, a compact disk read only memory (CD-ROM), a compact disk rewritable (CD-RW), and a magneto-optical disk; a semiconductor device, such as a read-only memory (ROM), a random access memory (RAM) such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), flash memory, an electrically erasable programmable read-only memory (EEPROM); a phase change memory (PCM); a magnetic or optical card; or any other type of medium suitable for storing electronic instructions.

[0131] Therefore, embodiments of the present invention also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. These embodiments are also referred to as program products.

[0132] Simulation (including binary conversion, code deformation, etc.)

[0133] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may transform (e.g., using static binary transformation, dynamic binary transformation including dynamic compilation), morph, emulate, or otherwise convert an instruction into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on-processor, off-processor, or partially on-processor and partially off-processor.

[0134] Figure 11 1 is a block diagram illustrating a method for converting binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 11 It is shown that a program in a high-level language 1102 can be compiled using a first compiler 1104 to generate a first binary code (e.g., x86) 1106 that can be natively executed by a processor 1116 having at least one first instruction set core. In some embodiments, the processor 1116 having at least one first instruction set core represents any processor that performs substantially the same functionality as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise performing: 1) an essential portion of the instruction set of the Intel x86 instruction set core, or 2) an object code version of an application or other software that is targeted to run on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The first compiler 1104 represents a compiler that can be operated to generate binary code 1106 (e.g., object code) in a first instruction set that can be executed on the processor 1116 having at least one first instruction set core with or without additional linking processing. Similarly, Figure 11An alternative instruction set compiler 1108 is shown to be used to compile a program in a high-level language 1102 to generate alternative instruction set binary code 1110 that can be natively executed by a processor 1114 that does not have at least one first instruction set core (e.g., a processor that has a core that executes the MIPS instruction set of MIPS Technologies, Inc., of Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Inc., of Sunnyvale, California). An instruction converter 1112 is used to convert the first binary code 1106 into code that can be natively executed by the processor 1114 that does not have the first instruction set core. This converted code is unlikely to be identical to the alternative instruction set binary code 1110 because an instruction converter that can do so is difficult to manufacture; however, the converted code will perform general operations and be composed of instructions from the alternative instruction set. Therefore, the instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code 1106 through simulation, emulation, or any other process.

[0135] Apparatus and method for digital signal processing instructions

[0136] The following describes digital signal processing (DSP) instructions. In one embodiment, the circuits and logic for performing DSP operations are integrated into Figure 4B The execution engine unit 450 shown in FIG is integrated into the various cores described above (see, for example, Figure 6 and Figure 10 Cores 602A-N in and / or Figure 5A For example, the various source and destination registers may be Figure 4B SIMD registers in the physical register file(s) unit 458 and / or Figure 3 The vector register 310 in the vector register 310. The multiplication circuit, adder circuit, accumulation circuit and other circuits described below can be integrated into the execution component of the architecture described above. As an example and not limitation, the execution component includes Figure 4B 4. However, it should be noted that the underlying principles of the invention are not limited to these particular architectures.

[0137] One embodiment of the present invention includes circuitry and / or logic for processing digital signal processing (DSP) instructions. Specifically, one embodiment includes a multiply-accumulate (MAC) architecture having eight 16×16-bit multipliers and two 64-bit accumulators. The instruction set architecture (ISA) described below can handle various multiplication and MAC operations on 128-bit packed (8-bit, 16-bit, or 32-bit data elements) integer, fixed-point, and complex data types. In addition, certain instructions have direct support for highly efficient fast Fourier transforms (FFTs) and finite impulse response (FIR) filtering, as well as post-processing of accumulated data through shift, rounding, and saturation operations.

[0138] One embodiment of the new DSP instructions uses opcode encodings based on the VEX.128 prefix, and several of the SSE / SSE2 / AVX instructions that handle post-processing of data are used with the DSP ISA. VEX-encoded 128-bit DSP instructions with memory operands may have relaxed memory alignment requirements.

[0139] In one embodiment, the instruction also supports various integer and fixed-point data types, including:

[0140] 1) Q31 data types with more than 16 bits, used for signals requiring analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC);

[0141] 2) Q15 data type commonly used in DSP algorithms;

[0142] 3) 16-bit complex data type; and

[0143] 4) 32-bit complex data type.

[0144] The instruction set architecture described herein targets a wide range of standard DSP (eg, FFT, filtering, pattern matching, correlation, polynomial estimation, etc.) and statistical operations (eg, mean, moving average, variance, etc.).

[0145] Target applications of embodiments of the present invention include sensors, audio, classification tasks for computer vision, and speech recognition. The DSP ISA described herein includes a wide range of instructions suitable for deep neural networks (DNNs), automatic speech recognition (ASR), sensor fusion using Kalman filtering, and other major DSP applications. Given a weight sequence {w1, w2, ... w k} and the input sequence {x1,x2,x3,…x n Many image processing and machine learning tasks require the calculation of yi=w1x i +w2x i +1+…+wk x i +k-1 defines the resulting sequence {y1,y2,y3,…y n+1-k}.

[0146] Figure 12 The diagram illustrates an exemplary processor 1255 including multiple cores 0-N for executing multiple instruction threads simultaneously, upon which embodiments of the present invention may be implemented. The illustrated embodiment includes DSP instruction decoding circuitry / logic 1231 within decoder 1230 and DSP instruction execution circuitry / logic 1241 within execution unit 1240. These pipeline components may perform the operations described herein in response to decoding and executing DSP instructions. Although Figure 12 Only details of a single core (Core 0) are shown in FIG, but it will be understood that each of the other cores of processor 1255 may include similar components.

[0147] Before describing the specific details of an embodiment of the present invention, a description of the various components of an exemplary processor 1255 is provided directly below. Multiple cores 0-N may each include a memory management unit 1290 for performing memory operations (e.g., such as load / store operations), a set of general purpose registers (GPRs) 1205, a set of vector registers 1206, and a set of mask registers 1207. In one embodiment, multiple vector data elements are packed into each vector register 1206, and each vector register 1206 may have a width of 512 bits for storing two 256-bit values, four 128-bit values, eight 64-bit values, sixteen 32-bit values, etc. However, the underlying principles of the present invention are not limited to any particular size / type of vector data. In one embodiment, mask registers 1207 include eight 64-bit operand mask registers (e.g., implemented as mask registers k0-k7 described herein) for performing bit mask operations on the values ​​stored in vector registers 1206. However, the underlying principles of the present invention are not limited to any particular mask register size / type.

[0148] Each core 0-N may include a dedicated first level (L1) cache 1212 and a second level (L2) cache 1211 for caching instructions and data according to a specified cache management policy. The L1 cache 1212 includes a separate instruction cache 1220 for storing instructions and a separate data cache 1221 for storing data. Instructions and data stored in each processor cache are managed at the granularity of a cache line, which may be a fixed size (e.g., 64 bytes, 128 bytes, 512 bytes in length). Each core of this exemplary embodiment has an instruction fetch unit 1210 for fetching instructions from main memory 1200 and / or a shared third level (L3) cache 1216. The instruction fetch unit 1210 includes various well-known components, including: a next instruction pointer 1203 for storing the address of the next instruction to be fetched from the memory 1200 (or one of the caches); a translation lookaside buffer (ITLB) 1204 for storing mappings of recently used virtual to physical instruction addresses to improve address translation speed; a branch prediction unit 1202 for speculatively predicting instruction branch addresses; and a branch target buffer (BTB) 1201 for storing branch addresses and target addresses.

[0149] As mentioned, decode unit 1230 includes DSP instruction decode circuitry / logic 1231 for decoding the DSP instructions described herein into micro-operations or "uops," and DSP instruction execution circuitry / logic 1241 for executing DSP instructions. Writeback / retirement unit 1250 retires executed instructions and writes back results.

[0150] Vector packed double complex multiplication

[0151] Negate the sum and accumulate the real part

[0152] One embodiment of the present invention uses Figure 14A The architecture shown in FIG. 1 is used to perform vector packed double complex multiplication, negate the sum, and accumulate the real parts. As described below, one particular embodiment performs a two's complement negation by inverting the bits of the temporary result and adding 1 to generate the final result. The described embodiment operates on signed words in 128-bit packed data registers (such as, for example, xmm1, xmm2, and xmm3 / m128). However, it should be noted that the underlying principles of the present invention are not limited to this.

[0153] In one embodiment, the first accumulator performs the operation: Real-(((16+16i)×(16+16i))+Real-((16+16i)×(16+16i)))+64=64 to calculate and accumulate the real part of the complex number, and the second accumulator performs the operation: Real-(((16+16i)×(16+16i))+Real((16+16i)×(16+16i)))+64=64 to calculate and accumulate another real part. As mentioned, in the aforementioned representation, the numbers represent the number of bits used to represent each number (e.g., 16+16i means a complex number represented by a 16-bit real part and a 16-bit imaginary part).

[0154] One particular embodiment decodes and executes a single instruction to perform a vector packed double complex multiply-add with real accumulate, sometimes identified herein by the mnemonic VPNCDPWQRE. The following code specifies the individual operations performed in one embodiment, where TEMP0, TEMP1, TEMP2, and TEMP3 are registers or memory locations for storing intermediate values, and DEST is the destination register:

[0155] TEMP0[33:0]←(((SRC2[47:32]*SRC3[47:32])-(SRC2[63:48]*SRC3[63:48]))+((SRC2[15:0]*SRC3[15:0])-(SRC2[31:16]*SRC3[31:16])));

[0156] TEMP1[33:0]←(((SRC2[111:96]*SRC3[111:96])-(SRC2[127:112]*SRC3[12 7:112]))+((SRC2[79:64]*SRC3[79:64])-(SRC2[95:80]*SRC3[95:80])));

[0157] TEMP2[33:0]←(~TEMP0[33:0]+1'b1);

[0158] TEMP3[33:0]←(~TEMP1[33:0]+1'b1);

[0159] (*2's complement inversion*)

[0160] DEST[63:0]←AddToQuadword({{30{TEMP2

[33] }},TEMP2[33:0]},DEST[63:0]);

[0161] DEST[127:64]←AddToQuadword({{30{TEMP3

[33] }},TEMP3[33:0]},DEST[127:64]);

[0162] Thus, TEMP0 stores the results of multiplications and additions / subtractions using data elements from the lower halves of SRC2 and SRC3 (i.e., bits 63:0), and TEMP1 stores the results of multiplications and additions / subtractions using data elements from the upper halves of SRC2 and SRC3 (i.e., bits 127:64). Real numbers are generated by these operations because each product consists of a real number multiplied by a real number or an imaginary number multiplied by an imaginary number.

[0163] In one embodiment, the values ​​in TEMP0 and TEMP1 are then inverted using 2's complement inversion by inverting the bits of each value and then increasing the inverted result by 1. The resulting value in TEMP2 (after 2's complement inversion) is then accumulated with the current value in the lower half of DEST (i.e., DEST[63:0]), and the resulting value in TEMP3 is accumulated with the current value in the upper half of DEST (i.e., DEST[127:64]) to generate the real portion of the accumulation.

[0164] Figure 14A The diagram illustrates an exemplary architecture for implementing the above operations, including a first source register SRC2 1401 storing data elements S2A-S2H and a second source register SRC3 1402 storing data elements S3A-S3H (S2 is used herein as a shorthand for SRC2 and S3 is used herein as a shorthand for SRC3). In one embodiment, elements A, C, E, and G are real numbers, and data elements B, D, F, and H are imaginary numbers. Eight multipliers 1405 multiply the real or imaginary data elements in SRC2 1401 with the corresponding real or imaginary data elements in SRC3 1402 to generate eight products (e.g., S3A*S2A, S3B*S2B, S3C*S2C, etc.). The first and second sets of adder networks 1410-1411 add or subtract the products according to the above code. For example, when executing one embodiment of the VPNCDPWQRE instruction, adder network 1410 performs the following operations:

[0165] S2C*S3C-S2D*S3D+S2A*S3A-S2B*S3B;

[0166] And the adder network 1411 performs the operation:

[0167] S2G*S3G-S2H*S3H+S2E*S3E-S2F*S3F.

[0168] In one embodiment, 2's complement negation circuitry (e.g., within the first and second sets of adder networks 1410-1411) negates the above values ​​using 2's complement negation by inverting the bits of each value and adding 1. Additionally, each of the temporary results (e.g., stored in TEMP2 and TEMP3) may be sign-extended or zero-extended to the same size (e.g., 64 bits in one embodiment) of the value from the destination with which each of the temporary results is to be accumulated. An example of sign extension is provided:

[0169] DEST[63:0]←AddToQuadword({{30{TEMP2

[33] }},TEMP2[33:0]},DEST[63:0]);

[0170] DEST[127:64]←AddToQuadword({{30{TEMP3

[33] }},TEMP3[33:0]},DEST[127:64]).

[0171] In the above example, 30{TEMP3

[33] } and 30{TEMP2

[33] } means that the value in bit 33 is copied 30 times before accumulation to create a 64-bit result.

[0172] The accumulation circuitry, including adders 1420-1421, combines the above results with the previously accumulated results (if any) stored in SRC1 / DEST register 1460. Specifically, the outputs AN0_A through AN0_D of adder network 1410 are combined with the accumulated data in element positions AD in SRC1 / DEST register 1460. The results are saturated by saturation circuit 1440 (i.e., if one or more of the values ​​is greater than the supported maximum, the maximum value is output). These results are then stored back to the lower 64 bits (element positions AD) of SRC1 / DEST register 1460. Similarly, the outputs AN1_A through AN1_D of adder network 1411 are added to the accumulated data in element positions EH in SRC1 / DEST register 1460, respectively. The results are saturated by saturation circuit 1441 and stored back to the upper half (element positions EH) of SRC1 / DEST register 1460.

[0173] Figure 15 A method according to one embodiment is illustrated in FIG. The method may be implemented within the context of the processor architectures described herein, but is not limited to any particular processor architecture.

[0174] At 1501, a first instruction is fetched, the first instruction having fields for an opcode, first and second packed data source operands representing complex numbers having real and imaginary values, and a packed data destination operand. At 1502, the first instruction is decoded. At 1503, the real and imaginary values ​​associated with the first and second source operands are stored as packed data elements in first and second source registers, and the first instruction is scheduled for execution. As mentioned, in one embodiment, the first and second source operands are stored in a 128-bit packed data register that stores 16-bit packed data elements, each packed data element comprising a real or imaginary value.

[0175] At 1504, the first decoded instruction is executed to multiply the selected packed real data elements from the first source register by the corresponding packed real data elements from the second source register to generate a first real product. Additionally, the selected packed imaginary data elements from the first source register are multiplied by the corresponding packed imaginary data elements from the second source register to generate a second real product.

[0176] At 1505, selected combinations of the first and second real products are added / subtracted to generate first and second sets of temporary results, respectively. As described above, in one embodiment, this includes the operations ((S2C*S3C)-(S2D*S3D))+((S2A*S3A)-(S2B*S3B)) to generate a first temporary result, and ((S2G*S3G)-(S2H*S3H))+((S2E*S3E)-(S2F*S3F)) to generate a second temporary result, where S2C*S3C, S2D*S3D, S2A*S3A, and S2B*S3B are the first set of real products, and S2G*S3G, S2H*S3H, S2E*S3E, and S2F*S3F are the second set of real products.

[0177] Additionally, at 1506, the bits of the first and second temporary results are inverted and 1 is added to each temporary result to generate third and fourth temporary results, respectively. As mentioned, this can be accomplished using third and fourth storage locations (e.g., TEMP2 and TEMP3), depending on the operation.

[0178] TEMP2[33:0]←(~TEMP0[33:0]+1'b1);

[0179] TEMP3[33:0]←(~TEMP1[33:0]+1'b1);

[0180] Furthermore, as described above, the values ​​in TEMP2 and TEMP3 may be zero-extended or sign-extended prior to accumulation.

[0181] At 1507, in one embodiment, the third interim result is combined with the lower 64 bits from the destination register, and the accumulated result is stored back to the lower 64 bits (across four packed data element positions) in the destination register. Similarly, the fourth interim result is combined with the upper 64 bits from the destination register, and the accumulated result is stored back to the upper 64 bits (four packed data element positions) in the destination register. In one embodiment, the accumulated result is saturated before being stored back to the destination register, if necessary.

[0182] At 1508, the result of the first instruction is committed to memory (eg, and made globally visible).

[0183] Although the real and imaginary values ​​described above are 16 bits long, the basic principles of the present invention can be implemented using data elements of any size. For example, the real and imaginary parts can be 8 bits, 32 bits, or 64 bits and still comply with the basic principles of the present invention.

[0184] Vector packed double complex multiplication

[0185] Add and accumulate the imaginary parts

[0186] One embodiment of the present invention uses Figure 14A The architecture shown in

[0045] is used to multiply the packed imaginary and real parts of complex numbers using signed words. As described below, one embodiment also performs a two's complement negation by inverting the bits of the temporary result and adding 1, and may also sign-extend or zero-extend the result before accumulation. The described embodiment operates on signed words in 128-bit packed data registers (such as, for example, xmm1, xmm2, and xmm3 / m128). However, it should be noted that the underlying principles of the present invention are not limited to this.

[0187] In one embodiment, the first accumulator performs the operation: Imaginary-(((16+16i)×(16+16i))+Imaginary((16+16i)×(16+16i)))+64i=64i to calculate and accumulate the first imaginary part, and the second accumulator performs the operation: Imaginary-(((16+16i)×(16+16i))+Imaginary((16+16i)×(16+16i)))+64i=64i to calculate and accumulate the second imaginary part. As mentioned, in the aforementioned representation, the digits represent the number of bits used to represent each number (e.g., 16+16i means a complex number represented by a 16-bit real part and a 16-bit imaginary part).

[0188] One particular embodiment decodes and executes a single instruction to perform a vector packed double complex multiply-add and accumulate of the imaginary parts, identified herein by the mnemonic VPNCDPWQIMM. The following code specifies multiple individual operations performed in one embodiment, where TEMP0, TEMP1, TEMP2, and TEMP3 are registers or memory locations for storing intermediate values, and DEST is the destination register.

[0189] TEMP0[33:0]←(((SRC2[47:32]*SRC3[63:48])+(SRC2[63:48]*SRC3[47:32]))+((SRC2[15:0]*SRC3[31:16])+(SRC2[31:16]*SRC3[15:0])));

[0190] TEMP1[33:0]←(((SRC2[111:96]*SRC3[127:112])+(SRC2[127:112]*SRC3[1 11:96]))+((SRC2[79:64]*SRC3[95:80])+(SRC2[95:80]*SRC3[79:64])));

[0191] TEMP2[33:0]←(~TEMP0[33:0]+1'b1);

[0192] TEMP3[33:0]←(~TEMP1[33:0]+1'b1);

[0193] (*2's complement inversion*)

[0194] DEST[63:0]←AddToQuadword({{30{TEMP2

[33] }},TEMP2[33:0]},DEST[63:0]);

[0195] DEST[127:64]←AddToQuadword({{30{TEMP3

[33] }},TEMP3[33:0]},DEST[127:64]).

[0196] TEMP0 stores the results of multiplications and additions using data elements from the lower halves of SRC2 and SRC3 (i.e., bits 63:0), and TEMP1 stores the results of multiplications and additions using data elements from the upper halves of SRC2 and SRC3 (i.e., bits 127:64). Imaginary numbers are generated by these operations because each product consists of an imaginary number multiplied by a real number. In one embodiment, each multiplication is performed using a data element from SRC2 and a data element in an adjacent position in SRC3 (i.e., two adjacent data elements must include a real part and an imaginary part).

[0197] The values ​​in TEMP0 and TEMP1 can be 2's complement inverted by reversing their bits and adding 1. In one embodiment, the results are stored in additional temporary storage locations TEMP2 and TEMP3, respectively. As described above, the results in TEMP2 and TEMP3 can then be zero-extended or sign-extended to 64 bits before accumulation. The resulting value in TEMP2 is then accumulated with the current value in the lower half of DEST (i.e., DEST[63:0]), and the resulting value in TEMP3 is accumulated with the current value in the upper half of DEST (i.e., DEST[127:64]) to generate the accumulated imaginary part.

[0198] return Figure 14A , first source register SRC2 1401 stores data elements S2A-S2H, and second source register SRC3 1402 stores data elements S3A-S3H. In one embodiment, elements A, C, E, and G are real numbers, and data elements B, D, F, and H are imaginary numbers. Eight multipliers 1405 multiply the real / imaginary data elements in SRC2 with the imaginary / real data elements in SRC3 to generate eight imaginary products. In this case, the products added and stored in TEMP0 are S2C*S3D+S2D*S3C+S2A*S3B+S2B*S3A, and the products added and stored in TEMP1 are S2G*S3H+S2H*S3G+S2E*S3F+S2F*S3E. The first and second sets of adder networks 1410-1411 add the imaginary products according to the above code. For example, adder network 1410 performs an addition operation:

[0199] TEMP0[33:0]←S2C*S3D+S2D*S3C+S2A*S3B+S2B*S3A;

[0200] And the adder network 1411 performs the addition operation:

[0201] TEMP1[33:0]←S2G*S3H+S2H*S3G+S2E*S3F+S2F*S3E.

[0202] As mentioned, in one embodiment, the 2's complement inverter circuits in the first and second sets of adder networks 1410-1411 (or elsewhere) may be inverted. Figure 14A The bits of the result of the addition / subtraction are added by 1. Thus, in this embodiment, the adder network 1410 performs the operation:

[0203] TEMP2[33:0]←(~TEMP0[33:0]+1'b1);

[0204] And the adder network 1411 performs the operation:

[0205] TEMP3[33:0]←(~TEMP1[33:0]+1'b1).

[0206] Additionally, the values ​​may be zero-extended or sign-extended so that they are the appropriate size (eg, 64 bits) for accumulation.

[0207] The accumulation circuitry, including adders 1420-1421, adds the above result to the previously accumulated result (if any) stored in SRC1 / DEST register 1460. Specifically, the outputs AN0_A through AN0_D of adder network 1410 are added to the accumulated data in element positions AD (i.e., the lower 64 bits) of SRC1 / DEST register 1460. The imaginary result is saturated by saturation circuit 1440 (i.e., if one or more of the values ​​is greater than the supported maximum, the maximum value is output). The result is then stored back in SRC1 / DEST register 1460 at element positions AD. Similarly, the outputs AN1_A through AN1_D of adder network 1411 are added to the accumulated data in element positions EH of SRC1 / DEST register 1460. The imaginary result is saturated by saturation circuit 1441 and output back to the same region of SRC1 / DEST register 1460 (e.g., the upper 64 bits).

[0208] Figure 14BThe figure shows additional details of one embodiment including 2's complement negation circuits 1470 and 1471, which use 2's complement negation to negate the sum of products calculated by adder networks 1410 and 1411, respectively. Extension circuits 1480 and 1481 receive the negated sum of products and responsively zero-extend or sign-extend these values ​​to generate a result of the appropriate size (e.g., 64 bits) for accumulation with the current SRC1 / DEST 1460 register value. Zero extension in one embodiment includes adding multiple zeros to the value, while sign extension includes duplicating bit values. Subsequently, accumulators 1490-1491 use the 64-bit temporary result and the packed 64-bit value from the SRC1 / DEST register 1460 to perform the accumulation operation described herein.

[0209] Figure 16 A method according to one embodiment is illustrated in FIG. The method may be implemented within the context of the processor architectures described herein, but is not limited to any particular processor architecture.

[0210] At 1601, a first instruction is fetched, the first instruction having fields for an opcode, first and second packed data source operands representing complex numbers having real and imaginary values, and a packed data destination operand. At 1602, the first instruction is decoded. At 1603, the real and imaginary values ​​associated with the first and second source operands are stored as packed data elements in first and second source registers, and the first instruction is scheduled for execution. As mentioned, in one embodiment, the first and second source operands are stored in a 128-bit packed data register that stores 16-bit packed data elements, each packed data element comprising a real or imaginary value.

[0211] At 1604, a first decoded instruction is executed to multiply the selected real value from the first operand with the selected imaginary value from the second operand to generate a first imaginary product, and to multiply the selected imaginary value from the first operand with the selected real value from the second operand to generate a second imaginary product.

[0212] At 1605, selected combinations of the first and second imaginary products are added to generate first and second sets of temporary results, respectively. As described above, in one embodiment, this includes the operations: S2C*S3D+S2D*S3C+S2A*S3B+S2B*S3A and S2G*S3H+S2H*S3G+S2E*S3F+S2F*S3E, where S2C*S3D, S2D*S3C, S2A*S3B, and S2B*S3A are the first set of imaginary products, and S2G*S3H, S2H*S3G, S2E*S3F, and S2F*S3E are the second set of imaginary products.

[0213] At 1606, the bits of the first and second temporary results are reversed and 1 is added to each temporary result to generate third and fourth temporary results, respectively. As mentioned, this can be accomplished using the third and fourth storage locations (e.g., TEMP2 and TEMP3). Additionally, the results in TEMP2 and TEMP3 can be zero-extended or sign-extended as previously described.

[0214] In one embodiment, at 1607, the third interim result is combined with the lower 64 bits from the destination register, and the accumulated result is stored back to the lower 64 bits of the destination register (data element positions AD). Similarly, the fourth interim result is combined with the upper 64 bits from the destination register, and the accumulated result is stored back to the upper 64 bits of the destination register (data element positions EH). In one embodiment, the accumulated result is saturated, if necessary, before being stored back to the destination register.

[0215] At 1608, the result of the first instruction is committed to memory (eg, and made globally visible).

[0216] Although the real and imaginary values ​​described above are 16 bits long, the basic principles of the present invention can be implemented using data elements of any size. For example, the real and imaginary parts can be 8 bits, 32 bits, or 64 bits and still comply with the basic principles of the present invention.

[0217] In the foregoing description, embodiments of the present invention have been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and variations may be made to these embodiments without departing from the broader spirit and scope of the present invention as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0218] Embodiments of the present invention may include the steps described above. These steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by dedicated hardware components that contain hard-wired logic for performing these steps, or by any combination of programmed computer components and custom hardware components.

[0219] As described herein, instructions may refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform certain operations or have predetermined functions, or software instructions stored in a memory embodied in a non-transitory computer-readable medium. Thus, the techniques shown in the figures may be implemented using code and data stored on and executed by one or more electronic devices (e.g., a terminal station, a network element, etc.). Such electronic devices use computer machine-readable media such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read-only memory; flash memory devices; phase change memory) and transient computer machine-readable communication media (e.g., electrical, optical, acoustic or other forms of propagated signals - such as carrier waves, infrared signals, digital signals, etc.) to store and transmit code and data (internally and / or over a network with other electronic devices). In addition, such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens and / or displays), and network connections. The coupling of the set of processors to other components is typically through one or more buses and bridges (also referred to as bus controllers). The storage device and the signal carrying the network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device typically stores code and / or data for execution on the set of one or more processors of the electronic device. Of course, one or more parts of the embodiments of the present invention can be implemented using different combinations of software, firmware and / or hardware. Throughout this specific embodiment, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without some of these specific details. In some instances, well-known structures and functions are not described in detail to avoid obscuring the subject matter of the present invention. Therefore, the scope and spirit of the present invention should be determined according to the appended claims.

Claims

1. A processor, comprising: a decoder for decoding the first instruction to generate a decoded instruction; a first source register for storing a first plurality of packed real and imaginary data elements; a second source register for storing a second plurality of packed real and imaginary data elements; as well as An execution circuit, configured to execute the decoded instruction, the execution circuit comprising: a multiplier circuit for selecting real data elements and imaginary data elements to be multiplied in the first source register and the second source register, the multiplier circuit for multiplying each selected imaginary data element in the first source register with a selected real data element in the second source register, and for multiplying each selected real data element in the first source register with a selected imaginary data element in the second source register to generate a plurality of imaginary products, an adder circuit for adding a first subset of the plurality of imaginary products to generate a first temporary result and for adding a second subset of the plurality of imaginary products to generate a second temporary result, a negation circuit for negating the first temporary result to generate a third temporary result, and for negating the second temporary result to generate a fourth temporary result, and Accumulation circuitry for combining the third provisional result with first data from a destination register to generate a first final result, and for combining the fourth provisional result with second data from the destination register to generate a second final result, and for storing the first and second final results back in the destination register.

2. The processor of claim 1, wherein: Real and imaginary values ​​are stored in the first and second source registers as 16-bit data elements, each imaginary value is stored in a data element position adjacent to the data element position of its corresponding real value, each combination of real and imaginary values ​​representing a complex number.

3. The processor according to claim 1 or 2, wherein: The first source register and the second source register comprise 128-bit packed data registers configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H, respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

4. The processor of claim 3, wherein: To execute the decoded instruction, the multiplier circuit is to perform multiplications S1C*S2D, S1D*S2C, S1A*S2B, S1B*S2A, S1G*S2H, S1H*S2G, S1E*S2F, S1F*S2E to generate the plurality of imaginary products, where S1 identifies the first source register, S2 identifies the second source register, and AH identifies packed data elements in data element positions AH in the first source register and the second source register, respectively.

5. A method comprising: decoding the first instruction to generate a decoded instruction; storing a first plurality of packed real and imaginary data elements in a first source register; storing a second plurality of packed real and imaginary data elements in a second source register; selecting real data elements and imaginary data elements to be multiplied in the first source register and the second source register; multiplying each selected imaginary data element in the first source register with a selected real data element in the second source register, and multiplying each selected real data element in the first source register with a selected imaginary data element in the second source register to generate a plurality of imaginary products; summing a first subset of the plurality of imaginary products to generate a first temporary result, and summing a second subset of the plurality of imaginary products to generate a second temporary result; performing negation on the first temporary result to generate a third temporary result, and performing negation on the second temporary result to generate a fourth temporary result; accumulating the third interim result with first data from a destination register to generate a first final result, and accumulating the fourth interim result with second data from the destination register to generate a second final result; as well as The first final result and the second final result are stored back in the destination register.

6. The method according to claim 5, wherein: Real and imaginary values ​​are stored in the first and second source registers as 16-bit data elements, each imaginary value is stored in a data element position adjacent to the data element position of its corresponding real value, each combination of real and imaginary values ​​representing a complex number.

7. The method according to claim 5 or 6, wherein: The first source register and the second source register comprise 128-bit packed data registers configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H, respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

8. A machine-readable medium having program code stored thereon, the program code, when executed by a machine, causing the machine to: decoding the first instruction to generate a decoded instruction; storing a first plurality of packed real and imaginary data elements in a first source register; storing a second plurality of packed real and imaginary data elements in a second source register; selecting real data elements and imaginary data elements to be multiplied in the first source register and the second source register; multiplying each selected imaginary data element in the first source register with a selected real data element in the second source register, and multiplying each selected real data element in the first source register with a selected imaginary data element in the second source register to generate a plurality of imaginary products; summing a first subset of the plurality of imaginary products to generate a first temporary result, and summing a second subset of the plurality of imaginary products to generate a second temporary result; performing negation on the first temporary result to generate a third temporary result, and performing negation on the second temporary result to generate a fourth temporary result; accumulating the third interim result with first data from a destination register to generate a first final result, and accumulating the fourth interim result with second data from the destination register to generate a second final result; as well as The first final result and the second final result are stored back in the destination register.

9. The machine-readable medium of claim 8, wherein: Real and imaginary values ​​are stored in the first and second source registers as 16-bit data elements, each imaginary value is stored in a data element position adjacent to the data element position of its corresponding real value, each combination of real and imaginary values ​​representing a complex number.

10. The machine-readable medium of claim 8 or 9, wherein: The first source register and the second source register comprise 128-bit packed data registers configurable with data element positions A, B, C, D, E, F, G, and H for storing data elements A, B, C, D, E, F, G, and H, respectively, and wherein data elements A, C, E, and G are real data elements and data elements B, D, F, and H are corresponding imaginary data elements.

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