PCIE device and operation method thereof

Abstract

The invention provides a PCIE device and an operation method thereof. The PCIE device comprises a PCIE interface, a PCIE controller, a VFID controller and a core circuit. And the PCIE controller receives and processes the PCIE packet from the host through the PCIE interface. The core circuit provides resources of the PCIE device to the host. The VFID controller is coupled between the PCIE controller and the core circuit. The VFID controller replaces the PCIE VFID in the first packet which is pre-sent to the core circuit by the PCIE controller with the internal VFID, and then transmits the first packet with the internal VFID to the core circuit. And the VFID controller replaces the internal VFID in the second packet which is pre-transmitted back to the PCIE controller by the core circuit with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to a PCIE (Peripheral Component Interconnect Express, or PCIe) device and an operating method thereof. Background Art

[0002] PCIE is a commonly used interface between computers and peripheral components. Depending on the application scenario, peripheral components include AI (Artificial Intelligence) cards or other peripheral components, while AI cards include GPU (Graphics Processing Unit) cards, GPGPU (General-Purpose GPU) cards, or other AI computing components. Peripheral components with PCIE interfaces are called PCIE devices. Virtual functions (VFs) are widely used in PCIE devices. PCIE devices can be divided into multiple parts to provide multiple virtual functions, which can operate simultaneously on the PCIE device and share resources. These virtual functions may belong to different users and have different system images (SIs). In some application scenarios, PCIE devices are widely deployed in the cloud and may be allocated to multiple users simultaneously. Each user may occupy one or more virtual functions.

[0003] In the PCIE protocol, memory write operations (MemWr) are called posted requests, while memory read operations (MemRd) are called non-posted requests. Because PCIE devices are divided into multiple sections, the host can reset each section if it becomes suspended. The Function Level Reset (FLR) mechanism enables software to reset portions of the PCIE device hardware at a function-level granularity. A function-level reset may cause the virtual function to lose track of any outstanding requests (such as outstanding non-posted requests). Any completion messages (response messages to non-posted requests) that arrive after a function-level reset are called "stale completions." If the host's software issues a function-level reset to the PCIE device for a virtual function (assuming its identifier is VFID_0) while there are outstanding requests (such as outstanding non-posted requests), and then re-enables the same virtual function identifier (such as reusing virtual function identifier VFID_0 to another virtual function) without waiting for potential "stale completions", any subsequently arriving "stale completions" may be mistaken by the other virtual function as requests issued since the function-level reset, resulting in data corruption.

[0004] Software can prevent data corruption caused by "late completion" in a variety of ways. As systems grow larger and applications become more complex, outstanding non-release requests may take longer to return response packets to the host. In large networks and complex systems, to ensure that function-level resets complete safely and without corrupting system data, software should take appropriate actions, such as increasing the wait time to ensure that all non-release requests return. Increasing the wait time can impair system performance because system software may have to wait longer before reusing virtual functions and hardware resources.

[0005] It should be noted that the content in the "Background" section is intended to facilitate understanding of the present invention. Some (or all) of the content disclosed in this section may not be known to those skilled in the art. The content disclosed in this section does not imply that such content was known to those skilled in the art prior to the filing of this application. Summary of the Invention

[0006] The present invention is directed to a PCIE device and an operating method thereof.

[0007] In an embodiment according to the present invention, a PCIE device includes a PCIE interface, a PCIE controller, a VFID controller, and a core circuit. The PCIE interface is used to connect to a host. The PCIE controller is coupled to the PCIE interface. The PCIE controller receives and processes PCIE packets from the host via the PCIE interface. The core circuit is used to provide resources of the PCIE device to the host. The VFID controller is coupled between the PCIE controller and the core circuit. The VFID controller replaces the PCIE VFID in a first packet pre-sent from the PCIE controller to the core circuit with an internal VFID, and then transmits the first packet with the internal VFID to the core circuit. The VFID controller replaces the internal VFID in a second packet pre-sent from the core circuit back to the PCIE controller with a PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

[0008] In an embodiment according to the present invention, the operating method includes: receiving, by a PCIE controller of a PCIE device, and processing a PCIE packet from a host through a PCIE interface of the PCIE device; replacing, by a VFID controller of the PCIE device, a PCIE VFID in a first packet pre-sent from the PCIE controller to a core circuit of the PCIE device with an internal VFID, and then transmitting the first packet with the internal VFID to the core circuit; and replacing, by the VFID controller, the internal VFID in a second packet pre-sent back from the core circuit to the PCIE controller with a PCIE VFID, and then transmitting the second packet with the PCIE VFID to the PCIE controller.

[0009] Based on the above, embodiments of the present invention add an intermediate layer, a "VFID controller," between the PCIE controller and the existing core circuitry of the PCIE device. The VFID controller replaces the VFID in packets pre-sent from the PCIE controller to the core circuitry from the PCIE VFID to the internal VFID, and also replaces the VFID in packets pre-sent from the core circuitry to the PCIE controller from the internal VFID to the PCIE VFID. A host may issue a function-level reset to the PCIE device for the previous virtual function (assuming its identifier is VFID_0), releasing the PCIE VFID VFID_0. The host then reuses the same PCIE VFID VFID_0 for the new virtual function. In this scenario where the same PCIE VFID is reused for different virtual functions, although the previous and new virtual functions use the same PCIE VFID VFID_0 at different times, the core circuitry can use different internal VFIDs for the previous and new virtual functions. Therefore, the VFID controller can identify whether packets pre-sent from the core circuitry to the PCIE controller are for the previous virtual function or the new virtual function. Based on this, the VFID controller can release the VFID in advance and improve reliability.

[0010] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of a circuit block of a PCIE device according to an embodiment of the present invention; Figure 2 1 is a flow chart of an operating method of a PCIE device according to an embodiment of the present invention; Figure 3 FIG. 1 is a schematic diagram of a circuit module of a PCIE controller and a VFID controller according to an embodiment of the present invention.

[0012] Explanation of Figure Numbers 10: Host 100: PCIE device 110: PCIE interface 120: PCIE controller 121: Receiving controller 122: Send controller 123: PCIE VFID queue 130: VFID controller 131: VFID lookup table 132: Receiving control circuit 133: FLR control circuit 134: Send control circuit 140: Core Circuit CORE_VFID: internal VFID PCIE_VFID: PCIE VFID DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if a first device is described as being coupled (or connected) to a second device, this should be interpreted to mean that the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device via another device or some other means of connection. Terms such as "first" and "second" throughout this specification (including the claims) are used to name components or to distinguish between different embodiments or scopes, and are not intended to limit the upper or lower limits on the number of components or the order of components. Furthermore, whenever possible, components, members, and steps using the same reference numbers in the drawings and embodiments represent identical or similar parts. Components, members, and steps using the same reference numbers or the same terminology in different embodiments may refer to the relevant descriptions. It should be understood that features of the following embodiments may be combined. For example, features of the second embodiment may be implemented in combination with features of the first embodiment. Those skilled in the art can select appropriate feature combinations based on actual design requirements.

[0015] Figure 1 FIG2 is a circuit block diagram of a PCIE device according to an embodiment of the present invention. Based on a request from a host 10 , the PCIE device 100 can provide resources (eg, memory space or other hardware resources) to the host 10 . Figure 1 The PCIE device 100 shown includes a PCIE interface 110, a PCIE controller 120, a VFID controller 130, and core circuitry 140. By adding an intermediate layer (VFID controller 130) between the PCIE controller 120 and the core circuitry 140, the PCIE device 100 releases the PCIE VFID early, improving reliability. The VFID controller 130 replaces the VFID in packets sent from the PCIE controller 120 to the core circuitry 140, and also replaces the VFID in packets sent from the core circuitry 140 to the PCIE controller 120.

[0016] The PCIE interface 110 is used to connect to the host 10. The PCIE controller 120 is coupled to the PCIE interface 110. The PCIE controller 120 receives and processes PCIE packets from the host 10 via the PCIE interface 110. The VFID controller 130 is coupled between the PCIE controller 120 and the core circuit 140. Based on a request from the host 10, the core circuit 140 provides resources (e.g., memory space, computing power, or other hardware resources) of the PCIE device 100 to the host 10 via the PCIE interface 110, the PCIE controller 120, and the VFID controller 130. Depending on the actual design and application, the PCIE controller 120 may include a conventional PCIE controller or another PCIE controller.

[0017] Figure 2 This is a flow chart of an operating method of a PCIE device according to an embodiment of the present invention. Figure 1 and Figure 2 In step S210, the PCIE controller 120 receives and processes a PCIE packet from the host 10 via the PCIE interface 110. In step S220, the VFID controller 130 replaces the PCIE VFID PCIE_VFID in the first packet pre-sent from the PCIE controller 120 to the core circuit 140 with the internal VFID CORE_VFID. Depending on the actual application scenario, the content of the first packet may include a request (e.g., a read command) from the host 10 to the PCIE device 100. The VFID controller 130 then transmits the first packet with the internal VFID CORE_VFID to the core circuit 140.

[0018] The core circuit 140 executes the request (first packet) from the host 10 and then transmits the corresponding data (second packet) to the PCIE controller 120 via the VFID controller 130. In step S230, the VFID controller 130 replaces the internal VFID CORE_VFID in the second packet previously transmitted from the core circuit 140 to the PCIE controller 120 with the PCIE VFID PCIE_VFID and then transmits the second packet with the PCIE VFID PCIE_VFID to the PCIE controller 120.

[0019] The host 10 may issue a function-level reset to the PCIE device 100 for the previous virtual function (assuming its identifier is PCIE_VFID_0), releasing the PCIE VFID PCIE_VFID_0. The host 10 then reuses the same PCIE VFID PCIE_VFID_0 for the new virtual function. In this scenario where the same PCIE VFID PCIE_VFID is reused for different virtual functions, although the previous and new virtual functions use the same PCIE VFID PCIE_VFID_0 at different times, the core circuit 140 uses different internal VFIDs CORE_VFID. Therefore, the VFID controller 130 can identify whether the packet pre-sent by the core circuit 140 to the PCIE controller 120 is for the previous virtual function (which has been deactivated due to the reset) or the new virtual function (which is currently activated). This allows the VFID controller to release the VFID in advance, improving reliability.

[0020] In some embodiments, the VFID controller 130 can use a VFID lookup table to replace the PCIE VFID PCIE_VFID with the internal VFID CORE_VFID, and the VFID controller 130 can use the VFID lookup table to restore the internal VFID CORE_VFID to the PCIE VFID PCIE_VFID. For example (but not limited to), the VFID lookup table includes a valid bit field, a PCIE VFID field, and a hash bit field.

[0021] The VFID controller 130 retrieves the hash bit corresponding to the PCIE VFID PCIE_VFID in the first packet (the packet pre-sent by the PCIE controller 120 to the core circuit 140) from the VFID lookup table. The VFID controller 130 combines the PCIE VFID PCIE_VFID and the hash bit to generate the internal VFID CORE_VFID. This embodiment does not limit the specific implementation of the PCIE VFID PCIE_VFID and the hash bit. For example, assuming that the PCIE VFID PCIE_VFID has N bits and the hash bit has M bits. Then there may be 2 N Different virtual functions, and each virtual function can correspond to 2 M An internal VFID CORE_VFID.

[0022] This embodiment does not limit the combination of the PCIE VFID PCIE_VFID and the hash bits. For example, VFID controller 130 can use a hash algorithm to map the PCIE VFID PCIE_VFID to an internal VFIDCORE_VFID, so that each PCIE VFID PCIE_VFID can correspond to multiple internal VFIDs CORE_VFID. Combining the internal VFID CORE_VFID from the PCIEVFID PCIE_VFID and the hash bits is simple, easy, and hardware-friendly. Restoring the PCIE VFID PCIE_VFID from the internal VFIDCORE_VFID and the hash bits is simple, easy, and hardware-friendly.

[0023] For example, assuming the number of bits N of PCIE VFID PCIE_VFID is 2, there are 2 2 = 4 original PCIE VFID PCIE_VFID, respectively {0, 1, 2, 3}. Assuming the number of hash bits M = 1, each original PCIE VFID PCIE_VFID can correspond to 2 1 = 2 internal VFIDs CORE_VFID. Table 1 below shows a first embodiment of the hash algorithm. In the embodiment shown in Table 1, the PCIE VFID PCIE_VFID is placed in the MSB (Most Significant Bit) of the internal VFID CORE_VFID, while the hash bit is placed in the LSB (Least Significant Bit) of the internal VFID CORE_VFID. In this case, for example, when the internal VFID CORE_VFID is 0 or 1, the core circuit 140 can determine that the original PCIE VFID PCIE_VFID is 0.

[0024] Table 1: PCIE VFID PCIE_VFID and hash bit combination

[0025] Table 2 below shows a second embodiment of the hash algorithm. In the embodiment shown in Table 2, assuming the number of bits N of the PCIE VFID PCIE_VFID is 2, assuming the number of hash bits M is 1, the PCIE VFID PCIE_VFID is placed in the LSB portion of the internal VFIDCORE_VFID, and the hash bit is placed in the MSB portion of the internal VFID CORE_VFID. In this case, for example, when the internal VFID CORE_VFID is 0 or 4, the core circuit 140 can determine to select the original PCIE VFID PCIE_VFID as 0.

[0026] Table 2: PCIE VFID PCIE_VFID and hash bit combination

[0027] Table 3 below shows a third embodiment of a hash algorithm. In the embodiment shown in Table 3, it is assumed that the number of bits N in the PCIE VFID PCIE_VFID is 2, the number of hash bits M is 1, and the hash bit is placed between two bits in the PCIE VFID PCIE_VFID. In this case, for example, when the internal VFID CORE_VFID is 0 or 2, the core circuit 140 can select the original PCIE VFID PCIE_VFID as 0.

[0028] Table 3: PCIE VFID PCIE_VFID and hash bit combination

[0029] Table 4 below shows a fourth embodiment of a hash algorithm. In the embodiment shown in Table 4, assuming the number of bits N of the PCIE VFID PCIE_VFID is 2, assuming the number of hash bits M is 2, the PCIE VFID PCIE_VFID is placed in the MSB portion of the internal VFIDCORE_VFID, and the hash bits are placed in the LSB portion of the internal VFID CORE_VFID. In this case, for example, when the internal VFID CORE_VFID is 0, 1, 2, or 3, the core circuit 140 can determine to select the original PCIE VFID PCIE_VFID as 0.

[0030] Table 4: PCIE VFID PCIE_VFID and hash bit combination

[0031] Table 5 below shows a fifth embodiment of a hash algorithm. In the embodiment shown in Table 5, assuming the number of bits N of the PCIE VFID PCIE_VFID is 2, assuming the number of hash bits M is 2, the PCIE VFID PCIE_VFID is placed in the LSB portion of the internal VFIDCORE_VFID, and the hash bits are placed in the MSB portion of the internal VFID CORE_VFID. In this case, for example, when the internal VFID CORE_VFID is 0, 4, 8, or 12, the core circuit 140 can determine to select the original PCIE VFID PCIE_VFID as 0.

[0032] Table 5: PCIE VFID PCIE_VFID and hash bit combination

[0033] Table 6 below shows a sixth embodiment of a hash algorithm. In the embodiment shown in Table 6, it is assumed that the number of bits N in the PCIE VFID PCIE_VFID is 2, the number of hash bits M is 2, and the hash bits are placed between two bits in the PCIE VFID PCIE_VFID. In this case, for example, when the internal VFID CORE_VFID is 0, 2, 4, or 6, the core circuit 140 can select the original PCIE VFID PCIE_VFID as 0.

[0034] Table 6: PCIE VFID PCIE_VFID and hash bit combination

[0035] The VFID controller 130 extracts the PCIE VFID PCIE_VFID from the internal VFID CORE_VFID in the second packet (the packet pre-transmitted back to the PCIE controller 120 by the core circuit 140). For example, the VFID controller 130 can refer to the descriptions in Tables 1 to 6 above to infer the original PCIE VFID PCIE_VFID from the internal VFID CORE_VFID in the second packet. Next, the VFID controller 130 retrieves the valid bit corresponding to the PCIE VFID PCIE_VFID extracted from the internal VFID CORE_VFID from the VFID lookup table. If the valid bit indicates that the virtual function corresponding to the PCIE VFID PCIE_VFID has been reset and the PCIE VFID PCIE_VFID has not been reused, for example, if the valid bit is 0, the VFID controller 130 discards the second packet without forwarding it to the PCIE controller 120.

[0036] In response to the valid bit indicating that the PCIE VFID PCIE_VFID is already in use by a virtual function, for example, the valid bit is 1, the VFID controller 130 retrieves the hash bit corresponding to the PCIE VFID PCIE_VFID extracted from the internal VFID CORE_VFID from the VFID lookup table. The VFID controller 130 then combines the PCIE VFID PCIE_VFID with the hash bit to generate a reference VFID. The VFID controller 130 compares the internal VFID CORE_VFID of the second packet with the reference VFID to obtain a comparison result. In response to the comparison result indicating a mismatch between the two, the VFID controller 130 discards the second packet without transmitting it to the PCIE controller 120. In response to the comparison result indicating a match between the two, the VFID controller 130 replaces the internal VFID CORE_VFID in the second packet with the PCIE VFID PCIE_VFID and then transmits the second packet with the PCIE VFID PCIE_VFID to the PCIE controller 120.

[0037] In response to the PCIE controller 120 receiving a function-level reset command with the PCIE VFID PCIE_VFID issued by the host 10, the PCIE controller 120 transmits a function-level reset signal with the PCIE VFID PCIE_VFID to the VFID controller 130. Based on the function-level reset signal, the VFID controller 130 immediately discards all packets associated with the PCIE VFID PCIE_VFID. Furthermore, the VFID controller 130 also transmits a function-level reset signal to the core circuit 140, causing the core circuit 140 to immediately discard all outstanding requests (e.g., outstanding non-posted requests) associated with the PCIE VFID PCIE_VFID. In response to the VFID controller 130 receiving the function-level reset signal with the PCIE VFID PCIE_VFID sent by the PCIE controller 120, the VFID controller 130 sets the valid bit associated with the PCIE VFID PCIE_VFID in the VFID lookup table to an invalid state (e.g., the valid bit is set to 0), thereby causing the VFID controller 130 to discard all return packets associated with the PCIE VFID PCIE_VFID.

[0038] In some embodiments, in response to the VFID controller 130 receiving a function-level reset signal with the PCIE VFID PCIE_VFID sent by the PCIE controller 120, the VFID controller 130 further changes the hash bit associated with the PCIE VFID PCIE_VFID in the VFID lookup table. For example (but not limited to), the VFID controller 130 changing the hash bit in the VFID lookup table includes: incrementing the hash bit by 1; and resetting the hash bit to 0 if the hash bit overflows. In other embodiments, upon receiving the function-level reset signal, the VFID controller 130 temporarily refrains from changing the hash bit associated with the PCIE VFID PCIE_VFID in the VFID lookup table. Instead, the VFID controller 130 waits until the PCIE VFID PCIE_VFID is reused before changing the corresponding hash bit in the VFID lookup table.

[0039] In response to the PCIE controller 120 receiving the notification information sent by the host 10 to instruct the activation of the virtual function with the PCIE VFID PCIE_VFID, the PCIE controller 120 transmits an activation notification signal with the PCIE VFID PCIE_VFID to the VFID controller 130. Based on the activation notification signal, the VFID controller 130 sets the valid bit associated with the PCIE VFID PCIE_VFID in the VFID lookup table to a valid state (e.g., the valid bit is set to 1).

[0040] In some embodiments, in response to the VFID controller 130 receiving a startup notification signal with the PCIE VFID PCIE_VFID from the PCIE controller 120, the VFID controller 130 further changes a hash bit associated with the PCIE VFID PCIE_VFID in the VFID lookup table. For example (but not limited to), the VFID controller 130 changing the hash bit in the VFID lookup table includes: incrementing the hash bit by 1; and resetting the hash bit to 0 if the hash bit overflows. In other embodiments, the VFID controller 130 does not change the hash bit associated with the PCIE VFID PCIE_VFID in the VFID lookup table upon receiving the startup notification signal. Instead, the VFID controller 130 changes the corresponding hash bit in the VFID lookup table as soon as the VFID controller 130 receives a function-level reset signal with the PCIE VFID PCIE_VFID.

[0041] Figure 3 FIG. 1 is a schematic diagram of a circuit module of a PCIE controller and a VFID controller according to an embodiment of the present invention. Figure 3 The PCIE controller 120 and the VFID controller 130 shown can be used as Figure 1One of many implementation examples of the PCIE controller 120 and the VFID controller 130 is shown. Figure 3 The PCIE device 100, PCIE interface 110, PCIE controller 120, VFID controller 130 and core circuit 140 shown in FIG. Figure 1 In the Figure 3 In the illustrated embodiment, the PCIE controller 120 includes a receive controller 121, a transmit controller 122, and a PCIE VFID queue 123, while the VFID controller 130 includes a VFID lookup table 131, a receive control circuit 132, an FLR control circuit 133, and a transmit control circuit 134. Depending on the design, in some embodiments, at least one of the PCIE controller 120, receive controller 121, transmit controller 122, PCIE VFID queue 123, VFID controller 130, VFID lookup table 131, receive control circuit 132, FLR control circuit 133, transmit control circuit 134, and core circuit 140 may be implemented as hardware circuits. In other embodiments, at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140 may be implemented as a combination of hardware, firmware, and software (i.e., a program).

[0042] In hardware terms, at least one of the PCIE controller 120 , receive controller 121 , transmit controller 122 , PCI E VFID queue 123 , VFID controller 130 , VFID lookup table 131 , receive control circuit 132 , FLR control circuit 133 , transmit control circuit 134 , and core circuit 140 may be implemented as a logic circuit on an integrated circuit. For example, the relevant functions of at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134 and the core circuit 140 can be implemented in various logic blocks, modules and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, ASICs (Application-Specific Integrated Circuits), DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), CPUs (Central Processing Units), or other processing units. The relevant functions of at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCI E VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0043] In software or firmware form, the functions associated with at least one of the PCIE controller 120, receive controller 121, transmit controller 122, PCIE VFID queue 123, VFID controller 130, VFID lookup table 131, receive control circuit 132, FLR control circuit 133, transmit control circuit 134, and core circuit 140 may be implemented as programming codes. For example, at least one of the PCIE controller 120, receive controller 121, transmit controller 122, PCIE VFID queue 123, VFID controller 130, VFID lookup table 131, receive control circuit 132, FLR control circuit 133, transmit control circuit 134, and core circuit 140 may be implemented using a general programming language (e.g., C, C++, or assembly language) or other suitable programming language. The programming codes may be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory or a storage device. An electronic device (e.g., a computer, a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute programming code from the non-transitory machine-readable storage medium to implement the relevant functions of at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140.

[0044] The PCIE controller 120 receives PCIE packets from the host 10 via the PCIE interface 110. PCIE packets are decoded at the physical layer, data link layer, and transaction layer to generate TLPs (Transaction Layer Packets). These TLPs are then sent to the receive controller 121. The receive controller 121 receives the decoded TLPs and transmits them to the core circuit 140 via the VFID controller 130. Depending on the actual design and application, the receive controller 121 may convert the TLPs into other protocols, such as the Advanced eXtensible Interface (AXI) protocol or any other protocol recognized by the core circuit 140, and then transmit them to the core circuit 140 via the VFID controller 130. The PCIE VFID queue 123 manages the VFIDs of the PCIE device 100. The sending controller 122 receives the request or response packet from the core circuit 140 through the VFID controller 130 , converts the packet into a TLP packet, and transmits it back to the host 10 through the PCIE interface 110 .

[0045] The VFID lookup table 131 includes a valid bit (V) field, a PCIE VFID (PCIE_VFID) field, and a hash bit (HASH_BIT) field. The valid bit (V) field indicates whether the virtual function is active. The PCIE VFID (PCIE_VFID) field contains information from the PCIE controller 120. The PCIE VFID (PCIE_VFID) is used in packets sent to and from the PCIE controller 120. The receive control circuit 132 is coupled between the PCIE controller 120 and the core circuit 140. Before sending the first packet (pre-sent by the PCIE controller 120 to the core circuit 140), the receive control circuit 132 uses the VFID lookup table 131 to replace the PCIE VFID (PCIE_VFID) in the first packet with the internal VFID (CORE_VFID).

[0046] For example, the receive control circuit 132 retrieves the hash bit HASH_BIT corresponding to the PCIE VFID PCIE_VFID of the first packet from the VFID lookup table 131. The receive control circuit 132 combines the PCIE VFID PCIE_VFID and the hash bit HASH_BIT using a hash algorithm to generate the internal VFID CORE_VFID. This embodiment does not limit the specific implementation of the PCIE VFID PCIE_VFID and the hash bit HASH_BIT. This embodiment also does not limit the combination of the PCIE VFID PCIE_VFID and the hash bit HASH_BIT. For example, the PCIE VFID PCIE_VFID, the hash bit HASH_BIT, and the internal VFID CORE_VFID can refer to the relevant descriptions in Tables 1 to 6 above and be deduced accordingly. Next, the receiving control circuit 132 replaces the PCIE VFID PCIE_VFID in the first packet with the internal VFID CORE_VFID, and then transmits the first packet with the internal VFID CORE_VFID to the core circuit 140 .

[0047] For the received request (the first packet with the internal VFID CORE_VFID), core circuit 140 passes the generated internal VFID CORE_VFID to all sub-modules. The sub-modules then extract the PCI E VFID PCIE_VFID from the internal VFID CORE_VFID (see Tables 1 through 6 for details) for further operation. After processing the received request, core circuit 140 transmits a response to PCIE controller 120 via VFID controller 130.

[0048] The transmit control circuit 134 is coupled between the PCIE controller 120 and the core circuit 140. Before sending the second packet (the packet pre-transmitted back by the core circuit 140 to the PCIE controller 120) to the PCIE controller 120, the transmit control circuit 134 uses the VFID lookup table 131 to restore the internal VFID CORE_VFID in the second packet to the PCIE VFID PCIE_VFID, and then transmits the second packet with the PCIE VFID PCIE_VFID to the PCIE controller 120.

[0049] For example, the transmit control circuit 134 extracts the PCIE VFID PCIE_VFID from the internal VFID CORE_VFID of the second packet (see the descriptions of Tables 1 to 6 above for details). The transmit control circuit 134 retrieves the valid bit V corresponding to the PCIE VFID PCIE_VFID extracted from the internal VFID CORE_VFID from the VFID lookup table 131. In response to the valid bit V indicating that the virtual function corresponding to the PCIE VFID PCIE_VFID has been reset and the PCIE VFID has not been reused, for example, if the valid bit V is 0, the transmit control circuit 134 discards the second packet without transmitting it to the PCIE controller 120.

[0050] In response to the valid bit V indicating that the PCIE VFID PCIE_VFID is already in use by a virtual function, for example, the valid bit V is 1, the transmit control circuit 134 retrieves the hash bit HASH_BIT corresponding to the PCIE VFID PCIE_VFID extracted from the internal VFID CORE_VFID from the VFID lookup table 131. The transmit control circuit 134 combines the PCIE VFID PCIE_VFID and the hash bit HASH_BIT to generate a reference VFID. The transmit control circuit 134 then compares the internal VFID CORE_VFID of the second packet with the reference VFID to obtain a comparison result. In response to the comparison result indicating a mismatch between the two, the transmit control circuit 134 discards the second packet without transmitting it to the PCIE controller 120. In response to the comparison result indicating a match between the two, the transmit control circuit 134 replaces the internal VFID CORE_VFID in the second packet with the PCIE VFID PCIE_VFID and then transmits the second packet with the PCIE VFID PCIE_VFID to the PCIE controller 120. The sending controller 122 decodes the returned response (the second packet) and transmits it back to the transaction layer, the data link layer, and the physical layer, and finally transmits it back to the host 10 .

[0051] In response to the PCIE controller 120 receiving a function-level reset command with the PCIE VFID PCIE_VFID issued by the host 10, the PCIE controller 120 transmits a function-level reset signal with the PCIE VFID PCIE_VFID to the FLR control circuit 133. The FLR control circuit 133 is coupled to the PCIE controller 120 and between the receive control circuit 132 and the transmit control circuit 134. In response to the FLR control circuit 133 receiving the function-level reset signal with the PCIE VFID PCIE_VFID issued by the PCIE controller 120, the FLR control circuit 133 transmits the function-level reset signal to the receive control circuit 132, the transmit control circuit 134, and the core circuit 140. Based on the notification from the FLR control circuit 133 , the receiving control circuit 132 and the sending control circuit 134 immediately abandon all packets associated with the PCIE VFID PCIE_VFID, and the core circuit 140 immediately abandons all outstanding requests (e.g., outstanding non-issued requests) associated with the PCIE VFID PCIE_VFID.

[0052] Furthermore, in response to the VFID controller 130 receiving a function-level reset signal with the PCIE VFID PCIE_VFID from the PCIE controller 120, the receive control circuit 132 sets the valid bit V associated with the PCIE VFID PCIE_VFID in the VFID lookup table 131 to an invalid state (e.g., the valid bit V is set to 0), thereby causing the transmit control circuit 134 to discard all return packets associated with the PCIE VFID PCIE_VFID. In some embodiments, in response to the VFID controller 130 receiving a function-level reset signal with the PCIE VFID PCIE_VFID from the PCIE controller 120, the receive control circuit 132 further changes the hash bit HASH_BIT associated with the PCIE VFID PCIE_VFID in the VFID lookup table 131. For example (but not limited to this), the receiving control circuit 132 changing the hash bit HASH_BIT in the VFID lookup table includes: adding 1 to the content of the hash bit HASH_BIT; and if the hash bit HASH_BIT overflows, resetting the content of the hash bit HASH_BIT to 0. In other embodiments, upon receiving a function-level reset signal, the receiving control circuit 132 temporarily does not change the hash bit HASH_BIT associated with the PCIE VFID PCIE_VFID in the VFID lookup table 131, but waits until the PCIE VFID PCIE_VFID is reused later before changing the corresponding hash bit HASH_BIT in the VFID lookup table 131.

[0053] After completing all the above steps related to function-level reset, VFID controller 130 sends a "FLR Reset Done" message to PCIE controller 120. PCIE controller 120 reclaims the reset VFID and reuses it when needed. When the PCIE VFID PCIE_VFID is reused, the receive control circuit 132 in VFID controller 130 sets the corresponding valid bit V in VFID lookup table 131 to active (e.g., set to 1), indicating that the corresponding virtual function is active.

[0054] In response to the PCIE controller 120 receiving notification information from the host 10 indicating the activation of a virtual function with the PCIE VFID PCIE_VFID, the PCIE controller 120 transmits an activation notification signal with the PCIE VFID PCIE_VFID to the receive control circuit 132. The receive control circuit 132 decodes the activation notification signal to locate an entry in the VFID lookup table 131. Based on the activation notification signal, the receive control circuit 132 sets the valid bit V associated with the PCIE VFID PCIE_VFID in the VFID lookup table 131 to a valid state (e.g., the valid bit V is set to 1). In some embodiments, in response to the receive control circuit 132 receiving the activation notification signal with the PCIE VFID PCIE_VFID from the PCIE controller 120, the receive control circuit 132 also changes the hash bit HASH_BIT associated with the PCIE VFID PCIE_VFID in the VFID lookup table 131. For example (but not limited to this), the receiving control circuit 132 changing the hash bit HASH_BIT in the VFID lookup table 131 includes: adding 1 to the content of the hash bit HASH_BIT; and if the hash bit HASH_BIT overflows, resetting the content of the hash bit HASH_BIT to 0. In other embodiments, the receiving control circuit 132 does not change the hash bit HASH_BIT associated with the PCIE VFID PCIE_VFID in the VFID lookup table 131 upon receiving the startup notification signal. Instead, the receiving control circuit 132 changes the corresponding hash bit HASH_BIT in the VFID lookup table 131 as early as when the receiving control circuit 132 receives a function-level reset signal with the PCIE VFID PCIE_VFID.

[0055] In summary, by swapping the VFIDs between the PCIE controller 120 and the core circuit 140, the core circuit 140 will track the different VFIDs from the PCIE controller 120. This way, when the PCIE controller 120 reuses the PCIE VFID PCIE_VFID that was just released by a function-level reset, the core circuit 140 will not immediately reuse the previous internal VFID CORE_VFID. Taking the hash algorithm in Table 1 as an example, assuming that the hash bit HASH_BIT was 0 before PCIE_VFID = 00 was recycled, the internal VFID CORE_VFID will now be {00, 0} = 0. After PCIE_VFID = 00 is recycled, the corresponding hash bit HASH_BIT in the VFID lookup table 131 can be changed (for example, by increasing the hash bit HASH_BIT to 1). Thus, when the next virtual function is activated and PCIE_VFID = 00 is reused, the internal VFID CORE_VFID will be the new {00, 1} = 1. When the VFID controller 130 receives a response packet with CORE_VFID = 0, the VFID controller 130 checks the VFID lookup table 131 and finds that the current correct CORE_VFID = 1 instead of 0. The VFID controller 130 knows that the response packet comes from the previously reset VFID and should discard the response packet.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PCIE device, characterized in that: The PCIE device includes: PCIE interface, used to connect to the host; A PCIE controller coupled to the PCIE interface, wherein the PCIE controller receives and processes PCIE packets from the host through the PCIE interface; a core circuit, configured to provide resources of the PCIE device to the host; and A VFID controller is coupled between the PCIE controller and the core circuit, wherein The VFID controller replaces the PCI E VFID in the first packet pre-sent by the PCIE controller to the core circuit with the internal VFID, and then transmits the first packet with the internal VFID to the core circuit; and The VFID controller replaces the internal VFID in the second packet pre-transmitted back from the core circuit to the PCIE controller with the PCIE VFID, and then transmits the second packet carrying the PCIE VFID to the PCIE controller.

2. The PCIE device according to claim 1, wherein: The VFID controller replaces the PCIE VFID with the internal VFID using a VFID lookup table, and the VFID controller restores the internal VFID to the PCIE VFID using the VFID lookup table.

3. The PCIE device according to claim 2, wherein: The VFID lookup table includes a PCIE VFID field and a hash bit field. The VFID controller retrieves the hash bit corresponding to the PCIE VFID of the first packet from the VFID lookup table, The VFID controller combines the PCIE VFID and the hash bits to generate the internal VFID, and The VFID controller replaces the PCIE VFID in the first packet with the internal VFID.

4. The PCIE device according to claim 2, wherein: The VFID lookup table includes a valid bit field and a PCIE VFID field. The VFID controller extracts the PCIE VFID from the internal VFID of the second packet, The VFID controller retrieves the valid bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, and In response to the valid bit indicating that the virtual function corresponding to the PCIE VFID has been reset and the PCIE VFID has not been reused, the VFID controller discards the second packet without transmitting it to the PCIE controller.

5. The PCIE device according to claim 4, wherein: The VFID lookup table also includes a hash bit field, In response to the valid bit indicating that the PCIE VFID has been used by the virtual function, the VFID controller retrieves a hash bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, the VFID controller combines the PCIE VFID and the hash bit to generate a reference VFID, and the VFID controller compares the internal VFID of the second packet with the reference VFID to obtain a comparison result; In response to the comparison result indicating a mismatch, the VFID controller discards the second packet without transmitting it to the PCIE controller; as well as In response to the comparison result indicating a match, the VFID controller replaces the internal VFID in the second packet with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

6. The PCIE device according to claim 1, wherein: In response to the PCIE controller receiving a function level reset command with the PCIE VFID issued by the host, the PCIE controller transmits a function level reset signal with the PCIE VFID to the VFID controller; and The VFID controller immediately discards all packets associated with the PCIE VFID based on the function level reset signal.

7. The PCIE device according to claim 6, wherein: In response to the VFID controller receiving the function-level reset signal with the PCIE VFID sent by the PCIE controller, the VFID controller sets a valid bit associated with the PCIE VFID in a VFID lookup table to an invalid state, thereby causing the VFID controller to discard all return packets associated with the PCIE VFID.

8. The PCIE device according to claim 7, wherein: In response to the VFID controller receiving the function level reset signal with the PCIE VFID sent by the PCIE controller, the VFID controller further changes a hash bit associated with the PCIE VFID in the VFID lookup table.

9. The PCIE device according to claim 8, wherein: The VFID controller changes the hash bit in the VFID lookup table including: Increment the contents of the hash bit by 1; and If the hash bits overflow, the contents of the hash bits are reset to 0.

10. The PCIE device according to claim 6, wherein: The VFID controller further transmits the function-level reset signal to the core circuit, so that the core circuit immediately abandons all outstanding requests related to the PCIE VFID.

11. The PCIE device according to claim 1, wherein: In response to the PCIE controller receiving notification information sent by the host to instruct the virtual function with the PCIE VFID to be started, the PCIE controller transmits a start notification signal with the PCIE VFID to the VFID controller; and The VFID controller sets a valid bit related to the PCIE VFID in a VFID lookup table to a valid state based on the startup notification signal.

12. The PCIE device according to claim 11, wherein: In response to the VFID controller receiving the startup notification signal carrying the PCIE VFID sent by the PCIE controller, the VFID controller further changes a hash bit associated with the PCIE VFID in the VFID lookup table.

13. The PCIE device according to claim 12, wherein: The VFID controller changes the hash bit in the VFID lookup table including: Increment the contents of the hash bit by 1; and If the hash bits overflow, the contents of the hash bits are reset to 0.

14. The PCIE device according to claim 1, wherein: The VFID controller includes: VFID lookup table; a receiving control circuit coupled between the PCIE controller and the core circuit, wherein the receiving control circuit uses the VFID lookup table to replace the PCIE VFID in the first packet with the internal VFID before sending the first packet to the core circuit; and A sending control circuit is coupled between the PCIE controller and the core circuit, wherein the sending control circuit uses the VFID lookup table to restore the internal VFID in the second packet to the PCIE VFID before sending the second packet to the PCIE controller.

15. The PCIE device according to claim 14, wherein: The VFID lookup table includes a PCIE VFID field and a hash bit field. The receiving control circuit retrieves the hash bit corresponding to the PCIE VFID of the first packet from the VFID lookup table, The receiving control circuit combines the PCIE VFID and the hash bit to generate the internal VFID, and The receiving control circuit replaces the PCIE VFID in the first packet with the internal VFID.

16. The PCIE device according to claim 14, wherein: The VFID lookup table includes a valid bit field and a PCIE VFID field. The sending control circuit extracts the PCIE VFID from the internal VFID of the second packet, The sending control circuit takes out the valid bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, and In response to the valid bit indicating that the virtual function corresponding to the PCIE VFID has been reset and the PCIE VFID has not been reused, the sending control circuit discards the second packet without transmitting it to the PCIE controller.

17. The PCIE device according to claim 16, wherein: The VFID lookup table also includes a hash bit field, In response to the valid bit indicating that the PCIE VFID has been used by the virtual function, the transmit control circuit retrieves a hash bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, the transmit control circuit combines the PCIE VFID and the hash bit to generate a reference VFID, and the transmit control circuit compares the internal VFID of the second packet with the reference VFID to obtain a comparison result; In response to the comparison result indicating a mismatch, the sending control circuit discards the second packet without transmitting it to the PCIE controller; as well as In response to the comparison result indicating a match, the transmission control circuit replaces the internal VFID in the second packet with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

18. The PCIE device according to claim 14, wherein: The VFID controller further includes: A functional level reset control circuit is coupled to the PCIE controller and coupled between the receiving control circuit and the sending control circuit, wherein In response to the PCIE controller receiving a function level reset command with the PCIE VFID issued by the host, the PCIE controller transmits a function level reset signal with the PCIE VFID to the function level reset control circuit; and In response to the function-level reset control circuit receiving the function-level reset signal with the PCIE VFID sent by the PCIE controller, the function-level reset control circuit transmits the function-level reset signal to the receiving control circuit and the transmitting control circuit, so that the receiving control circuit and the transmitting control circuit immediately discard all packets associated with the PCIE VFID.

19. The PCIE device according to claim 18, wherein: In response to the VFID controller receiving the function-level reset signal with the PCIE VFID sent by the PCIE controller, the receiving control circuit sets the valid bit associated with the PCIE VFID in the VFID lookup table to an invalid state, thereby causing the sending control circuit to discard all return packets associated with the PCIE VFID.

20. The PCIE device according to claim 19, wherein: In response to the VFID controller receiving the function level reset signal with the PCIE VFID sent by the PCIE controller, the receiving control circuit further changes a hash bit associated with the PCIE VFID in the VFID lookup table.

21. The PCIE device according to claim 20, wherein: The receiving control circuit changing the hash bit in the VFID lookup table includes: Increment the contents of the hash bit by 1; and If the hash bits overflow, the contents of the hash bits are reset to 0.

22. The PCIE device according to claim 18, wherein: The function-level reset control circuit further transmits the function-level reset signal to the core circuit, so that the core circuit immediately abandons all outstanding requests related to the PCIE VFID.

23. The PCIE device according to claim 14, wherein: In response to the PCIE controller receiving notification information sent by the host to instruct the activation of the virtual function with the PCIE VFID, the PCIE controller transmits an activation notification signal with the PCIE VFID to the receiving control circuit; as well as The receiving control circuit sets a valid bit related to the PCIE VFID in the VFID lookup table to a valid state based on the start notification signal.

24. The PCIE device according to claim 23, wherein: In response to the receiving control circuit receiving the start notification signal carrying the PCIE VFID sent by the PCIE controller, the receiving control circuit further changes a hash bit associated with the PCIE VFID in the VFID lookup table.

25. The PCIE device according to claim 24, wherein: The receiving control circuit changing the hash bit in the VFID lookup table includes: Increment the contents of the hash bit by 1; and If the hash bits overflow, the contents of the hash bits are reset to 0.

26. A method for operating a PCIE device, characterized in that: The operation method includes: receiving and processing a PCIE packet from a host via a PCIE interface of the PCIE device by a PCIE controller of the PCIE device, wherein the PCIE controller is coupled to the PCIE interface; a VFID controller of the PCIE device replacing a PCIE VFID in a first packet that the PCIE controller is to send to a core circuit of the PCIE device with an internal VFID, and then transmitting the first packet with the internal VFID to the core circuit, wherein the core circuit is configured to provide resources of the PCIE device to the host, and the VFID controller is coupled between the PCIE controller and the core circuit; and The VFID controller replaces the internal VFID in the second packet to be sent back from the core circuit to the PCIE controller with the PCIE VFID, and then transmits the second packet carrying the PCIE VFID to the PCIE controller.

27. The operating method according to claim 26, characterized in that: The operation method further includes: The VFID controller replaces the PCIE VFID with the internal VFID using a VFID lookup table, and The VFID controller uses the VFID lookup table to restore the internal VFID to the PCIE VFID.

28. The operating method according to claim 27, characterized in that: The VFID lookup table includes a PCIE VFID field and a hash bit field, and the operating method further includes: The VFID controller retrieves the hash bit corresponding to the PCIE VFID of the first packet from the VFID lookup table; The VFID controller combines the PCIE VFID and the hash bit to generate the internal VFID; and The VFID controller replaces the PCIE VFID in the first packet with the internal VFID.

29. The operating method according to claim 27, characterized in that: The VFID lookup table includes a valid bit field and a PCIE VFID field, and the operating method further includes: Extracting, by the VFID controller, the PCIE VFID from the internal VFID of the second packet; The VFID controller retrieves from the VFID lookup table a valid bit corresponding to the PCIE VFID extracted from the internal VFID; and In response to the valid bit indicating that the virtual function corresponding to the PCIE VFID has been reset and the PCIE VFID has not been reused, the VFID controller discards the second packet without transmitting it to the PCIE controller.

30. The operating method according to claim 29, characterized in that: The VFID lookup table further includes a hash bit field, and the operating method further includes: In response to the valid bit indicating that the PCIE VFID has been used by the virtual function, the VFID controller retrieves, from the VFID lookup table, a hash bit corresponding to the PCIE VFID extracted from the internal VFID, the VFID controller combines the PCIE VFID and the hash bit to generate a reference VFID, and the VFID controller compares the internal VFID of the second packet with the reference VFID to obtain a comparison result; In response to the comparison result indicating a mismatch, the VFID controller discards the second packet without transmitting it to the PCIE controller; and In response to the comparison result indicating a match, the VFID controller replaces the internal VFID in the second packet with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

31. The operating method according to claim 26, characterized in that: The operation method further includes: In response to the PCIE controller receiving a function level reset command with the PCIE VFID issued by the host, the PCIE controller transmits a function level reset signal with the PCIE VFID to the VFID controller; and All packets associated with the PCIE VFID are immediately discarded by the VFID controller based on the function level reset signal.

32. The operating method according to claim 31, characterized in that: The operation method further includes: In response to the VFID controller receiving the function-level reset signal with the PCIE VFID sent by the PCIE controller, the VFID controller sets the valid bit associated with the PCIE VFID in the VFID lookup table to an invalid state, thereby causing the VFID controller to discard all return packets associated with the PCIE VFID.

33. The operating method according to claim 32, characterized in that: The operation method further includes: In response to the VFID controller receiving the function level reset signal with the PCIE VFID sent by the PCIE controller, the VFID controller further changes a hash bit associated with the PCIE VFID in the VFID lookup table.

34. The operating method according to claim 33, characterized in that: The VFID controller changes the hash bit in the VFID lookup table including: Increment the contents of the hash bit by 1; and If the hash bits overflow, the contents of the hash bits are reset to 0.

35. The operating method according to claim 31, characterized in that: The operation method further includes: The VFID controller transmits the function-level reset signal to the core circuit, so that the core circuit immediately abandons all outstanding requests related to the PCIE VFID.

36. The operating method according to claim 26, characterized in that: The operation method further includes: In response to the PCIE controller receiving notification information sent by the host to instruct the activation of the virtual function with the PCIE VFID, the PCIE controller transmits a startup notification signal with the PCIE VFID to the VFID controller; and The VFID controller sets a valid bit related to the PCIE VFID in a VFID lookup table to a valid state based on the startup notification signal.

37. The operating method according to claim 36, characterized in that: The operation method further includes: In response to the VFID controller receiving the startup notification signal carrying the PCIE VFID sent by the PCIE controller, the VFID controller further changes a hash bit associated with the PCIE VFID in the VFID lookup table.

38. The operating method according to claim 37, characterized in that: The VFID controller changes the hash bit in the VFID lookup table including: Increment the contents of the hash bit by 1; and If the hash bits overflow, the contents of the hash bits are reset to 0.

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