Pcie device and operating method thereof

Abstract

The application provides a PCIE device and an operating method thereof. The PCIE device includes a PCIE interface, a PCIE controller, a VFID controller and a core circuit. The PCIE controller receives and processes PCIE packets from a host through the PCIE interface. The core circuit provides resources of the PCIE device to the host. The VFID controller is coupled between the PCIE controller and the core circuit. The VFID controller replaces a PCIE VFID in a first packet sent from the PCIE controller to the core circuit with an internal VFID, and then transmits the first packet with the internal VFID to the core circuit. The VFID controller replaces the internal VFID in a second packet sent from the core circuit to the PCIE controller with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

Description

TECHNICAL FIELD

[0001] The present application relates to an electronic device, and more particularly, to a Peripheral Component Interconnect Express (PCIE) device and an operating method thereof. BACKGROUND

[0002] PCIE is a commonly used connection interface between a computer and a peripheral component. Based on actual application scenarios, the peripheral component includes an AI (Artificial Intelligence) card or other peripheral components, and the AI card includes a GPU (Graphics Processing Unit) card, a GPGPU (General-Purpose GPU) card, or other AI operation components. A peripheral component with a PCIE interface is referred to as a PCIE device. Virtual functions (VFs) are widely used in PCIE devices. A PCIE device can be divided into multiple parts to provide multiple virtual functions, wherein the virtual functions can operate simultaneously on the PCIE device and share resources. These virtual functions can come from different users and have different system images (SIs). In some application scenarios, PCIE devices are widely deployed in the cloud and can be assigned to multiple users at the same time. Each user can occupy one or more virtual functions.

[0003] In PCIE protocol, memory write operation (MemWr) is called posted request, and memory read operation (MemRd) is called non-posted request. Since PCIE device is divided into multiple parts, host can reset the part when each part is suspended. Function Level Reset (FLR) mechanism enables software to reset part of hardware of PCIE device at function level granularity. Function Level Reset can cause virtual function to lose track of any outstanding request (e.g. outstanding non-posted request). Any completion message (response message of non-posted request) arrived after function level reset is called "Stale Completions". If software of host issues function level reset to PCIE device for a virtual function (assume its identifier is VFID_0) when there is outstanding request (e.g. outstanding non-posted request) for the virtual function, and then re-enable the same virtual function identifier (e.g. reuse virtual function identifier VFID_0 for another virtual function) without waiting for potential "Stale Completions", any subsequently arrived "Stale Completions" can be mistaken by another virtual function as belonging to request issued after function level reset, thus causing data corruption.

[0004] Software can avoid data corruption caused by "Stale Completions" in many ways. As system size grows, application complexity increases. Outstanding non-posted request can take longer time to return response packet to host. In large network and complex system, in order to ensure that function level reset can be completed safely and without damaging system data, software should take corresponding operation, e.g. extend waiting time to ensure that all non-posted request will return. Extending waiting time will harm system performance, because system software can need to wait longer time to reuse virtual function and hardware resource.

[0005] It should be noted that the contents of the section "BACKGROUND" are used to assist in understanding the present application. Part (or all) of the contents disclosed in the section "BACKGROUND" can not be known art to those skilled in the art. The contents disclosed in the section "BACKGROUND" do not represent that the contents are known to those skilled in the art before the present application. SUMMARY

[0006] The present application is directed to a PCIE device and its operation method.

[0007] In embodiments according to the present application, the PCIE device includes a PCIE interface, a PCIE controller, a VFID controller, and a core circuit. The PCIE interface is configured to connect to a host. The PCIE controller is coupled to the PCIE interface. The PCIE controller receives and processes PCIE packets from the host via the PCIE interface. The core circuit is configured to provide resources of the PCIE device to the host. The VFID controller is coupled between the PCIE controller and the core circuit. The VFID controller replaces a PCIE VFID in a first packet sent by the PCIE controller to the core circuit with an internal VFID, and then transmits the first packet with the internal VFID to the core circuit. The VFID controller replaces the internal VFID in a second packet sent by the core circuit to the PCIE controller with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

[0008] In embodiments according to the present application, the operation method includes: receiving and processing, by a PCIE controller of a PCIE device, PCIE packets from a host via a PCIE interface of the PCIE device; replacing, by a VFID controller of the PCIE device, a PCIE VFID in a first packet sent by the PCIE controller to a core circuit of the PCIE device with an internal VFID, and then transmitting the first packet with the internal VFID to the core circuit; and replacing, by the VFID controller, the internal VFID in a second packet sent by the core circuit to the PCIE controller with the PCIE VFID, and then transmitting the second packet with the PCIE VFID to the PCIE controller.

[0009] Based on the above, embodiments of the present application add an intermediate layer "VFID controller" between the original core circuit of the PCIE controller and the PCIE device. The VFID controller replaces the VFID in the packet sent by the PCIE controller to the core circuit from the PCIE VFID to the internal VFID, and replaces the VFID in the packet sent by the core circuit to the PCIE controller from the internal VFID to the PCIE VFID. The host may issue a function level reset to the PCIE device for a previous virtual function (assuming its identifier is VFID_0), that is, the PCIE VFID VFID_0 is released, and then the host reuses the VFID_0 of the same PCIE VFID for a new virtual function. In the context of "the same PCIE VFID being reused for different virtual functions", although the previous virtual function and the new virtual function use the same PCIE VFID VFID_0 at different times, the previous virtual function and the new virtual function can use different internal VFIDs for the core circuit. Therefore, the VFID controller can identify whether the packet sent by the core circuit to the PCIE controller corresponds to the previous virtual function or the new virtual function. Accordingly, the VFID controller can release the VFID in advance while improving reliability.

[0010] In order to make the above features and advantages of the present application more apparent, specific embodiments are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a circuit block diagram of a PCIE device according to an embodiment of the present application;

[0012] Figure 2 is a flowchart of an operation method of a PCIE device according to an embodiment of the present application;

[0013] Figure 3 is a circuit block diagram of a PCIE controller and a VFID controller according to an embodiment of the present application.

[0014] BRIEF DESCRIPTION OF DRAWINGS

[0015] 10: host

[0016] 100: PCIE device

[0017] 110: PCIE interface

[0018] 120: PCIE controller

[0019] 121: receiving controller

[0020] 122: sending controller

[0021] 123: PCIE VFID queue

[0022] 130: VFID controller

[0023] 131: VFID lookup table

[0024] 132: receive control circuit

[0025] 133: FLR control circuit

[0026] 134: send control circuit

[0027] 140: core circuit

[0028] CORE VFID: internal VFID

[0029] PCIE VFID: PCIE VFID DETAILED DESCRIPTION

[0030] Reference will now be made to exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, identical or similar components shown in the figures and described in the text are labeled with the same reference numerals throughout the description.

[0031] The term "coupled" or "connected" used in the entire specification (including claims) can refer to any direct or indirect connection. For example, if a first device is coupled or connected to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or connection means. The terms "first", "second", and the like used in the entire specification (including claims) are used to name components, or to distinguish different embodiments or ranges, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components. In addition, wherever possible, the same components, members, steps represented by the same reference numerals in the drawings and embodiments are used to represent the same or similar parts. Components / members / steps using the same reference numerals or using the same terms in different embodiments can be referred to each other in the relevant description. It should be understood that the features of the following embodiments can be combined with each other. For example, the features of the second embodiment can be combined with the features of the first embodiment. Those skilled in the art can select appropriate combinations of features according to actual design needs.

[0032] Figure 1 is a circuit module schematic diagram of a PCIE device according to an embodiment of the present application. Based on the request of the host 10, the PCIE device 100 can provide resources (such as memory space or other hardware resources) to the host 10. Figure 1The PCIE device 100 includes a PCIE interface 110, a PCIE controller 120, a VFID controller 130, and a core circuit 140. By adding an intermediate layer (the VFID controller 130) between the PCIE controller 120 and the core circuit 140, the PCIE device 100 releases PCIE VFIDs in advance while improving reliability. The VFID controller 130 replaces the VFID in the packet sent by the PCIE controller 120 to the core circuit 140 and replaces the VFID in the packet sent by the core circuit 140 to the PCIE controller 120.

[0033] The PCIE interface 110 is configured to connect to the host 10. The PCIE controller 120 is coupled to the PCIE interface 110. The PCIE controller 120 receives and processes PCIE packets from the host 10 through the PCIE interface 110. The VFID controller 130 is coupled between the PCIE controller 120 and the core circuit 140. Based on the request of the host 10, the core circuit 140 provides resources (e.g., memory space, computing power, or other hardware resources) of the PCIE device 100 to the host 10 through the PCIE interface 110, the PCIE controller 120, and the VFID controller 130. Based on actual design and application, the PCIE controller 120 includes a known PCIE controller or other PCIE controller.

[0034] Figure 2 FIG. 1 is a flowchart of an operation method of a PCIE device according to an embodiment of the present application. Please refer to FIG. 1 and FIG. 2. Figure 1 Figure 2 In step S210, the PCIE controller 120 receives and processes PCIE packets from the host 10 through the PCIE interface 110. In step S220, the VFID controller 130 replaces the PCIE VFID PCIE VFID in the first packet sent by the PCIE controller 120 to the core circuit 140 with an internal VFID CORE VFID. Based on actual application scenarios, the content of the first packet can include a request (e.g., a read command) made by the host 10 to the PCIE device 100. Then, the VFID controller 130 transmits the first packet with the internal VFID CORE VFID to the core circuit 140.

[0035] ​The core circuit 140 executes the request (first packet) of the host 10, and then returns the data (second packet) corresponding to the request to the PCIE controller 120 through the VFID controller 130. In step S230, the VFID controller 130 replaces the internal VFID CORE VFID in the second packet pre-returned to the PCIE controller 120 by the core circuit 140 with the PCIE VFID PCIE VFID, and then transmits the second packet with the PCIE VFID PCIE VFID to the PCIE controller 120.

[0036] The host 10 can issue a function-level reset to the PCIE device 100 for a previous virtual function (assuming its identifier is PCIE VFID PCIE VFID 0), i.e., the PCIE VFID PCIE VFID 0 is released. Then, the host 10 reuses the same PCIE VFID PCIE VFID 0 for a new virtual function. In the context of "the same PCIE VFID PCIE VFID being reused for different virtual functions", although the previous virtual function and the new virtual function use the same PCIE VFID PCIE VFID 0 at different time periods, the previous virtual function and the new virtual function can use different internal VFIDs CORE VFIDs to the core circuit 140. Therefore, the VFID controller 130 can identify whether the packet pre-transmitted by the core circuit 140 to the PCIE controller 120 corresponds to the previous virtual function (the virtual function that has been disabled due to the reset) or the new virtual function (the virtual function that is currently enabled). Based on this, the VFID controller can release the VFID in advance, while improving the reliability.

[0037] In some embodiments, the VFID controller 130 can use a VFID lookup table to replace the PCIE VFID PCIE VFID with the internal VFID CORE VFID, and the VFID controller 130 can use the VFID lookup table to restore the internal VFID CORE VFID to the PCIE VFID PCIE VFID. For example (but not limited to), the VFID lookup table includes a valid bit field, a PCIE VFID field, and a hash bit field.

[0038] The VFID controller 130 retrieves the hash bit corresponding to the PCIE VFID PCIE_VFID in the first packet (the packet pre-sent by the PCIE controller 120 to the core circuit 140) from the VFID lookup table. The VFID controller 130 combines the PCIE VFID PCIE_VFID and the hash bit to generate the internal VFID CORE_VFID. This embodiment does not limit the specific implementation of the PCIE VFID PCIE_VFID and the hash bit. For example, assuming that the PCIE VFID PCIE_VFID has N bits and the hash bit has M bits. Then there may be 2 N Different virtual functions, and each virtual function can correspond to 2 M An internal VFID CORE_VFID.

[0039] This embodiment does not limit the combination of the PCIE VFID PCIE_VFID and the hash bits. For example, VFID controller 130 can use a hash algorithm to map the PCIE VFID PCIE_VFID to an internal VFIDCORE_VFID, so that each PCIE VFID PCIE_VFID can correspond to multiple internal VFIDs CORE_VFID. Combining the internal VFID CORE_VFID from the PCIEVFID PCIE_VFID and the hash bits is simple, easy, and hardware-friendly. Restoring the PCIE VFID PCIE_VFID from the internal VFIDCORE_VFID and the hash bits is simple, easy, and hardware-friendly.

[0040] For example, assuming the number of bits N of PCIE VFID PCIE_VFID is 2, there are 2 2 = 4 original PCIE VFID PCIE_VFID, respectively {0, 1, 2, 3}. Assuming the number of hash bits M = 1, each original PCIE VFID PCIE_VFID can correspond to 2 1 = 2 internal VFIDs CORE_VFID. Table 1 below shows a first embodiment of the hash algorithm. In the embodiment shown in Table 1, the PCIE VFID PCIE_VFID is placed in the MSB (Most Significant Bit) of the internal VFID CORE_VFID, while the hash bit is placed in the LSB (Least Significant Bit) of the internal VFID CORE_VFID. In this case, for example, when the internal VFID CORE_VFID is 0 or 1, the core circuit 140 can determine that the original PCIE VFID PCIE_VFID is 0.

[0041] Table 1: Combination of PCIE VFID PCIE VFID and hash bit

[0042]

[0043] Table 2 below shows a second embodiment of the hash algorithm. In the embodiment shown in Table 2, it is assumed that the number of bits N of the PCIE VFID PCIE VFID is 2, that the number of bits M of the hash bit is 1, that the PCIE VFID PCIE VFID is placed in the LSB portion of the internal VFID CORE VFID, and that the hash bit is placed in the MSB portion of the internal VFID CORE VFID. At this time, for example, when the internal VFID CORE VFID is 0 or 4, the core circuit 140 can know that the original PCIE VFID PCIE VFID is 0.

[0044] Table 2: Combination of PCIE VFID PCIE VFID and hash bit

[0045]

[0046] Table 3 below shows a third embodiment of the hash algorithm. In the embodiment shown in Table 3, it is assumed that the number of bits N of the PCIE VFID PCIE VFID is 2, that the number of bits M of the hash bit is 1, and that the hash bit is placed between the two bits of the PCIE VFID PCIE VFID. At this time, for example, when the internal VFID CORE VFID is 0 or 2, the core circuit 140 can know that the original PCIE VFID PCIE VFID is 0.

[0047] Table 3: Combination of PCIE VFID PCIE VFID and hash bit

[0048]

[0049] Table 4 below shows a fourth embodiment of the hash algorithm. In the embodiment shown in Table 4, it is assumed that the number of bits N of the PCIE VFID PCIE VFID is 2, that the number of bits M of the hash bit is 2, that the PCIE VFID PCIE VFID is placed in the MSB portion of the internal VFID CORE VFID, and that the hash bit is placed in the LSB portion of the internal VFID CORE VFID. At this time, for example, when the internal VFID CORE VFID is 0, 1, 2, or 3, the core circuit 140 can know that the original PCIE VFID PCIE VFID is 0.

[0050] Table 4: Combination of PCIE VFID PCIE VFID and hash bits

[0051]

[0052] Table 5 below shows a fifth embodiment of the hash algorithm. In the embodiment shown in Table 5, it is assumed that the number of bits N of the PCIE VFID PCIE VFID is 2, that the number of bits M of the hash bits is 2, that the PCIE VFID PCIE VFID is placed in the LSB portion of the internal VFID CORE VFID, and that the hash bits are placed in the MSB portion of the internal VFID CORE VFID. At this time, for example, when the internal VFID CORE VFID is 0, 4, 8, or 12, the core circuit 140 can know that the original PCIE VFID PCIE VFID is 0.

[0053] Table 5: Combination of PCIE VFID PCIE VFID and hash bits

[0054]

[0055] Table 6 below shows a sixth embodiment of the hash algorithm. In the embodiment shown in Table 6, it is assumed that the number of bits N of the PCIE VFID PCIE VFID is 2, that the number of bits M of the hash bits is 2, and that the hash bits are placed between the two bits of the PCIE VFID PCIE VFID. At this time, for example, when the internal VFID CORE VFID is 0, 2, 4, or 6, the core circuit 140 can know that the original PCIE VFID PCIE VFID is 0.

[0056] Table 6: Combination of PCIE VFID PCIE VFID and hash bits

[0057]

[0058] The VFID controller 130 extracts the PCIE VFID PCIE VFID from the internal VFID CORE VFID of the second packet (the packet that the core circuit 140 pre-transmits to the PCIE controller 120). For example, the VFID controller 130 can infer the original PCIE VFID PCIE VFID from the internal VFID CORE VFID of the second packet according to the above-mentioned descriptions of Tables 1-6. Next, the VFID controller 130 obtains the valid bit corresponding to the PCIE VFID PCIE VFID extracted from the internal VFID CORE VFID from the VFID lookup table. In response to the valid bit indicating that the virtual function corresponding to the PCIE VFID PCIE VFID has been reset and the PCIE VFID PCIE VFID has not been reused, such as the valid bit being 0, the VFID controller 130 discards the second packet without transmitting the second packet to the PCIE controller 120.

[0059] In response to the valid bit indicating that the PCIE VFID PCIE VFID has been used by a virtual function, such as the valid bit being 1, the VFID controller 130 obtains the hash bit corresponding to the PCIE VFID PCIE VFID extracted from the internal VFID CORE VFID from the VFID lookup table. Then, the VFID controller 130 combines the PCIE VFID PCIE VFID and the hash bit to generate a reference VFID. The VFID controller 130 compares the internal VFID CORE VFID of the second packet with the reference VFID to obtain a comparison result. In response to the comparison result indicating that the two do not match, the VFID controller 130 discards the second packet without transmitting the second packet to the PCIE controller 120. In response to the comparison result indicating that the two match, the VFID controller 130 replaces the internal VFID CORE VFID in the second packet with the PCIE VFID PCIE VFID, and then transmits the second packet with the PCIE VFID PCIE VFID to the PCIE controller 120.

[0060] In response to the PCIE controller 120 receiving the function-level reset command with the PCIE VFID PCIE VFID from the host 10, the PCIE controller 120 transmits a function-level reset signal with the PCIE VFID PCIE VFID to the VFID controller 130. The VFID controller 130 immediately abandons all packets associated with the PCIE VFID PCIE VFID based on the function-level reset signal. In addition, the VFID controller 130 also transmits the function-level reset signal to the core circuit 140 to cause the core circuit 140 to immediately abandon all outstanding requests (e.g., outstanding non-posted requests) associated with the PCIE VFID PCIE VFID. In response to the VFID controller 130 receiving the function-level reset signal with the PCIE VFID PCIE VFID from the PCIE controller 120, the VFID controller 130 sets the valid bit associated with the PCIE VFID PCIE VFID in the VFID lookup table to the invalid state (e.g., the valid bit is set to 0), thereby causing the VFID controller 130 to abandon all return packets associated with the PCIE VFID PCIE VFID.

[0061] In some embodiments, in response to the VFID controller 130 receiving the function-level reset signal with the PCIE VFID PCIE VFID from the PCIE controller 120, the VFID controller 130 also changes the hash bit associated with the PCIE VFID PCIE VFID in the VFID lookup table. For example, but not limited to, the VFID controller 130 changing the hash bit in the VFID lookup table includes: incrementing the content of the hash bit by 1; and resetting the content of the hash bit to 0 if the hash bit overflows. In other embodiments, upon receiving the function-level reset signal, the VFID controller 130 does not change the hash bit associated with the PCIE VFID PCIE VFID in the VFID lookup table temporarily, but waits until later when the PCIE VFID PCIE VFID is reused to change the corresponding hash bit in the VFID lookup table.

[0062] In response to the PCIE controller 120 receiving the notification information indicating to start the virtual function with the PCIE VFID PCIE VFID from the host 10, the PCIE controller 120 transmits a start notification signal with the PCIE VFID PCIE VFID to the VFID controller 130. The VFID controller 130 sets the valid bit associated with the PCIE VFID PCIE VFID in the VFID lookup table to the valid state (e.g., the valid bit is set to 1) based on the start notification signal.

[0063] In some embodiments, in response to VFID controller 130 receiving a start notification signal issued by PCIE controller 120 with PCIE VFID PCIE VFID, VFID controller 130 also changes the hash bit in VFID lookup table associated with PCIE VFID PCIE VFID. For example, but not limited to, VFID controller 130 changing the hash bit in VFID lookup table includes: incrementing the content of the hash bit by 1; and if the hash bit overflows, resetting the content of the hash bit to 0. In other embodiments, VFID controller 130 does not change the hash bit in VFID lookup table associated with PCIE VFID PCIE VFID upon receiving the start notification signal, but changes the corresponding hash bit in VFID lookup table as early as VFID controller 130 receives a function level reset signal with this PCIE VFID PCIE VFID.

[0064] Figure 3 is a circuit block diagram of PCIE controller and VFID controller shown according to an embodiment of the present application. Figure 3 The illustrated PCIE controller 120 and VFID controller 130 can be implemented as Figure 1 One of the many implementation examples of the illustrated PCIE controller 120 and VFID controller 130. Figure 3 The illustrated PCIE device 100, PCIE interface 110, PCIE controller 120, VFID controller 130 and core circuit 140 can refer to the related descriptions of Figure 1 . In Figure 3In the illustrated embodiment, the PCIE controller 120 includes a receive controller 121, a transmit controller 122, and a PCIE VFID queue 123, and the VFID controller 130 includes a VFID lookup table 131, a receive control circuit 132, a FLR control circuit 133, and a transmit control circuit 134. Depending on different designs, in some embodiments, the implementation of at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140 can be a hardware circuit. In other embodiments, the implementation of at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140 can be a combination of more than one of hardware, firmware, and software (i.e., a program).

[0065] In hardware form, at least one of the PCIE controller 120, the reception controller 121, the transmission controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the reception control circuit 132, the FLR control circuit 133, the transmission control circuit 134, and the core circuit 140 can be implemented as a logic circuit on an integrated circuit. For example, the related functions of at least one of the PCIE controller 120, the reception controller 121, the transmission controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the reception control circuit 132, the FLR control circuit 133, the transmission control circuit 134, and the core circuit 140 can be implemented as various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, ASICs (Application-Specific Integrated Circuits), DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), CPUs (Central Processing Units), or other processing units. The related functions of at least one of the PCIE controller 120, the reception controller 121, the transmission controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the reception control circuit 132, the FLR control circuit 133, the transmission control circuit 134, and the core circuit 140 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

[0066] In terms of software or firmware, the functions of at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140 can be implemented as programming codes. For example, at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140 is implemented using a general programming language (e.g., C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a "non-transitory machine-readable storage medium." In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory or a storage device. An electronic device (e.g., a computer, a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functions of at least one of the PCIE controller 120, the receive controller 121, the transmit controller 122, the PCIE VFID queue 123, the VFID controller 130, the VFID lookup table 131, the receive control circuit 132, the FLR control circuit 133, the transmit control circuit 134, and the core circuit 140.

[0067] The PCIE controller 120 receives PCIE packets from the host 10 through the PCIE interface 110. The PCIE packets are decoded through the physical layer, the data link layer, and the transaction layer to generate TLPs (Transaction Layer Packets). The TLPs are sent to the receive controller 121. The receive controller 121 receives the decoded TLPs and transmits them to the core circuit 140 through the VFID controller 130. Depending on the actual design and application, the receive controller 121 can convert the TLPs to other protocols, such as the AXI (Advanced eXtensible Interface) protocol or any other protocol recognizable by the core circuit 140, and then transmit them to the core circuit 140 through the VFID controller 130. The PCIE VFID queue 123 manages the VFIDs of the PCIE device 100. The send controller 122 receives request or response packets from the core circuit 140 through the VFID controller 130, converts the packets to TLPs, and transmits them back to the host 10 through the PCIE interface 110.

[0068] The VFID lookup table 131 includes a valid bit V field, a PCIE VFID PCIE VFID field, and a hash bit HASH BIT field. The valid bit V field is used to indicate whether the virtual function is in an active state. The content of the PCIE VFID PCIE VFID field comes from the PCIE controller 120. The PCIE VFID PCIE VFID is used for packets to and from the PCIE controller 120. The receive control circuit 132 is coupled between the PCIE controller 120 and the core circuit 140. Before sending the first packet (the packet sent by the PCIE controller 120 to the core circuit 140) to the core circuit 140, the receive control circuit 132 uses the VFID lookup table 131 to replace the PCIE VFID PCIE VFID in the first packet with an internal VFID CORE VFID.

[0069] For example, the receiving control circuit 132 extracts the hash bit HASH_BIT corresponding to the PCIE VFID PCIE VFID of the first packet from the VFID lookup table 131. The receiving control circuit 132 generates the internal VFID CORE VFID according to the combination of the PCIE VFID PCIE VFID and the hash bit HASH_BIT by using a hash algorithm. The present embodiment does not limit the specific implementation of the PCIE VFID PCIE VFID and the hash bit HASH_BIT. The present embodiment also does not limit the combination manner of the PCIE VFID PCIE VFID and the hash bit HASH_BIT. For example, the PCIE VFID PCIE VFID, the hash bit HASH_BIT and the internal VFID CORE VFID can refer to the related descriptions of the above Tables 1 to 6 and be analogized. Next, the receiving control circuit 132 replaces the PCIE VFID PCIE VFID in the first packet with the internal VFID CORE VFID, and then transmits the first packet with the internal VFID CORE VFID to the core circuit 140.

[0070] For the received request (the first packet with the internal VFID CORE VFID), the core circuit 140 transmits the generated internal VFID CORE VFID to all sub-modules, and then the sub-modules extract the PCIE VFID PCIE VFID (for details, refer to the related descriptions of the above Tables 1 to 6) from the internal VFID CORE VFID for operation. After the core circuit 140 processes the received request, the core circuit 140 transmits a response to the PCIE controller 120 through the VFID controller 130.

[0071] The sending control circuit 134 is coupled between the PCIE controller 120 and the core circuit 140. Before transmitting the second packet (the packet pre-transmitted by the core circuit 140 to the PCIE controller 120) to the PCIE controller 120, the sending control circuit 134 uses the VFID lookup table 131 to restore the internal VFID CORE VFID in the second packet to the PCIE VFID PCIE VFID, and then transmits the second packet with the PCIE VFID PCIE VFID to the PCIE controller 120.

[0072] For example, the sending control circuit 134 extracts the PCIE VFID PCIE VFID from the internal VFID CORE VFID of the second packet (see the above description of Tables 1-6). The sending control circuit 134 retrieves the valid bit V corresponding to the PCIE VFID PCIE VFID extracted from the internal VFID CORE VFID from the VFID lookup table 131. In response to the valid bit V indicating that the virtual function corresponding to the PCIE VFID PCIE VFID has been reset and the PCIE VFID has not been repurposed, e.g., the valid bit V is 0, the sending control circuit 134 discards the second packet without transmitting it to the PCIE controller 120.

[0073] In response to the valid bit V indicating that the PCIE VFID PCIE VFID has been repurposed, e.g., the valid bit V is 1, the sending control circuit 134 retrieves the hash bit HASH BIT corresponding to the PCIE VFID PCIE VFID extracted from the internal VFID CORE VFID from the VFID lookup table 131, the sending control circuit 134 combines the PCIE VFID PCIE VFID and the hash bit HASH BIT to generate a reference VFID, and the sending control circuit 134 compares the internal VFID CORE VFID of the second packet with the reference VFID to obtain a comparison result. In response to the comparison result indicating that the two do not match, the sending control circuit 134 discards the second packet without transmitting it to the PCIE controller 120. In response to the comparison result indicating that the two match, the sending control circuit 134 replaces the internal VFID CORE VFID in the second packet with the PCIE VFID PCIE VFID, and then transmits the second packet with the PCIE VFID PCIE VFID to the PCIE controller 120. The sending controller 122 decodes the returned response (second packet) and transmits it back to the transaction layer, the data link layer, and the physical layer, and finally back to the host 10.

[0074] In response to the PCIE controller 120 receiving the function-level reset command with the PCIE VFID PCIE VFID from the host 10, the PCIE controller 120 transmits a function-level reset signal with the PCIE VFID PCIE VFID to the FLR control circuit 133. The FLR control circuit 133 is coupled to the PCIE controller 120, and is coupled between the receive control circuit 132 and the transmit control circuit 134. In response to the FLR control circuit 133 receiving the function-level reset signal with the PCIE VFID PCIE VFID from the PCIE controller 120, the FLR control circuit 133 transmits the function-level reset signal to the receive control circuit 132, the transmit control circuit 134, and the core circuit 140. Based on the notification from the FLR control circuit 133, the receive control circuit 132 and the transmit control circuit 134 immediately discard all packets related to the PCIE VFID PCIE VFID, and the core circuit 140 immediately discards all outstanding requests (e.g., outstanding non-posted requests) related to the PCIE VFID PCIE VFID.

[0075] In addition, in response to the VFID controller 130 receiving the function-level reset signal with the PCIE VFID PCIE VFID from the PCIE controller 120, the receive control circuit 132 sets the valid bit V in the VFID lookup table 131 related to the PCIE VFID PCIE VFID to an invalid state (e.g., the related valid bit V is set to 0), so that the transmit control circuit 134 discards all return packets related to the PCIE VFID PCIE VFID. In some embodiments, in response to the VFID controller 130 receiving the function-level reset signal with the PCIE VFID PCIE VFID from the PCIE controller 120, the receive control circuit 132 also changes the hash bit HASH BIT in the VFID lookup table 131 related to the PCIE VFID PCIE VFID. For example, but not limited to, the receive control circuit 132 changing the hash bit HASH BIT in the VFID lookup table includes: incrementing the content of the hash bit HASH BIT by 1; and if the hash bit HASH BIT overflows, resetting the content of the hash bit HASH BIT to 0. In other embodiments, upon receiving the function-level reset signal, the receive control circuit 132 does not change the hash bit HASH BIT in the VFID lookup table 131 related to the PCIE VFID PCIE VFID temporarily, but waits until this PCIE VFID PCIE VFID is reused to change the corresponding hash bit HASH BIT in the VFID lookup table 131.

[0076] After all the above steps for function level reset are completed, the VFID controller 130 sends a "FLR Reset Done" message to the PCIE controller 120. The PCIE controller 120 will reclaim the reset VFID and reuse it when needed by the system. When this PCIE VFID PCIE VFID is reused, the receive control circuit 132 in the VFID controller 130 will set the corresponding valid bit V in the VFID lookup table 131 (e.g., the valid bit V is set to 1) to indicate that the corresponding virtual function is active.

[0077] In response to the PCIE controller 120 receiving the notification from the host 10 indicating to start the virtual function with the PCIE VFID PCIE VFID, the PCIE controller 120 sends a start notification signal with the PCIE VFID PCIE VFID to the receive control circuit 132. The receive control circuit 132 decodes the start notification signal to find the entry in the VFID lookup table 131. The receive control circuit 132 sets the valid bit V in the VFID lookup table 131 associated with the PCIE VFID PCIE VFID to valid (e.g., the valid bit V is set to 1) based on the start notification signal. In some embodiments, in response to the receive control circuit 132 receiving the start notification signal with the PCIE VFID PCIE VFID from the PCIE controller 120, the receive control circuit 132 also changes the hash bit HASH BIT in the VFID lookup table 131 associated with the PCIE VFID PCIE VFID. For example, but not limited to, the receive control circuit 132 changing the hash bit HASH BIT in the VFID lookup table 131 includes: incrementing the content of the hash bit HASH BIT by 1; and if the hash bit HASH BIT overflows, resetting the content of the hash bit HASH BIT to 0. In other embodiments, the receive control circuit 132 does not change the hash bit HASH BIT in the VFID lookup table 131 associated with the PCIE VFID PCIE VFID when receiving the start notification signal, but changes the corresponding hash bit HASH BIT in the VFID lookup table 131 early when the receive control circuit 132 receives the function level reset signal with this PCIE VFID PCIE VFID.

[0078] In summary, by replacing the VFID between the PCIE controller 120 and the core circuit 140, the core circuit 140 will track different VFID from the PCIE controller 120. In this way, when the PCIE controller 120 reuses the PCIE VFID PCIE VFID just released by the function level reset, the core circuit 140 will not immediately reuse the last internal VFID CORE VFID. Taking the hash algorithm of the above table 1 as an example, assuming that the hash bit HASH BIT is 0 before the PCIE VFID = 00 is recycled, the internal VFID CORE VFID will be the new {00, 0} = 0. After the PCIE VFID = 00 is recycled, we can change the corresponding hash bit HASH BIT in the VFID lookup table 131 (for example, increase the hash bit HASH BIT to 1). In this way, when the next virtual function is started and the PCIE VFID = 00 is reused, the internal VFID CORE VFID will be the new {00, 1} = 1. When the VFID controller 130 receives a response packet with CORE VFID = 0, the VFID controller 130 checks the VFID lookup table 131 and finds that the current correct CORE VFID = 1 instead of 0. The VFID controller 130 knows that the response packet comes from the last reset VFID and should be discarded.

[0079] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIE device, comprising: The PCIE device comprises: a PCIE interface for connecting a host; a PCIE controller coupled to the PCIE interface, wherein the PCIE controller receives and processes PCIE packets from the host through the PCIE interface; a core circuit for providing resources of the PCIE device to the host; and a VFID controller coupled between the PCIE controller and the core circuit, wherein the VFID controller replaces a PCIE VFID in a first packet pre-transmitted by the PCIE controller to the core circuit with an internal VFID, and then transmits the first packet with the internal VFID to the core circuit; and the VFID controller replaces the internal VFID in a second packet pre-transmitted by the core circuit to the PCIE controller with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller; wherein the internal VFID is used to identify PCIE packets transmitted between the VFID controller and the core circuit; wherein, in a context where the same PCIE VFID is reused for different virtual functions, the VFID controller identifies whether a first packet pre-transmitted by the core circuit to the PCIE controller corresponds to a previous virtual function or a new virtual function of the PCIE device to determine whether to release the PCIE VFID in advance, in a case where the previous virtual function and the new virtual function use the same PCIE VFID at different time periods and use different internal VFIDs for the core circuit.

2. The PCIE device of claim 1, wherein, The VFID controller replaces the PCIE VFID with the internal VFID using a VFID lookup table, and the VFID controller restores the internal VFID to the PCIE VFID using the VFID lookup table.

3. The PCIE device of claim 2, wherein, The VFID lookup table comprises a PCIE VFID field and a hash bit field, The VFID controller extracts a hash bit corresponding to the PCIE VFID of the first packet from the VFID lookup table, The VFID controller generates the internal VFID by combining the PCIE VFID and the hash bit, and The VFID controller replaces the PCIE VFID in the first packet with the internal VFID.

4. The PCIE device of claim 2, wherein, The VFID lookup table comprises a valid bit field and a PCIE VFID field, The VFID controller extracts the PCIE VFID from the internal VFID of the second packet, The VFID controller extracts a valid bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, and The VFID controller replaces the internal VFID in the second packet with the PCIE VFID. In response to the valid bit indicating that the virtual function corresponding to the PCIE VFID has been reset and the PCIE VFID has not been repurposed, the VFID controller discards the second packet without transmitting to the PCIE controller.

5. The PCIE device of claim 4, wherein, The VFID lookup table further includes a hash bit field, In response to the valid bit indicating that the PCIE VFID has been used by the virtual function, the VFID controller extracts the hash bit corresponding to the PCIE VFID from the internal VFID from the VFID lookup table, the VFID controller combines the PCIE VFID and the hash bit to generate a reference VFID, and the VFID controller compares the internal VFID of the second packet with the reference VFID to obtain a comparison result; In response to the comparison result indicating a mismatch, the VFID controller discards the second packet without transmitting to the PCIE controller; and In response to the comparison result indicating a match, the VFID controller replaces the internal VFID in the second packet with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

6. The PCIE device of claim 1, wherein, in response to the PCIE controller receiving a function level reset command issued by the host with the PCIE VFID, the PCIE controller transmits a function level reset signal with the PCIE VFID to the VFID controller; and the VFID controller immediately abandons all packets related to the PCIE VFID based on the function level reset signal.

7. The PCIE device of claim 6, wherein, in response to the VFID controller receiving the function level reset signal with the PCIE VFID from the PCIE controller, the VFID controller sets a valid bit related to the PCIE VFID in a VFID lookup table to an invalid state, thereby causing the VFID controller to abandon all return packets related to the PCIE VFID.

8. The PCIE device of claim 7, wherein, in response to the VFID controller receiving the function level reset signal with the PCIE VFID from the PCIE controller, the VFID controller further changes a hash bit related to the PCIE VFID in the VFID lookup table.

9. The PCIE device of claim 8, wherein, the VFID controller changing the hash bit in the VFID lookup table includes: incrementing a content of the hash bit; and if the hash bit overflows, resetting the content of the hash bit to 0.

10. The PCIE device of claim 6, wherein, the VFID controller further transmits the function level reset signal to the core circuit to cause the core circuit to immediately abandon all outstanding requests related to the PCIE VFID.

11. The PCIE device of claim 1, wherein, in response to the PCIE controller receiving the notification information issued by the host for indicating to start a virtual function with the PCIE VFID, the PCIE controller transmits a start notification signal with the PCIE VFID to the VFID controller; and the VFID controller sets a valid bit in a VFID lookup table related to the PCIE VFID as valid based on the start notification signal.

12. The PCIE device of claim 11, wherein, in response to the VFID controller receiving the start notification signal with the PCIE VFID transmitted by the PCIE controller, the VFID controller further changes a hash bit in the VFID lookup table related to the PCIE VFID.

13. The PCIE device of claim 12, wherein, the VFID controller changing the hash bit in the VFID lookup table comprises: incrementing a content of the hash bit by 1; and if the hash bit overflows, resetting the content of the hash bit to 0.

14. The PCIE device of claim 1, wherein, the VFID controller comprises: a VFID lookup table; a receiving control circuit coupled between the PCIE controller and the core circuit, wherein the receiving control circuit replaces the PCIE VFID in the first packet with the internal VFID using the VFID lookup table before transmitting the first packet to the core circuit; and a transmitting control circuit coupled between the PCIE controller and the core circuit, wherein the transmitting control circuit restores the internal VFID in the second packet to the PCIE VFID using the VFID lookup table before transmitting the second packet to the PCIE controller.

15. The PCIE device of claim 14, wherein, the VFID lookup table comprises a PCIE VFID field and a hash bit field, the receiving control circuit extracts a hash bit corresponding to the PCIE VFID of the first packet from the VFID lookup table, the receiving control circuit combines the PCIE VFID and the hash bit to generate the internal VFID, and the receiving control circuit replaces the PCIE VFID in the first packet with the internal VFID.

16. The PCIE device of claim 14, wherein, the VFID lookup table comprises a valid bit field and a PCIE VFID field, the transmitting control circuit extracts the PCIE VFID from the internal VFID of the second packet, the transmitting control circuit extracts a valid bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, and in response to the valid bit indicating that a virtual function corresponding to the PCIE VFID has been reset and the PCIE VFID has not been reused, the transmitting control circuit discards the second packet without transmitting to the PCIE controller.

17. The PCIE device of claim 16, wherein, the VFID lookup table further comprises a hash bit field, In response to the valid bit indicating that the PCIE VFID has been used by the virtual function, the sending control circuit extracts a hash bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, the sending control circuit combines the PCIE VFID and the hash bit to generate a reference VFID, and the sending control circuit compares the internal VFID of the second packet with the reference VFID to obtain a comparison result; In response to the comparison result indicating a mismatch, the sending control circuit discards the second packet without transmitting to the PCIE controller; and In response to the comparison result indicating a match, the sending control circuit replaces the internal VFID in the second packet with the PCIE VFID, and then transmits the second packet with the PCIE VFID to the PCIE controller.

18. The PCIE device of claim 14, wherein, The VFID controller further comprises: a function level reset control circuit coupled to the PCIE controller, and coupled between the receiving control circuit and the sending control circuit, wherein in response to the PCIE controller receiving a function level reset command issued by the host with the PCIE VFID, the PCIE controller transmits a function level reset signal with the PCIE VFID to the function level reset control circuit; and in response to the function level reset control circuit receiving the function level reset signal with the PCIE VFID issued by the PCIE controller, the function level reset control circuit transmits the function level reset signal to the receiving control circuit and the sending control circuit, so that the receiving control circuit and the sending control circuit immediately discard all packets related to the PCIE VFID.

19. The PCIE device of claim 18, wherein in response to the VFID controller receiving the function level reset signal with the PCIE VFID issued by the PCIE controller, the receiving control circuit sets a valid bit related to the PCIE VFID in the VFID lookup table to an invalid state, so that the sending control circuit discards all return packets related to the PCIE VFID.

20. The PCIE device of claim 19, wherein in response to the VFID controller receiving the function level reset signal with the PCIE VFID issued by the PCIE controller, the receiving control circuit further changes a hash bit related to the PCIE VFID in the VFID lookup table.

21. The PCIE device of claim 20, wherein, The receiving control circuit changing the hash bit in the VFID lookup table comprises: incrementing a content of the hash bit; and if the hash bit overflows, resetting the content of the hash bit to 0.

22. The PCIE device of claim 18, wherein, The function level reset control circuit also transmits the function level reset signal to the core circuit to make the core circuit immediately abandon all uncompleted requests related to the PCIE VFID.

23. The PCIE device of claim 14, wherein, in response to the PCIE controller receiving notification information issued by the host to indicate starting a virtual function with the PCIE VFID, the PCIE controller transmits a start notification signal with the PCIE VFID to the receiving control circuit; and the receiving control circuit sets a valid bit in the VFID lookup table related to the PCIE VFID to a valid state based on the start notification signal.

24. The PCIE device of claim 23, wherein, in response to the receiving control circuit receiving the start notification signal with the PCIE VFID issued by the PCIE controller, the receiving control circuit also changes a hash bit in the VFID lookup table related to the PCIE VFID.

25. The PCIE device of claim 24, wherein, the receiving control circuit changing the hash bit in the VFID lookup table includes: incrementing a content of the hash bit; and if the hash bit overflows, resetting the content of the hash bit to 0.

26. A method of operating a PCIE device, the method comprising: The operation method includes: receiving and processing, by a PCIE controller of a PCIE device, a PCIE packet from a host through a PCIE interface of the PCIE device, wherein the PCIE controller is coupled to the PCIE interface; replacing, by a VFID controller of the PCIE device, a PCIE VFID in a first packet intended to be sent by the PCIE controller to a core circuit of the PCIE device with an internal VFID, and then transmitting the first packet with the internal VFID to the core circuit, wherein the core circuit is configured to provide resources of the PCIE device to the host, and the VFID controller is coupled between the PCIE controller and the core circuit; and replacing, by the VFID controller, the internal VFID in a second packet intended to be sent by the core circuit to the PCIE controller with the PCIE VFID, and then transmitting the second packet with the PCIE VFID to the PCIE controller; wherein the internal VFID is used to identify a PCIE packet transmitted between the VFID controller and the core circuit. In a situation where the same PCIE VFID is reused by different virtual functions, the VFID controller identifies whether a first packet sent by the core circuit to the PCIE controller corresponds to a previous virtual function or a new virtual function, in a case where the previous virtual function and the new virtual function applied to the PCIE device use the same PCIE VFID at different time periods and the previous virtual function and the new virtual function use different internal VFIDs for the core circuit, to determine whether to release the PCIE VFID in advance.

27. The method of operation of claim 26, wherein, The operation method further includes: replacing, by the VFID controller, the PCIE VFID with the internal VFID using a VFID lookup table, and restoring, by the VFID controller, the internal VFID to the PCIE VFID using the VFID lookup table.

28. The method of operation of claim 27, wherein, The VFID lookup table includes a PCIE VFID field and a hash bit field, and the operation method further includes: extracting, by the VFID controller, a hash bit corresponding to the PCIE VFID of the first packet from the VFID lookup table; generating, by the VFID controller, the internal VFID by combining the PCIE VFID and the hash bit; and replacing, by the VFID controller, the PCIE VFID in the first packet with the internal VFID.

29. The method of claim 27, wherein: The VFID lookup table includes a valid bit field and a PCIE VFID field, and the operation method further includes: extracting, by the VFID controller, the PCIE VFID from the internal VFID of the second packet; extracting, by the VFID controller, a valid bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table; and in response to the valid bit indicating that the virtual function corresponding to the PCIE VFID has been reset and the PCIE VFID has not been reused, discarding, by the VFID controller, the second packet without transmitting to the PCIE controller.

30. The method of operating according to claim 29, wherein, The VFID lookup table further includes a hash bit field, and the operation method further includes: in response to the valid bit indicating that the PCIE VFID has been used by the virtual function, extracting, by the VFID controller, a hash bit corresponding to the PCIE VFID extracted from the internal VFID from the VFID lookup table, generating, by the VFID controller, a reference VFID by combining the PCIE VFID and the hash bit, and comparing, by the VFID controller, the internal VFID of the second packet and the reference VFID to obtain a comparison result; in response to the comparison result indicating a mismatch, discarding, by the VFID controller, the second packet without transmitting to the PCIE controller; and In response to the comparison result indicating a match, replacing, by the VFID controller, the internal VFID in the second packet with the PCIE VFID, and then transmitting the second packet with the PCIE VFID to the PCIE controller.

31. The method of claim 26, wherein, The operation method further includes: In response to the PCIE controller receiving a function level reset command issued by the host with the PCIE VFID, transmitting, by the PCIE controller, a function level reset signal with the PCIE VFID to the VFID controller; and Abandoning, by the VFID controller, all packets related to the PCIE VFID based on the function level reset signal.

32. The method of operating according to claim 31, wherein, The operation method further includes: In response to the VFID controller receiving the function level reset signal with the PCIE VFID issued by the PCIE controller, setting, by the VFID controller, a valid bit in a VFID lookup table related to the PCIE VFID to an invalid state, so as to make the VFID controller abandon all backhaul packets related to the PCIE VFID.

33. The method of operating according to claim 32, wherein, The operation method further includes: In response to the VFID controller receiving the function level reset signal with the PCIE VFID issued by the PCIE controller, changing, by the VFID controller, also a hash bit in the VFID lookup table related to the PCIE VFID.

34. The method of operating according to claim 33, wherein, The VFID controller changing the hash bit in the VFID lookup table includes: incrementing a content of the hash bit; and if the hash bit overflows, resetting the content of the hash bit to 0.

35. The operating method according to claim 31, characterized in that, The operation method further includes: Transmitting, by the VFID controller, the function level reset signal to the core circuit, so as to make the core circuit abandon all uncompleted requests related to the PCIE VFID immediately.

36. The method of operating of claim 26, wherein, The operation method further includes: In response to the PCIE controller receiving notification information issued by the host for indicating starting a virtual function with the PCIE VFID, transmitting, by the PCIE controller, a start notification signal with the PCIE VFID to the VFID controller; and Setting, by the VFID controller, a valid bit in a VFID lookup table related to the PCIE VFID to an effective state based on the start notification signal.

37. The method of operating according to claim 36, wherein, The operation method further includes: In response to the VFID controller receiving the start notification signal with the PCIE VFID issued by the PCIE controller, changing, by the VFID controller, also a hash bit in the VFID lookup table related to the PCIE VFID.

38. The method of operating of claim 37, wherein, The VFID controller changing the hash bit in the VFID lookup table includes: incrementing a content of the hash bit; and if the hash bit overflows, resetting the content of the hash bit to 0.

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