A high voltage ideal diode circuit and method capable of driving a large capacitance load

Abstract

The application discloses a high-voltage ideal diode circuit and method capable of driving a large-capacitance load, which comprises a power tube NPW1, a power tube NPW2, a clamping loop and an error amplifier EA, the drain of the power tube NPW1 is connected with a first input end of the clamping loop and an input signal VIN, the source of the power tube NPW1 is connected with the source of the power tube NPW2 and a second input end of the clamping loop, the drain of the power tube NPW2 generates an output signal VOUT, the output end of the clamping loop is connected with the non-inverting input end of the error amplifier EA, the inverting input end of the error amplifier EA is connected with a reference voltage VREF, and the output end of the error amplifier EA is connected with the gate of the power tube NPW1 and the gate of the power tube NPW2. The application can realize wide-range capacitance load driving without additional compensation circuits.

Description

TECHNICAL FIELD

[0001] The application relates to a high-voltage ideal diode circuit and method, in particular to a high-voltage ideal diode circuit and method capable of driving a large-capacitance load, and belongs to the technical field of semiconductor integrated circuits. BACKGROUND

[0002] The ideal diode circuit realizes high-efficiency energy transmission, accurate current direction control and seamless power switching in a power supply system through an active control + MOSFET technology, is especially suitable for scenes with strict requirements on power consumption, size and reliability, and represents the trend of development of modern power management towards 'zero loss' and 'intelligentization'.

[0003] The ideal diode circuit has key characteristics such as low forward conduction loss, fast reverse recovery, true reverse current blocking and fast load transient response, so that the ideal diode controller can provide higher-efficiency and more robust reverse battery protection. The main advantages such as low forward conduction loss, low leakage and simplified load distribution enable the ideal diode controller to more efficiently and reliably power the OR power supply.

[0004] For the design of a high-voltage load switch, the N-type switch has a clear cost advantage. The traditional ideal diode circuit takes the difference between the input voltage and the output voltage of the load switch as a detection signal, controls the gate voltage of the power tube through a negative feedback loop, thereby clamping the difference between the input voltage and the output voltage, and realizing the ideal diode function. When the load switch needs to drive a large-capacitance load, the ideal diode control loop of this scheme has great challenges in stability, because the gain stage output of the loop provides a low-frequency pole, the gate of the power tube provides a low-frequency pole, and the load end provides a dynamic pole, so the system is difficult to compensate. Therefore, it is necessary to propose a high-voltage ideal diode circuit capable of driving a large-capacitance load. SUMMARY

[0005] The technical problem to be solved by the application is to provide a high-voltage ideal diode circuit and method capable of driving a large-capacitance load, and to realize wide-range capacitance load driving.

[0006] To solve the above technical problems, the technical scheme adopted by the application is as follows:

[0007] The application discloses a high-voltage ideal diode circuit capable of driving a large-capacitance load. The circuit comprises a power tube NPW1, a power tube NPW2, a clamping loop and an error amplifier EA. The drain of the power tube NPW1 is connected with a first input end of the clamping loop and an input signal VIN, the source of the power tube NPW1 is connected with the source of the power tube NPW2 and a second input end of the clamping loop and generates a signal VS, the drain of the power tube NPW2 generates an output signal VOUT, the output end of the clamping loop is connected with the non-inverting input end of the error amplifier EA and generates a signal VSEN, the inverting input end of the error amplifier EA is connected with a reference voltage VREF, the output end of the error amplifier EA is connected with the gate of the power tube NPW1 and the gate of the power tube NPW2, and the power supply end of the error amplifier EA is connected with a signal VCP, and the grounding end of the error amplifier EA is grounded.

[0008] Further, the clamping loop comprises resistors R1-R4, high-voltage PMOS tubes PDM1-PDM5, PMOS tubes PM1-PM2, a high-voltage NMOS tube NDM1, a current source I1 and a current source I2. One end of the resistor R1 is connected with an input signal VIN as a first input end of the clamping loop, one end of the resistor R2 is connected with a signal VS as a second input end of the clamping loop, the other end of the resistor R1 is connected with the drain of the high-voltage PMOS tube PMD3 and the source of the high-voltage PMOS tube PDM5 at a node A, the other end of the resistor R2 is connected with the drain of the high-voltage PMOS tube PDM4 at a node B, the gate of the high-voltage PMOS tube PDM3 is connected with the gate of the high-voltage PMOS tube PMD4, the gate of the high-voltage PMOS tube PDM1, one end of the resistor R3, one end of the current source I1 and the gate of the high-voltage PMOS tube PDM2, the source of the high-voltage PMOS tube PDM3 is connected with the source of the PMOS tube PM1, the source of the high-voltage PMOS tube PDM4 is connected with the source of the PMOS tube PM2, the gate of the PMOS tube PM1 is connected with the drain of the high-voltage PMOS tube PDM1, the other end of the resistor R3 and the gate of the PMOS tube PM2, the drain of the PMOS tube PM1 is connected with the source of the high-voltage PMOS tube PDM1, the drain of the PMOS tube PM2 is connected with the source of the high-voltage PMOS tube PDM2, the drain of the high-voltage PMOS tube PDM2 is connected with one end of the current source I2 and the gate of the high-voltage PMOS tube PDM5, the drain of the high-voltage PMOS tube PDM5 is connected with the drain of the high-voltage NMOS tube NDM1, the gate of the high-voltage NMOS tube NDM1 is connected with a bias voltage VBIAS, the source of the high-voltage NMOS tube NDM1 is connected with one end of the resistor R4 and generates a signal VSEN as an output end of the clamping loop, the other end of the current source I1, the other end of the current source I2 and the other end of the resistor R4 are grounded.

[0009] Further, the clamping loop further comprises diodes D1-D6, the cathode of diode D1 is connected with the anode of diode D2, the source of high-voltage PMOS PDM3 and the source of PMOS PM1, the cathode of diode D2 is connected with the anode of diode D3, the anode of diode D1 is connected with the gate of PMOS PM1, the drain of high-voltage PMOS PDM1, the other end of resistor R3, the cathode of diode D3, the cathode of diode D6, the anode of diode D4 and the gate of PMOS PM2, the cathode of diode D4 is connected with the source of high-voltage PMOS PDM4, the source of PMOS PM2 and the anode of diode D5, the cathode of diode D5 is connected with the anode of diode D6.

[0010] Further, the clamping loop further comprises diodes D7-D9, the anode of diode D7 is connected with node A, the cathode of diode D7 is connected with the anode of diode D8, the cathode of diode D8 is connected with the anode of diode D9, the cathode of diode D9 is connected with the gate of high-voltage PMOS PDM5, the drain of high-voltage PMOS PDM2 and one end of current source I2.

[0011] Further, a charge pump is further comprised, the input end of the charge pump is connected with signal VS, and the output end of the charge pump generates signal VCP.

[0012] Further, the high-voltage PMOS PDM1 and the high-voltage PMOS PDM2 have the same width-length ratio, the high-voltage PMOS PDM3 and the high-voltage PMOS PDM4 have the same width-length ratio, the PMOS PM1 and the PMOS PM2 have the same width-length ratio, and the current of current source I1 and the current of current source I2 are equal.

[0013] A control method of a high-voltage ideal diode circuit capable of driving a large-capacitance load, comprising the following steps:

[0014] Resistors R1-R4, high-voltage PMOS PDM1-PDM5, PMOS PM1-PM2, high-voltage NMOS NDM1, current source I1 and current source I2 constitute a clamping loop, so that the voltages of node A and node B are equal;

[0015] The high-voltage PMOS PDM1 and the high-voltage PMOS PDM2 have the same width-length ratio, the high-voltage PMOS PDM3 and the high-voltage PMOS PDM4 have the same width-length ratio, the PMOS PM1 and the PMOS PM2 have the same width-length ratio, and the current of current source I1 and the current of current source I2 are equal.

[0016] The resistor R3, the high-voltage PMOS PDM1~PDM4, the PMOS PM1~PM2, the current source I1 and the current source I2 constitute a common-gate amplifier, when the voltage VA of the node A is greater than the voltage VB of the node B, the gate voltage of the high-voltage PMOS PDM5 is pulled low by the current source I2, thereby pulling down the voltage VA of the source node A of the high-voltage PMOS PDM5, forming a negative feedback and finally reaching a steady state VA=VB;

[0017] Let the resistance values of the resistor R1 and the resistor R2 be R, and the currents of the current source I1 and the current source I2 be I, then the current ISEN flowing through the source of the high-voltage PMOS PDM5 satisfies the following relationship:

[0018] ;

[0019] The signal VSEN of the non-inverting input terminal of the error amplifier EA is:

[0020] ;

[0021] The clamping loop clamps the voltages of the node A and the node B to be equal, so that the difference between the input signal VIN and the signal VS is in a linear relationship with the voltage of the signal VSEN;

[0022] The clamping loop, the error amplifier EA, the power tube NPW1 and the power tube NPW2 constitute an ideal diode control loop, and when the ideal diode control loop works normally, the following relationship is satisfied:

[0023] ;

[0024] ;

[0025] Therefore, the difference between the input signal VIN and the signal VS is adjusted by designing the ratio of R and the resistance R4 and the size of the reference voltage VREF;

[0026] The power tube NPW1 and the power tube NPW2 are designed to be the same size, when the input signal VIN is loaded with a voltage, the current flows through the channel of the power tube NPW1 and the channel of the power tube NPW2, and the forward voltage drop of the ideal diode is:

[0027] ;

[0028] The error amplifier EA is powered by a charge pump output voltage to turn on the power tube NPW1 and the power tube NPW2;

[0029] When the switch is normally loaded, that is, VIN-VOUT>VD, the signal VSEN is pulled up to VB-VGS1, VGS1 is the gate-source voltage of the high-voltage NMOS tube NDM1, in order to make the error amplifier EA work in the comparator state when the load switch is normally loaded, the voltage of the signal VSEN is greater than the reference voltage VREF by 1V or more, therefore the bias voltage VBIAS is designed as VBIAS>VREF+1V+VGS1, which ensures that the error amplifier EA can make the output voltage reach the upper rail when normally loaded, that is, VCP;

[0030] At this time, the current source of the source degeneration structure composed of the high-voltage NMOS tube NDM1 and the resistor R4 limits the current ISEN, and the current limiting value ISEN max Determined by the following formula:

[0031] ;

[0032] When the load of the switch gradually decreases, the voltage of the output signal VOUT and the signal VS rises, resulting in a decrease in the current ISEN, the voltage of the signal VSEN decreases, and the output voltage of the error amplifier EA decreases, thereby reducing the voltage of the signal VS, forming a negative feedback;

[0033] When the switch loads a power source greater than the input at the output end, that is, VOUT>VIN, since the ideal diode control loop detects the source-drain voltage drop of the power tube NPW1, not the difference between the input signal VIN and the output signal VOUT, it is not affected by the voltage of the output signal VOUT, therefore the ideal diode control loop still works normally, and the source voltage of the power tube remains at VIN-0.5*VD; Since the voltage of the output signal VOUT is higher than that of the input signal VIN at this time, the power tube NPW1 only drives the internal circuit and does not provide load current, and the power tube NPW1 works in the sub-threshold region, and the power tube NPW2 is the same, therefore the current generated by the high-voltage output signal VOUT will not be back-feeding to the input signal VIN, realizing the reverse blocking function of the ideal diode;

[0034] Since the ideal diode control circuit moves the detection point from the output signal VOUT node to the source of the power tube NPW1, a zero point Z1 is introduced, and the expression of the zero point Z1 is:

[0035] ;

[0036] Wherein, CL is the load capacitance size of the output signal VOUT node, RON2 is the equivalent resistance when the power tube NPW2 works in the linear region, since the power tube NPW1 and the power tube NPW2 have the same size, therefore, RON1 = RON2 = RON, RON1 is the equivalent resistance when the power tube NPW1 works in the linear region; the zero point Z1 is a dynamic zero point and follows the load capacitance CL, when the load capacitance CL is very large, the zero point Z1 is a low frequency zero point; the source of the power tube NPW1 also has a pole P1 following the load capacitance, and the pole P1 is expressed as:

[0037] ;

[0038] Wherein, IOUT is the output current of the load switch when the ideal diode control loop works normally; the pole P1 position is less than the zero point Z1, and also follows the load capacitance CL, therefore, the zero point Z1 dynamically follows the pole P1, and realizes the pole offset compensation.

[0039] Compared with the prior art, the present application has the following advantages and effects: the present application provides a high-voltage ideal diode circuit and method capable of driving a large-capacitance load, adopts an ideal diode control loop to realize the drain-source voltage difference control of a power tube, when a small-current load is output, the source voltage of the power tube is very close to the drain voltage, the source voltage will be clamped to a preset value, and the output voltage will also reach the preset value synchronously, thereby realizing the function of a forward diode; when the output is switched to a higher power supply than the input, the power tube will be adaptively turned off, thereby realizing the function of a reverse diode; since the detection point of the ideal diode control loop is between the drain and the source, a zero point following the output pole is introduced, the output pole is dynamically compensated, and therefore, a wide range of capacitance load driving can be realized without an additional compensation circuit. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a schematic diagram of a high-voltage ideal diode circuit capable of driving a large-capacitance load. DETAILED DESCRIPTION

[0041] In order to describe the technical solutions adopted by the present application in detail to achieve the predetermined technical purposes, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments, and the technical means or technical features in the embodiments of the present application can be replaced without creative labor, which will be described in detail below with reference to the drawings and in combination with the embodiments.

[0042] As Figure 1As shown, the high-voltage ideal diode circuit capable of driving a large-capacitance load of the present application comprises power transistor NPW1, power transistor NPW2, a clamping loop and error amplifier EA, the drain of power transistor NPW1 is connected to the first input terminal of the clamping loop and input signal VIN, the source of power transistor NPW1 is connected to the source of power transistor NPW2 and the second input terminal of the clamping loop and generates signal VS, the drain of power transistor NPW2 generates output signal VOUT, the output terminal of the clamping loop is connected to the non-inverting input terminal of error amplifier EA and generates signal VSEN, the inverting input terminal of error amplifier EA is connected to reference voltage VREF, the output terminal of error amplifier EA is connected to the gate of power transistor NPW1 and the gate of power transistor NPW2, the power supply terminal of error amplifier EA is connected to signal VCP, and the ground terminal of error amplifier EA is grounded.

[0043] The clamping loop comprises resistors R1-R4, high-voltage PMOS transistors PDM1-PDM5, PMOS transistors PM1-PM2, high-voltage NMOS transistor NDM1, current source I1 and current source I2, one end of resistor R1 is connected to input signal VIN as the first input terminal of the clamping loop, one end of resistor R2 is connected to signal VS as the second input terminal of the clamping loop, the other end of resistor R1 is connected to the drain of high-voltage PMOS transistor PMD3 and the source of high-voltage PMOS transistor PDM5 at node A, the other end of resistor R2 is connected to the drain of high-voltage PMOS transistor PDM4 at node B, the gate of high-voltage PMOS transistor PDM3 is connected to the gate of high-voltage PMOS transistor PMD4, the gate of high-voltage PMOS transistor PDM1, one end of resistor R3, one end of current source I1 and the gate of high-voltage PMOS transistor PDM2, the source of high-voltage PMOS transistor PDM3 is connected to the source of PMOS transistor PM1, the source of high-voltage PMOS transistor PDM4 is connected to the source of PMOS transistor PM2, the gate of PMOS transistor PM1 is connected to the drain of high-voltage PMOS transistor PDM1, the other end of resistor R3 and the gate of PMOS transistor PM2, the drain of PMOS transistor PM1 is connected to the source of high-voltage PMOS transistor PDM1, the drain of PMOS transistor PM2 is connected to the source of high-voltage PMOS transistor PDM2, the drain of high-voltage PMOS transistor PDM2 is connected to one end of current source I2 and the gate of high-voltage PMOS transistor PDM5, the drain of high-voltage PMOS transistor PDM5 is connected to the drain of high-voltage NMOS transistor NDM1, the gate of high-voltage NMOS transistor NDM1 is connected to bias voltage VBIAS, the source of high-voltage NMOS transistor NDM1 is connected to one end of resistor R4 and generates signal VSEN as the output terminal of the clamping loop, the other end of current source I1, the other end of current source I2 and the other end of resistor R4 are grounded.

[0044] The clamping loop further comprises diodes D1-D6, the cathode of diode D1 is connected with the anode of diode D2, the source of high-voltage PMOS PDM3 and the source of PMOS PM1, the cathode of diode D2 is connected with the anode of diode D3, the anode of diode D1 is connected with the gate of PMOS PM1, the drain of high-voltage PMOS PDM1, the other end of resistor R3, the cathode of diode D3, the cathode of diode D6, the anode of diode D4 and the gate of PMOS PM2, the cathode of diode D4 is connected with the source of high-voltage PMOS PDM4, the source of PMOS PM2 and the anode of diode D5, the cathode of diode D5 is connected with the anode of diode D6.

[0045] The clamping loop further comprises diodes D7-D9, the anode of diode D7 is connected with node A, the cathode of diode D7 is connected with the anode of diode D8, the cathode of diode D8 is connected with the anode of diode D9, the cathode of diode D9 is connected with the gate of high-voltage PMOS PDM5, the drain of high-voltage PMOS PDM2 and one end of current source I2.

[0046] The high-voltage ideal diode circuit capable of driving a large-capacitance load further comprises a charge pump, the input end of the charge pump is connected with signal VS, and the output end of the charge pump generates signal VCP.

[0047] The high-voltage PMOS PDM1 and the high-voltage PMOS PDM2 have the same width-length ratio, the high-voltage PMOS PDM3 and the high-voltage PMOS PDM4 have the same width-length ratio, the PMOS PM1 and the PMOS PM2 have the same width-length ratio, and the current of current source I1 and the current of current source I2 are equal.

[0048] The control method of the high-voltage ideal diode circuit capable of driving a large-capacitance load comprises the following steps:

[0049] The resistors R1-R4, the high-voltage PMOS PDM1-PDM5, the PMOS PM1-PM2, the high-voltage NMOS NDM1, the current source I1 and the current source I2 constitute a clamping loop, so that the voltages of node A and node B are equal.

[0050] The working principle of the clamping loop is as follows:

[0051] The high-voltage PMOS PDM1 and the high-voltage PMOS PDM2 have the same width-length ratio, the high-voltage PMOS PDM3 and the high-voltage PMOS PDM4 have the same width-length ratio, the PMOS PM1 and the PMOS PM2 have the same width-length ratio, and the current of current source I1 and the current of current source I2 are equal.

[0052] The resistor R3, the high-voltage PMOS PDM1~PDM4, the PMOS PM1~PM2, the current source I1 and the current source I2 constitute a common-gate amplifier, when the voltage VA of the node A is greater than the voltage VB of the node B, the gate voltage of the high-voltage PMOS PDM5 is pulled low by the current source I2, thereby pulling down the voltage VA of the source node A of the high-voltage PMOS PDM5, forming a negative feedback and finally reaching a steady state VA=VB.

[0053] Let the resistance of the resistor R1 and the resistor R2 be R, and the current of the current source I1 and the current source I2 be I, then the current ISEN flowing through the source of the high-voltage PMOS PDM5 satisfies the following relationship:

[0054] .

[0055] The signal VSEN of the non-inverting input terminal of the error amplifier EA is:

[0056] ;

[0057] The clamping loop clamps the voltages of the node A and the node B to be equal, so that the difference between the input signal VIN and the signal VS is in a linear relationship with the voltage of the signal VSEN.

[0058] The clamping loop, the error amplifier EA, the power tube NPW1 and the power tube NPW2 constitute an ideal diode control loop, and when the ideal diode control loop works normally, the following relationship is satisfied:

[0059] ;

[0060] ;

[0061] Therefore, the difference between the input signal VIN and the signal VS is adjusted by designing the ratio of R and the resistance R4 and the size of the reference voltage VREF.

[0062] The power tube NPW1 and the power tube NPW2 are designed to be the same size, when the input signal VIN loads the voltage, the current flows through the channel of the power tube NPW1 (the body diode is reverse biased), and at the same time flows through the channel and the body diode of the power tube NPW2 (the body diode is forward biased), so that the drain-source voltage difference of the power tube NPW1 and the source-drain voltage difference of the power tube NPW2 will be inconsistent, however, in order to control the power consumption, the forward voltage drop of the general ideal diode circuit is designed to be about 10mV~20mV, which almost does not cause the conduction of the body diode (about 0.6V), so that most of the current still flows through the channel, resulting in that the drain-source voltage drop of the power tube NPW1 is almost equal to the source-drain voltage drop of the power tube NPW2, thereby obtaining the forward voltage drop of the ideal diode:

[0063] .

[0064] The working principle of the ideal diode control loop is as follows:

[0065] The error amplifier EA is powered by the charge pump output voltage, which is generally designed to be 5V higher than the source voltage of the power tube NPW1 / NPW2 to turn on the power tube NPW1 and the power tube NPW2.

[0066] When the switch is normally loaded, that is, VIN-VOUT>VD, the signal VSEN is pulled up to VB-VGS1, and VGS1 is the gate-source voltage of the high-voltage NMOS tube NDM1, which is generally about 0.8V. In order to make the error amplifier EA work in the comparator state when the load switch is normally loaded, the voltage of the signal VSEN is more than 1V higher than the reference voltage VREF, so the bias voltage VBIAS is designed as VBIAS>VREF+1V+VGS1, which ensures that the error amplifier EA can reach the upper rail, that is, VCP, when normally loaded, thereby improving the efficiency of the load switch.

[0067] At this time, the current source of the source degeneration structure composed of the high-voltage NMOS tube NDM1 and the resistor R4 limits the current ISEN, and the current limiting value ISEN max which is determined by the following formula:

[0068] .

[0069] When the load of the switch gradually decreases, the voltages of the output signal VOUT and the signal VS rise, resulting in a decrease in the current ISEN, a decrease in the voltage of the signal VSEN, and a decrease in the output voltage of the error amplifier EA, which in turn reduces the voltage of the signal VS, forming a negative feedback.

[0070] When the switch loads a power source greater than the input at the output end, that is, VOUT>VIN, since the ideal diode control loop detects the source-drain voltage drop of the power tube NPW1, not the difference between the input signal VIN and the output signal VOUT, it is not affected by the voltage of the output signal VOUT, so the ideal diode control loop still works normally, and the source voltage of the power tube remains at VIN-0.5*VD; Since the voltage of the output signal VOUT is higher than that of the input signal VIN at this time, the power tube NPW1 only drives the internal circuit and does not provide load current, and the power tube NPW1 works in the sub-threshold region and is almost in the off state, and the power tube NPW2 is the same, so the current generated by the high-voltage output signal VOUT will not be back-feeding to the input signal VIN, realizing the reverse blocking function of the ideal diode.

[0071] The principle of the ideal diode control loop driving a large-capacitance load is as follows:

[0072] Since the ideal diode control circuit moves the detection point from the output signal VOUT node to the source of the power transistor NPW1, a zero point Z1 is introduced, and the expression of the zero point Z1 is:

[0073] ;

[0074] wherein CL is the size of the load capacitance of the output signal VOUT node, RON2 is the equivalent resistance when the power transistor NPW2 works in the linear region, and since the power transistor NPW1 and the power transistor NPW2 have the same size, RON1 = RON2 = RON is set, wherein RON1 is the equivalent resistance when the power transistor NPW1 works in the linear region; the zero point Z1 is a dynamic zero point and changes with the load capacitance CL, and when the load capacitance CL is very large, the zero point Z1 is a low-frequency zero point; the source of the power transistor NPW1 also has a pole P1 which changes with the load capacitance, and the pole P1 is expressed as:

[0075] ;

[0076] wherein IOUT is the output current of the load switch when the ideal diode control loop works normally; the pole P1 is smaller than the zero point Z1 and also changes with the load capacitance CL, so the zero point Z1 dynamically follows the pole P1, and the pole compensation is realized.

[0077] Finally, the ideal diode control loop only has a low-frequency main pole, i.e. the output of the error amplifier EA, and a high-frequency pole, i.e. the non-inverting input terminal of the error amplifier EA, so the ideal diode control loop does not need additional compensation and has no stability problem.

[0078] In addition, due to the follow-up of the zero point Z1 and the pole P1, there is no stability problem when driving a small-capacitance load or even a capacitance load.

[0079] The error amplifier EA can adopt various implementation manners, such as a folded cascode structure, a fully differential structure, etc.

[0080] The application provides a high-voltage ideal diode circuit and method which can drive a large-capacitance load, adopts an ideal diode control loop to realize the drain-source voltage difference control of a power transistor, when the output carries a small-current load, the source voltage of the power transistor is very close to the drain voltage, and the source voltage is clamped to a preset value, and the output voltage is also synchronized to reach the preset value, thereby realizing the function of a forward diode; when the output is switched to a higher power supply than the input, the power transistor is adaptively turned off, thereby realizing the function of a reverse diode; since the detection point of the ideal diode control loop is between the drain and the source, a zero point which follows the output pole is introduced, and the output pole is dynamically compensated, thereby realizing the driving of a wide-range capacitance load without an additional compensation circuit.

[0081] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes or modifications to the above disclosed technical contents to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any simple modification, equivalent replacement and improvement of the above embodiments, as long as it does not depart from the technical solution of the present application, and is within the spirit and principle of the present application, shall be within the protection scope of the present application.

Claims

1. A high voltage ideal diode circuit capable of driving a large capacitance load, characterized by: The power tube NPW1, the power tube NPW2, the clamping loop and the error amplifier EA, the drain of the power tube NPW1 is connected with the first input terminal of the clamping loop and the input signal VIN, the source of the power tube NPW1 is connected with the source of the power tube NPW2 and the second input terminal of the clamping loop and generates the signal VS, the drain of the power tube NPW2 generates the output signal VOUT, the output terminal of the clamping loop is connected with the positive input terminal of the error amplifier EA and generates the signal VSEN, the inverting input terminal of the error amplifier EA is connected with the reference voltage VREF, the output terminal of the error amplifier EA is connected with the gate of the power tube NPW1 and the gate of the power tube NPW2, the power supply terminal of the error amplifier EA is connected with the signal VCP, the ground terminal of the error amplifier EA is grounded; The clamping loop comprises resistors R1-R4, high-voltage PMOS tubes PDM1-PDM5, PMOS tubes PM1-PM2, high-voltage NMOS tube NDM1, current sources I1 and I2, one end of the resistor R1 is connected with the input signal VIN as the first input terminal of the clamping loop, one end of the resistor R2 is connected with the signal VS as the second input terminal of the clamping loop, the other end of the resistor R1 is connected with the drain of the high-voltage PMOS tube PMD3 and the source of the high-voltage PMOS tube PDM5 at node A, the other end of the resistor R2 is connected with the drain of the high-voltage PMOS tube PDM4 at node B, the gate of the high-voltage PMOS tube PDM3 is connected with the gate of the high-voltage PMOS tube PMD4, the gate of the high-voltage PMOS tube PDM1, one end of the resistor R3, one end of the current source I1 and the gate of the high-voltage PMOS tube PDM2, the source of the high-voltage PMOS tube PDM3 is connected with the source of the PMOS tube PM1, the source of the high-voltage PMOS tube PDM4 is connected with the source of the PMOS tube PM2, the gate of the PMOS tube PM1 is connected with the drain of the high-voltage PMOS tube PDM1, the other end of the resistor R3 and the gate of the PMOS tube PM2, the drain of the PMOS tube PM1 is connected with the source of the high-voltage PMOS tube PDM1, the drain of the PMOS tube PM2 is connected with the source of the high-voltage PMOS tube PDM2, the drain of the high-voltage PMOS tube PDM2 is connected with one end of the current source I2 and the gate of the high-voltage PMOS tube PDM5, the drain of the high-voltage PMOS tube PDM5 is connected with the drain of the high-voltage NMOS tube NDM1, the gate of the high-voltage NMOS tube NDM1 is connected with the bias voltage VBIAS, the source of the high-voltage NMOS tube NDM1 is connected with one end of the resistor R4 and generates the signal VSEN as the output terminal of the clamping loop, the other end of the current source I1, the other end of the current source I2 and the other end of the resistor R4 are grounded.

2. A high voltage ideal diode circuit capable of driving a large capacitive load according to claim 1, characterized in that: The clamping loop further comprises diodes D1-D6, the cathode of diode D1 is connected with the anode of diode D2, the source of high-voltage PMOS PDM3 and the source of PMOS PM1, the cathode of diode D2 is connected with the anode of diode D3, the anode of diode D1 is connected with the gate of PMOS PM1, the drain of high-voltage PMOS PDM1, the other end of resistor R3, the cathode of diode D3, the cathode of diode D6, the anode of diode D4 and the gate of PMOS PM2, the cathode of diode D4 is connected with the source of high-voltage PMOS PDM4, the source of PMOS PM2 and the anode of diode D5, and the cathode of diode D5 is connected with the anode of diode D6.

3. The high voltage ideal diode circuit capable of driving a large capacitive load according to claim 1, wherein: The clamping loop further comprises diodes D7-D9, the anode of diode D7 is connected with node A, the cathode of diode D7 is connected with the anode of diode D8, the cathode of diode D8 is connected with the anode of diode D9, and the cathode of diode D9 is connected with the gate of high-voltage PMOS PDM5, the drain of high-voltage PMOS PDM2 and one end of current source I2.

4. The high voltage ideal diode circuit capable of driving a large capacitive load according to claim 1, wherein: The clamping loop further comprises a charge pump, the input end of the charge pump is connected with signal VS, and the output end of the charge pump generates signal VCP.

5. The high voltage ideal diode circuit capable of driving a large capacitive load according to claim 1, wherein: The high-voltage PMOS PDM1 and the high-voltage PMOS PDM2 have the same width-length ratio, the high-voltage PMOS PDM3 and the high-voltage PMOS PDM4 have the same width-length ratio, the PMOS PM1 and the PMOS PM2 have the same width-length ratio, and the current of current source I1 and the current of current source I2 are equal.

6. A control method of the high-voltage ideal diode circuit capable of driving a large-capacitance load according to any one of claims 1 to 5, characterized by The clamping loop comprises the following steps: The resistor R1-R4, the high-voltage PMOS PDM1-PDM5, the PMOS PM1-PM2, the high-voltage NMOS NDM1, the current source I1 and the current source I2 constitute a clamping loop, so that the voltages of node A and node B are equal; The high-voltage PMOS PDM1 and the high-voltage PMOS PDM2 have the same width-length ratio, the high-voltage PMOS PDM3 and the high-voltage PMOS PDM4 have the same width-length ratio, the PMOS PM1 and the PMOS PM2 have the same width-length ratio, and the current of current source I1 and the current of current source I2 are equal. The resistor R3, the high-voltage PMOS PDM1-PDM4, the PMOS PM1-PM2, the current source I1 and the current source I2 constitute a common-gate amplifier, when the voltage VA of node A is greater than the voltage VB of node B, the gate voltage of high-voltage PMOS PDM5 is pulled down by current source I2, thereby pulling down the voltage VA of node A, forming a negative feedback and finally reaching a steady state VA=VB; Let the resistance of resistor R1 and resistor R2 be R, and the current of current source I1 and the current of current source I2 be I, then the current ISEN flowing through the source of high-voltage PMOS PDM5 satisfies the following relationship: ； The signal VSEN of the non-inverting input end of error amplifier EA is: ； The clamping loop clamps the voltages of node A and node B to be equal, so that the difference between input signal VIN and signal VS is in a linear relationship with the voltage of signal VSEN; The clamping loop, the error amplifier EA, the power transistor NPW1 and the power transistor NPW2 constitute an ideal diode control loop, and the ideal diode control loop meets the following relationship when normally working: ； ； Therefore, the difference between the input signal VIN and the signal VS is adjusted by the ratio of the design R and the resistance R4 and the size of the reference voltage VREF; The power transistor NPW1 and the power transistor NPW2 are designed to be the same size, and when the input signal VIN is loaded with a voltage, the current flows through the channel of the power transistor NPW1 and the channel of the power transistor NPW2, and the forward voltage drop of the ideal diode is: ； The error amplifier EA is powered by the charge pump output voltage to turn on the power transistor NPW1 and the power transistor NPW2; When the switch is normally loaded, that is, VIN-VOUT>VD, the signal VSEN is pulled up to VB-VGS1, VGS1 is the gate-source voltage of the high-voltage NMOS transistor NDM1, in order to make the error amplifier EA work in the comparator state when the load switch is normally loaded, the voltage of the signal VSEN is greater than the reference voltage VREF by 1V, therefore the bias voltage VBIAS is designed as VBIAS>VREF+1V+VGS1, which ensures that the error amplifier EA can reach the upper rail when normally loaded, that is, VCP; The source degeneration structure current source composed of high-voltage NMOS transistor NDM1 and resistor R4 limits the current ISEN at this time, and the current limiting value ISEN max Is determined by the following formula: ； When the load of the switch gradually decreases, the voltage of the output signal VOUT and the signal VS rises, resulting in a decrease in the current ISEN, the voltage of the signal VSEN decreases, and the output voltage of the error amplifier EA decreases, thereby reducing the voltage of the signal VS, forming a negative feedback; When the switch loads a power source greater than the input at the output end, that is, VOUT>VIN, since the ideal diode control loop detects the source-drain voltage drop of the power transistor NPW1, not the difference between the input signal VIN and the output signal VOUT, it is not affected by the voltage of the output signal VOUT, therefore the ideal diode control loop still works normally, and the power transistor source voltage still maintains at VIN-0.5*VD; Since the voltage of the output signal VOUT is higher than that of the input signal VIN at this time, the power transistor NPW1 only drives the internal circuit and does not provide load current, and the power transistor NPW1 works in the sub-threshold region, and the power transistor NPW2 is the same, therefore the current generated by the high-voltage output signal VOUT will not be back-primed to the input signal VIN, realizing the reverse blocking function of the ideal diode; Since the ideal diode control circuit moves the detection point from the output signal VOUT node to the source of the power transistor NPW1, a zero point Z1 is introduced, and the expression of the zero point Z1 is: ； Wherein, CL is the load capacitance size of the output signal VOUT node, RON2 is the equivalent resistance when the power tube NPW2 works in the linear region, because the power tube NPW1 and the power tube NPW2 have the same size, so RON1=RON2=RON, RON1 is the equivalent resistance when the power tube NPW1 works in the linear region; the zero point Z1 is a dynamic zero point and follows the load capacitance CL change, when the load capacitance CL is very large, the zero point Z1 is a low frequency zero point; the source of the power tube NPW1 also has a pole P1 following the load capacitance change, the pole P1 is expressed as: ； Wherein, IOUT is the output current of the load switch when the ideal diode control loop works normally; the pole P1 position is less than the zero point Z1, and also follows the load capacitance CL change, so the zero point Z1 dynamically follows the pole P1, realizes the pole offset compensation.

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