Joint passivation back contact battery with specific opening structure and manufacturing method and application thereof

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a joint passivation back contact cell with a specific opening structure and a manufacturing method and application thereof, and the method comprises the steps: S6, directly depositing a transparent conductive film layer on the surface of a second doped silicon layer; s7, performing second opening on the second semiconductor layer and the transparent conductive film layer on the outer surface corresponding to the area where the first semiconductor layer is located to form a second opening area; the width of the second opening area is controlled to be 20%-100% of the width of the corresponding first semiconductor layer; s8, first silver paste is directly printed on the corresponding exposed surface of the second opening area obtained in the S7, and then laser sintering is conducted on the first silver paste; and printing second silver paste on the outer surface of a region corresponding to the position of the first opening region, and baking and curing the second silver paste. According to the invention, the carrier export performance can be improved while the damage to each functional film layer is effectively reduced, so that the conversion efficiency of the cell is improved, the process is simplified, and the cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a combined passivation back contact battery with a specific opening structure, a preparation method thereof, and applications thereof. Background Art

[0002] Existing combined passivated back contact cells have two semiconductors of different polarities and two semiconductor openings. The ends of the two semiconductors overlap, and an isolation trench is provided in the overlapping region. A transparent conductive film layer is provided on each semiconductor opening, and a metal electrode is provided on the outer surface of the transparent conductive film layer. It is generally manufactured through the following steps: S101, providing silicon wafers; S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer arranged in sequence; S103, performing a first etching opening on the back surface obtained in S102 to form a first opening area; S104, forming a textured surface at least in the first opening area by texturing cleaning, and removing the mask layer; S105, depositing a second semiconductor layer on the back side, the second semiconductor layer comprising an intrinsic amorphous silicon layer and a second doped silicon layer arranged in sequence; S106, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second opening region spaced apart from the first opening region; S107, performing HF cleaning on the opening to remove the residual oxide layer; S108, depositing a transparent conductive film layer on the back surface obtained in S107; S109, performing a third etching opening on the transparent conductive film layer corresponding to the overlapping area between the first opening area and the second opening area according to a preset pattern to form an isolation groove, and then performing solution cleaning; S110 , forming metal electrodes on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second opening area.

[0003] As can be seen from the above, S106-S109 involve two openings (the second semiconductor opening and the transparent conductive film opening) and subsequent solution cleaning (e.g., solution treatment is required after the second semiconductor opening, and the transparent conductive film opening typically also involves a solution treatment process), which increases the manufacturing difficulty. Furthermore, the numerous solution treatment steps increase the risk of corrosion defects such as undercutting and drilling of the battery film, which affects the battery conversion efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the existing combined back contact battery in the prior art, which has complex processes, increases the difficulty of production and affects the battery conversion efficiency, and provides a combined passivated back contact battery with a specific opening structure and its preparation method and application. The present invention can effectively reduce the damage to each functional film layer while improving the carrier extraction performance, thereby improving the battery conversion efficiency, while simplifying the process and reducing costs.

[0006] In order to achieve the above objectives, in a first aspect, the present invention provides a method for manufacturing a combined passivated back contact cell, comprising the following steps: S1, provide silicon wafers; S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer; S3, performing a first opening on the back surface obtained in S2 to form a first opening area; S4, texturing and cleaning, forming a texturing surface at least in the first opening area; S5, depositing a second semiconductor layer on the back side, where the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer; S6, directly depositing a transparent conductive film layer on the surface of the second doped silicon layer obtained in S5; S7, performing a second opening on the second semiconductor layer and the transparent conductive film layer located on the outer surface corresponding to the area where the first semiconductor layer is located, so as to expose the first semiconductor layer or its corresponding mask layer, thereby forming a second opening area; and controlling the width of the second opening area to be 20%-100% of the width of the corresponding first semiconductor layer; S8. First, directly print the first silver paste on the exposed surface corresponding to the second opening area obtained in S7, and then laser sinter the first silver paste to form a first silver paste electrode; then print the second silver paste on the outer surface of the area corresponding to the position of the first opening area, and then bake and solidify the second silver paste to form a second silver paste electrode.

[0007] In some preferred embodiments of the present invention, in S8, the baking and curing temperature of the second silver paste is 180-250° C., and / or the baking and curing time is 5-30 min.

[0008] In some preferred embodiments of the present invention, in S8, the laser sintering conditions include: an energy density of 1-20 J / cm 2 , the laser sintering time is 0.001-0.5ms.

[0009] In some preferred embodiments of the present invention, laser sintering uses green laser or infrared laser.

[0010] In some preferred embodiments of the present invention, the process of S8 forming the first silver paste electrode also includes: after laser sintering, short-time baking auxiliary sintering is performed, and then the second silver paste is printed; wherein, the conditions for short-time baking auxiliary sintering include: the temperature of short-time baking auxiliary sintering is 100-600℃, and the time is 30-600s.

[0011] In some preferred embodiments of the present invention, the manufacturing method further comprises a step of removing at least a portion of the mask layer by cleaning in S4.

[0012] More preferably, when the thickness of the mask layer finally retained in S4 is 0-20nm, the temperature of the short-time baking auxiliary sintering in S8 is controlled to be less than 300°C and not less than 100°C, and the time is 30-600s; when the thickness of the mask layer finally retained in S4 is greater than 20nm, the temperature of the short-time baking auxiliary sintering in S8 is controlled to be 300-650°C, and the time is 5-120s.

[0013] In some preferred embodiments of the present invention, the thickness of the mask layer finally retained in S4 is 0-100 nm, and / or the thickness of the mask layer formed in S2 is 20-150 nm.

[0014] In some preferred embodiments of the present invention, the width of the second opening region is 150-500 μm, and / or the width of the first opening region is 400-800 μm.

[0015] In some preferred embodiments of the present invention, the production method further comprises at least one of the following processes: In process 1, S6, the thickness of the transparent conductive film layer is controlled to be 15-80 nm; Process 2: In S7, the second opening is opened by laser; In process three, S8, the first silver paste is a laser sintering type silver paste, and the second silver paste is a baking curing type silver paste; Process 4: The thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm -3 The thickness of the intrinsic amorphous silicon layer is 5-15nm; the thickness of the second doped silicon layer is 7-45nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 ; Process five, S5, also includes the step of forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer.

[0016] In a second aspect, the present invention provides a back-contact battery, which is manufactured by the manufacturing method of the combined passivation back-contact battery described in the first aspect.

[0017] In a third aspect, the present invention provides a combined passivated back contact battery with a specific opening structure, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, a first opening area formed between adjacent first semiconductor layers, two ends of the second semiconductor layer respectively extending outward to cover the portion of the back side of the adjacent first semiconductor layer, and a second opening area not covering the second semiconductor layer is opened on the back side of the first semiconductor layer, the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer, the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer, and further comprises: a transparent conductive film layer arranged outside the second semiconductor layer, a second silver paste electrode arranged outside the transparent conductive film layer corresponding to the first opening area, and a first silver paste electrode arranged on the outer surface of the area where the second opening area is located, the first silver paste electrode is a laser sintering type silver paste electrode, the second silver paste electrode is a baking-cured type silver paste electrode, and no transparent conductive film layer is arranged on the second opening area; and the width of the second opening area is 20%-100% of the width of the corresponding first semiconductor layer.

[0018] In some preferred embodiments of the present invention, the width of the second opening region is 150-500 μm, and / or the width of the first opening region is 400-800 μm.

[0019] In some preferred embodiments of the present invention, the combined passivated back contact cell further comprises at least one of the following structures: Structure 1: The width of the first silver paste electrode is 20-100 μm, and the width of the second silver paste electrode is 20-100 μm; Structure 2: Bake-cured silver paste is a silver paste electrode formed by baking and curing at temperatures below 100-300°C; Structure 3: The width of the second opening area is 150-500 μm, and the width of the first opening area is 400-800 μm; Structure 4: The portion of the silicon wafer located at the first opening area is a textured surface, and the portion of the silicon wafer corresponding to the first semiconductor layer is a polished surface; Structure 5: The thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm -3 The thickness of the intrinsic amorphous silicon layer is 5-15nm; the thickness of the second doped silicon layer is 7-45nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 ; Structure 6 also includes a front passivation layer and an anti-reflection layer sequentially provided on the front side of the silicon wafer; Structure 7: A mask layer may or may not be provided between the first semiconductor layer and the first silver paste electrode; and a mask layer may or may not be provided between the second semiconductor layer and the first semiconductor layer in the thickness direction of the second semiconductor layer covering the corresponding area of ​​the first semiconductor layer.

[0020] In a fourth aspect, the present invention provides a battery assembly comprising the back-contact battery described in the second aspect, or the combined passivated back-contact battery with a specific opening structure described in the third aspect.

[0021] Beneficial effects: The present invention adopts the above-mentioned technical scheme, especially directly performing S6 deposition of a transparent conductive film layer after depositing the second semiconductor layer in the combined passivation structure, and then opening a second opening area with a wider proportion, eliminating the isolation groove opening step, simplifying the process, and forming different types of silver paste electrodes on the outer surfaces of the corresponding opening areas of semiconductor layers with different structures, effectively reducing the first silver paste line resistivity and contact resistivity, and can effectively reduce the damage to various functional film layers (such as the second semiconductor layer) while improving the carrier extraction performance, thereby improving the battery conversion efficiency, while simplifying the process and reducing costs.

[0022] On the one hand, the present invention specifically performs S6 deposition of a transparent conductive film layer directly after depositing the second semiconductor layer, and then opens a second opening area with a wider proportion, combines the second semiconductor layer opening and the isolation groove opening in the traditional process into one, eliminates the isolation opening process, significantly shortens the process steps, simplifies the process, and after the process is simplified, reduces the solution treatment steps (solution treatment after the second semiconductor layer opening, solution cleaning after the isolation groove opening), reduces damage to various functional film layers, and improves battery conversion efficiency. On the other hand, while simplifying the process, the present invention also retains a transparent conductive film layer on the outer surface of the second semiconductor layer corresponding to the heat-sensitive intrinsic amorphous silicon layer and uses a baked-cured second silver paste. This area does not undergo a long high-temperature treatment process and has low carrier collection capacity. The transparent conductive film layer in this area further facilitates carrier extraction. Furthermore, the present invention employs laser sintering to form a first silver paste electrode on the surface of the first semiconductor layer and its corresponding mask layer corresponding to the heat-resistant tunneling oxide layer. This significantly improves the conductivity of the first silver paste and significantly reduces the contact resistivity with the first semiconductor layer, making it easier to extract carriers from this area. This allows for excellent carrier extraction without the need for a transparent conductive film layer. Furthermore, because the laser can precisely control the heat radiation zone, it also prevents damage to the corresponding area of ​​the second semiconductor layer. Furthermore, the present invention specifically controls the second opening area to an appropriate width ratio of the first semiconductor layer, which helps increase the tolerance of the first silver paste electrode and reduces the impact of film residue in the second opening area on battery performance. This replaces the isolation trench that separates the N / P electrodes in traditional processes.

[0023] In the combined passivated back contact battery with a specific opening structure of the present invention, a second opening area with an appropriate width ratio is specially set, and the opening of the second semiconductor layer and the opening of the isolation groove in the traditional process are combined into one, and the isolation groove is eliminated, so that the structure and its corresponding opening process are simplified; and different silver paste electrodes are set on semiconductors with different structures. Specifically, the metal electrode corresponding to the second opening area of ​​the first semiconductor layer adopts the first silver paste electrode to be directly connected to the first semiconductor layer, and the metal electrode corresponding to the first opening area of ​​the second semiconductor layer adopts the second silver paste electrode. The second silver paste electrode is connected to the second semiconductor layer through a transparent conductive film layer. It can simplify the structure and its preparation process and avoid damage to the various functional film layers, which is beneficial to the extraction of carriers, improves the battery conversion efficiency and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 It is a cross-sectional view of a specific embodiment of the back contact battery of the present invention.

[0026] Figure 2 for Figure 1 A partial enlarged view of .

[0027] Description of Reference Numerals 1. Silicon wafer, 21. Tunneling oxide layer, 22. First doped polysilicon layer, 23. Mask layer, 31. Intrinsic amorphous silicon layer, 32. Second doped silicon layer, 33. Transparent conductive film layer, 4. First silver paste electrode, 5. Second silver paste electrode. DETAILED DESCRIPTION

[0028] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0029] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0030] The endpoints of the ranges and any values ​​disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0031] In the present invention, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0032] In a first aspect, the present invention provides a method for manufacturing a combined passivated back contact cell, comprising the following steps: S1, provide silicon wafers; S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer; S3, performing a first opening on the back surface obtained in S2 to form a first opening area; S4, texturing and cleaning, forming a texturing surface at least in the first opening area; S5, depositing a second semiconductor layer on the back side, where the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer; S6, directly depositing a transparent conductive film layer on the surface of the second doped silicon layer obtained in S5; S7, performing a second opening on the second semiconductor layer and the transparent conductive film layer located on the outer surface corresponding to the area where the first semiconductor layer is located, so as to expose the first semiconductor layer or its corresponding mask layer, thereby forming a second opening area; and controlling the width of the second opening area to be 20%-100% of the width of the corresponding first semiconductor layer; S8. First, directly print the first silver paste on the exposed surface corresponding to the second opening area obtained in S7, and then laser sinter the first silver paste to form a first silver paste electrode; then print the second silver paste on the outer surface of the area corresponding to the position of the first opening area, and then bake and solidify the second silver paste to form a second silver paste electrode.

[0033] The width of the second opening area is 20%-100% of the width of the corresponding first semiconductor layer, for example, it can be 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, 100%, etc., and the range between any two point values, preferably 35%-98%.

[0034] In the present invention, it is understood that the tunnel oxide layer is located between the silicon wafer and the first doped polysilicon layer, and the intrinsic amorphous silicon layer is located on a side of the second doped silicon layer close to the silicon wafer.

[0035] The present invention deposits a transparent conductive film layer directly after the second semiconductor layer is deposited, instead of performing a second opening after the second semiconductor layer is deposited and then depositing the transparent conductive film layer in the traditional process, and then opening a second opening area with a wider proportion. The second semiconductor layer opening and the isolation groove opening in the traditional process are combined into one, and the isolation opening process is eliminated, which significantly shortens the process steps, simplifies the process, reduces damage to various functional film layers, and improves the battery conversion efficiency.

[0036] In some preferred embodiments of the present invention, in S8, the second silver paste is cured at a temperature of 180-250°C, preferably 185-250°C, and / or for a curing time of 5-30 minutes. The present invention employs suitable curing conditions of temperature and / or time to form the second silver paste electrode, which facilitates full curing of the second silver paste and formation of good contact with the transparent conductive film layer, while preventing high-temperature curing during laser sintering from damaging the passivation effect of the second semiconductor layer.

[0037] In some preferred embodiments of the present invention, in S8, the laser sintering conditions include: an energy density of 1-20 J / cm 2 , preferably 3-20J / cm 2 The laser sintering time is 0.001-0.5ms, more preferably 0.01-0.5ms. The present invention uses laser sintering conditions with appropriate energy density and time to form the first silver paste electrode, which is more conducive to the first silver paste being fully solidified and sintered, and forming a good ohmic contact with the underlying first semiconductor layer, thereby further effectively reducing the first silver paste line resistivity and contact resistivity.

[0038] In some preferred embodiments of the present invention, laser sintering uses green laser or infrared laser.

[0039] In the present invention. In some preferred embodiments of the present invention, the process of forming the first silver paste electrode in S8 further includes: after laser sintering, a short-time baking auxiliary sintering is performed, and then the second silver paste is printed. The short-time baking auxiliary sintering of the present invention can assist in repairing local defects caused by laser sintering, and is more conducive to further reducing the contact resistivity between the silver paste electrode and the polycrystalline layer, and improving the contact performance between the silver paste electrode and the bottom polycrystalline layer.

[0040] Furthermore, in the present invention, whether to perform short-time baking auxiliary sintering can be selected based on whether the first silver paste contains glass oxide, the retained thickness of the mask layer, and whether the contact resistance of the first semiconductor layer needs to be improved, so as to reduce the first silver paste line resistivity and contact resistivity to the target level; among them, silver paste containing glass oxide generally requires short-time baking auxiliary sintering after laser sintering to reduce the contact resistivity.

[0041] More preferably, the conditions for the short-time baking auxiliary sintering include: a temperature of 100-600°C, more preferably 100-300°C, and even more preferably 100-200°C, for 30-600 seconds. Using this preferred condition for the short-time baking auxiliary sintering facilitates controlling the sintering temperature and time while assisting in sintering the first silver paste, effectively preventing the passivation effect of the second semiconductor layer from being damaged by prolonged high temperatures.

[0042] In some preferred embodiments of the present invention, the manufacturing method further includes a step of removing at least a portion of the mask layer by cleaning in S4. The cleaning step may be cleaning during the texturing cleaning step or an additional cleaning step. Appropriate thinning facilitates silver ions to penetrate the mask layer during laser sintering, forming a silver-silicon alloy with the underlying polysilicon, thereby reducing the contact resistivity of the silver paste electrode.

[0043] More preferably, when the thickness of the mask layer finally retained in S4 is 0-20 nm, the temperature of the short-time baking auxiliary sintering in S8 is controlled to be less than 300° C. and not less than 100° C., and the time is 30-600 s.

[0044] In some preferred embodiments of the present invention, when the thickness of the mask layer finally retained in S4 is greater than 20 nm, the temperature of the short-time baking auxiliary sintering in S8 is controlled to be 300-650° C. and the time is 5-120 s.

[0045] In the above-mentioned preferred scheme of the present invention, the temperature and time of the short-time baking auxiliary sintering in S8 are controlled according to the thickness of the mask layer finally retained in S4, which can optimize the auxiliary sintering effect according to the different film layer structures, and is more conducive to targeted improvement of the contact performance between the silver paste electrode and the bottom polycrystalline layer.

[0046] In some preferred embodiments of the present invention, the thickness of the mask layer ultimately retained in S4 is 0-100 nm. Retaining a thinner mask layer in S4 is more conducive to providing a protective layer of a certain thickness for the first semiconductor layer, thereby preventing damage to the film layer during subsequent processes and facilitating good contact between the first silver paste and the first semiconductor layer.

[0047] Preferably, in the present invention, the thickness of the mask layer formed in S2 is 20-150 nm.

[0048] The type of the mask layer in the present invention can refer to the prior art, for example, the type can be at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, preferably silicon nitride.

[0049] The texturing cleaning in S4 of the present invention can also simultaneously form a texturing surface on the front side of the silicon wafer, and the front side structure of the silicon wafer can be selected according to actual needs.

[0050] In some preferred embodiments of the present invention, the width of the second opening region is 150-500 μm.

[0051] Preferably, in the present invention, the width of the first opening region is 400-800 μm.

[0052] In some preferred embodiments of the present invention, the thickness of the transparent conductive film layer is controlled to be 15-80 nm in S6. Using a transparent conductive film layer of appropriate thickness is more conducive to balancing the technical requirements of the laser opening effect of the second opening region and the carrier collection efficiency of the second semiconductor layer through adjusting the film thickness.

[0053] In the present invention, performing a second opening in S7 to expose the first semiconductor layer or its corresponding mask layer means etching away the second semiconductor layer and the transparent conductive film layer in the target area, and the second opening exposes the first semiconductor layer or the mask layer corresponding to the first semiconductor layer. It is understood that when a portion of the mask layer is removed in S4, the second opening exposes the mask layer corresponding to the first semiconductor layer, and when all the mask layers are removed in S4, the second opening exposes the first semiconductor layer.

[0054] In some preferred embodiments of the present invention, the second opening in S7 is performed by laser opening, which is more conducive to achieving rapid and non-destructive opening of the multi-layer structure by matching the laser wavelength pulse width with the film layer structure, thereby avoiding damage to other non-processed film layers. The laser opening can be performed by a green laser or an ultraviolet laser. The selection of conditions for the laser opening in the present invention is relatively wide, as long as the opening of the target area can be achieved; for example, the laser pulse width can be nanometers, picoseconds, or femtoseconds, and preferably an ultraviolet picosecond laser is used for the second opening; for another example, the laser beam used can be flat-top shaped, and preferably a rectangular flat-top shaping laser is used.

[0055] In the present invention, preferably, in S8, the first silver paste is a laser-sintered silver paste, and the second silver paste is a bake-cured silver paste. Both laser-sintered silver paste and bake-cured silver paste have common meanings in the art and are formed using different methods (e.g., laser sintering or bake-curing). Silver pastes corresponding to the formation methods can be selected from the prior art to form corresponding types of electrodes. In some preferred embodiments of the present invention, in S8, the first silver paste comprises a first silver powder, a first organic vehicle, and optionally a glass oxide, and the second silver paste comprises a second silver powder, a second organic vehicle, and no glass oxide. Exemplarily, the first silver paste comprises 75-90 wt% of the first silver powder, 10-30 wt% of the first organic vehicle, and 0-5 wt%, preferably 1-5 wt%, of glass oxide, and the second silver paste comprises 80-93 wt% of the second silver powder, 7-20 wt% of the second organic vehicle, and no glass oxide. More preferably, the first silver powder contains at least 60 wt% nano-scale silver powder and at least 5 wt% submicron-scale silver powder, with the nano-scale silver powder having a size of 10-100 nm and the submicron-scale silver powder having a size of 0.1-1 μm. The second silver powder contains at least 60 wt% micro-nanoscale silver powder particles and at least 5 wt% flaky silver powder, with the micro-nanoscale silver powder having a size of 0.1-3 μm and the flaky silver powder having a size of 0.5-5 μm. The corresponding silver powders can be of any desired size; for example, the second silver powder can be spherical particles and / or flakes, while the first silver powder is granular. Furthermore, the second silver paste preferably includes additives and solvents, such as PVP and dibutyl phthalate, and solvents such as terpineol and acetone.

[0056] In S8 of the present invention, the first silver paste and the second silver paste may be printed by, for example, a screen printing method.

[0057] In some preferred embodiments of the present invention, the thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm -3 .

[0058] Preferably, the thickness of the intrinsic amorphous silicon layer is 5-15 nm; the thickness of the second doped silicon layer is 7-45 nm, and the effective doping concentration is 2e18 cm -3 -3e20cm -3 .

[0059] In some preferred embodiments of the present invention, S5 further includes the step of forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer. The formation of the front passivation layer and the anti-reflection layer can be performed before or after forming the second semiconductor layer, depending on actual needs.

[0060] In a second aspect, the present invention provides a back contact cell, which is manufactured by the method for manufacturing a combined passivation back contact cell according to the first aspect. The structure of the back contact cell according to the second aspect of the present invention is the same as that of the combined passivation back contact cell according to the third aspect described below.

[0061] In a third aspect, the present invention provides a combined passivated back contact battery with a specific opening structure, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, a first opening area formed between adjacent first semiconductor layers, two ends of the second semiconductor layer respectively extending outward to cover the portion of the back side of the adjacent first semiconductor layer, and a second opening area not covering the second semiconductor layer is opened on the back side of the first semiconductor layer, the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer, the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer, and further comprises: a transparent conductive film layer arranged outside the second semiconductor layer, a second silver paste electrode arranged outside the transparent conductive film layer corresponding to the first opening area, and a first silver paste electrode arranged on the outer surface of the area where the second opening area is located, the first silver paste electrode is a laser sintering type silver paste electrode, the second silver paste electrode is a baking-cured type silver paste electrode, and no transparent conductive film layer is arranged on the second opening area; and the width of the second opening area is 20%-100% of the width of the corresponding first semiconductor layer. The present invention arranges a second silver paste electrode and a first silver paste electrode in different semiconductor structures, and cooperates with a wider second opening area, without the need to set an isolation groove, which can not only simplify the preparation process, but also improve the carrier extraction and promote the improvement of battery conversion efficiency.

[0062] In some preferred embodiments of the present invention, the width of the second opening region is 150-500 μm, and / or the width of the first opening region is 400-800 μm.

[0063] In some preferred embodiments of the present invention, the width of the first silver paste electrode is 20-100 μm, and the width of the second silver paste electrode is 20-100 μm. Using second and first silver paste electrodes of appropriate widths is more conducive to optimizing silver paste consumption and reducing costs while ensuring sufficient conductivity.

[0064] Preferably, the baking-curing silver paste is a silver paste electrode formed by baking and curing at a temperature below 100-300°C.

[0065] In some preferred embodiments of the present invention, a mask layer may or may not be provided between the second semiconductor layer and the first semiconductor layer in the thickness direction of the second semiconductor layer covering the corresponding region of the first semiconductor layer.

[0066] In the present invention, a mask layer is preferably provided or not provided between the first semiconductor layer and the first silver paste electrode. In this solution, the mask layer is relatively thin, with a thickness of 0-100 nm.

[0067] In some preferred embodiments of the present invention, a portion of the silicon wafer located at the first opening region is a textured surface, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface.

[0068] In some preferred embodiments of the present invention, the thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm -3 .

[0069] Preferably, the thickness of the intrinsic amorphous silicon layer is 5-15 nm; the thickness of the second doped silicon layer is 7-45 nm, and the effective doping concentration is 2e18 cm -3 -3e20cm -3 .

[0070] The combined passivation back contact cell of the present invention may also include other conventional cell structures. In some preferred embodiments of the present invention, the combined passivation back contact cell further includes a front passivation layer and an anti-reflection layer sequentially disposed on the front side of the silicon wafer.

[0071] In a fourth aspect, the present invention provides a battery assembly comprising the back-contact cell described in the second aspect, or the combined passivated back-contact cell with a specific opening structure described in the third aspect. The battery assembly, such as a battery module, is any structure containing the back-contact cell or combined passivated back-contact cell of the present invention.

[0072] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0073] Example 1 A combined passivation back contact battery, the cross-sectional view of which is as follows Figure 1 and Figure 2 As shown, the steps of its production method are as follows: S1, providing silicon wafer 1; S2, forming a first semiconductor layer and a mask layer 23 with a thickness of 60nm (specifically silicon nitride) on the back side of the silicon wafer 1 in sequence; the first semiconductor layer includes a tunneling oxide layer 21 with a thickness of 1.5nm and a 80nm thick layer with an effective doping concentration of 2e20cm -3 A first doped polysilicon layer 22 (N type); S3, performing a first opening on the back surface obtained in S2, forming a first opening area with a width of 500 μm; S4, texturing and cleaning, forming a texturing surface at least in the first opening area, and removing part of the mask layer 23, leaving the mask layer 23 with a thickness of 15 nm; S5, depositing a second semiconductor layer on the back side, the second semiconductor layer comprising an intrinsic amorphous silicon layer 31 with a thickness of 5 nm and an 8 nm thick silicon layer with an effective doping concentration of 5e19 cm -3 A second doped silicon layer 32 (P-type) is formed; and a front passivation layer and an anti-reflection layer are sequentially formed on the front surface of the silicon wafer 1; S6. Depositing a transparent conductive film layer 33 (ITO) with a thickness of 40 nm directly on the surface of the second doped silicon layer 32 obtained in S5; S7. Using laser opening, a second opening is performed on the second semiconductor layer and the transparent conductive film layer 33 located on the outer surface corresponding to the area where the first semiconductor layer is located, so as to expose the mask layer 23 corresponding to the first semiconductor layer, thereby forming a second opening area. The width of the second opening area is controlled to be 95% of the width of the first semiconductor layer, and the width of the second opening area is 450 μm. S8. Using a screen printing method, first directly print a first silver paste with a width of 50 μm on the exposed surface corresponding to the second opening area obtained in S7, then perform laser sintering on the first silver paste, and then perform a short-time baking to assist sintering, to form a first silver paste electrode 4. The first silver paste is composed of: based on the total mass of the first silver paste, a first silver powder (which is high-purity silver, the high-purity silver containing 75wt% nano-silver powder with a size of 10-100nm and 10wt% submicron silver powder with a size of 0.1-1μm, commercially available) with a mass content of 85wt%, a glass oxide (specifically Bi2O3-SiO2 system) with a mass content of 1wt%, and a first organic vehicle (specifically ethyl cellulose) with a mass content of 14wt%.

[0074] Among them, the laser sintering conditions are: laser sintering uses green laser with an energy density of 4J / cm 2 The laser sintering time is 0.08ms. The conditions of short-time baking auxiliary sintering are as follows: the short-time baking auxiliary sintering temperature is 200℃ and the time is 60s. The line resistivity of the corresponding first silver paste electrode is 1.046Ω / cm and the contact resistivity is 10.370 mΩ·cm. 2 . Then, a second silver paste with a width of 60 μm is printed on the outer surface of the area corresponding to the position of the first opening area by screen printing, and the second silver paste is baked and cured to form a second silver paste electrode 5, thereby forming a fine gate electrode. Baking and curing: the temperature is 195°C and the time is 10 minutes. The second silver paste is composed of: based on the total mass of the second silver paste, the mass content of the second silver powder (containing 10wt% flake silver powder with a size in the range of 0.5-5μm and 75wt% nano silver powder with a size in the range of 0.05-1μm, commercially available) is 85wt%, the second organic carrier (specifically 7wt% epoxy resin); solvent (5wt% pine ethanol, 2wt% acetone); additives (0.5wt% PVP, 0.5wt% dibutyl phthalate). The line resistivity of the second silver paste electrode is 1.343Ω / cm and the contact resistivity is 93.650 mΩ·cm 2 .

[0075] Example 2 The process was carried out in accordance with Example 1, except that the energy density of laser sintering was adjusted to 2 J / cm 2 The corresponding line resistivity and contact resistivity of the first silver paste electrode are shown in Table 1 below.

[0076] Example 3 The same procedure was followed as in Example 1, except that the curing temperature of the second silver paste was adjusted to 180° C. The line resistivity and contact resistivity of the corresponding second silver paste electrode are shown in Table 1 below.

[0077] Example 4 The process was carried out in accordance with Example 1, except that no short-time baking auxiliary sintering was performed after the laser sintering. The line resistivity and contact resistivity of the corresponding first silver paste electrode are shown in Table 1 below.

[0078] Example 5 Refer to Example 1, except that when the thickness of the mask layer finally retained in S4 is 30 nm, the short-time baking auxiliary sintering temperature in S8 is controlled at 300°C, and the baking time is 45 s. The line resistivity and contact resistivity of the corresponding first silver paste electrode are shown in Table 1 below.

[0079] Example 6 The same method was used as in Example 1, except that the auxiliary sintering temperature in S8 short-time baking was 350° C. The line resistivity and contact resistivity of the corresponding first silver paste electrode are shown in Table 1 below.

[0080] Example 7 The same process was performed as in Example 1, except that the mask layer was completely removed in S4, the first silver paste did not contain glass oxide in S8, and no short-time baking to assist sintering was performed. The line resistivity and contact resistivity of the corresponding first silver paste electrodes are shown in Table 1 below.

[0081] Example 8 The process is carried out in accordance with Example 1, except that the width of the second opening region in S7 is 40% of the width of the first semiconductor layer.

[0082] Comparative Example 1 The process is carried out in accordance with Example 1, except that a conventional post-texturing preparation method is used to form a conventional battery structure. Specifically, after S3, the following steps are performed: S4, texturing cleaning, forming a texturing surface at least in the first opening area and completely removing the mask layer; S5, depositing a second semiconductor layer on the back side, the second semiconductor layer comprising an intrinsic amorphous silicon layer with a thickness of 5nm and an 8nm thick layer with an effective doping concentration of 5e19cm -3 A second doped silicon layer (P-type) is formed on the front side of the silicon wafer; and a front passivation layer and an anti-reflection layer are formed in sequence on the front side of the silicon wafer; S6, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second etched opening region spaced apart from the first opening region, wherein the width of the second etched opening region is 200 μm; S7, performing HF treatment on the opening to remove the residual oxide layer; S8, depositing a transparent conductive film layer on the back surface of the substrate obtained in S7; S9, performing a third etching opening according to a preset pattern on the portion of the transparent conductive film layer corresponding to the overlapping area between the first opening area and the second etching opening area to form an isolation groove, wherein the width of the isolation groove is 80 μm; S10. Metal electrodes are formed on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second etched opening area by screen printing. The metal electrodes are second silver paste electrodes (the composition of which is the same as the second silver paste in Example 1).

[0083] Comparative Example 2 The process is carried out in accordance with Example 1, except that in S6 the width of the second opening region is controlled to be 15% of the width of the first semiconductor layer.

[0084] Test Case The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. The method for measuring the resistivity of the silver paste electrode line is as follows: collecting the unit length L and resistance R of the fine grid electrode at the five-square grid position of the battery, and calculating the fine grid electrode line resistivity ρ L The average value is calculated as ρ L=R / L.

[0085] The method for measuring the contact resistivity of silver paste electrodes is as follows: refer to the following group standard: T / CPI A 0051-2023 "Test method for contact resistivity of metal electrodes of crystalline silicon photovoltaic cells - Transmission line model method (TLM)". This standard is cited for testing BC cells. Specifically, the TLM method is used to collect and test strip samples with an electrode width W of 1 cm from the semi-finished cell (wherein different types of silicon wafers are used for different semiconductor film layers. Specifically, the first silver paste located in the N-type semiconductor conductive area is collected using the corresponding cell with an N-type silicon wafer as the substrate, and the second silver paste located in the P-type semiconductor conductive area is collected using the corresponding cell with a P-type silicon wafer as the substrate). Then, the resistance R between electrodes with different spacings d is collected. T , and fitted the linear curve R T =k·d+2R c , the contact resistivity ρ is calculated using the TLM model c , whose general model is ρ c =Rc 2 W 2 / R sh , where R c is the contact resistance. According to the above fitting curve, when d=0, R T =2Rc; W is the electrode width; R sh is the sheet resistance, and the slope of the fitting curve k=R sh / W obtains.

[0086] Table 1

[0087] The above results show that, compared to the comparative example, the embodiment of the present invention can improve carrier extraction performance while simplifying the process and reducing damage to various functional film layers (such as the second semiconductor layer), thereby maintaining high battery conversion efficiency and reducing costs. However, the solution in Comparative Example 1, which includes isolation trenches and uses the second silver paste as electrodes, has high line and contact resistivities, resulting in a slightly higher battery series resistance (RS), which limits the improvement of the fill factor (FF) and is reflected in the relatively poor final battery efficiency.

[0088] Furthermore, according to Examples 1 and 2-8, it can be seen that by adopting the preferred scheme of the present invention, by using the first silver paste as the metal electrode of the first semiconductor region, and by combining the second semiconductor region opening and the isolation groove opening into one, the two electrodes of the battery cell are isolated. By combining the combined passivation battery process and optimizing the manufacturing process, it is more conducive to reducing the first silver paste line resistivity and contact resistivity, thereby achieving the effect of improving the battery conversion efficiency.

[0089] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, various simple variations of the technical solution of the present invention may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed in the present invention and fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a combined passivation back contact battery, characterized in that: The following steps are involved: S1, provide silicon wafers; S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer; S3, performing a first opening on the back surface obtained in S2 to form a first opening area; S4, texturing and cleaning, forming a texturing surface at least in the first opening area; S5, depositing a second semiconductor layer on the back side, where the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer; S6, directly depositing a transparent conductive film layer on the surface of the second doped silicon layer obtained in S5; S7, performing a second opening on the second semiconductor layer and the transparent conductive film layer located on the outer surface corresponding to the area where the first semiconductor layer is located, so as to expose the first semiconductor layer or its corresponding mask layer, thereby forming a second opening area; and controlling the width of the second opening area to be 20%-100% of the width of the corresponding first semiconductor layer; S8. First, directly print the first silver paste on the exposed surface corresponding to the second opening area obtained in S7, and then laser sinter the first silver paste to form a first silver paste electrode; then print the second silver paste on the outer surface of the area corresponding to the position of the first opening area, and then bake and solidify the second silver paste to form a second silver paste electrode.

2. The method for manufacturing a combined passivated back contact cell according to claim 1, characterized in that: In S8, the baking and curing temperature of the second silver paste is 180-250° C., and / or the baking and curing time is 5-30 minutes.

3. The method for manufacturing a combined passivated back contact cell according to claim 1 or 2, characterized in that: In S8, the laser sintering conditions include: energy density of 1-20J / cm 2 , the laser sintering time is 0.001-0.5 ms; And / or, the laser sintering uses a green laser or an infrared laser.

4. The method for manufacturing a combined passivated back contact cell according to claim 1, characterized in that: The process of S8 forming the first silver paste electrode also includes: after laser sintering, short-time baking auxiliary sintering is performed, and then the second silver paste is printed; wherein, the conditions for short-time baking auxiliary sintering include: the temperature of short-time baking auxiliary sintering is 100-600℃, and the time is 30-600s.

5. The method for manufacturing a combined passivated back contact cell according to claim 4, characterized in that: The manufacturing method also includes a step of removing at least part of the mask layer by cleaning in S4. When the thickness of the mask layer finally retained in S4 is 0-20nm, the temperature of the short-time baking auxiliary sintering in S8 is controlled to be less than 300°C and not less than 100°C, and the time is 30-600s; when the thickness of the mask layer finally retained in S4 is greater than 20nm, the temperature of the short-time baking auxiliary sintering in S8 is controlled to be 300-650°C, and the time is 5-120s.

6. The method for manufacturing a combined passivated back contact cell according to claim 5, characterized in that: The thickness of the mask layer finally retained in S4 is 0-100 nm, and / or the thickness of the mask layer formed in S2 is 20-150 nm.

7. The method for manufacturing a combined passivated back contact cell according to claim 1, characterized in that: The width of the second opening region is 150-500 μm, and / or the width of the first opening region is 400-800 μm.

8. The method for manufacturing a combined passivated back contact cell according to claim 1, characterized in that: The production method further comprises at least one of the following processes: In process 1, S6, the thickness of the transparent conductive film layer is controlled to be 15-80 nm; Process 2: In S7, the second opening is opened by laser; In process three, S8, the first silver paste is a laser sintering type silver paste, and the second silver paste is a baking curing type silver paste; Process 4: The thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm -3 The thickness of the intrinsic amorphous silicon layer is 5-15nm; the thickness of the second doped silicon layer is 7-45nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 ; Process five, S5, also includes the step of forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer.

9. A back contact battery, characterized in that: The battery is prepared by the method for preparing a combined passivated back contact battery as claimed in any one of claims 1 to 8.

10. A combined passivated back contact cell with a specific opening structure, comprising a silicon wafer, first and second semiconductor layers alternately arranged on the back side of the silicon wafer, a first opening region formed between adjacent first semiconductor layers, two ends of the second semiconductor layer respectively extending outward to cover the portion of the back side of the adjacent first semiconductor layer, and a second opening region not covering the second semiconductor layer is formed on the back side of the first semiconductor layer, the first semiconductor layer comprising a tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer comprising an intrinsic amorphous silicon layer and a second doped silicon layer, characterized in that: Also includes: A transparent conductive film layer is arranged outside the second semiconductor layer, a second silver paste electrode is arranged outside the transparent conductive film layer corresponding to the first opening area, and a first silver paste electrode is arranged on the outer surface of the area where the second opening area is located. The first silver paste electrode is a laser sintering type silver paste electrode, and the second silver paste electrode is a baking-cured type silver paste electrode. No transparent conductive film layer is arranged on the second opening area; and the width of the second opening area is 20%-100% of the width of the corresponding first semiconductor layer.

11. The combined passivated back contact cell with a specific opening structure according to claim 10, characterized in that: The combined passivated back contact cell further includes at least one of the following structures: Structure 1: The width of the first silver paste electrode is 20-100 μm, and the width of the second silver paste electrode is 20-100 μm; Structure 2: Bake-cured silver paste is a silver paste electrode formed by baking and curing at temperatures below 100-300°C; Structure 3: The width of the second opening area is 150-500 μm, and the width of the first opening area is 400-800 μm; Structure 4: The portion of the silicon wafer located at the first opening area is a textured surface, and the portion of the silicon wafer corresponding to the first semiconductor layer is a polished surface; Structure 5: The thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm -3 The thickness of the intrinsic amorphous silicon layer is 5-15nm; the thickness of the second doped silicon layer is 7-45nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 ; Structure 6 also includes a front passivation layer and an anti-reflection layer sequentially provided on the front side of the silicon wafer; Structure 7: A mask layer may or may not be provided between the first semiconductor layer and the first silver paste electrode; and a mask layer may or may not be provided between the second semiconductor layer and the first semiconductor layer in the thickness direction of the second semiconductor layer covering the corresponding area of ​​the first semiconductor layer.

12. A battery assembly, characterized in that: It comprises the back contact cell according to claim 9 or the combined passivated back contact cell with a specific opening structure according to claim 10 or 11.

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