Silicon wafer, battery piece, battery string and photovoltaic device

Abstract

The invention provides a silicon wafer, a battery piece, a battery string and a photovoltaic device, and relates to the technical field of photovoltaics. A plurality of hole structures are arranged in the silicon wafer, the silicon wafer comprises a first surface and a second surface which are opposite, and at least part of the hole structures are through hole structures; and / or at least part of the hole structure is a blind hole structure extending from the first surface to the inside of the silicon wafer; the first surface comprises a first side with the length of L1 and a second side with the length of L2, and L1 is larger than or equal to L2; the marginal area comprises a first marginal area and a second marginal area which are distributed in an intersecting manner; the width of the first edge area is W1; the thickness of the silicon wafer is H; 0.05 < = W1 / H < = 40. According to the invention, the risk of fracture or breakage of the silicon wafer with the hole structure is reduced, and the mechanical strength is improved; a good visual effect is ensured; a good electrical effect is ensured; insufficient absorption caused by excessive silicon material removal is avoided, and high photoelectric conversion efficiency is ensured.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a silicon wafer, a battery wafer, a battery string and a photovoltaic device. Background Art

[0002] Solar cells based on silicon wafers have higher photoelectric conversion efficiency, higher stability and reliability, and scalable production costs. Therefore, silicon wafers have received a lot of attention in the photovoltaic field.

[0003] In recent years, with the differentiation of demand scenarios for photovoltaic products, some perforated photovoltaic products are needed.

[0004] At present, in punched photovoltaic products, the mechanical strength of the substrate is greatly affected after the substrate is punched, and the problem of fragmentation during the production process is very serious, which has caused great obstacles to its large-scale commercial implementation and application. Summary of the Invention

[0005] The present invention provides a silicon wafer, a battery cell, a battery string and a photovoltaic device, aiming to solve the problem of poor mechanical strength of the substrate of existing transparent or semi-transparent photovoltaic products due to openings in the substrate.

[0006] A first aspect of the present invention provides a silicon wafer having a plurality of hole structures disposed therein; the silicon wafer comprising: a first surface and a second surface opposite to each other along a thickness direction thereof;

[0007] At least some of the hole structures are through-hole structures, the through-hole structures connecting the first surface and the second surface, the aperture B1 of the through-hole structure in the first surface being greater than or equal to the aperture B2 of the through-hole structure in the second surface; and / or at least some of the hole structures are blind hole structures; the blind hole structures extend from the first surface into the silicon wafer; the hole structures are not provided in an edge region of the first surface; the first surface comprises: a first side and a second side, the length of the first side being L1, the length of the second side being L2, and L1 ≥ L2; the edge region comprises: a first edge region and a second edge region intersectingly distributed; the first edge region is provided along the first side, and the second edge region is provided along the second side;

[0008] The width of the first edge region is W1;

[0009] The thickness of the silicon wafer is H;

[0010] 0.05≤W1 / H≤40.

[0011] In the present application, for silicon materials, the silicon wafer provided in the present application has a value of 0.05≤W1 / H≤40. First, for silicon wafers with a hole structure, breakage or cracking is more likely to occur in the first edge region containing the first side (longer side) on the first surface. Therefore, in the present application, the focus is on the width of the first edge region in the first surface; second, the H of the silicon wafer is within a certain range: when H is smaller, the toughness of the silicon wafer with a hole structure is improved, and the brittleness of the silicon wafer with a hole structure is reduced. When H is larger, the toughness of the silicon wafer with a hole structure is reduced, and the brittleness of the silicon wafer with a hole structure is increased. , when the toughness of the silicon wafer with the hole structure is high, the probability of its cracking or breaking will also be reduced. That is to say, within a certain range, the H of the silicon wafer has a significant correlation with the probability of cracking or breaking of the silicon wafer with the hole structure, and the H of the silicon wafer also has an important correlation with the electrical effect. Taking into account the above-mentioned first and second factors, when the width W1 of the first edge area in the first surface is less than 0.05H, W1 is too small, the hole structure in the first surface is too close to the first side, and the risk of the silicon wafer in the first edge area of ​​the first surface of the silicon wafer including the first side is higher. At the same time, relative to W1 , the thickness H of the silicon wafer is too large. If the silicon wafer is too thick, it will lead to excessive electrical loss in the body region and excessive side loss, resulting in a significant decrease in photoelectric conversion efficiency. Moreover, when W1 is less than 0.05H, W1 is too small, the processing parameters of the hole structure are difficult to guarantee, and the yield of the hole structure is also low. Therefore, 0.05H≤W1, the width of W1 is suitable, and the first edge area of ​​the first surface of the silicon wafer including the first side of the silicon wafer has basically no risk of breakage or cracking, which significantly improves the mechanical strength of the silicon wafer with the hole structure, and the yield of the hole structure is high, which is easy to achieve mass production, and at the same time can ensure the photoelectric conversion efficiency of the battery; In summary, Regarding the first and second factors, when the width W1 of the first edge area in the first surface is greater than 40H, W1 is too large, the hole structure in the first surface is too far away from the edge of the silicon wafer, and the transparency and visual effects are poor. Moreover, relative to W1, the thickness H of the silicon wafer is too small, and the mechanical strength and electrical effects of the silicon wafer are difficult to guarantee. Therefore, in this application, W1≤40H is the result of optimizing and balancing multiple factors including transparency, visual effect, mechanical strength and electrical effects of the silicon wafer. Not only is the transparency and visual effect good, the mechanical strength of the silicon wafer is high, but also the electrical effect is good, laying a good foundation for the commercial application of such photovoltaic products.

[0012] To sum up, the present application, firstly, significantly reduces the risk of cracking or breaking of a silicon wafer with a hole structure, especially reduces the risk of cracking or breaking of the first edge area in the first surface of the silicon wafer with a hole structure, and improves the mechanical strength; secondly, ensures good visual effects and yield, and is easy to achieve mass production; thirdly, in the through-hole structure, when the aperture of the hole structure in the first surface is larger than the aperture of the hole structure in the second surface, there is an angle between the hole wall of the through-hole and the thickness direction of the silicon wafer, and the through-hole structure is a tapered through-hole; or, when there is an angle between the hole wall of the blind hole and the thickness direction of the silicon wafer, the blind hole structure is a tapered blind hole; for tapered through holes and tapered blind holes, when the angle here is small, the hole wall is close to being parallel to the thickness direction of the silicon wafer. After the light shines on one side of the hole wall, the light is reflected more in the hole, which can increase the light transmission path. For the tapered through holes and tapered blind holes, during the actual installation of the solar cells, due to the longitude and latitude of the installation site, the solar cells are usually tilted. One side of the hole wall of the tapered through holes and tapered blind holes can be nearly perpendicular to the light, greatly increasing the light receiving area of ​​the silicon wafer or solar cell, increasing the light absorption rate, and improving the electrical efficiency. Therefore, the present application ensures a good electrical effect; fourthly, it avoids removing too much silicon material to cause insufficient absorption, ensuring high photoelectric conversion efficiency. In addition, when the hole structure is a through hole structure, a larger field of view from the second surface and a smaller field of view from the first surface can be achieved. The photovoltaic product corresponding to the silicon wafer can be used in application scenarios where different fields of view are obtained from different surfaces, expanding the application scenarios of photovoltaic products. Since the blind hole structure does not penetrate the silicon wafer, the side opposite to the first surface of the silicon wafer still has good mechanical strength. At the same time, due to the presence of the hole structure, the transmittance or transmittance can also be increased, which can still improve the visual effect.

[0013] In some possible implementations of the present application, the width of the second edge region is W2; 1≤(W1 / W2)≤(L1 / L2).

[0014] W1 ≥ W2 reduces the risk of cracking or breaking in the first edge region of the first surface, including the first edge. However, when (W1 / W2) > (L1 / L2), the width of the first edge region of the first surface, including the first edge, is much larger than the width of the second edge region, including a portion of the second edge. The probability of cracking or breaking in the first edge region, including the first edge, is already very small, and the hole structure is too far from the edge of the silicon wafer, resulting in a decrease in transparency and visual effects. Therefore, in this application, the width of the second edge region is W2; 1 ≤ (W1 / W2) ≤ (L1 / L2). This not only reduces the risk of cracking or breaking in the first edge region of the first surface, including the first edge, and improves mechanical strength, but also ensures good transparency and visual effects.

[0015] In some embodiments, the silicon wafer can be rectangular, in which case L1>L2, or square, in which case L1=L2. When the silicon wafer is rectangular, W1 / W2 can be determined based on the ratio of L1 / L2. When the silicon wafer is square, W1 / W2 can be 1.

[0016] In some possible implementations of the present application, when the hole structure is a through-hole structure:

[0017] 0.5≤(B1-B2)÷(B1 / 2))≤1.

[0018] It can be ensured that the light transmittance of the solar cell prepared by using the silicon wafer can be maintained at 50% or above of the designed light transmittance when viewed from the first surface to the second surface, with good light transmittance effect and good visual effect.

[0019] In some possible implementations of this application,

[0020] At the position where the midline of the thickness direction of the silicon wafer is located, the aperture of the hole structure is B3; B1 ≥ B3;

[0021] 0.1≤(B1-B3)÷(H / 2)≤50.

[0022] (B1-B3)÷(H / 2) represents the average decreasing slope or rate of the pore structure's pore size along the direction of the pore structure's extension (i.e., the thickness direction of the silicon wafer) from the first surface. A value less than 0.1 indicates that the average decreasing slope or rate of the pore structure's pore size is too small, and the pore structure tends to maintain a constant pore size, resulting in an insufficiently significant improvement in visual quality. A value greater than 50 indicates that the average decreasing slope or rate of the pore structure's pore size is too large or too rapid, and the process parameters for forming the pore structure may be difficult to control, making mass production difficult. The process window for forming the pore structure is narrow, resulting in a low yield. Therefore, a value between 0.1 and 50 ensures a more pronounced visual effect, eases mass production, and results in a high yield. At the same time, (B1-B3)÷(H / 2) can characterize the angle between the hole wall of the hole structure and the thickness direction of the silicon wafer. When 0.1≤(B1-B3)÷(H / 2)≤50, there is an angle between the hole wall of the hole structure and the thickness direction of the silicon wafer. The hole structure is a conical hole structure. When the angle here is small, the hole wall is close to being parallel to the thickness direction of the silicon wafer. After the light shines on one side of the hole wall, the light is reflected more in the hole, which can increase the light transmission path; during the actual installation of the battery cell, due to the longitude and latitude of the installation site, the battery cell is usually tilted. One side of the hole wall of the conical hole structure can be close to perpendicular to the light, which greatly increases the light receiving area of ​​the silicon wafer or battery cell, increases the light absorption rate, and improves the electrical efficiency. Therefore, the present application ensures good electrical effects.

[0023] In some possible implementations of the present application, B3 is 1 μm to 100 μm.

[0024] In some possible implementations of the present application, the cross-sectional shape of the hole structure along the thickness direction of the silicon wafer includes at least one of a rectangle, a trapezoid, and a waist shape; and / or,

[0025] The cross-sectional profile of the hole structure on the first surface includes an arc segment; the closer to the center of the first surface, the closer the cross-sectional profile of the hole structure on the first surface is to a circle.

[0026] The further away from the center of the first surface, the closer it is to the aforementioned edge area. Since there is no hole structure in the aforementioned edge area, the visual effect is inferior to that of the position where the hole structure is set. By setting a hole structure with a cross-sectional profile close to a non-circular shape at a position close to the aforementioned edge area, it is helpful to offset the problem of inconsistent visual effects caused by the edge area.

[0027] In some possible implementations of the present application, W1 is 0.005 mm to 10 mm; and / or,

[0028] H is 2 μm to 200 μm.

[0029] In some possible implementations of the present application, B1 is 10 μm to 500 μm; and / or,

[0030] The distance A between adjacent hole structures is 1 μm to 500 μm.

[0031] A second aspect of the present invention provides a battery cell comprising: an electrode structure, and any of the aforementioned silicon wafers; the electrode structure is disposed on the silicon wafer.

[0032] In some possible implementations of the present application, the electrode structure is staggered with the hole structure.

[0033] Staggering the electrode structure with the hole structure not only ensures the conductivity of the electrode structure, but also avoids the problem of reduced light transmittance or transmittance caused by the electrode structure blocking the hole structure.

[0034] In some possible implementations of the present application, the electrode structure includes: a gate line electrode, and the hole structures are arranged in an array on one side of the cell where the gate line electrode is located;

[0035] On the same side of the silicon wafer, the distance between the gate line electrode and the center line between two adjacent hole columns is less than or equal to 10 μm; the center line is along the extending direction of the gate line electrode.

[0036] On the same side of the silicon wafer, the center lines of the gate electrode and the adjacent hole structure roughly overlap or completely overlap, which avoids the gate electrode being cut off by the hole structure as much as possible, is beneficial to the collection and transmission of carriers, ensures the conductivity of the electrode structure, and avoids the problem of reduced transmittance or transmittance caused by the gate electrode blocking the hole structure.

[0037] In some possible implementations of the present application, the electrode structure includes: a plurality of front gate line electrodes located on the light-facing side of the silicon wafer, and a plurality of back gate line electrodes located on the backlight-repellent side of the silicon wafer;

[0038] The hole structure is a through-hole structure:

[0039] The number of hole structures between adjacent front gate line electrodes is greater than or equal to the number of hole structures between adjacent back gate line electrodes.

[0040] In bifacial cells, since the hole structures are through-holes, the number of hole structures is equal for both the light-facing and backlight-facing sides of the silicon wafer. By setting the number of hole structures between adjacent front-facing gridline electrodes on the light-facing side of the silicon wafer to be greater than or equal to the number of hole structures between adjacent back-facing gridline electrodes on the backlight-facing side of the silicon wafer, the sparsity of the gridlines on different sides can be adjusted to meet the different conductivity requirements of the cell for the light-facing and backlight-facing sides. Specifically, the back-facing gridline electrodes on the backlight side are arranged more densely to increase the current collection effect, while the front-facing gridline electrodes on the light-facing side are arranged more sparsely to increase the light trapping effect. Therefore, this is an optimized choice that takes into account the carrier collection and light-facing power generation efficiency of the cell, ensuring not only the light transmittance or transmittance and visual effect of the bifacial cell, but also the current collection effect and light-facing power generation efficiency of the bifacial cell.

[0041] In some possible implementations of the present application, the hole structures are arranged in arrays on both the light-facing side and the backlight-facing side of the silicon wafer;

[0042] The number of columns of the hole structures between adjacent front gate line electrodes is greater than or equal to the number of columns of the hole structures between adjacent back gate line electrodes.

[0043] The back grid line electrodes on the backlight side are arranged more densely to increase the current collection effect, and the front grid line electrodes on the light side are arranged more sparsely to reduce shading and increase the light trapping effect.

[0044] In some possible implementations of the present application, the spacing between adjacent front gate line electrodes is G1, and the spacing between adjacent back gate line electrodes is G2;

[0045] On the same side of the silicon wafer, along the extending direction of the gate line electrode, the spacing between adjacent hole structures is G3;

[0046] G1-G2=n×G3; n is an integer from 1 to 10.

[0047] On the basis of ensuring the light transmittance or transmittance and visual effect of the bifacial cell, and also ensuring the current collection effect and front power generation rate of the bifacial cell, the size of G3 will affect the aesthetic effect of the bifacial cell, and will also affect the mechanical strength and electrical effect of the cell. Limiting the relationship between G1, G2, and G3 within this relationship can further ensure the light transmittance or transmittance and visual effect of the bifacial cell, and further ensure the current collection effect, front power generation rate and mechanical strength of the bifacial cell.

[0048] In some possible implementations of the present application, the electrode structure includes: electrode structures that are spaced and alternately distributed; and the electrode structures are all located on the backlight side of the silicon wafer.

[0049] According to a third aspect of the present invention, a battery string is provided. The battery string is formed by sequentially connecting a plurality of any of the aforementioned battery cells in series and / or in parallel.

[0050] In some possible implementations of the present application, along the extension direction of the battery string, the spacing between adjacent battery cells is D;

[0051] When D>H, H≤W1≤0.5D; the mechanical strength of the silicon wafer with the hole structure is significantly improved, and the visual effect of the wafer spacing can be blurred through the first edge area, which can enhance the visual effect of the silicon wafer or battery string at and near the spacing, and improve the appearance.

[0052] When H≥D>0, 0.5H≤W1≤H; the mechanical strength of the silicon wafer with the hole structure is significantly improved; at the same time, when H≥D>0, D in the battery string is smaller and densely packed, W1≤H, and the transparency and visual effects are better.

[0053] When D≤0, H≤W1≤|D|. When D≤0, corresponding to grid or shingle stacking, problems such as hidden cracks are more likely to occur at the stacking locations of adjacent cells. The stacking locations of adjacent cells are usually at the edge of the cells, so fewer holes are set up at the stacking locations of adjacent cells. Therefore, when H≤W1, the risk of hidden cracks at the stacking locations of adjacent cells can be avoided. At the same time, when W1≤|D|, the transparency and visual effects are better.

[0054] A fourth aspect of the present invention provides a photovoltaic device comprising: a plurality of any of the aforementioned battery strings.

[0055] The above-mentioned silicon wafers, battery cells, battery strings and photovoltaic devices have the same or similar beneficial effects, and to avoid repetition, they are not described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 A schematic diagram of the first surface structure of a first silicon wafer according to an embodiment of the present invention is shown;

[0058] Figures 2 to 6 Schematic diagrams of partial cross-sectional structures of five silicon wafers in an embodiment of the present invention are shown;

[0059] Figure 7 A schematic diagram of the first surface structure of a second silicon wafer according to an embodiment of the present invention is shown;

[0060] Figure 8 A schematic diagram of a partially enlarged structure of a battery cell in an embodiment of the present invention is shown when viewed from above or below.

[0061] Description of the accompanying figures:

[0062] 1-silicon wafer, 11-hole structure, 12-first surface, 13-second surface, 111-first textured area, 112-continuous flat area, 113-second textured area, 21-gate line electrode. DETAILED DESCRIPTION

[0063] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0064] The present invention provides a silicon wafer having a plurality of hole structures 11 disposed therein. The number of hole structures 11 in the silicon wafer is not limited. The silicon wafer includes: a first surface and a second surface opposite to each other along its thickness direction; of the first surface and the second surface, one is the light-facing side of the silicon wafer and the other is the backlight side of the silicon wafer. For example, the first surface can be the light-facing side of the silicon wafer and the second surface is the backlight side of the silicon wafer; or, the first surface can be the backlight side of the silicon wafer and the second surface is the light-facing side of the silicon wafer. The thickness of the silicon wafer is usually smaller than the length and width of the silicon wafer, so the dimensions of the light-facing side and the backlight side are usually larger than the dimensions of the other surfaces. In a cell or photovoltaic device, during its normal operation, the light-facing side of the silicon wafer mainly receives light, and the light-facing side and the backlight side are opposite to each other. Among the above-mentioned plurality of hole structures: at least some of the hole structures 11 are through-hole structures, and the through-hole structures connect the first surface 12 and the second surface 13. And / or, among the aforementioned plurality of hole structures: at least some of the hole structures 11 are blind hole structures, extending from the first surface 12 into the silicon substrate. All hole structures in the silicon wafer may be through hole structures, or all hole structures in the silicon wafer may be blind hole structures, or some of the hole structures in the silicon wafer may be through hole structures and others may be blind hole structures.

[0065] For example, refer to Figure 2 、 Figure 3 and Figure 4 The hole structures 11 are all through-hole structures connecting the first surface 12 and the second surface 13. For each through-hole structure, its pore size B1 on the first surface 12 is greater than or equal to its pore size B2 on the second surface 13, or, for any through-hole structure, its pore size on the first surface 12 is greater than or equal to the pore size of any through-hole structure on the second surface 13. For example, Figure 2 、 Figure 4 In the embodiment, the aperture of the through-hole structure on the first surface 12 is larger than the aperture of the through-hole structure on the second surface 13; Figure 3 In the embodiment, the aperture of the through hole structure on the first surface 12 is equal to the aperture of the through hole structure on the second surface 13. Figure 5 and Figure 6 The hole structure 11 is a blind hole structure extending from the first surface 12 into the silicon wafer 1 . In this case, the hole structure 11 does not extend into the second surface.

[0066] It should be noted that the overall extension direction of the hole structure 11 can be along the thickness direction E of the silicon wafer, but it is allowed to bend or bend in other directions. In this application, when the pore size of the hole structure on the first surface 12 is equal to the pore size on the second surface 13, the pore size of the portion between the first surface 12 and the second surface 13 in the hole structure is not limited to be equal to the pore size of the first surface 12 and the pore size of the second surface 13. Figure 3Equal, or not equal. In this application, the term "equal" includes: equal, or approximately equal within a certain error range, where the error range means that the absolute value of the difference between the two does not exceed 10% of any of the comparison objects. For example, the aforementioned Figure 3 In the embodiment, the pore size of the pore structure on the first surface 12 is equal to the pore size of the pore structure on the second surface 13, which may include the pore size of the first surface 12 being equal to the pore size of the pore structure on the second surface 13, and may also include the absolute value of the difference between the pore size of the pore structure on the first surface 12 and the pore size of the pore structure on the second surface 13 being less than or equal to 10% of the pore size of the first surface 12 or 10% of the pore size of the second surface 13.

[0067] Reference Figure 1 、 Figure 7 and Figure 8 , the edge area of ​​the first surface 12 is not provided with a hole structure 11; the first surface includes: a first side and a second side, the length of the first side is L1, the length of the second side is L2, L1 ≥ L2, refer to Figure 1 and Figure 8 , L1>L2, the first surface 12 is rectangular or substantially rectangular, refer to Figure 7 , L1=L2, the first surface 12 is square or substantially square. The edge region includes: a first edge region and a second edge region that intersect and are distributed. The first edge region is arranged along the first side, and the extension direction of the first edge region can be considered to be substantially parallel to the first side; the second edge region is arranged along the second side, and the extension direction of the second edge region can be considered to be substantially parallel to the second side.

[0068] Reference Figure 1 , the width of the first edge area is W1, and the direction of the width of the first edge area is perpendicular to the extension direction of the first side. It should be noted that the width of the first edge area refers to: the distance between the hole boundary of the hole structure 11 adjacent to the first side and the first side. When the hole boundaries of the hole structures 11 adjacent to the first side are close to the hole boundaries of the first side and are evenly distributed along the extension direction of the first side, W1 here is the distance between the hole boundary of any one of the hole structures 11 adjacent to the first side and the first side; when the hole boundaries of the hole structures 11 adjacent to the first side are close to the hole boundaries of the first side and are staggered along the extension direction of the first side: W1 here is the average value of the distances between the hole boundaries of the multiple hole structures 11 adjacent to the first side and the first side, and the multiple means greater than or equal to 2, or, W1 here is the distance between the hole boundary of the outermost hole structure 11 adjacent to the first side and the first side. The method of determining W1 here includes but is not limited to the method of the above example.

[0069] The thickness of the silicon wafer is H. If the thickness of the silicon wafer is uniform, the thickness H of the silicon wafer can be the dimension from any point on one of the aforementioned opposing first and second surfaces of the silicon wafer to a corresponding position on the other of the opposing first and second surfaces. If the thickness of the silicon wafer is non-uniform, the thickness H of the silicon wafer can be the average of the dimensions from multiple points on one of the opposing first and second surfaces to corresponding positions on the other of the opposing first and second surfaces, where "multiple" here means greater than or equal to 2. Alternatively, the thickness H of the silicon wafer can be the dimension from any point on one of the opposing first and second surfaces of the silicon wafer to a corresponding position on the other of the opposing first and second surfaces, where a corresponding position here means that the orthographic projections coincide along the thickness direction of the silicon wafer. Methods for determining H here include, but are not limited to, the methods described in the examples above.

[0070] In the related art, the main reason why transparent or translucent photovoltaic products have poor mechanical strength due to the openings in the substrate is that: in the related art, the edges of the substrates of transparent or translucent photovoltaic products do not have blank areas without openings; or, although the edges of the substrates of transparent or translucent photovoltaic products have blank areas without openings, the size of the blank areas does not take into account the different surfaces, long and short sides, thickness of the substrate and the relationship between the materials, resulting in poor mechanical strength of the substrate.

[0071] In response to the above technical problems, for silicon materials, the silicon wafer provided in this application has a W1 / H of 0.05≤40. First, for silicon wafers with a hole structure, breakage or cracking is more likely to occur in the first edge region of the first surface containing the first side (longer side). Therefore, in this application, the width of the first edge region in the first surface is focused on. Second, the H of the silicon wafer is within a certain range: when H is small, the toughness of the silicon wafer with a hole structure is improved, and the brittleness of the silicon wafer with a hole structure is reduced. When H is large, the toughness of the silicon wafer with a hole structure is reduced, and the brittleness of the silicon wafer with a hole structure is reduced. The brittleness of the silicon wafer increases. When the toughness of the silicon wafer with the hole structure is high, the probability of its cracking or breaking will also decrease. That is to say, within a certain range, the H of the silicon wafer has a significant correlation with the probability of cracking or breaking of the silicon wafer with the hole structure, and the H of the silicon wafer also has an important correlation with the electrical effect. Taking the above-mentioned first and second factors into consideration, when the width W1 of the first edge area in the first surface is less than 0.05H, W1 is too small, the hole structure in the first surface is too close to the first side, and the risk of the silicon wafer in the first edge area of ​​the first surface of the silicon wafer containing the first side is relatively high. High, at the same time, relative to W1, the thickness H of the silicon wafer is too large. The selection of too thick silicon wafer will lead to excessive electrical loss in the body region and excessive side loss, resulting in a significant decrease in photoelectric conversion efficiency. Moreover, when W1 is less than 0.05H, W1 is too small, the processing parameters of the hole structure are difficult to guarantee, and the yield of the hole structure is also low. Therefore, 0.05H≤W1, the width of W1 is suitable, and the first edge area of ​​the first surface of the silicon wafer including the first side of the silicon wafer has basically no risk of breakage or cracking, which significantly improves the mechanical strength of the silicon wafer with the hole structure, and the yield of the hole structure is high, which is easy to achieve mass production, and can To ensure the photovoltaic conversion efficiency of the cell; Taking into account the factors of the first and second aspects above, when the width W1 of the first edge region in the first surface is greater than 40H, W1 is too large, the hole structure in the first surface is too far from the edge of the silicon wafer, and the transparency and visual effects are poor. In addition, the thickness H of the silicon wafer is too small relative to W1, and the mechanical strength and electrical effects of the silicon wafer are also difficult to ensure. Therefore, in this application, W1≤40H is the result of an optimized balance after combining multiple factors such as transparency, visual effect, mechanical strength and electrical effects of the silicon wafer. Not only is the transparency and visual effect good, the mechanical strength of the silicon wafer is high, but also the electrical effect is good. Furthermore, in the silicon wafer provided in this application, 0.5≤W1 / H≤20.

[0072] To sum up, the present application, firstly, significantly reduces the risk of cracking or breaking of a silicon wafer with a hole structure, especially reduces the risk of cracking or breaking of the first edge area in the first surface of the silicon wafer with a hole structure, and improves the mechanical strength; secondly, ensures good transparency, visual effect and yield, and is easy to achieve mass production; thirdly, in the through-hole structure, when the aperture of the hole structure in the first surface is larger than the aperture of the hole structure in the second surface, there is an angle between the hole wall of the through-hole and the thickness direction of the silicon wafer, and the through-hole structure is a tapered through-hole; or, when the angle between the hole wall of the blind hole and the thickness direction of the silicon wafer is small, the blind hole structure is a tapered blind hole; for tapered through holes and tapered blind holes, when the angle here is small, the hole wall is close to being parallel to the thickness direction of the silicon wafer. After the light shines on one side of the hole wall, the light is reflected more in the hole, which can increase the light transmission path. For tapered through holes and tapered blind holes, during the actual installation of the solar cells, due to the longitude and latitude of the installation site, the solar cells are usually tilted. One side of the hole wall of the tapered through hole or tapered blind hole can be close to perpendicular to the light, greatly increasing the light receiving area of ​​the silicon wafer or solar cell, increasing the light absorption rate, and improving the electrical efficiency. Therefore, this application ensures a good electrical effect; fourthly, it avoids removing too much silicon material to cause insufficient absorption, ensuring high photoelectric conversion efficiency. In addition, when the hole structure is a through hole structure, it can achieve a larger field of view from the second surface and a smaller field of view from the first surface, or the effect of obtaining different fields of view from different surfaces. The photovoltaic product corresponding to the silicon wafer can be used in application scenarios where different fields of view are obtained from different surfaces, expanding the application scenarios of photovoltaic products. Since the blind hole structure does not penetrate the silicon wafer, the side opposite to the first surface of the silicon wafer still has good mechanical strength. At the same time, due to the presence of the hole structure, the transmittance or transmittance can also be increased, which can still improve the visual effect.

[0073] For example, in the silicon wafer provided in the present application, W1 / H can be 0.05, 0.08, 0.1, 0.3, 0.5, 0.9, 1, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 7, 8, 8.5, 9, 10, 11, 12, 12.5, 15, 16, 16.5, 18, 19.5, 20, 22, 25, 30, 35, 37, or 40.

[0074] It should be noted that, in the present application, the first surface 12 can be the light-facing surface or the backlight surface of the silicon wafer, and there is no specific limitation on this. The visual effects mentioned in the present application may include: anti-glare, anti-peeping, transparency, etc.

[0075] In some possible embodiments of the present application, the width of the second edge area is W2; 1≤(W1 / W2)≤(L1 / L2), where W2 is determined in the same or similar manner as W1, and will not be described again to avoid repetition.

[0076] Specifically, the greater the difference between L1 and L2, the greater the length of the first side of the first surface of the silicon wafer with the hole structure, the greater the length of the second side. In this case, the first edge region of the first surface containing the first side is more likely to crack or break, while the probability of the second edge region of the first surface containing a portion of the second side cracking or breaking may be relatively smaller. Therefore, W1 ≥ W2, reducing the risk of the first edge region of the first surface containing the first side cracking or breaking. However, when (W1 / W2) > (L1 / L2), the width of the first edge region of the first surface containing the first side is much greater than the width of the second edge region containing a portion of the second side. The probability of the first edge region containing the first side cracking or breaking is already very small, and the hole structure is too far from the edge of the silicon wafer, resulting in a decrease in transparency and visual effects. Therefore, in the present application, when L1 ≥ L2, the width of the second edge region is W2; 1 ≤ (W1 / W2) ≤ (L1 / L2), not only reducing the risk of cracking or breaking in the first edge region of the first surface containing the first side, but also improving mechanical strength, but also ensuring good transparency and visual effects.

[0077] It should be noted that, in the case where L1 ≥ 4L2, L1 / L2 ≥ 4. Therefore, in this case, the ratio of W1 / W2 can be considered to be roughly between 1 and 4, or greater than 4. For another example, the ratio of W1 / W2 can range from 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.2, 4.5, 4.8, 5, 5.5, 6, etc. In some embodiments, the silicon wafer can be a rectangular wafer, in which case L1>L2, or it can be a square wafer, in which case L1=L2. When the silicon wafer is rectangular, W1 / W2 can be determined based on the ratio of L1 / L2. When the silicon wafer is square, W1 / W2 can be 1.

[0078] In some possible embodiments of the present application, refer to Figure 2 、 Figure 3 and Figure 4 In the case where the hole structure 11 is a through-hole structure connecting the first surface 12 and the second surface 13: the second surface 13 is the surface of the silicon wafer along the thickness direction E of the through-hole structure with the smaller aperture of the first surface and the second surface. On the first surface 12, the aperture of the through-hole structure is B1; on the second surface 13, the aperture of the through-hole structure is B2; 0.5≤(B1-B2)÷(H×tan(θ / 2))≤1, or, 0.5≤(B1-B2)÷(B1 / 2)≤1. For the same through-hole structure, θ is the angle between the line connecting the aperture starting point of the through-hole structure on the first surface 12 and the center of the through-hole structure on the second surface 13, and the line connecting the aperture ending point of the through-hole structure on the first surface 12 and the center of the through-hole structure on the second surface 13.

[0079] Specifically, Figure 2 In the figure, the dotted line F extending in the up-down direction is Figure 2 In the cross section shown in the silicon wafer, the center line of the through-hole structure in the second surface 13. The aperture B1 of the through-hole structure in the first surface 12, the aperture B2 of the through-hole structure in the second surface 13, and the thickness H of the silicon wafer are all related to the transmittance or transparency. For example, when viewed from the first surface 12 to the second surface 13, the larger B2 is, the greater the transmittance or transparency is. However, when the θ or B1 / 2 is set to be large, the transmittance or transparency will decrease when viewed from the first surface 12 to the second surface 13. Therefore, 0.5≤(B1-B2)÷(H×tan(θ / 2))≤1, or 0.5≤(B1-B2)÷(B1 / 2)≤1 can ensure that the transmittance of the battery cell prepared using the silicon wafer can be maintained at 50% or more of the designed transmittance when viewed from the first surface 12 to the second surface 13, with better transmittance and better visual effect. The shape of the through-hole structure is not limited here. For example, Figure 2 In the embodiment, the cross-section of the through-hole structure along the thickness direction of the silicon wafer is a trapezoidal structure.

[0080] It should be noted that, on a surface, the aperture of a through-hole structure or a hole structure refers to: the distance between the two boundaries of the through-hole structure or hole structure that are farther apart along the direction of the longer side of the surface; or the distance between the two boundaries of the through-hole structure or hole structure that are farther apart along the direction of the shorter side of the surface; or the larger of the two distances, the distance between the two boundaries of the through-hole structure or hole structure that are farther apart along the direction of the shorter side of the surface and the distance between the two boundaries of the through-hole structure or hole structure that are farther apart along the direction of the longer side of the surface. On a surface, the starting point and end point of the aperture of a through-hole structure or hole structure refer to: the two boundaries of the through-hole structure or hole structure that are farther apart along the direction of the longer side of the surface; or the two boundaries of the through-hole structure or hole structure that are farther apart along the direction of the shorter side of the surface. For the blind hole structure, the method for determining the aperture of the hole structure in the first surface 12, and the method for determining the starting point and end point of the aperture of the hole structure are the same or similar to the method for determining the aperture of the through hole structure in the first surface 12 here, and the method for determining the starting point and end point of the aperture of the through hole structure, and will not be repeated here.

[0081] For example, (B1-B2)÷(B1 / 2) can be 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1.

[0082] In some possible embodiments of the present application, refer to Figure 4 、 Figure 5 and Figure 6 , in the first surface 12, the aperture of the hole structure 11 is B1; the aperture of the hole structure at the position of the center line of the thickness direction of the silicon wafer 1 is B3; B1 ≥ B3; 0.1 ≤ (B1-B3) ÷ (H / 2) ≤ 50. The position of the center line of the thickness direction of the silicon wafer 1 refers to: the position of half the thickness of the silicon wafer. The relationship for the hole structure 11 is Figure 2 、 Figure 3 、 Figure 4 The through hole structure and the hole structure 11 are Figure 5 、 Figure 6 The blind hole structure in the embodiment is applicable to the embodiment of the present invention, wherein the blind hole structure here extends from the first surface 12 to at least half of the thickness of the silicon wafer.

[0083] Specifically, (B1-B3)÷(H / 2) can characterize the average decreasing slope or rate of the aperture of the hole structure 11 along the extension direction of the hole structure (i.e., the thickness direction of the silicon wafer) starting from the first surface 12. If this value is less than 0.1, it means that the average decreasing slope or rate of the aperture of the hole structure 11 is too small, and the hole structure 11 tends to have a constant aperture size, and the improvement in the visual effect is not obvious enough. If this value is greater than 50, it means that the average decreasing slope or rate of the aperture of the hole structure 11 is too large or too fast, and the process parameters for forming the hole structure 11 may not be easy to control, and it is not easy to achieve mass production. The process window for forming the hole structure 11 is narrow, and the yield is low. Therefore, in this application, the value is between 0.1 and 50, which ensures a more obvious visual effect, is easy to achieve mass production, and has a high yield. At the same time, (B1-B3)÷(H / 2) can characterize the angle between the hole wall of the hole structure and the thickness direction of the silicon wafer. When 0.1≤(B1-B3)÷(H / 2)≤50, there is an angle between the hole wall of the hole structure and the thickness direction of the silicon wafer. The hole structure is a conical hole structure. When the angle is small, the hole wall is close to being parallel to the thickness direction of the silicon wafer. After the light hits one side of the hole wall, the light is reflected more in the hole, which can increase the light transmission path. During the actual installation of the battery cell, due to the longitude and latitude of the installation site, the battery cell is usually tilted. One side of the hole wall of the conical hole structure can be close to perpendicular to the light, which greatly increases the light receiving area of ​​the silicon wafer or battery cell, increases the light absorption rate, and improves the electrical efficiency. Therefore, the present application ensures a good electrical effect. Furthermore, the value can also be around 1 to 25.

[0084] For example, (B1-B3)÷(H / 2) can be 0.1, 0.5, 0.9, 1, 1.5, 3, 5, 8, 10, 12, 15, 19, 20, 22, 25, 29, 30, 35, 40, 42, 45, 48, or 50.

[0085] In some possible embodiments of the present application, B3 is 1 μm (micrometer) to 100 μm. B3 is a choice based on the commonly used sizes of silicon wafers in current battery cells, combined with visual and mechanical effects. It can not only achieve good visual effects, but also obtain better mechanical strength.

[0086] For example, B3 can be 1μm, 1.5μm, 3μm, 5μm, 10μm, 15μm, 18μm, 20μm, 23μm, 25μm, 30μm, 35μm, 40μm m, 45μm, 50μm, 50.5μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm.

[0087] In some possible embodiments of the present application, refer to Figure 7 The cross-sectional profile of the hole structure 11 on the first surface 12 includes: an arc segment; the closer to the center of the first surface 12, the closer the cross-sectional profile of the hole structure 11 on the first surface 12 is to a circle, that is, the farther away from the center of the first surface 12, the closer the cross-sectional profile of the hole structure 11 on the first surface 12 is to a non-circular shape; the farther away from the center of the first surface 12, the closer it is to the aforementioned edge area. Since the aforementioned edge area does not have a hole structure, the visual effect is inferior to that of the position where the hole structure is set. By setting a hole structure 11 with a cross-sectional profile close to a non-circular shape at a position close to the aforementioned edge area, it is helpful to offset the problem of inconsistent visual effects caused by the edge area. It should be noted that burrs may exist on the boundary line of the circle here.

[0088] In some possible embodiments of the present application, the pore size B1 of the hole structure 11 on the first surface 12 is 10 μm to 500 μm. B1 is a commonly used size of current battery cells or silicon wafers. The combination of visual effects and mechanical effects can not only achieve good visual effects, but also obtain better mechanical strength.

[0089] For example, B1 may be 10 μm, 15 μm, 30 μm, 50 μm, 100 μm, 150 μm, 180 μm, 200 μm, 230 μm, 250 μm, 255 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm.

[0090] In some possible embodiments of the present application, when the hole structure 11 is a through-hole structure extending from the first surface 12 to the second surface 13, the hole diameter B2 on the second surface 13 is 10 μm to 500 μm. B2 is selected based on the commonly used dimensions of current solar cells or silicon wafers, taking into account both visual and mechanical effects. This not only achieves a good visual effect but also provides good mechanical strength. Here, B2 ≤ B1.

[0091] For example, B2 can be 10 μm, 15 μm, 30 μm, 50 μm, 100 μm, 150 μm, 180 μm, 200 μm, 230 μm, 250 μm, 255 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm.

[0092] In some possible embodiments of the present application, the spacing A between adjacent hole structures 11 is 1 μm to 500 μm. The spacing A between adjacent hole structures 11 may refer to the spacing between the centers of adjacent hole structures 11 on the first surface 12, which may include the spacing A1 between the centers of adjacent hole structures 11 on the first surface 12 along the extension direction of the first side, and may also include the spacing A2 between the centers of adjacent hole structures 11 on the first surface 12 along the extension direction of the second side. In the case where the hole structure 11 is a through-hole structure, the spacing A between adjacent hole structures 11 may also include the spacing between the centers of adjacent hole structures 11 on the second surface 13, which may include the spacing between the centers of adjacent hole structures 11 on the second surface 13 along the extension direction of the first side, and may also include the spacing between the centers of adjacent hole structures 11 on the second surface 13 along the extension direction of the second side. Alternatively, the spacing A between adjacent hole structures 11 may refer to half the spacing between the boundary of one end of two adjacent hole structures 11 and the boundary of the other end of the other hole structure 11 on the first surface 12, which may be included along the extension direction of the first side of the first surface 12; or, the spacing A between adjacent hole structures 11 may refer to half the spacing between the boundary of one end of two adjacent hole structures 11 and the boundary of the other end of the other hole structure 11 on the first surface 12, which may be included along the extension direction of the second side of the first surface 12. In the case where the hole structure 11 is a through-hole structure, the spacing A between the adjacent hole structures 11 may also include the corresponding parameters on the second surface, which will not be repeated here. For different surfaces and different directions, the spacing between the centers of adjacent hole structures 11 can refer to a spacing between the centers of any two adjacent hole structures 11 on the same surface and in the same direction, or the average value of the spacings corresponding to any multiple adjacent hole structures 11 on the same surface and in the same direction, where the multiple refers to 2 or more.Alternatively, the spacing A between adjacent hole structures 11 may refer to half of the spacing between the boundary of one end of two adjacent hole structures 11 and the boundary of the other end of the other hole structure 11 on the first surface 12, which may be included on the first surface 12 along the extension direction of the first side, or the average value of multiple halves, where multiple refers to two or more; or, the spacing A between adjacent hole structures 11 may refer to half of the spacing between the boundary of one end of two adjacent hole structures 11 and the boundary of the other end of the other hole structure 11 on the first surface 12 along the extension direction of the second side, or the average value of multiple halves, where multiple refers to two or more. In the case where the hole structure 11 is a through-hole structure, the spacing A between the adjacent hole structures 11 may also include the corresponding parameters on the second surface, which will not be repeated here. The spacing A between adjacent hole structures 11 is less than 1 μm, the distribution density of the hole structures 11 is large, the mechanical strength of the silicon wafer may not be easy to guarantee, and the processing accuracy of the hole structure 11 and other process yields are difficult to control, and the yield is low; the spacing A between adjacent hole structures 11 is greater than 500 μm, the distribution density of the hole structure 11 is small, the transmittance or transparency is not easy to guarantee, and the visual effect may be poor. Therefore, in this application, the spacing A between adjacent hole structures is 1 μm to 500 μm, which not only ensures the mechanical strength of the silicon wafer and the yield of mass production, but also balances the transmittance or transparency and visual effect.

[0093] For example, A can be 1 μm, 10 μm, 15 μm, 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 190 μm, 200 μm, 230 μm, 250 μm, 255 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm.

[0094] In some possible embodiments of the present application, the cross-sectional shape of the hole structure 11 along the thickness direction E of the silicon wafer includes at least one of a rectangle, a trapezoid, and a waist shape. The cross-sectional shape of the hole structure 11 is easy to prepare and has flexible and diverse visual effects. For example, Figure 2 In the figure, the cross-section of the hole structure 11 along the thickness direction E of the silicon wafer is a trapezoid. When viewed from the first surface 12 to the second surface 13, the visual field decreases, while when viewed from the second surface 13 to the first surface 12, the visual field increases. The photovoltaic products corresponding to the silicon wafer of this shape can be used in scenes such as car windows. The second surface 13 can be set close to the inside of the car, and the first surface 12 can be set close to the outside of the car. This can not only increase the field of view inside the car, but also prevent people from outside the car from peeping into the car, and improve the privacy effect inside the car. For another example, Figure 2 The photovoltaic product corresponding to the silicon wafer of this shape is applied in scenes such as carports. The second surface 13 can be set close to the ground and the first surface 12 can be set away from the ground to increase the field of view in the carport. Figure 3 In the figure, the cross-section of the hole structure along the thickness direction of the silicon wafer is waist-shaped, and the aperture of the hole structure in the first surface 12 and the second surface 13 is the same. The photovoltaic products corresponding to the silicon wafer of this shape can be used in scenes with roughly the same visual effects when viewed from the first surface 12 and the second surface 13.

[0095] In some possible embodiments of the present application, the width W1 of the first edge region is 0.005mm (millimeter) to 10mm. If W1 is less than 0.005mm, W1 is too small, the hole structure in the first surface is too close to the first edge, and the risk of the silicon wafer being broken or cracked in the first edge region of the first surface of the silicon wafer containing the first edge is high, and the processing accuracy of the hole structure is difficult to ensure, and the yield is low. If W1 is greater than 10mm, W1 is too large, the hole structure in the first surface is too far away from the edge of the silicon wafer, and the transparency and visual effects are poor. Therefore, in the present application, W1 is 0.005mm to 10mm, which significantly reduces the risk of cracking or breaking of the silicon wafer with the hole structure, especially reduces the risk of cracking or breaking of the first edge region in the first surface of the silicon wafer with the hole structure, improves the mechanical strength, and ensures good transparency and visual effects. Further, W1 can be 0.2mm to 4mm, and further, W1 can be 0.5mm to 1mm.

[0096] For example, W1 is 0.005mm, 0.008mm, 0.009mm, 0.01mm, 0.012mm, 0.02mm, 0.05mm, 0.08mm, 0.09mm, 0.1mm, 0.12mm, 0.15mm, 0.18mm, 0.2mm, 0.4mm, 0.5mm, 0.6mm, 0.8mm, 0 .9mm, 1mm, 1.2mm, 1.5mm, 1.8mm, 1.9mm, 2mm, 2.2mm, 2.5mm, 2.8mm, 3mm, 3.22mm, 3.5mm, 3.6mm, 3.9mm, 4mm, 4.5mm, 5mm, 6mm, 7mm, 7.5mm, 8mm, 8.5mm, 9mm, 10mm.

[0097] In some possible embodiments of the present application, the thickness H of the silicon wafer is 2μm to 200μm. If H is less than 2μm, the thickness of the silicon wafer is too thin, and the mechanical strength and electrical effects of the silicon wafer are difficult to guarantee. If H is greater than 200μm, the thickness H of the silicon wafer is too large, and there may be material waste on the silicon wafer. Moreover, the silicon wafer is too thick and brittle, and is prone to mechanical problems such as hidden cracks. Therefore, in the present application, the thickness H of the silicon wafer is 2μm to 200μm, and H is less than 2μm. This can ensure the mechanical strength and electrical effects of the silicon wafer and avoid material waste, and has good mechanical properties.

[0098] For example, H is 2 μm, 4 μm, 5 μm, 8 μm, 9 μm, 10 μm, 20 μm, 50 μm, 60 μm, 80 μm, 100 μm, 120 μm, 150 μm, 170 μm, 180 μm, and 200 μm.

[0099] In some possible embodiments of the present application, the overall transmittance of the silicon wafer can be 5% to 80%. The transmittance mentioned in this application is defined as the transmittance when the light is incident perpendicularly on the light-facing surface of the silicon wafer. For example, the transmittance can be defined as the ratio of the wattage of light that can be received by the backlight surface divided by 1000W when 1000W of light is incident perpendicularly on the light-facing surface of the silicon wafer.

[0100] The present application also provides a solar cell comprising an electrode structure and any one of the aforementioned silicon wafers. The electrode structure is used to extract current from the solar cell. The electrode structure is located on at least one opposite side of the silicon wafer along its thickness. The solar cell only needs to include any one of the aforementioned silicon wafers, and the specific cell type is not limited. For example, the solar cell may be a TOPCon (passivated contact) cell, an SHJ (heterojunction) cell, etc., without specific limitation.

[0101] It should be noted that, in this application, when determining the thickness of a silicon wafer in a cell containing the silicon wafer, the thickness of the portion of the cell excluding the electrode structure may be considered to be the thickness of the silicon wafer in the cell. Specifically, in a cell containing the silicon wafer, excluding the silicon wafer, the thickness of the remaining film layer structure is typically at the nanometer level, while the thickness H of the silicon wafer is at the hundred-micrometer level. Compared to the hundred-micrometer level, the thickness of the remaining film layer at the nanometer level is negligible. Therefore, when determining the thickness of the silicon wafer in a cell containing the silicon wafer, the thickness of the portion of the cell excluding the electrode structure may be considered to be the thickness of the silicon wafer in the cell.

[0102] In some possible embodiments of the present application, the electrode structure is staggered with the hole structure 11. Specifically, the electrode structure's electrical conductivity is severely impaired after being disconnected by the hole structure 11. Therefore, staggering the electrode structure with the hole structure 11 not only ensures the electrode structure's electrical conductivity but also avoids the problem of reduced light transmittance or transmittance caused by the electrode structure blocking the hole structure 11. Staggering the electrode structure with the hole structure may mean that all electrode structures in the cell are staggered with the hole structure.

[0103] In some possible embodiments of the present application, refer to Figure 8 The electrode structure includes: a gate electrode 21, and an array of hole structures 11 on one side of the cell where the gate electrode 21 is located. On the same side of the silicon wafer, the spacing between the gate electrode 21 and the center line between two adjacent hole columns is less than or equal to 10μm. The center line is along the extension direction of the gate electrode 21. Specifically, the gate electrode 21 here can be located on the first surface side, then the hole structure 11 is arranged in an array on the first surface side, then the spacing between the gate electrode 21 located on the first surface 12 side and the center line between the two adjacent hole columns 11 on the first surface 12 is less than or equal to 10μm; the hole structure 11 here can be a through-hole structure, and the gate electrode 21 here can also be located on the second surface side, then the hole structure 11 is arranged in an array on the second surface side, then the spacing between the gate electrode 21 located on the second surface 13 side and the center line between the two adjacent hole structure columns on the second surface 13 is less than or equal to 10μm. That is, on the same side of the silicon wafer, the gate electrode 21 and the midline between two adjacent hole structure columns are roughly or completely overlapped, which avoids the gate electrode 21 being cut off by the hole structure as much as possible, which is beneficial to the collection and transmission of carriers, ensures the conductivity of the electrode structure, and avoids the problem of reduced transmittance or transmittance caused by the gate electrode 21 blocking the hole structure 11. For example, Figure 8 In the figure, the dotted lines Y1 and Y2 represent the center lines between two adjacent hole columns. At the location of center line Y1, the gate electrode 21 and the center line Y1 between the two adjacent hole columns coincide with each other, and the spacing between them is 0. At the location of center line Y2, there is a spacing between the gate electrode 21 and the center line Y2 between the two adjacent hole columns, and the spacing between them is less than or equal to 10μm. For example, the spacing here can be 0, 0.1μm, 0.2μm, 0.5μm, 0.8μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, or 10μm.

[0104] In some possible embodiments of the present application, the electrode structure includes: a plurality of front gateline electrodes and a plurality of back gateline electrodes, wherein the front gateline electrodes are located on the light-facing side of the silicon wafer, and the back gateline electrodes are located on the backlight-receiving side of the silicon wafer. The cell is a bifacial cell having electrode structures on both sides of the silicon wafer. The hole structure 11 is a through-hole structure connecting the first surface 12 to the second surface 13. The number of hole structures 11 between adjacent front gateline electrodes on the light-facing side of the silicon wafer is greater than or equal to the number of hole structures 11 between adjacent back gateline electrodes on the backlight-receiving side of the silicon wafer. That is, in a double-sided cell, since the hole structure 11 is a through hole, the number of hole structures 11 is equal for the light-facing side and the backlight side of the silicon wafer. By setting the number of hole structures 11 between adjacent front gate line electrodes on the light-facing side of the silicon wafer to be greater than or equal to the number of hole structures 11 between adjacent back gate line electrodes on the backlight side of the silicon wafer, the sparseness of the gate lines on different sides can be set to match the different conductive requirements of the cell on the light-facing side and the backlight side, thereby expanding the application scenarios of the cell. More specifically, in the bifacial cell, since the hole structure 11 is a through hole, the number of hole structures 11 is equal for the light-facing side and the backlight side of the silicon wafer. On the light-facing side of the silicon wafer, the number of hole structures 11 between adjacent front gate line electrodes is larger, while on the backlight side of the silicon wafer, the number of hole structures 11 between adjacent back gate line electrodes is smaller. This can achieve an effect in which the front gate line electrodes on the light-facing side of the silicon wafer are sparser than the back gate line electrodes on the backlight side of the silicon wafer. The front gate line electrodes on the light-facing side of the silicon wafer are sparser, which can reduce shading; the back gate line electrodes on the backlight side of the silicon wafer are denser, which can improve the carrier collection efficiency as much as possible. Therefore, this is an optimized choice considering the carrier collection and light-facing power generation efficiency of the cell, which not only ensures the transmittance or transmittance and visual effect of the bifacial cell, but also ensures the current collection effect and light-facing power generation efficiency of the bifacial cell.

[0105] In some possible embodiments of the present application, the hole structures 11 are arranged in an array on both the light-facing and backlight-facing sides of the silicon wafer. The number of columns of hole structures 11 between adjacent front gate electrodes on the light-facing side of the silicon wafer is greater than or equal to the number of columns of hole structures 11 between adjacent back gate electrodes on the backlight side of the silicon wafer. The columns of hole structures 11 extend in a direction substantially parallel to the direction of the gate electrodes. For example, the angle between the columns of hole structures 11 and the gate electrodes is less than or equal to 10°. Specifically, in the bifacial cell, since the hole structure 11 is a through hole, the number of hole structures 11 is equal for the light-facing side and the backlight side of the silicon wafer. On the light-facing side of the silicon wafer, the number of hole structures 11 between adjacent front gate line electrodes is larger, while on the backlight side of the silicon wafer, the number of hole structures 11 between adjacent back gate line electrodes is smaller. This can achieve an effect in which the light-facing gate line electrodes on the light-facing side of the silicon wafer are sparser than the back gate line electrodes on the backlight side of the silicon wafer. The light-facing gate line electrodes on the light-facing side of the silicon wafer are sparser, which can reduce shading; the back gate line electrodes on the backlight side of the silicon wafer are denser, which can improve the carrier collection efficiency as much as possible. Therefore, this is an optimized choice considering the carrier collection and light-facing power generation efficiency of the cell, which not only ensures the transmittance or transmittance and visual effect of the bifacial cell, but also ensures the current collection effect and light-facing power generation efficiency of the bifacial cell.

[0106] The angle between the extension direction of the column of the hole structure 11 and the extension direction of the gate electrode is less than or equal to 10°, which means that the extension direction of the column of the hole structure 11 is substantially parallel to the extension direction of the gate electrode. The angle here can be, for example, 10°, 8.5°, 7°, 6°, 5.5°, 5°, 4.5°, 4°, 3°, 2°, 1°, or 0°. For example, Figure 8 In the figure, the left-right direction is the extension direction of the gate line electrode, and the extension direction of the column of the hole structure 11 is also the left-right direction, and the angle between the two can be 0°.

[0107] It should be noted that, in the present application, for bifacial cells, when the front grid line electrodes on the front side of the silicon wafer are sparser than the back grid line electrodes on the backlight side of the silicon wafer, the difference in sparseness or density between the two is not limited. For example, the difference between the two can be greater than or equal to 1, etc. For example, on the light-facing side of the silicon wafer, the number of columns of the hole structure between adjacent front grid line electrodes can be 3 columns, and on the backlight side of the silicon wafer, the number of columns of the hole structure between adjacent back grid line electrodes can be 2 columns. For another example, on the light-facing side of the silicon wafer, the number of columns of the hole structure between adjacent front grid line electrodes can be 4 columns, and on the backlight side of the silicon wafer, the number of columns of the hole structure between adjacent back grid line electrodes can be 3 columns.

[0108] In some possible embodiments of the present application, the front gateline electrodes on the light-facing side of the silicon wafer are more sparse than the back gateline electrodes on the back-facing side of the silicon wafer. The spacing between adjacent front gateline electrodes is G1, and the spacing between adjacent back gateline electrodes is G2. On the same side of the silicon wafer, along the extension direction of the gateline electrodes, the spacing between adjacent hole structures 11 is G3. That is, G3 here can be the spacing between the centers of adjacent hole structures 11 along the extension direction of the gateline electrodes, or can be one spacing between adjacent hole structures 11, or the average of multiple spacings. G3 here can be the spacing along the extension direction of the gateline electrodes within the aforementioned spacing A between adjacent hole structures. G1-G2=n×G3. G3 can be the smaller of G3 on the light-facing side of the silicon wafer and G3 on the back-facing side of the silicon wafer, or G3 can be either G3 on the light-facing side or G3 on the back-facing side of the silicon wafer. n is an integer from 1 to 10. For example, G3 here refers to the average value of multiple spacings of the hole structure on the light-facing side of the silicon wafer and the average value of multiple spacings of the hole structure on the backlight side of the silicon wafer, where multiple here means greater than or equal to 2.

[0109] Specifically, while ensuring the bifacial cell's light transmittance or transmittance, visual effects, current collection efficiency, and light-facing power generation efficiency, the size of G3 affects the bifacial cell's aesthetics, mechanical strength, and electrical performance. Limiting the relationship between G1, G2, and G3 to this equation further ensures the bifacial cell's light transmittance or transmittance, visual effects, current collection efficiency, light-facing power generation efficiency, and mechanical strength. Here, n can be 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0110] In some possible embodiments of the present application, the electrode structure includes: spaced and alternating electrode structures; the electrode structures are all located on the backlight side of the silicon wafer. This cell is a back-contact cell with an electrode structure only on the backlight side of the silicon wafer. Since there is no electrode structure on the light-facing side, it maximizes the use of incident photons, increases short-circuit current, and improves the appearance. The spacing here can prevent short circuits, and the alternation here refers to the distribution of one light-facing electrode, followed by a backlight-facing electrode, and then another light-facing electrode along a direction.

[0111] In some possible embodiments of the present application, in a battery cell, reference is made to Figure 4 and Figure 5For the same hole structure 11, along the thickness direction E of the silicon wafer, from the first surface 12 toward the interior of the wafer, the inner wall of the hole structure 11 includes, in order: a first textured region 111, a continuous flat region 112, and a second textured region 113. The surface roughness of both the first and second textured regions 111, 113 is greater than that of the continuous flat region 112. Here, at least the first textured region 111 can enhance light trapping, improving the electrical performance of photovoltaic products.

[0112] The continuous flat region 112 may or may not have a suede structure. The first suede region 111 and the second suede region 113 may have a suede structure at least partially. The surface undulations of the first suede region 111 and the second suede region 113 are both greater than the surface undulations of the continuous flat region 112. In other words, the surface topography of the first suede region 111 and the second suede region 113 is more complex than that of the flat region 112. When the first suede area 111, the second suede area 113 and the continuous flat area 112 are all provided with suede structures, the surface undulations of the first suede area 111 and the second suede area 113 are greater than the surface undulations of the continuous flat area 112. In one case, the number of convexities and / or concaveities in the area where the suede structure is provided on the first suede area 111 and the second suede area 113 may be greater than the number of convexities and / or concaveities in the area where the suede structure is provided on the continuous flat area 112; in another case, the number of convexities and / or concaveities in the area where the suede structure is provided on the first suede area 111 and the second suede area 113 may be greater than the number of convexities and / or concaveities in the area where the suede structure is provided on the continuous flat area 112. The degree of convexity and / or concavity in the area where the velvet structure is provided in the continuous flat area 112 is greater than the degree of convexity and / or concavity in the area where the velvet structure is provided; in another case, the convexity and / or concavity arrangement of the first velvet area 111 and the second velvet area 113 may be more disorderly than the convexity and / or concavity arrangement of the area where the velvet structure is provided in the continuous flat area 112; in another case, the convexity height and / or concavity depth of the area where the velvet structure is provided in the first velvet area 111 and the second velvet area 113 may be greater than the convexity height and / or concavity depth of the area where the velvet structure is provided in the continuous flat area 112. The morphology of the area where the velvet structure is provided on the first velvet area 111 and the second velvet area 113 is more complex. The above-mentioned velvet structure may be a pyramid structure, which may be a positive pyramid structure or an inverted pyramid structure, and there is no specific limitation on this.

[0113] It should be noted that for through-hole structures, the second suede region 113 is located near the second surface, while for blind-hole structures, the second suede region 113 is located at a position where the blind hole is away from the first surface. The boundary between the first suede region 111 and the continuous flat region 112 can be located at a location where the surface undulation changes significantly on the side close to the first surface. The boundary between the second suede region 113 and the continuous flat region 112 can be located at a location where the surface undulation changes significantly on the side away from the first surface.

[0114] In some possible embodiments of the present application, in a solar cell, at least a portion of the first surface 12 is provided with a first velvet structure, and at least a portion of the first velvet region 111 is provided with a second velvet structure. The first velvet structure and the second velvet structure have different sizes, where the sizes may refer to the bottom size of the velvet structure, the height of the velvet structure, etc. The first velvet region is located at the junction of the hole structure and the first surface. Since the hole structure extends along the depth direction of the silicon wafer, there is usually a corner at this location, and therefore the risk of hidden cracks is greater. The first velvet region 111 eliminates corner burrs and surface cracks by providing a velvet structure, reduces the initial crack density, releases stress, reduces the risk of hidden cracks, and improves the mechanical strength at this location. The first velvet structure may be provided on all or part of the first surface 12. When the first velvet structure is provided on part of the first surface 12, the relative size of the area provided with the first velvet structure is not limited. The second suede structure is provided in the entire area or part of the first suede area 111. When the second suede structure is provided in part of the first suede area 111, the relative size of the area provided with the second suede structure is not limited.

[0115] In some possible embodiments of the present application, in the battery cell, reference Figure 4 、 Figure 5 and Figure 6 At least one of the first velvet area 111 and the second velvet area 113 is an arc-shaped velvet area; the curvature radius at any position of the arc-shaped velvet area is R, 200μm≥R≥1μm. Specifically, since the extension direction of the hole structure is along the depth direction of the silicon wafer, there are usually corners in the first velvet area 111 and the second velvet area 113, so the risk of hidden cracks here is relatively high. By setting the first velvet area 111 and the second velvet area 113 in an arc shape, corner burrs and surface cracks can be eliminated, the initial crack density can be reduced, stress can be released, the risk of hidden cracks can be reduced, and the mechanical strength at this position can be improved. When the curvature radius R is within the above range, the process is easy to implement, the yield is high, and mass production is easy to achieve.

[0116] For example, the aforementioned R may be 1 μm, 1.5 μm, 3 μm, 5 μm, 10 μm, 15 μm, 18 μm, 20 μm, 23 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 50.5 μm, 55 μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 120μm, 130μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm.

[0117] In some possible embodiments of the present application, in the battery cell, reference Figure 4 , along the direction from the first surface 12 into the silicon wafer 1: the length C1 of the continuous flat area 112 accounts for a ratio greater than or equal to 4% of the length C2 of the inner wall of the hole structure. The continuous flat area 112 is usually less likely to be exposed to light. This ratio is within the above range, which is easy to process, has a high yield, and has good electrical effects. For example, the ratio can be: 4%, 4.5%, 5%, 8%, 10%, 12%, 14%, 15%, 20%, 22%, 25%, 28%, 30%. It should be noted that C2 here is the sum of the length of the first velvet area 111, the length C1 of the continuous flat area 112, and the length of the second velvet area 113 along the direction from the first surface 12 into the silicon wafer 1.

[0118] In some possible embodiments of the present application, in the battery cell, reference Figure 4 、 Figure 5 and Figure 6 The angle β between the continuous flat region 112 and the base plane perpendicular to the thickness direction of the silicon substrate is 75°≥β≥25°. When β is within this range, the probability of the continuous flat region 112 receiving light can be increased, thereby improving the optical path within the silicon wafer, improving the electrical performance of photovoltaic products, and increasing the yield of the hole structure. For example, β can be 75°, 70°, 65°, 60°, 55°, 50°, 45°, 40°, 35°, 30°, 25°, or 20°.

[0119] In some possible embodiments of the present application, in the cell, (H / 2)×cosβ≥C2≥50×(H / 2)×cosβ, and the relationship between β, H, and C2 is limited to this range. This can not only increase the probability of the continuous flat area 112 receiving light, but also improve the optical path within the silicon wafer, improve the electrical performance of the photovoltaic product, but also increase the mechanical strength of the silicon wafer.

[0120] The present application also provides a battery string, which is formed by sequentially connecting a plurality of any of the aforementioned battery cells in series and / or in parallel. The battery string may further include an interconnection member electrically connecting the positive electrode of the preceding battery cell with the negative electrode of the succeeding battery cell along the extension direction of the battery string. The interconnection member may be a conductive backplane, a soldering ribbon, or the like.

[0121] In some possible embodiments of the present application, along the extension direction of the battery string, the spacing between adjacent battery cells is D; when D>H, H≤W1≤0.5D; when H≥D>0, 0.5H≤W1≤H; when D≤0, H≤W1≤|D|.

[0122] Specifically, when D>H, H≤W1, the silicon wafer in the first edge area including the first edge on the first surface of the silicon wafer or battery cell has basically no risk of breakage or cracking, which significantly improves the mechanical strength of the silicon wafer with a hole structure; at the same time, when D>H, it means that the spacing between the battery cells is positive and has a large cell spacing. In this case, the position where the spacing D is located appears as a black edge during the operation of the battery string or photovoltaic product, and the visual effect of the position where the spacing D is located is poor. At the same time, the width of the first edge area in the first surface of the silicon wafer or battery cell is too large, and its visual effect is also poor. When W1≤0.5D, the visual effect of the cell spacing can be blurred by the first edge area, which can improve the visual effect of the silicon wafer or battery string at and near the spacing, thereby improving the appearance. In summary, when D>H and H≤W1≤0.5D, the first edge region of the first surface of the silicon wafer or solar cell, including the first side, is essentially free of the risk of chipping or cracking. This significantly improves the mechanical strength of the silicon wafer with the hole structure. Furthermore, the first edge region can blur the visual effect of the wafer spacing, enhancing the visual effect of the silicon wafer or solar cell string at and near the spacing, and improving the appearance. It should be noted that when D>H, D is approximately 1mm to 2mm.

[0123] When H≥D>0, 0.5H≤W1, the first edge region of the first surface of the silicon wafer or solar cell, including the first side, is substantially free of the risk of chipping or cracking, significantly improving the mechanical strength of the silicon wafer with the hole structure. Furthermore, when H≥D>0, D in the cell string is small, indicating close packing, and W1≤H, resulting in better transparency and visual effects. For example, W1 can be 0.5H, 0.55H, 0.6H, 0.65H, 0.7H, 0.75H, 0.8H, 0.85H, 0.9H, 0.95H, or H.

[0124] When D≤0, corresponding to stacked grids or stacked tiles, problems such as hidden cracks are more likely to occur at the stacking position of adjacent battery cells. The stacking position of adjacent battery cells is usually the edge area of ​​the battery cell, so fewer hole structures are set at the stacking position of adjacent battery cells. Therefore, H≤W1 here can avoid the risk of hidden cracks at the stacking position of adjacent battery cells; at the same time, W1≤|D|, the transparency and visual effects are better.

[0125] The present application also provides a photovoltaic device comprising any of the aforementioned battery strings. The photovoltaic device only needs to include any of the aforementioned battery strings, and the specific form of the photovoltaic device is not limited. For example, whether the photovoltaic device includes a frame, etc. is not limited. For another example, the photovoltaic device may include a photovoltaic module, a photovoltaic system, etc. The photovoltaic system here may be a distributed photovoltaic system, or a photovoltaic and building integrated system (BIPV), etc. The photovoltaic device may be various photovoltaic products including the aforementioned battery strings. The opposite sides of the battery string in the photovoltaic module may also be provided with packaging materials, etc., and their specific structure is not limited.

[0126] It should be noted that the relevant parts of the silicon wafers, battery cells, battery strings, and photovoltaic devices mentioned in this application can be referenced to each other. In order to avoid repetition, the relevant parts are briefly described or not elaborated.

[0127] The following are specific examples and comparative examples.

[0128] Example 1

[0129] Referring to Table 1 below, 1000 rectangular silicon wafers were provided and fabricated with through-hole structures under the same process conditions. It was specified that B1 for each wafer was 150 μm, B2 was 100 μm, the width W1 of the first edge region of each wafer was 14 μm (0.014 mm), the thickness H of each wafer was 140 μm, and W1 / H = 0.1. Silicon wafers with the aforementioned through-hole structures were then used to prepare solar cells and form photovoltaic modules using the same process. The resulting photovoltaic modules contained a total of 850 solar cells (i.e., an 85% yield in Example 1 in Table 1). The remaining 150 wafers were somewhat broken during the process of drilling and forming the photovoltaic modules, and were therefore defective.

[0130] For 100 cells formed using the same parameters and process as above: one cell was placed on a test platform, with one of its surfaces facing the test platform along the thickness direction in contact with the test platform. One short side of the cell was fixed, and a 5N (Newton) force was steadily applied to the other short side of the cell. During the application of this force, the unfixed portion of the cell experienced moderate warping. After the warping stabilized, the displacement of the cell along its long side, 4 cm from the fixed short side, was measured relative to the test platform. Based on this displacement and the cell structure, the stress at the location corresponding to the through-hole closest to the fixed short side in the first edge region of the cell was calculated. The arithmetic mean of the stresses for the 100 cells was then calculated, yielding a value of 630 Pa. The arithmetic mean of the displacements for the 100 cells was calculated, yielding a value of 25E-5 (μm). The aforementioned stress can, to a certain extent, reflect the mechanical strength of the cell. Excessive stress can easily cause breakage or fragmentation. The aforementioned displacement can, to a certain extent, reflect the toughness of the cell. Cells with greater displacement have better toughness, and better toughness reduces the probability of breakage or fragmentation. Taking both stress and toughness into account can improve the yield rate of the cell.

[0131] An observer viewed the first surface of each cell from a distance of 3 meters, and could not see the edge of each cell (i.e., the visual effect was good in Table 1). The cell efficiency of these 100 cells was measured, and the arithmetic average of these 100 cell efficiencies was calculated, resulting in a value of 17%.

[0132] Starting from Example 2, in order to avoid repetition, the subsequent examples and comparative examples only describe the differences from Example 1, and the rest are the same as those in Example 1.

[0133] Example 2

[0134] The only difference between Example 2 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 144 μm (0.144 mm), the thickness H of each silicon wafer is 180 μm, and W1 / H = 0.8. The resulting photovoltaic module contains a total of 900 cells (i.e., a 90% yield in Example 2 as shown in Table 1). The remaining 100 silicon wafers were damaged to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0135] The test was carried out under the same test conditions, and the test results are shown in the row of Example 2 in Table 1 below.

[0136] Example 3

[0137] The only difference between Example 3 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 130 μm (0.13 mm), the thickness H of each silicon wafer is 130 μm, and W1 / H = 1. The resulting photovoltaic module contains a total of 860 cells (i.e., an 86% yield in Example 3 as shown in Table 1). The remaining 140 silicon wafers were damaged to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0138] The test was carried out under the same test conditions, and the test results are shown in the row of Example 3 in Table 1 below.

[0139] Example 4

[0140] The only difference between Example 4 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 500 μm (0.5 mm), the thickness H of each silicon wafer is 100 μm, and W1 / H = 5. The resulting photovoltaic module contains a total of 950 cells (i.e., a 95% yield in Example 4 as shown in Table 1). The remaining 50 silicon wafers were damaged to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0141] The test was carried out under the same test conditions, and the test results are shown in the row of Example 4 in Table 1 below.

[0142] Example 5

[0143] The only difference between Example 5 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 750 μm (0.75 mm), the thickness H of each silicon wafer is 50 μm, and W1 / H = 15. The resulting photovoltaic module contains a total of 800 cells (i.e., the 80% yield in Example 5 shown in Table 1). The remaining 200 silicon wafers were damaged to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0144] The test was carried out under the same test conditions, and the test results are shown in the row of Example 5 in Table 1 below.

[0145] Example 6

[0146] The only difference between Example 6 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 3000 μm (3 mm), the thickness H of each silicon wafer is 120 μm, and W1 / H = 25. The resulting photovoltaic module contains a total of 950 cells (i.e., a 95% yield in Example 6 as shown in Table 1). The remaining 50 silicon wafers were damaged to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0147] Tests were conducted under the same test conditions, and the test results are shown in the row corresponding to Example 6 in Table 1 below. In Table 1 below, the phrase "subtly visible margin" in the row corresponding to Example 6 means that a person viewing the first surface of each cell from a distance of 3 meters can vaguely see the edge of each cell.

[0148] Example 7

[0149] The only difference between Example 7 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 750 μm (0.75 mm), the thickness H of each silicon wafer is 25 μm, and W1 / H = 30. The resulting photovoltaic module contains a total of 700 solar cells (i.e., the yield rate of Example 7 in Table 1 is 70%). The remaining 300 silicon wafers were broken to some extent during the process of drilling and forming the photovoltaic module, and are defective.

[0150] The test was carried out under the same test conditions, and the test results are shown in the row of Example 7 in Table 1 below.

[0151] Example 8

[0152] The only difference between Example 8 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 3330 μm (3.33 mm), the thickness H of each silicon wafer is 90 μm, and W1 / H = 37. The resulting photovoltaic module contains a total of 900 solar cells (i.e., the 90% yield in Example 8 shown in Table 1). The remaining 100 silicon wafers were damaged to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0153] Tests were conducted under the same test conditions, and the test results are shown in the row corresponding to Example 8 in Table 1 below. In Table 1 below, the phrase "subtly visible margin" in the row corresponding to Example 8 means that a person viewing the first surface of each cell from a distance of 3 meters can vaguely see the edge of each cell.

[0154] Comparative Example 1

[0155] The only difference between Comparative Example 1 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 2 μm (0.002 mm), the thickness H of each silicon wafer is 140 μm, and W1 / H = 0.0142. The resulting photovoltaic module contains a total of 500 cells (i.e., a 50% yield in Comparative Example 1 in Table 1). The remaining 500 silicon wafers were somewhat broken during the process of drilling and forming the photovoltaic module and are therefore defective.

[0156] The test was carried out under the same test conditions, and the test results were referred to the row of Comparative Example 1 in Table 1 below.

[0157] Since the yield rate in Comparative Example 1 is only 50%, which is too low and has no application value, the battery efficiency is not measured.

[0158] Comparative Example 2

[0159] The only difference between Comparative Example 2 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 2 μm (0.002 mm), the thickness H of each silicon wafer is 100 μm, and W1 / H = 0.02. The resulting photovoltaic module contains a total of 400 cells (i.e., the 40% yield in Comparative Example 2 in Table 1). The remaining 600 silicon wafers were broken to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0160] The test was carried out under the same test conditions, and the test results were referred to the row of Comparative Example 2 in Table 1 below.

[0161] Since the yield rate in Comparative Example 2 is only 40%, which is too low and has no application value, the battery efficiency is not measured.

[0162] Comparative Example 3

[0163] The only difference between Comparative Example 3 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 1 μm (0.001 mm), the thickness H of each silicon wafer is 21 μm, and W1 / H = 0.048. The resulting photovoltaic module contains a total of 50 cells (i.e., the 5% yield in Comparative Example 3 in Table 1). The remaining 950 silicon wafers were broken to some extent during the process of drilling and forming the photovoltaic module and are defective.

[0164] The test was carried out under the same test conditions, and the test results were referred to the row of Comparative Example 3 in Table 1 below.

[0165] Since the yield rate in Comparative Example 3 is only 5%, which is too low and has no application value, the battery efficiency is not measured.

[0166] Comparative Example 4

[0167] The only difference between Comparative Example 4 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 8010 μm (8.01 mm), the thickness H of each silicon wafer is 200 μm, and W1 / H = 40.05. The resulting photovoltaic module contains a total of 1000 solar cells (i.e., the yield rate of 100% in Comparative Example 4 in Table 1).

[0168] Tests were conducted under the same test conditions, and the test results are shown in the row corresponding to Comparative Example 4 in Table 1 below. In Table 1 below, the visible margin in the row corresponding to Comparative Example 4 means that when a person is viewing the first surface of each cell from a distance of 3 meters, the edge area of ​​each cell is clearly visible, resulting in poor visual effect.

[0169] Since the battery cells formed in Comparative Example 4 can be viewed from a distance of 3 meters from each battery cell, the edge area of ​​each battery cell can be clearly seen. The visual effect is too poor and has no application value, so the battery efficiency was not measured.

[0170] Comparative Example 5

[0171] The only difference between Comparative Example 5 and Example 1 is that the width W1 of the first edge region of each silicon wafer is 8000 μm (8 mm), the thickness H of each silicon wafer is 500 μm, and W1 / H=16.

[0172] Tests were conducted under the same test conditions, and the test results are shown in the row corresponding to Comparative Example 5 in Table 1 below. In Table 1 below, the visible margin in the row corresponding to Comparative Example 5 means that when a person is viewing the first surface of each cell from a distance of 3 meters, the edge area of ​​each cell is clearly visible, resulting in poor visual effect.

[0173] Since the battery efficiency of the battery cell formed in Comparative Example 5 is only 8%, which is too low and most likely has no application value, its yield rate was not considered.

[0174] Table 1: Parameter comparison table of examples and comparative examples

[0175]

[0176] By comparing the above embodiments and comparative examples, it can be concluded that when W1 / H exceeds the range of 0.05 to 40, the mechanical strength is likely to deteriorate, resulting in a low yield rate or a significantly poor visual effect. When W1 is less than 0.005mm, the mechanical strength is likely to deteriorate, resulting in a low yield rate. At the same time, when the thickness of the battery cell exceeds the range of H from 2μm to 200μm, the battery efficiency is likely to be low. Therefore, in this application, W1 / H is 0.05 to 40, W1 is 0.005mm to 10mm, and H is 2μm to 200μm, which improves mechanical strength, improves yield rate, and has a better visual effect and higher battery efficiency.

[0177] In addition, because the through-holes set on the silicon wafer or battery cell have a greater impact on the mechanical strength, yield, visual effect, battery efficiency, etc. of the silicon wafer / battery cell, the above-mentioned experiments focus on the through-hole sub-solution. Regarding blind holes, the inventors of this application also conducted some experiments. Because the hole structure opened on the silicon wafer / battery cell does not have a through-hole setting, it causes less damage to the silicon wafer / battery cell body. Therefore, the mechanical strength and yield of the blind hole samples within the same W1 / H ratio range are improved by 30-50% compared with the through-hole sub-solution. Because there is no through-hole structure, the observer can observe a certain color difference between the unperforated area and the perforated area when he is close to the battery cell, and no obvious white space can be observed. The blind hole sub-solution is slightly better in terms of visual effect. The battery efficiency of the samples in the blind hole sub-solution is in the range of 25.3-26.4%.

[0178] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0179] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A silicon wafer, characterized in that: The silicon wafer is provided with a plurality of hole structures; the silicon wafer comprises: a first surface and a second surface opposite to each other along its thickness direction; At least part of the hole structure is a through-hole structure, the through-hole structure connects the first surface and the second surface, and a pore diameter B1 of the through-hole structure on the first surface is greater than or equal to a pore diameter B2 of the through-hole structure on the second surface; And / or, at least part of the hole structure is a blind hole structure; the blind hole structure extends from the first surface into the silicon wafer; The hole structure is not provided in the edge area of ​​the first surface; the first surface includes: a first side and a second side, the length of the first side is L1, the length of the second side is L2, and L1 ≥ L2; the edge area includes: a first edge area and a second edge area that are intersectingly distributed; the first edge area is provided along the first side, and the second edge area is provided along the second side; The width of the first edge region is W1; The thickness of the silicon wafer is H; 0.05≤W1 / H≤40.

2. The silicon wafer according to claim 1, wherein The width of the second edge region is W2; 1≤(W1 / W2)≤(L1 / L2).

3. The silicon wafer according to claim 1, wherein: When the hole structure is a through-hole structure: 0.5≤(B1-B2)÷(B1 / 2)≤1.

4. The silicon wafer according to claim 1, wherein At the position where the midline of the thickness direction of the silicon wafer is located, the aperture of the hole structure is B3; B1 ≥ B3; 0.1≤(B1-B3)÷(H / 2)≤50.

5. The silicon wafer according to claim 4, wherein: B3 is 1 μm to 100 μm.

6. The silicon wafer according to any one of claims 1 to 5, characterized in that: The cross-sectional shape of the hole structure along the thickness direction of the silicon wafer includes at least one of a rectangle, a trapezoid, and a waist shape; and / or, The cross-sectional profile of the hole structure on the first surface includes an arc segment; the closer to the center of the first surface, the closer the cross-sectional profile of the hole structure on the first surface is to a circle.

7. The silicon wafer according to any one of claims 1 to 5, characterized in that: W1 is 0.005 mm to 10 mm; and / or, H is 2 μm to 200 μm.

8. The silicon wafer according to any one of claims 1 to 5, characterized in that: B1 is 10 μm to 500 μm; and / or, The distance A between adjacent hole structures is 1 μm to 500 μm.

9. A battery cell, characterized in that: include: An electrode structure, and a silicon wafer as claimed in any one of claims 1 to 8; The electrode structure is arranged on the silicon wafer.

10. The battery cell according to claim 9, characterized in that: The electrode structures are staggered with the hole structures.

11. The battery cell according to claim 9, characterized in that: The electrode structure includes: a gate line electrode, and the hole structure array is arranged on one side of the battery cell where the gate line electrode is located; On the same side of the silicon wafer, the distance between the gate line electrode and the center line between two adjacent hole columns is less than or equal to 10 μm; the center line is along the extension direction of the gate line electrode.

12. The battery cell according to any one of claims 9 to 11, characterized in that: The electrode structure includes: a plurality of front gate line electrodes located on the light-facing side of the silicon wafer, and a plurality of back gate line electrodes located on the backlight-facing side of the silicon wafer; The hole structure is a through-hole structure: The number of hole structures between adjacent front gate line electrodes is greater than or equal to the number of hole structures between adjacent back gate line electrodes; and / or, The hole structures are arranged in arrays on both the light-facing side and the backlight side of the silicon wafer, and the number of columns of hole structures between adjacent front gate line electrodes is greater than or equal to the number of columns of hole structures between adjacent back gate line electrodes.

13. The battery cell according to claim 12, characterized in that: The spacing between adjacent front gate line electrodes is G1, and the spacing between adjacent back gate line electrodes is G2; On the same side of the silicon wafer, along the extending direction of the gate line electrode, the spacing between adjacent hole structures is G3; G1-G2=n×G3; n is an integer from 1 to 10.

14. The battery cell according to any one of claims 9 to 11, characterized in that: The electrode structure includes: electrode structures that are spaced and alternately distributed, and the electrode structures are all located on the backlight side of the silicon wafer.

15. A battery string, characterized in that: The battery string is formed by sequentially connecting a plurality of battery cells according to any one of claims 9 to 14 in series and / or in parallel.

16. The battery string according to claim 15, characterized in that Along the extension direction of the battery string, the spacing between adjacent battery cells is D; When D>H, H≤W1≤0.5D; In the case of H≥D>0, 0.5H≤W1≤H; When D≤0, H≤W1≤|D|.

17. A photovoltaic device, characterized in that: include: A battery string as claimed in any one of claims 15 to 16.

Images