Accelerating query processing on processing unit

Abstract

Query processing systems and methods are disclosed herein. In an example system, query information for processing a query is received over a network. A first processing architecture loads a data set associated with a query into a shared memory. The second processing architecture accesses the data set from the shared memory. In one example, first and second processing architectures and shared memory are integrated in a hardware chip (e.g., a chiplet that includes several processor architectures, such as CPUs and graphics processing units (GPUs). The query is processed using a second processing architecture based on the dataset accessed from the shared memory to generate query results. And providing a query result through a network. In this manner, the computing device may execute queries based on different processing systems contained therein.

Description

Background Art

[0001] Traditionally, traditional central processing units (CPUs) have been used to process database workloads. While CPU performance has improved over time, such as through the implementation of different hardware instructions or compilation techniques, utilizing CPUs for database workloads still includes inefficiencies such as limited memory access capabilities, parallel processing, and other scaling limitations. While other types of hardware have been explored to address these limitations, such hardware often has other constraints that limit overall performance gains. Summary of the Invention

[0002] This summary is provided to introduce a series of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosed subject matter, nor is it intended to be used to limit the scope of the disclosed embodiments.

[0003] Disclosed herein are query processing systems and methods. In an example system, query information for processing a query is received over a network. A first processing architecture loads a data set associated with the query into a shared memory. A second processing architecture accesses the data set from the shared memory. In one example, the first processing architecture, the second processing architecture, and the shared memory are integrated into a hardware chip (e.g., a chiplet containing several processor architectures, such as a CPU and a graphics processing unit (GPU)). The query is processed using the second processing architecture based on the data set accessed from the shared memory to generate a query result. The query result is provided over the network. In this manner, a computing device can execute a query based on different processing systems contained therein.

[0004] Other features and advantages of the embodiments, as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. It should be noted that the claimed subject matter is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Based on the teachings contained herein, additional embodiments will be apparent to those skilled in the relevant art(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate embodiments of the application and, together with the description, further serve to explain the principles of the embodiments and to enable those skilled in the relevant art to make and use the embodiments.

[0006] Figure 1 A block diagram of a system for processing queries on a computing device is shown according to an example embodiment.

[0007] Figure 2 A block diagram of another system for processing queries on a computing device is shown according to an example embodiment.

[0008] Figure 3 A flowchart of a method for processing a query according to an example embodiment is shown.

[0009] Figure 4 A flow chart of a method for accessing shared memory during query processing according to an example embodiment is shown.

[0010] Figure 5 A flow chart of a method for generating an executable file for processing a query according to an example embodiment is shown.

[0011] Figure 6 A flowchart of a method for generating an executable file based on a machine learning framework according to an example embodiment is shown.

[0012] Figure 7 Depicted are example executions of SQL queries on different hardware backends having different memory bandwidth characteristics according to example embodiments.

[0013] Figure 8 Illustrated is an example system of how multiple cores may perform simple and value aggregation according to an example embodiment.

[0014] Figure 9 Illustrated is an example data synchronization in a system according to an example embodiment.

[0015] Figure 10 A block diagram of an example computer system is shown in which embodiments may be implemented.

[0016] The subject matter of the present application will now be described with reference to the accompanying drawings. In the accompanying drawings, like reference numerals indicate identical or functionally similar elements. Additionally, the leftmost digit(s) of a reference numeral identifies the drawing in which the reference numeral first appears. DETAILED DESCRIPTION

[0017] I. Introduction

[0018] The following detailed description discloses many example embodiments. The scope of this patent application is not limited to the disclosed embodiments, but also covers combinations of the disclosed embodiments and modifications to the disclosed embodiments. It should be noted that any section / subsection titles provided herein are not intended to be limiting. Embodiments are described throughout the document, and any type of embodiment can be included under any section / subsection. In addition, the embodiments disclosed in any section / subsection can be combined in any way with any other embodiment described in the same section / subsection and / or different sections / subsections.

[0019] II. Example Embodiments

[0020] Traditional CPUs are often used to process database workloads. While CPU performance has improved over time, such as through the implementation of different hardware instructions or compilation techniques, utilizing CPUs for database workloads still includes inefficiencies such as limited memory access capabilities, parallel processing, and other scaling limitations. While other types of hardware have been explored to address these limitations, such hardware often has other constraints that limit overall performance gains.

[0021] For example, alternative hardware has been employed to improve parallelization and memory access capabilities compared to the CPU. This alternative hardware is embodied in independent or discrete chips (such as graphics processing units (GPUs), field programmable gate arrays (FPGAs), or other independent hardware accelerators), which typically have more processing cores and higher memory bandwidth. Such hardware is coupled to other computing components (such as the CPU) via a computing bus (such as a PCIe bus), which has a data bandwidth far lower than the processing capabilities of the independent chips. In addition, these types of chips do not utilize memory shared with the CPU of the computing system. Therefore, for processing on the hardware accelerator, data is transferred from another memory (e.g., CPU memory) to the independent accelerator located on a separate chip via a relatively slow computing bus. Therefore, even with these alternative types of hardware, there are still bottlenecks that limit their performance (e.g., due to limitations of the bus used to transfer data between the CPU and the independent accelerator (which is implemented on a chip separate from the CPU)).

[0022] The embodiments described herein are intended to process queries. In an example system, query information for processing a query is received over a network. In one example, the query information is received in a computing device that includes a chiplet that includes several processor architectures, such as a CPU and a graphics processing unit (GPU). A first processing architecture loads a data set associated with the query into a shared memory. A second processing architecture accesses the data set from the shared memory. In an example system, the first processing architecture, the second processing architecture, and the shared memory are integrated into a hardware chip (e.g., in a single package or die). The query is processed using the second processing architecture (e.g., GPU) based on the data set accessed from the shared memory to generate a query result. The query result is provided over a network. In this way, a computing device can execute a query based on the different processing systems contained therein.

[0023] The techniques described herein advantageously provide improvements to computer processing, particularly improved utilization of computer resources and overall performance. For example, by utilizing processor components (e.g., CPUs and GPUs) having a combined architecture, increased computing power (e.g., due to a greater number of processing cores) and high memory bandwidth can be advantageously utilized to efficiently execute queries (e.g., in an example implementation, 2 times the memory bandwidth of a CPU-only machine and 12 petaflops), thereby allowing faster or accelerated query processing.

[0024] Furthermore, in combined architecture (e.g., CPU / GPU) implementations, bottlenecks (e.g., due to the limited capacity of computer buses such as PCIe buses) can be minimized or even avoided, which can further improve overall performance. For example, in other systems that use standalone accelerator-based processors (e.g., GPUs, which can have thousands of cores compared to just a few dozen in a CPU) to perform computations, data utilized by the GPU must first be transferred to the CPU's memory (which is typically larger than the GPU's memory), after which the GPU can access the data via a computer bus (e.g., a PCIe bus). However, computer buses typically have relatively slow bandwidth, resulting in bottlenecks that slow down processing. By utilizing memory shared between two processing architectures (e.g., CPU and GPU), the GPU can retrieve data stored therein by directly accessing the memory (i.e., without having to access the data via a computer bus), thereby improving the speed at which processing can occur. In other words, integrating multiple processing architectures (e.g., accelerator and CPU) and shared memory on a single hardware chip allows the components integrated therein to perform data access in a faster manner (e.g., by using direct memory access that is not available for standalone accelerator implementations). Compared to other technologies, by reducing or eliminating data access bottlenecks, not only can the access speed of such data be improved, but also the processing power of hardware accelerators can be enhanced. Based on at least these advantages and other advances described herein, the disclosed technology can improve various aspects of computing devices and computer processing.

[0025] Furthermore, the disclosed techniques allow queries to be executed on an alternative system (e.g., a system containing a processing chip with a combined architecture) that can execute the query with improved resource utilization. Thus, rather than executing the query on a system with lower overall performance, an executable file can be generated by a first system (e.g., a server), transmitted over a network to an alternative system that can execute the query with improved performance and return the results to the appropriate endpoint after processing. In this way, the resources and computing power of different systems can be efficiently utilized to perform different tasks associated with executing the query.

[0026] An example implementation of the technique directed to processing queries will now be described. For example, Figure 1 1 shows a block diagram of a system 100 for processing queries in a computing device according to an example embodiment. Figure 1 As shown, system 100 includes computing device 102 , network 110 , and server 114 .

[0027] The network 110 may include one or more networks, such as a local area network (LAN), a wide area network (WAN), a personal area network (PAN), an enterprise network, the Internet, etc., and may include wired and / or wireless portions. The game console 102 and the server 114 may be communicatively coupled via the network 110. In implementations, the game console 102 and the server 114 may communicate via one or more application programming interfaces (APIs) and / or according to other interfaces and / or technologies. The game console 102 and the server 114 may each include at least one network interface that enables communication with each other. Examples of such wired or wireless network interfaces include an IEEE 802.11 wireless LAN (WLAN) radio interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth TM interface, a near field communication (NFC) interface, etc. Other examples of network interfaces are described elsewhere herein.

[0028] Computing device 102 includes a query processor 104 configured to process one or more queries. Query processor 104 includes an acceleration processing unit 106 and a query processing engine 108. Acceleration processing unit 106 includes shared memory 110. In various implementations, the query processor may include one or more other components not explicitly shown, such as other hardware devices or components (e.g., memory, processor, etc.).

[0029] In an example, computing device 102 includes a device that includes an accelerated processing unit (APU). In an example, APU 106 includes one or more processing systems. Each processing system may include a different processing architecture. In some examples, APU 106 is a chiplet or hardware chip that includes multiple processing architectures and shared memory 110 shared between the processing architectures. In various embodiments, one or more of the processing architectures is a CPU and a hardware accelerator, such as a GPU. It should be understood that other types of accelerators may also be implemented within APU 106, such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or other types of accelerators. In various embodiments, multiple processing architectures (e.g., a CPU and an accelerator, such as a GPU) are integrated or implemented on a single package (e.g., a die) or hardware chip to form a combined chiplet. In implementations, each processing system may include multiple computing cores. For example, one processing system (e.g., a GPU) may include a greater number of processing cores than another processing system (e.g., a CPU) of APU 106.

[0030] Although Figure 1 108. The computing device 102 is illustrated in FIG. 102, but it should be understood that the disclosed techniques may be implemented with other types of computing devices in addition to or as an alternative to the computing device shown. For example, the disclosed techniques may be implemented using other types of computing devices that include an accelerated processing unit (APU), such as a gaming console that includes a processing chip with multiple processing architectures. In an example, the gaming console includes a device configured to output a video signal for presentation on a display screen, the video signal including one or more video frames (e.g., of a video game 108). For example, the gaming console may include a video game console (e.g., any version of Microsoft Any version of Sony Nintendo NES, or any version of Switch TM etc.), desktop computers, laptop computers, smartphones, tablet computers, wearable computing devices, head-mounted gaming devices, mixed and / or virtual reality devices (e.g., Microsoft HoloLens TM ), or any other processing device for executing one or more video games (e.g., video game applications) and outputting video frames generated by the video games to, such as a display device (which is collocated with and / or remotely located from the game console 102). Although Figure 1Although not shown in the figures, the display device of the game console may include any type of display suitable for receiving and displaying video frames generated by the video game. For example, the display device may be a liquid crystal display, a cathode ray tube display, a light emitting diode display, a plasma display, a display screen of a projection television, or any other type of display that can be coupled to the game console via an appropriate interface. The display device of the game console may be external to the game console or incorporated into the game console. Figure 10 Example computing devices are discussed that may incorporate the functionality of computing device 102. Any number of computing devices (eg, game consoles) may be present in an implementation in accordance with the disclosed technology.

[0031] In an example, shared memory 110 comprises a memory device utilized by APU 106 (e.g., by multiple processing systems implemented therein). In various implementations, memory 110 is integral to or part of APU 106 (e.g., on the same package). In some examples, shared memory 110 comprises on-chip memory that is directly accessed by the various processing architectures implemented on APU 106. For example, each processing architecture of APU 106 can access data stored in shared memory 110 via direct memory access (DMA). In various examples, during such access, data accessed from shared memory 110 by each such processing architecture is not transferred over a computing bus (e.g., a PCI or PCIe bus). In this way, data transferred between different processing systems of APU 106 does not need to be transferred over a computer bus, which can reduce overhead when performing operations such as executing queries. In some other implementations, the processing system (e.g., GPU) of the APU 106 may include a direct storage connection to a storage device on the computing device 102 (which may be part of the shared memory 110 or a separate storage device), so that the processing system can transfer data at a relatively high speed, thereby further improving performance. Figure 10 Examples of such memory devices are described.

[0032] The query processing engine 108 is configured to receive query information for one or more queries and process the query information to generate query results. In an example, the query information may include information for executing one or more database queries (such as structured query language (SQL) queries). In some implementations, the query information may be received over the network 110, such as from a query workload system 116 of a server 114. In some other implementations, the query information may be received from a device local to the computing device 102 (e.g., via a local computing device) or via user input.

[0033] In an implementation, the query processing engine 108 can be configured to access (including causing another component to access) a data set associated with the query information. For example, the query processing engine 108 can cause the APU 106 to access data stored remotely (e.g., in the cloud, at a server 114, or in another remote location). In other implementations, the data can be stored locally on the computing device 102 (e.g., on a storage device that is internal to or communicatively coupled to the computing device 102). In another implementation, the data can be transferred (or caused to be transferred) from the query workload system 116 along with the query information. In various examples, the data utilized by the APU 106 to process the query is transferred to the shared memory 110. In some examples, the data used to process the query is transferred to the shared memory in response to instructions executed by the CPU of the APU 106.

[0034] In various examples, the query processing engine 108 processes one or more queries based on the received query information using multiple processing architectures (e.g., APU 106) on a data set associated with the query. In some implementations, processing of the query can be achieved without transferring the portion of the data set accessed for processing the query over a peripheral component interconnect (PCI) or PCI Express (PCIe) compute bus. For example, after a first processing architecture (e.g., CPU) of the APU 106 stores data in the shared memory 110, a second processing architecture (e.g., GPU) of the APU 106 can directly access the data in the shared memory 110, such as via direct memory access. In this way, the second processing architecture does not need to obtain the data over the compute bus, which can improve the execution speed of the query.

[0035] In an example implementation, the query information received by the query processing engine 108 includes an executable file generated based on operations performed on the input query. For example, the query information can be generated based on at least a machine learning (ML) framework or compiler that is configured to automatically compile queries (e.g., SQL queries) into executable files. Examples include PyTorch, Antares, etc., as will be understood by those skilled in the relevant art. In some implementations, the executable file can be generated by the server 114. In other implementations, the computing device 102 or another computing device can generate the executable file. In examples, such ML frameworks and compilers can also be used to optimize the queries executed by the query processing engine 108. Additional details regarding the generation of the executable file will be described in more detail below.

[0036] The query processing engine 108 can process the query to generate query results and provide the query results over the network (e.g., to the server 114). In other examples, the query results can be provided locally (e.g., via a display coupled to the computing device 102, provided to a computing device local to the computing device 102, and / or provided for storage in a storage device internal or external to the computing device 102). In another implementation, the results of the query can be provided to an end-user computing device (e.g., the device from which the query was entered) or any other device or platform not explicitly shown (e.g., a data analysis machine, a dashboard, etc.).

[0037] The server 114 includes a query workload system 116 and an executable query generator 118. The server 114 includes any one or more server devices or other computing devices for receiving queries to be executed. Figure 10 An example computing device that can incorporate the functionality of server 114 is described. In the example, a query to be executed can be initiated from another computing device (not shown) via an appropriate user interface, including but not limited to an application, a web-based interface, or any other interface in which queries can be generated (automatically and / or manually) for execution. Queries can be generated to be executed against a data set, such as for analysis or other purposes. Queries can include SQL queries or any other type of query understood by those skilled in the art.

[0038] Once generated, the query may be transmitted to the query workload system 116. In an example, the query workload system 116 may be configured to manage the receipt, processing, and / or distribution of queries (and / or query results) across one or more devices coupled to the network 110. In some implementations, the query workload system 116 (or the executable query generator 118) may transmit query information (e.g., an executable file) for processing the query to the computing device 102. In some other embodiments, the query workload system and / or the executable query generator 118 transmits a data set associated with the query information, causes the transmission of a data set associated with the query information, or makes the data set associated with the query information accessible to the computing device 102.

[0039] The executable query generator 118 is configured to generate query information from the received query. The query information generated by the executable query generator 118 includes an executable file or other code (e.g., source code, assembly code, machine code, etc.) to be executed by the computing device 102. In one example implementation, when a query is received, the executable query generator 118 is configured to parse and / or optimize the query. The query can be parsed and / or optimized in various ways, such as by utilizing Apache Spark or another program. When parsing and / or optimizing the query, the executable query generator 118 can generate a physical query plan (e.g., in the form of a graph, such as a directed acyclic graph (DAG)) that includes one or more query operators. In an example, the graph can include a representation of how each operator (e.g., SQL operator) is executed to generate the query results.

[0040] In some implementations, one or more passes are performed on the graph. For example, the executable query generator 118 may analyze the graph starting with a high-level description of each operator in the graph and generate a code set (e.g., in a computer language or program) specific to the graph and / or the operators contained therein. In some implementations, the code set includes a neural network, a deep neural network, or a tensor program that can be configured for execution by one or more processing architectures (e.g., a GPU).

[0041] The executable query generator 118 may further compile and / or optimize the program. For example, a component within the executable query generator 118 may take the code set (e.g., a neural network program) as input, optimize the code using one or more techniques (e.g., fusion, tuning, etc.), and generate an assembly code (or other code) set that may be transmitted to the computing device 102 for execution. In an example, the assembly code (or other code) set generated by the executable query generator 118 may be generated based on the target hardware that will be used to execute the code, such as an APU present in the computing device 102. For example, where the APU 106 includes a CPU and a GPU, the assembly code (or other code) set may be generated in such a way as to identify how different processing systems of the APU 106 should be used to process different portions of the code (e.g., to improve performance).

[0042] In one example implementation, there may be multiple computing devices in the implementation, each coupled to the network 110, resulting in a cloud of connected computing devices (e.g., in a data center), each of which is configured to process one or more queries or portions thereof. In such an example, data analysis may be performed based on usage or demand time (e.g., hour, day, week) on a computing device (e.g., a gaming console). For example, when a gaming console is primarily used for gaming (e.g., as a cloud-based gaming infrastructure) during certain times or days (e.g., evenings and / or weekends) and has less demand or load during other times, these other times with lower demand or load can be used to process queries on the same devices as described herein. In this way, predictable patterns of gaming behavior can be exploited to determine when these same systems (including APUs) can be used for other purposes (e.g., query execution).

[0043] Those skilled in the relevant art will understand that implementation is not limited to Figure 1 For example, Figure 1 Any one or more of the components shown may be implemented on a computing device not explicitly shown, such as one or more cloud-based server devices. In addition, according to the example embodiments herein, there may also be Figure 1 Any additional component or components or subcomponents not expressly shown in the .

[0044] Figure 2 A block diagram of another system for processing queries on a computing device is depicted in accordance with an example embodiment. Figure 2 As shown, system 200 includes example implementations of query processor 104 and executable query generator 118, and query 210. Query processor 104 includes example implementations of query processing engine 108 and APU 106. Query processing engine 108 includes query program executor 202 and result communicator 204. APU 106 includes example implementations of accelerator 206, CPU 208, and shared memory 110. Figure 2 As shown, the executable query generator 118 includes a parser 212 , a set of libraries 214 , an optimizer 216 , a program generator 218 , and a plan converter 220 .

[0045] In the example, the executable query generator 118 obtains the query 210 and generates query information 234, which includes an executable file for processing the query. The query program executor 202 provides the query information 222 to the APU 106 for execution, which can be implemented by any one or more processing architectures implemented therein. Upon processing, the APU 106 generates query results and returns the query results 224 to the results communicator 204, which can perform any number of actions in response (e.g., store the results, transmit the results, etc.). Additional details regarding the operation and functionality of the system 200 are described below.

[0046] Query 210 comprises any type of input string to be executed by a computer program. In an example, query 210 can be user-generated (e.g., received by a user interface of a computing device) or automatically generated (e.g., by an analytics program or dashboard). In some embodiments, query 210 identifies one or more operations to be performed on a data set. For example, query 210 identifies an operation (e.g., select, update, parameter, etc.) to be performed on one or more fields of a database. In some examples, query 210 identifies specific field(s), row(s), column(s), or database(s) on which the operation is to be performed. In some implementations, query 210 comprises a Structured Query Language (SQL) query, although other types of queries written in other languages ​​are also contemplated herein.

[0047] In various implementations, query 210 also identifies or is accompanied by an identification of a desired processing architecture on which the query should be executed. For example, query 210 may include information indicating that the query should be executed on an accelerator (if an accelerator is available for execution), or on a CPU, or both. In some implementations, the identification of the desired processing architecture is specified in a parameter of query 210.

[0048] The parser 212 is configured to obtain and parse the query 210. For example, the parser 212 parses the query by accessing one or more libraries 214. For example, the libraries 214 may include a mapping of different strings (e.g., operations) specified in the query to database operators. For example, the parser 212 may be configured to generate a physical query plan 226 that includes a graph of operators (e.g., physical database operators) specified by the libraries 214. In some implementations, the query plan includes a directed acyclic graph (DAG).

[0049] Optimizer 216 is configured to optimize query 210 and / or the physical query plan generated by parser 212. For example, optimizer 216 can be configured to access library 214 to perform one or more optimizations to improve the execution efficiency of query 210. In some examples, optimizer 216 can select a particular query plan from multiple query plans generated by parser 214 based on resource cost (e.g., execution cost or time).

[0050] The query can be parsed and / or optimized in various ways, such as by utilizing Apache Spark or another program. When parsing and / or optimizing the query, the executable query generator 118 can generate a physical query plan (e.g., in the form of a graph) that includes one or more query operators. In an example, the graph can include a representation of how each operator (e.g., a SQL operator) is executed to generate the query results.

[0051] In the example system, plan converter 220 obtains physical query plan 230 from optimizer 216 and generates code based thereon. In various embodiments, plan converter 220 performs one or more passes on the physical query plan (e.g., a graph). For example, plan converter 220 may analyze the graph starting with a high-level description of each operator in the graph and generate code (e.g., in a computer language or program) specific to the graph and / or the operators contained therein.

[0052] In some implementations, the code set includes a neural network, a deep neural network, or a tensor program that can be configured for execution by one or more processing architectures (e.g., a GPU). In some examples, the plan converter 220 utilizes a machine learning framework to generate the code set.

[0053] In one example, the plan converter 220 loads the obtained query plan into memory and then traverses the graph. For each operator in the graph, the plan converter 220 identifies the corresponding code implementation (e.g., computational logic). For example, the plan converter 220 accesses a dictionary containing a mapping of operators to code implementations and uses the dictionary to identify a set of code implementations for the graph. In one implementation, the set of code implementations includes programs, such as neural network (or other ML or artificial intelligence (AI)) programs. In one example, as discussed above, the plan converter 220 includes an ML framework to generate code implementations. An example of such a framework is framework, which generates programs (e.g., neural network programs) and These examples are illustrative only, and other types of frameworks are also contemplated, including both ML frameworks and non-ML frameworks.In this manner, the parser 212, the optimizer 216, and / or the plan converter 220 can convert the query 210 into a code set.

[0054] In an example embodiment, plan converter 220 generates code implementations so that the code can be executed on different types of hardware (e.g., on different architectures). In some implementations, the code implementation targets hardware that processes queries in parallel (e.g., through multithreading or utilizing multiple processing cores). In some embodiments, plan converter 220 exports the generated set of code implementations (e.g., programs) into a separate library for retrieval by program generator 218.

[0055] Program generator 218 may obtain code set 232 from plan converter 220 and compile and / or optimize the code set (e.g., a program). For example, program generator 218 may take the code set (e.g., a neural network program) as input, optimize the code using one or more techniques (e.g., fusion, tuning, etc.), and generate an assembly code (or other code) set that may be transmitted to computing device 102 for execution. In an example, the assembly code (or other code) set generated by program generator 218 may be generated based on the target hardware that will be used to execute the code, such as an APU present in computing device 102. For example, where APU 106 includes a CPU and a GPU, the assembly code (or other code) set may be generated in such a way as to identify how different processing systems of APU 106 should be used to process different portions of the code (e.g., to improve performance). In some examples, program generator 218 generates the assembly code set based on a specific target architecture, such as the desired architecture identified in query 210 (e.g., based on an indication that the query should be executed on a specific architecture).

[0056] In one example, program generator 218 generates target-specific code that is mapped to each portion of the code implementation generated by plan converter 220. For example, based on the target architecture (e.g., the hardware that will be used to execute the executable file corresponding to the query), program generator 218 generates a code set from the code implementation set. In other words, program generator 218 can be configured to represent each code implementation corresponding to an operator of the query plan as code that can be executed on the target hardware.

[0057] In some other embodiments, the program generator 218 can perform one or more optimizations on the generated code to further improve processing efficiency, such as by improving multi-threaded utilization for certain types of hardware architectures. In an example, the program generator 218 compiles the code to generate query information (e.g., an executable file, such as a binary file) 234 that can be executed on the target architecture.

[0058] In the example, the query program executor 202 obtains the query information 234 (e.g., over a network). The query program executor 202 transmits the query information 222 to the APU 106 for processing. The APU 106 processes the query information using at least one of the accelerator 206 and / or the CPU 208. In the example, the accelerator 206 and the CPU 208 access the shared memory 110 (e.g., via direct memory access) to improve processing speed. It should be understood that although the APU is described as including two processing architectures (the accelerator 206 and the CPU 208), this implementation is meant to be illustrative only. The APU 106 may include any number of different processing architectures, all of which are integrated on a single chiplet and share a common memory that can be directly accessed.

[0059] In an example, the accelerator 206 includes a processor component for executing program code, which includes a hardware accelerator for execution. In various embodiments, the accelerator 206 includes a relatively large number of processing cores (e.g., hundreds or thousands). In some examples, one or more of such processing components is a tensor processing unit (TPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or other dedicated hardware processor that can perform certain types of processing in an accelerated manner (e.g., using a large number of processing cores).

[0060] The CPU 208 includes a processing component for executing program code. In an example, the CPU 208 is configured to receive query information 222 and cause data required for processing the query information to be loaded into the shared memory 110. For example, the CPU 208 may preload or prefetch data for storage in the shared memory 110 before processing the query information (e.g., by the accelerator 206) so that the data is present in the shared memory when the accelerator 206 begins processing the query. In other words, in various implementations, the CPU 208 may be configured to manage the input of data to the shared memory 110 and / or the output of data from the shared memory 110 from components external to the APU 106. Thus, even when the accelerator 206 is executing the query information, the CPU 208 is responsible for performing certain input / output functions of the shared memory 110.

[0061] In an example, the accelerator 206 is configured to directly access data in the shared memory 110. For example, the accelerator 206 can directly access the data required to process the query information from the shared memory 110 (e.g., using DMA technology) instead of relying on data transfer on a computer bus (e.g., a PCIe bus). After the accelerator 206 completes processing of the query information (or portion of the query information), the accelerator 206 can directly access the shared memory 110 to store such results (e.g., without having to transfer data to the CPU 208 via the PCIe bus). This is in contrast to certain other implementations (e.g., using a standalone GPU), in which data must be accessed and / or transferred to the CPU via the PCIe bus, resulting in bottlenecks and overall performance degradation. Therefore, by allowing the accelerator 206 and the CPU 208 to utilize the shared memory 110 for query processing (e.g., utilizing the same physical memory components), query processing can be improved.

[0062] While processing the query information, the CPU 208 can access the query result set from the shared memory 110 (e.g., via DMA) and provide the query results 224 to the results communicator 204. In an example, the results communicator 204 is configured to transmit the query results (e.g., via a network) to an endpoint. In an implementation, the endpoint can be any destination where the results are to be stored and / or reported, including but not limited to a storage device or cache local to the query processor 104, an external storage device (e.g., a cloud-based storage device), a query workload system 116, and / or an application or interface from which the query 210 is generated. These are merely examples, and other endpoints are also contemplated, as will be understood by those skilled in the relevant art.

[0063] Thus, query processing may be performed in various ways by the executable query generator and / or query processor 104. For example, Figure 3 300 is a flowchart of a method for processing a query according to an example embodiment. In an embodiment, the flowchart 300 is composed of Figure 1 The system 100 shown and / or Figure 2 Therefore, reference will be made to the device 200 shown. Figure 1 and Figure 2 Describe the flow chart 300. Based on the following information about the flow chart 300, Figure 1 System 100 and Figure 2 From the discussion of system 200, other structural and operational embodiments will be apparent to those skilled in the relevant art(s).

[0064] Flowchart 300 begins at step 302. In step 302, query information for processing a query is received via a network. For example, referring to Figure 1 and Figure 2 , the query program executor 202 is configured to receive query information 234 via the network 110. In the example, the query information is associated with the query 210. For example, as previously discussed, the executable query generator 118 can convert the query 210 (e.g., received via an interface or by other means) into an executable file in various ways for processing by the APU 106. Upon generating the executable file, the executable query generator 118 provides the executable file to the query processor 104 for processing.

[0065] In step 304, the first processing architecture loads the data set associated with the query into the shared memory. Figure 2 , the first processing architecture (e.g., CPU 208) loads data associated with query 210 into shared memory 110. The data loaded into shared memory 110 can be identified based on information included in query information 234. In various examples, the first processing architecture can be configured to retrieve data from a data source (such as a database). For example, the data set (e.g., which may include database data) can be retrieved from a storage device located within computing device 102 or remotely located (e.g., in a data repository, in the cloud, on a server, etc.). In implementation, the data set can include any number of fields, rows, and / or columns required to execute query 210.

[0066] Thus, in an example, data associated with a query may be preloaded into the shared memory 110 by the CPU 208. For example, upon receipt of query information for processing by the APU 106, the CPU 208 may be configured to cause the appropriate data set associated with the query to be retrieved from an appropriate storage device (e.g., local to or located remotely from the computing device 102) and store the data in the shared memory 110 for access by the second processing architecture.

[0067] In step 306, the associated data set is accessed from the shared memory by the second processing architecture. In an example, the shared memory 110 is present on a hardware chip that includes the first processing architecture and the second processing architecture, such that each of the above components is integrated into the hardware chip (e.g., a single hardware chip), as discussed above. According to various embodiments, the query program executor 202 provides query information to the APU 106 that includes both the processing architecture and the shared memory 110.

[0068] In an example, both the first processing architecture and the second processing architecture (e.g., the accelerator 206 and the CPU 208) can directly (e.g., via DMA) access data stored on the shared memory 110. For example, one of the processing architectures (such as the accelerator 206, if the query information is to be executed by the accelerator) is configured to access data associated with the query from the shared memory 110. In this way, the accelerator 206 can access the data required to process the query information from the shared memory without having to transfer the data to the accelerator via a communication bus. In other words, since the CPU 208 is configured to load data into the shared memory 110, the accelerator 206 can directly access the data that has been loaded into the shared memory without having to transfer the data to the accelerator via a PCIe bus or similar communication bus.

[0069] In step 308, the query information is processed based on the data set accessed from the shared memory using the second processing architecture to generate a query result. Figure 2 The second processing architecture (e.g., accelerator 206) is configured to process the query information based on the data set accessed from shared memory 110 to generate a query result. In an example, the processing architecture(s) that execute the query information execute one or more computer instructions defined in the query information on the data retrieved from shared memory 110 to generate query result 224.

[0070] In one example, one of the processing architectures (e.g., accelerator 206 or CPU 208) performs execution of the query information. For example, if query 210 indicates that the target processing architecture is an accelerator, the query information may be generated by the executable query generator in a manner such that accelerator 206 carries the execution of the query information (e.g., by utilizing a greater number of processing cores than CPU 208). In other examples, the query information may be executed by CPU 208. In yet another example, the query information may be executed by a combination of accelerator 206 and CPU 208.

[0071] Upon generating the query results, the processing architecture may be configured to store the query results in the shared memory 110 (eg, via direct memory access).

[0072] In step 310, the query results are provided via the network. Figure 2, the CPU 208 can be configured to access the query results from the shared memory 110 and provide the query results 224 to the result communicator 204. In an example, the result communicator of the query processing engine 108 can provide the query results to an endpoint. In one example, the endpoint can be a separate computing device (e.g., the server 114, the computing device of the user who generated the query, the computing device where the dashboard displaying the query results will be located, or various other computing devices). In another example, the query results are stored in a storage device located locally or remotely from the query processor 104.

[0073] As discussed above, the processing architecture integrated into APU 106 may utilize shared memory. For example, Figure 4 4 shows a flow chart of a method for accessing shared memory during query processing according to an example embodiment. In an embodiment, the flow chart 400 may be as follows: Figure 1 The system 100 shown and / or Figure 2 Therefore, we will continue to refer to the system 200 shown in FIG. Figure 1 and Figure 2 Describe the flow chart 400. Based on the following information about the flow chart 400, Figure 1 System 100 and Figure 2 From the discussion of system 200, other structural and operational embodiments will be apparent to those skilled in the relevant art(s).

[0074] Flowchart 400 begins at step 402. In step 402, query data is accessed via direct memory access of a shared memory. Figure 1 and Figure 2 , any one or more of the processing architectures integrated into the APU 106 (such as the accelerator 206 and / or the CPU 208) is configured to access data associated with the query 210 from the shared memory 110 via direct memory access (DMA). For example, using DMA techniques, a physical address (e.g., a pointer, etc.) can identify the address of a memory in which the data associated with the query is stored. In an example, one processing architecture can provide the address to another processing architecture (e.g., the CPU can provide the address to the accelerator) in various ways, such as by transmitting a packet using a communication channel or using a register write. After the appropriate processing architecture obtains the physical address, the shared memory 110 can be accessed at the identified physical address to directly obtain the query data. In this manner, access to the data by one processing architecture (e.g., the accelerator) does not involve transferring the query data between the first processing architecture (or its associated shared memory) via a communication bus (such as a PCIe bus). Instead, the shared memory is accessed directly, thereby speeding up the transfer of data required to process the query information.

[0075] As discussed above, query information may be generated by executable query generator 118 in various ways. For example, Figure 5 500 is a flowchart of a method for generating an executable file for processing a query according to an example embodiment. Figure 2 The system 200 shown is implemented. Therefore, reference will be made to Figure 2 Describe the flowchart 500. Based on the following about the flowchart 500 and Figure 2 From the discussion of system 200, other structural and operational embodiments will be apparent to those skilled in the relevant art(s).

[0076] Flowchart 500 begins at step 502. In step 502, the library is used to optimize the input query to generate a query plan. For example, referring to Figure 2 , the parser 212 and / or the optimizer 216 are configured to obtain an input query 210 and optimize the query using one or more libraries 214 to generate a query plan. As discussed above, in various embodiments, the query plan includes a physical query plan, where the physical query plan includes one or more query operators (e.g., in the form of a graph). In various examples, the query plan can be selected based on the time and / or cost of executing the query 210.

[0077] In step 504, the query plan is traversed to generate a query program including operator logic for each of the plurality of operators. Figure 2 The plan converter 220 is configured to traverse the query plan (e.g., based on the operators in the plan) to generate a query program that includes operator logic for each of the plurality of query operators present in the query plan. For example, the plan converter 220 may map each of the query operators in the query plan to a specific set of operator logic (e.g., computational logic or computer code). When generating the operator logic for each of the query operators in the query plan, a combined set of operator logic is generated that represents a query program for executing the query 210.

[0078] In step 506, an executable file is generated for the hardware chip based on at least the expression set corresponding to the operator logic. In an example, the hardware chip is configured to execute at least part of the expression set in parallel. For example, referring to Figure 2 The program generator 218 is configured to obtain a query program for executing the query 210 and generate an executable file for a specific hardware chip (eg, the APU 106) based at least on a set of expressions corresponding to the operator logic.

[0079] For example, program generator 218 may first identify the target processing architecture of APU 106 on which the query is to be executed. The identification of the target processing architecture may be based on inputs present in query 210. In another example, the identification may be automatically determined (e.g., based on device availability, current resource usage of the device, etc.). After identifying the target processing architecture (e.g., accelerator 206), program generator 218 may identify expressions corresponding to each operator logic in the query program. In an example, the expressions may be generated in a manner specific to the target processing architecture. For example, if the target processing architecture is accelerator 206, the expressions corresponding to the operator logic in the query program may be accelerator-specific expressions that will be executed by accelerator 206 rather than CPU 208. In some examples, the target architecture of APU 106 is configured to execute at least a portion of the expression set in parallel (e.g., using multiple threads, etc.) to improve performance. In other words, the expressions may be generated in a manner that takes advantage of the advantageous features of the processing architecture of the target hardware chip (e.g., parallel processing capabilities), thereby improving query execution. Upon generating the expression, the program generator 218 generates an executable file for transmission to the query program executor 202 .

[0080] As discussed above, in example implementations, executable files may be generated in various ways. For example, Figure 6 600 is a flowchart of a method for generating an executable file based on a machine learning framework according to an example embodiment. Figure 2 The system 200 shown here is implemented. Therefore, reference will continue to be made to Figure 2 Describe the flow chart 600. Based on the following Figure 2 From the discussion of flowchart 600 and system 200 , other structural and operational embodiments will be apparent to those skilled in the relevant art(s).

[0081] Flowchart 600 begins at step 602. In step 602, an executable file is generated based on a machine learning framework that converts a query into an executable file. For example, plan converter 220 and / or program generator 218 may include one or more machine learning frameworks configured to convert a query plan generated by optimizer 216 into an executable file that can be executed by the processing architecture of APU 106. In some implementations, the machine learning framework is configured to utilize machine learning techniques to generate a neural network program.

[0082] III. Additional Example Query Execution Embodiments A. Introduction

[0083] The following sections are intended to describe additional example embodiments in which the implementations described herein may be provided. Furthermore, the following sections explain additional context for such example embodiments, implementation-related details, and evaluations of such implementations. The following sections are intended to illustrate various aspects and / or benefits that may be achieved based on the techniques described herein and are not intended to be limiting. Therefore, while additional example embodiments are described, it should be understood that not all implementations require the features and evaluations described below.

[0084] In an example query processing embodiment, the techniques may be implemented by one or more of the computing device 102, the query processor 104, the APU 106, the query processing engine 108, the shared memory 110, the server 114, the query workload system 116, the executable query generator 118, the query program executor 202, the result communicator 204, the accelerator 206, the CPU 208, the query 210, the parser 214, the library 214, the optimizer 216, the program generator 218, or the plan converter 22 (including any subcomponents thereof). Other structural and operational implementations will be apparent to those skilled in the relevant art(s) based on the following discussion.

[0085] Disclosed herein are example embodiments for implementing query processing on a high-end chiplet device that integrates a CPU and a GPU. As described herein, such a chiplet device allows for improvements over traditional GPU implementations. For example, similar features as GPUs can be achieved without the disadvantage of having to transfer data over a PCIe bus.

[0086] To illustrate the capabilities available with these chiplet devices, example embodiments implement an extension of the Tensor Query Processor (TQP) that can be run on a console with a combined CPU / GPU (e.g., such as game consoles) with performance comparable to GPU implementations (e.g., P100GPU), but without the overhead of moving data from CPU memory to GPU memory. In the example, a combined CPU / GPU (e.g. Game console) is equipped with an Advanced Micro Drive with a memory bandwidth of approximately 550GB / s (AMD) CPU / GPU chiplets. For a selected set of queries (e.g., selected from the Transaction Processing Performance Council Benchmark H (TCPH)), improvements (e.g., in the 10x range) were achieved compared to other implementations (such as CPU-only solutions), while only slightly falling behind the performance of GPU implementations (e.g., P100). In addition, gaming consoles (e.g., ) can be implemented at cloud scale (e.g., due to cloud gaming products) to process SQL queries.

[0087] This paper describes additional details regarding the identification of a restricted set of query processing on CPUs and GPUs for analytical queries, highlighting CPU / GPU chiplets (e.g., combined CPU and GPU processor devices, also referred to herein as accelerated processing units (APUs)) for analytical workloads. Additional details regarding the performance of such devices are shown by running several selected TPCH queries on a gaming console, compared to a discrete GPU (P100) and CPU baselines.

[0088] B. Query Processing on CPU and GPU

[0089] In this section, we provide a qualitative evaluation of query processing (QP) for analytical queries on CPUs and GPUs. We describe some advantages and limitations of these hardware options with respect to QP.

[0090] Figure 7 Depicted is an example execution of an SQL query on different hardware backends with different memory bandwidth characteristics according to an example embodiment. In this example, it is assumed that the SQL query can be executed in three stages, each requiring a data scan, and each stage is memory-bound. If the query is executed on a CPU (denoted as "1" in the figure), the throughput of each stage can be expected to be approximately 300 GB / s, which can represent the maximum throughput achievable with double data rate (DDR) memory. In implementations, the CPU memory bandwidth is designed so that it aligns with the performance of each CPU core. For example, increasing the CPU memory bandwidth without increasing the number of CPU cores may result in insufficient bandwidth utilization. However, increasing the number of CPU cores can be expensive in implementation and therefore may not be cost-effective. For example, each CPU can consume approximately 10 GB / s of memory bandwidth. If the available memory bandwidth is increased (e.g., to 1 TB / s, such as by utilizing a Sapphire Rapids configuration with high-bandwidth memory (HBM)), at least hundreds of CPU cores may be required to achieve full utilization. Furthermore, synchronization overhead also increases with the number of CPU cores. Since each core executes independently, synchronization barriers between CPU cores can introduce increased overhead. Figure 3 Illustrated is an example system of how multiple cores can perform simple and value aggregation according to an example embodiment. Figure 8In the case of a CPU, an updated value from a register must pass through the Level 2 (L2) cache and be broadcast to other nodes (or otherwise provided to other nodes). This can trigger idle cycles for swapping between cache levels and applying other transaction protocols, such as cache coherence. In some implementations, some cache coherence protocols support cache-to-cache transfers at the Level 1 (L1) stage. In an implementation, coherence activity can be determined by application design, thread scheduling, and microarchitecture implementation.

[0091] We will now describe the QP on the GPU. Figure 7 In this case, the bandwidth of the HBM memory can be utilized in each stage, which is about an order of magnitude better than the CPU case. In the example, due to the design of the GPU, the GPU does not suffer the same synchronization overhead, and in fact, some GPU implementations can be equipped with hundreds of thousands of single instruction multiple thread (SIMT) cores. In some examples, such cores can be computationally weaker than CPU cores. Therefore, there can be a trade-off between single-thread performance and higher parallelism. Figure 9 As shown, which illustrates an example data synchronization on the GPU / APU in system 900), a group of threads in the GPU (typically 32 for NVIDIA or XBox, and 32 or 64 for AMD) form a single wavefront that executes the same instruction on each clock cycle. In this example, data computations within each wavefront are naturally synchronized without any additional overhead. It should also be noted that memory and control divergence can add additional overhead. In the example, different wavefronts within the same stream multiprocessor can share data through the L1 cache, which can be more efficient than the CPU through the L2 cache. In the example, data consistency can be controlled by the user program. One advantage of doing this is that it can potentially reduce or eliminate processor complexity that would otherwise require consistency to be guaranteed by transparent mechanisms. Finally, in some implementations, only data synchronization across stream multiprocessors requires the L2 cache. However, this approach is rarely used as long as the user program is efficiently designed to synchronize within each single wavefront or across multiple wavefronts within the same stream multiprocessor.

[0092] In some examples, GPUs can be optimized for throughput rather than single-threaded latency, as opposed to CPUs. Due to the hardware features described above, GPUs can outperform CPUs for data analytics workloads as long as the data fits into the (HBM) device memory. However, data is typically obtained from higher capacity locations, such as CPU memory, local or remote storage. This data copy operation may be required to go through a computer bus (e.g., a PCIe bus) that has limited bandwidth compared to both device and host memory. It is also important to note that, as opposed to transactional workloads, analytical workloads are mostly read-only, so the lack of hardware support for consistency is not a problem in the example implementation.

[0093] Now we will describe the CPU / GPU chiplet device. The first example is Figure 7 These devices may include similar or identical memory bandwidth to the CPU, leading to similar limitations as the CPU-only QP. In fact, a GPU may be used for computation here, but typically, such a GPU may be limited by memory bandwidth in some implementations. However, in Figure 7 In other CPU / GPU chiplet devices, represented as "6" in the figure, these limitations can be reduced or even avoided. Examples of such chiplet devices include, but are not limited to, Apple M1, AMD MI300, and game consoles (such as Xbox). In this case, the QP can take advantage of the high bandwidth of HBM memory without being limited by the computer bus (e.g., PCIe). Additionally, these devices have sufficient computing power to take advantage of the high memory bandwidth and are not affected by the CPU synchronization overhead because the GPU's SIMT-based wavefront execution can be used to achieve low synchronization overhead. In some examples, each core of such a chiplet device is designed using only key computational instructions. Although the per-core performance may be weaker than a conventional CPU due to simple instructions, limited speculative execution, and / or lack of hyperthreading, more cores can be packaged in a single chip, thereby achieving better utilization of high memory bandwidth. Finally, in the example, synchronization between CPU and GPU data access is more flexible and can be much cheaper than data copying PCIe.

[0094] Other hardware configuration. While the example embodiments described herein relate to CPU and GPU implementations, it should be understood that other hardware configurations, such as FPGAs and process-in-memory (PIM) devices, may also be used for data analytics workloads. However, for the purposes of this disclosure, the implementation focuses on devices that: (i) are production-ready and / or deployable (or already deployed) in the cloud; (ii) are capable of storing reasonable data (10+GB in size) in memory; and (iii) should be able to execute SQL queries end-to-end (including operations such as joins, filters, and aggregations). Finally, some of the limitations described above with respect to CPU and GPU implementations may also apply to other devices (e.g., FPGAs may also rely on PCIe for data transfer, while PIM devices may have lower bandwidth switching operations).

[0095] C. Additional Details

[0096] Example Implementation . In an example, TQP can be integrated with Antares or another appropriate compiler for deep learning models that can tune and generate code kernels for different hardware. In some implementations, Antares (or another appropriate compiler) can be extended to support executing the code set on a game console. In an example implementation, each input query is first parsed and optimized (e.g., using Apache Spark). TQP can convert the physics plan generated after parsing and optimization into a tree consisting of programs (e.g., PyTorch programs), one program for each physics operator in the original plan. Use an appropriate package (e.g., PyTorch) to freeze the computational graph consisting of PyTorch programs. The frozen computational graph (e.g., in TorchScript format, etc.) is provided to different packages (e.g., Antares or another compiler / optimizer). The compiler / optimizer performs various techniques, such as fusion and / or tuning to generate the optimal program, and then the code generator produces the final executable file, which can be transferred to the game console for execution. In some implementations, this implementation is automatic (e.g., without user input).

[0097] Hardware Setup Table 1 shows an example experimental environment based on different hardware setups, representing the CPU, GPU, and APU. The CPU model is a Xeon E5-2690 v4, with two sockets, 14 cores per socket, and 28 threads. The host memory is a DD4 2400, consisting of eight banks. The GPU model is an NVIDIA Tesla P100 (PCIe), and the XBox model is a standard X-series.

[0098] Table 1: Example settings for CPU / GPU / A100

[0099]

[0100]

[0101] Table 2: TPCH end-to-end delay (SF=1)

[0102]

[0103] Table 3: PCIe-v3 occupation delay (SF=1)

[0104]

[0105] SQL execution delay . Table 2 shows the TPCH end-to-end latency in the example implementation, while Table 3 shows the latency ratio spent on PCIe (v3) data copying. In the example, the NVIDIA P100 may include relatively powerful computing power, but its high latency on the PCIe interface reduces its performance advantage over the TPCH. In some cases, such as TPCH-6, its performance on the Compute Unified Device Architecture (CUDA) can even be slower than execution on the CPU. On the other hand, APU-based devices (e.g., XBox Series X) do not have this limitation and outperform other devices in all cases in terms of end-to-end latency. However, when comparing the non-PCIe times of the P100 and XBox, the P100 actually performs faster because it has an advantage in memory bandwidth over the XBox, while computing power (GFLops) is a secondary factor that benefits SQL performance.

[0106] According to the disclosed technology, the APU architecture provides a more efficient solution by bringing the CPU and GPU closer together, thereby allowing SQL calculations to be performed without copying data between the CPU and GPU via PCIe. Moreover, through APU implementation, SQL can take advantage of GPU-inspired processor design to efficiently perform multi-threaded calculations without always accessing the cache L2. Moreover, when processing SQL data, memory bandwidth can be more critical than computing power (TFLops) because data scanning is the main bottleneck. IV. Example Mobile Device and Computer System Implementation

[0107] As described herein, the embodiments and any circuits, components and / or subcomponents thereof, as well as the flowcharts / flowcharts described herein (including portions thereof and / or other embodiments) may be implemented in hardware or hardware with any combination of software and / or firmware, including as computer program code (program instructions) configured to be executed in one or more processors and stored in a computer-readable storage medium, or as hardware logic / circuitry, such as in a system on a chip (SoC), a field programmable gate array (FPGA), and / or an application-specific integrated circuit (ASIC). A SoC may include an integrated circuit chip that includes one or more of a processor (e.g., a microcontroller, a microprocessor, a digital signal processor (DSP), etc.), memory, one or more communication interfaces, and / or other circuits and / or embedded firmware to perform its functions.

[0108] The embodiments disclosed herein may be implemented in one or more computing devices, which may be mobile (mobile devices) and / or stationary (stationary devices), and may include any combination of features of such mobile and stationary computing devices. Figure 10 Describes examples of computing devices in which embodiments may be implemented. Figure 10 A block diagram of an exemplary computing environment 1000 is shown that includes a computing device 1002. The computing device 1002 is Figure 1 1002 and / or server 114, which may include one or more of the components of computing device 1002. In some embodiments, computing device 1002 communicates with devices external to computing environment 1000 via network 1004. Figure 10 1002 is communicatively coupled to a network (not shown). Network 1004 includes one or more networks, such as a local area network (LAN), a wide area network (WAN), an enterprise network, the Internet, etc., and may include one or more wired and / or wireless components. Network 1004 may additionally or alternatively include a cellular network for cellular communications. Computing device 1002 is described in detail below.

[0109] The computing device 1002 can be any of various types of computing devices. For example, the computing device 1002 can be a mobile computing device, such as a handheld computer (e.g., a personal digital assistant (PDA)), a laptop computer, a tablet computer (e.g., an Apple iPad), or a tablet computer. TM ), hybrid devices, notebook computers (e.g., Google Chromebook from Google LLC TM ), netbooks, mobile phones (e.g., cellular phones, such as Apple Inc. Smart phones, etc. AndroidTM operating system, etc.), wearable computing devices (e.g., head-mounted augmented reality and / or virtual reality devices, including smart glasses, such as Glass TM Oculus, Facebook Technologies LLC The computing device 1002 may alternatively be a stationary computing device, such as a desktop computer, a personal computer (PC), a stationary server device, a minicomputer, a mainframe computer, a supercomputer, etc.

[0110] like Figure 10 As shown, computing device 1002 includes various hardware and software components, including a processor 1010, storage 1020, one or more input devices 1030, one or more output devices 1050, one or more wireless modems 1060, one or more wired interfaces 1080, a power supply 1082, a location information (LI) receiver 1084, and an accelerometer 1086. Storage 1020 includes memory 1056 and storage device 1090, with memory 1056 including non-removable memory 1022 and removable memory 1024. Storage 1020 also stores an operating system 1012, applications 1014, and application data 1016. Wireless modem(s) 1060 include a Wi-Fi modem 1062, a Bluetooth modem 1064, and a cellular modem 1066. Output device(s) 1050 include a speaker 1052 and a display 1054. Input device(s) 1030 include a touch screen 1032, a microphone 1034, a camera 1036, a physical keyboard 1038, and a trackball 1040. Figure 10 All components of the computing device 1002 shown are present in all embodiments, in certain embodiments, additional components not shown may be present, and any combination of these components may be present. These components of the computing device 1002 are described below.

[0111] A single processor 1010 (e.g., a central processing unit (CPU), a microcontroller, a microprocessor, a signal processor, an ASIC (application-specific integrated circuit), and / or other physical hardware processor circuit) or multiple processors 1010 may be present in the computing device 1002 to perform tasks such as program execution, signal encoding, data processing, input / output processing, power control, and / or other functions. The processor 1010 may be a single-core or multi-core processor, and each processor core may be single-threaded or multi-threaded (to provide multiple execution threads concurrently). The processor 1010 is configured to execute program code stored in a computer-readable medium, such as the program code of an operating system 1012 and application programs 1014 stored in a storage device 1020. The program code is configured to cause the processor 1010 to perform operations, including the processes / methods disclosed herein. The operating system 1012 controls the allocation and use of components of the computing device 1002 and provides support for one or more application programs 1014 (also referred to as "applications" or "apps"). Applications 1014 may include general computing applications (e.g., email applications, calendars, contact managers, web browsers, messaging applications), other computing applications (e.g., word processing applications, mapping applications, media player applications, productivity suite applications), one or more machine learning (ML) models, and applications related to the embodiments disclosed elsewhere herein.

[0112] Any component in computing device 1002 may communicate with any other component depending on the functionality, although not all connections are shown for ease of illustration. Figure 10 As shown, bus 1006 is a multi-signal line communication medium (e.g., conductive traces in silicon, metal traces along a motherboard, wires, etc.) that may be present to communicatively couple processor 1010 to various other components of computing device 1002, although in other embodiments, alternative buses, other buses, and / or one or more individual signal lines may be present to communicatively couple components. Bus 1006 represents one or more bus structures of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures.

[0113] Storage 1020 is a physical storage device that includes one or both of memory 1056 and storage device 1090, which stores operating system 1012, application programs 1014, and application data 1016 according to any distribution. Non-removable storage 1022 includes one or more of RAM (random access memory), ROM (read only memory), flash memory, a solid-state drive (SSD), a hard disk drive (e.g., a disk drive for reading from and writing to a hard disk), and / or other physical memory device types. Non-removable storage 1022 may include main memory and may be separate from processor 1010 or fabricated in the same integrated circuit as processor 1010. Figure 10 As shown, non-removable memory 1022 stores firmware 1018, which may be present to provide low-level control of the hardware. Examples of firmware 1018 include BIOS (Basic Input / Output System, such as on a personal computer) and boot firmware (e.g., on a smartphone). Removable memory 1024 can be inserted into a socket on computing device 1002 or otherwise coupled to computing device 1002 and can be removed from computing device 1002 by a user. Removable memory 1024 can include any suitable removable memory device type, including an SD (Secure Digital) card, a Subscriber Identity Module (SIM) card well known in the GSM (Global System for Mobile Communications) communication system, and / or other removable physical memory device types. One or more storage devices in storage device 1090 can be present inside and / or outside the housing of computing device 1002 and can be removable or non-removable. Examples of storage device 1090 include a hard drive, an SSD, a thumb drive (e.g., a USB (Universal Serial Bus) flash drive), or other physical storage devices.

[0114] One or more programs may be stored in storage device 1020. Such programs include operating system 1012, one or more application programs 1014, and other program modules and program data. For example, examples of such applications may include computer program logic (e.g., computer program code / instructions) for implementing one or more of the following: query processor 104, query processing engine 108, query workload system 116, executable query generator 118, query program executor 202, result communicator 204, library 214, parser 212, optimizer 216, program generator 218, and / or plan converter 220, and any components and / or subcomponents thereof, and any other features (including portions thereof) illustrated and / or described herein, and / or other examples described herein.

[0115] The storage device 1020 also stores data used and / or generated by the operating system 1012 and the application programs 1014 as application data 1016. Examples of application data 1016 include web pages, text, images, tables, sound files, video data, and other data, which may also be sent to and / or received from one or more network servers or other devices via one or more wired or wireless networks. The storage device 1020 may be used to store other data, including subscriber identifiers (such as an International Mobile Subscriber Identity (IMSI)) and device identifiers (such as an International Mobile Equipment Identity (IMEI)). Such identifiers may be transmitted to a network server to identify the user and device.

[0116] A user may enter commands and information into the computing device 1002 through one or more input devices 1030 and may receive information from the computing device 1002 through one or more output devices 1050. The input device(s) 1030 may include one or more of a touch screen 1032, a microphone 1034, a camera 1036, a physical keyboard 1038, and / or a trackball 1040, and the output device(s) 1050 may include one or more of a speaker 1052 and a display 1054. Each of the input device(s) 1030 and the output device(s) 1050 may be integrated with the computing device 1002 (e.g., built into the housing of the computing device 1002) or external to the computing device 1002 (e.g., communicatively coupled to the computing device 1002 via wired or wireless interface(s) 1080 and / or wireless modem(s) 1060). Other input devices 1030 (not shown) may include a natural user interface (NUI), a pointing device (computer mouse), a joystick, a video game controller, a scanner, a touchpad, a stylus, a voice recognition system for receiving voice input, a gesture recognition system for receiving gesture input, and the like. Other possible output devices (not shown) may include piezoelectric or other tactile output devices. Some devices may provide more than one input / output function. For example, a display 1054 may display information and operate as a touch screen 1032 by receiving user commands and / or other information as a user interface (e.g., by touch, finger gestures, a virtual keyboard, etc.). There may be any number of each type of input device(s) 1030 and output device(s) 1050, including multiple microphones 1034, multiple cameras 1036, multiple speakers 1052, and / or multiple displays 1054.

[0117] One or more wireless modems 1060 can be coupled to antenna(s) (not shown) of computing device 1002 and can support bidirectional communication between processor 1010 and devices external to computing device 1002 via network 1004, as will be understood by those skilled in the relevant art(s). Wireless modems 1060 are shown generally and can include a cellular modem 1066 for communicating with one or more cellular networks, such as a GSM network for data and voice communications within a single cellular network, between cellular networks, or between a mobile device and the Public Switched Telephone Network (PSTN). Wireless modems 1060 can also or alternatively include other radio-based modem types, such as a Bluetooth modem 1064 (also referred to as a "Bluetooth device") and / or a Wi-Fi modem 1062 (also referred to as a "wireless adapter"). Wi-Fi modem 1062 is configured to communicate with an access point or other long-range Wi-Fi-capable device according to one or more wireless network protocols based on the IEEE (Institute of Electrical and Electronics Engineers) 802.11 family of standards, which are commonly used for local area networking and Internet access for devices. The Bluetooth modem 1064 is configured to communicate with another Bluetooth-capable device in accordance with the Bluetooth short-range wireless technology standard(s), such as IEEE 802.15.1, and / or as managed by the Bluetooth Special Interest Group (SIG).

[0118] The computing device 1002 may also include a power supply 1082, an LI receiver 1084, an accelerometer 1086, and / or one or more wired interfaces 1080. Example wired interfaces 1080 include a USB port, an IEEE 1394 (FireWire) port, an RS-232 port, an HDMI (High-Definition Multimedia Interface) port (e.g., for connection to an external display), a DisplayPort port (e.g., for connection to an internal display), an audio port, an Ethernet port, and / or a USB port. The purpose and function of each of these ports are well known to those skilled in the relevant art(s). The wired interface(s) 1080 of the computing device 1002 provide a wired connection between the computing device 1002 and the network 1004, or when one or more devices / peripherals are external to the computing device 1002 (e.g., pointing device, display 1054, speakers 1052, camera 1036, physical keyboard 1038, etc.), provide a wired connection between the computing device 1002 and such devices / peripherals. The power supply 1082 is configured to provide power to each of the components of the computing device 1002 and may receive power from a battery internal to the computing device 1002 and / or from a power cord plugged into a power port (e.g., a USB port, an A / C power port) of the computing device 1002. LI receiver 1084 may be used for location determination of computing device 1002 and may include a satellite navigation receiver, such as a Global Positioning System (GPS) receiver, or may include other types of location determiners configured to determine the location of computing device 1002 based on received information (e.g., using cellular tower triangulation, etc.). Accelerometer 1086 may be present to determine the orientation of computing device 1002.

[0119] Note that the components shown for computing device 1002 are not required or all-inclusive, and those skilled in the art will recognize that fewer or greater numbers of components may be present. For example, computing device 1002 may also include one or more of a gyroscope, a barometer, a proximity sensor, an ambient light sensor, a digital compass, and the like. Processor 1010 and memory 1056 may be co-located in the same semiconductor device package, such as included together in an integrated circuit chip, an FPGA, or a system on a chip (SOC), optionally along with other components of computing device 1002.

[0120] In an embodiment, computing device 1002 is configured to implement any of the above features of the flowcharts herein. Computer program logic for performing any operations, steps, and / or functions described herein may be stored in storage 1020 and executed by processor 1010.

[0121] In some embodiments, server infrastructure 1070 may be present in computing environment 1000 and may be communicatively coupled to computing device 1002 via network 1004. Server infrastructure 1070, when present, may be a network-accessible set of servers (e.g., a cloud-based environment or platform). Figure 10 As shown, server infrastructure 1070 includes clusters 1072. Each cluster in clusters 1072 may include a set of one or more computing nodes and / or a set of one or more storage nodes. Figure 10As shown, cluster 1072 includes nodes 1074. Each of nodes 1074 is accessible via network 1004 (e.g., in a "cloud-based" embodiment) to build, deploy, and manage applications and services. Any of nodes 1074 may be a storage node, which includes a plurality of physical storage disks, SSDs, and / or other physical storage devices accessible via network 1004 and is configured to store data associated with the applications and services managed by node 1074. For example, Figure 10 As shown, node 1074 can store application data 1078.

[0122] As a computing node, each of the nodes 1074 may include one or more server computers, server systems, and / or computing devices. For example, the nodes 1074 may include one or more of the components of the computing device 1002 disclosed herein. Each of the nodes 1074 may be configured to execute one or more software applications (or "applications") and / or services, and / or manage hardware resources (e.g., processors, memory, etc.) that may be utilized by users (e.g., clients) of the set of network-accessible servers. For example, Figure 10 As shown, node 1074 can operate application 1076. In an implementation, one of nodes 1074 can operate or include one or more virtual machines, where each virtual machine emulates, in isolation, a system architecture (e.g., an operating system) on which applications such as application 1076 can execute.

[0123] In embodiments, one or more of clusters 1072 may be collocated (e.g., housed in one or more nearby buildings with associated components such as backup power, redundant data communications, environmental controls, etc.) to form a data center, or may be arranged in other ways. Thus, in embodiments, one or more of clusters 1072 may be a data center in a distributed collection of data centers. In embodiments, exemplary computing environment 1000 comprises portions of a cloud-based platform, such as Amazon Web Services Inc.'s Amazon Web Services. or Google Cloud Platform from Google LLC TM , although these are merely examples and are not intended to be limiting.

[0124] In embodiments, the computing device 1002 may access the application 1076 for execution in any manner, such as by a client application and / or a browser at the computing device 1002. Example browsers include Microsoft Windows®, available from Microsoft Corp. of Redmond, Washington. Mozilla Corp. in Mountain View, California Apple Inc. of Cupertino, California and Google LLC of Mountain View, California Chrome.

[0125] For network (e.g., cloud) backup and data security purposes, computing device 1002 may additionally and / or alternatively synchronize copies of application programs 1014 and / or application data 1016 to be stored at network-based server infrastructure 1070 as application programs 1076 and / or application data 1078. For example, operating system 1012 and / or application programs 1014 may include a file hosting service client, such as Microsoft Corporation's Amazon Simple Storage Service (Amazon S3) by Amazon WebService Inc. Dropbox Inc. Google Drive by Google LLC TM The file hosting service client is configured to synchronize applications and / or data stored in the storage device 1020 at the network-based server infrastructure 1070 .

[0126] In some embodiments, a local server 1092 may be present in computing environment 1000 and may be communicatively coupled to computing device 1002 via network 1004. Local server 1092, if present, is hosted within the organization's infrastructure and, in many cases, is physically located on-site at the organization's facility. Local server 1092 is controlled, managed, and maintained by the organization's IT (information technology) personnel or an IT partner. Application data 1098 may be shared by local server 1092 among the organization's computing devices (including computing device 1002, if part of the organization)) via the organization's local network and / or other networks accessible to the organization, including the Internet. Furthermore, local server 1092 may provide applications, such as application 1096, to the organization's computing devices (including computing device 1002). Thus, local server 1092 may include storage 1094 (including one or more physical storage devices, such as storage disks and / or SSDs) for storing application 1096 and application data 1098, and may include one or more processors for executing application 1096. Furthermore, computing device 1002 may be configured to synchronize copies of application programs 1014 and / or application data 1016 for storage at local server 1092 as backups of application programs 1096 and / or application data 1098 .

[0127] The embodiments described herein can be implemented in one or more of the computing device 1002, the network-based server infrastructure 1070, and the local server 1092. For example, in some embodiments, the computing device 1002 can be used to implement the systems, clients, or devices disclosed elsewhere herein, or components / subcomponents thereof. In other embodiments, a combination of the computing device 1002, the network-based server infrastructure 1070, and / or the local server 1092 can be used to implement the systems, clients, or devices disclosed elsewhere herein, or components / subcomponents thereof.

[0128] As used herein, the terms "computer program medium," "computer-readable medium," and "computer-readable storage medium" are used to refer to physical hardware media. Examples of such physical hardware media include any hard disk, optical disk, SSD, other physical hardware media such as RAM, ROM, flash memory, digital video disk, zip disk, MEM (microelectronic machine) memory, nanotechnology-based storage devices, and other types of physical / tangible hardware storage media of storage device 1020. Such computer-readable media and / or storage media are distinct from and do not overlap with communication media and propagated signals (excluding communication media and propagated signals). Communication media embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal (such as a carrier wave). The term "modulated data signal" means a signal in which one or more of its characteristics is set or changed in a manner that encodes information in the signal. By way of example and not limitation, communication media include wireless media such as acoustic, RF, infrared, and other wireless media; as well as wired media. Embodiments also relate to such communication media that are separate from and do not overlap with embodiments relating to computer-readable storage media.

[0129] As described above, computer programs and modules (including application programs 1014) can be stored in storage device 1020. Such computer programs can also be received over network 1004 via wired interface(s) 1080 and / or wireless modem(s) 1060. When executed or loaded by the application, such computer programs enable computing device 1002 to implement the features of the embodiments discussed herein. Thus, such computer programs represent controllers of computing device 1002.

[0130] Embodiments also relate to computer program products including computer code or instructions stored on any computer readable medium or computer readable storage medium.Such computer program products include the physical storage devices of storage device 1020 and other physical storage types.

[0131] V. Additional Example Embodiments

[0132] Disclosed herein is a system for processing queries. The system includes a processor and a memory device storing program code, the program code being configured to cause the processor to: receive query information for processing the query over a network; load a data set associated with the query into a shared memory by a first processing architecture; access the data set from the shared memory by a second processing architecture, the first processing architecture, the second processing architecture, and the shared memory being integrated into a hardware chip; process the query information based on the data set accessed from the shared memory using the second processing architecture to generate a query result; and provide the query result over the network.

[0133] In one implementation of the above system, the first processing architecture and the second processing architecture are implemented in a processing chip of a gaming console.

[0134] In another implementation of the above system, the first processing architecture includes a central processing unit (CPU) and the second processing architecture includes a graphics processing unit (GPU).

[0135] In another implementation of the above system, the query comprises a Structured Query Language (SQL) query.

[0136] In another implementation of the above system, the program code is configured to cause the processor to access the data through direct memory access to the shared memory using the second processing architecture.

[0137] In another implementation of the above system, accessing the data does not include transmitting the data between the first processing architecture and the second processing architecture over the communication bus.

[0138] In another implementation of the above system, the query information includes an executable file, which is generated based on a machine learning framework that converts the query into an executable file.

[0139] In another implementation of the above system, the query information includes an executable file, which is generated in the following manner: using a library to optimize the query to generate a query plan; traversing the query plan to generate a query program, which includes operator logic for each of a plurality of operators; and generating an executable file for a hardware chip based at least on an expression set corresponding to the operator logic, the hardware chip being configured to execute at least part of the expression set in parallel.

[0140] Disclosed herein is a method for processing a query. The method includes: receiving query information for processing the query over a network; loading a data set associated with the query into a shared memory by a first processing architecture; accessing the data set from the shared memory by a second processing architecture, wherein the first processing architecture, the second processing architecture, and the shared memory are integrated into a hardware chip; processing the query information based on the data set accessed from the shared memory using the second processing architecture to generate a query result; and providing the query result over the network.

[0141] In one implementation of the above method, the first processing architecture and the second processing architecture are implemented in a processing chip of a gaming console.

[0142] In another implementation of the above method, the first processing architecture includes a central processing unit (CPU), and the second processing architecture includes a graphics processing unit (GPU).

[0143] In another implementation of the above method, the query includes a Structured Query Language (SQL) query.

[0144] In another implementation of the above method, accessing the data includes accessing the data through direct memory access to the shared memory using the second processing architecture.

[0145] In another implementation of the above method, accessing the data does not include transmitting the data between the first processing architecture and the second processing architecture via a communication bus.

[0146] In another implementation of the above method, the query information includes an executable file, which is generated based on a machine learning framework that converts the query into an executable file.

[0147] In another implementation of the above method, the query information includes an executable file, which is generated in the following manner: using a library to optimize the query to generate a query plan; traversing the query plan to generate a query program, which includes operator logic for each of a plurality of operators; and generating an executable file for a hardware chip based at least on an expression set corresponding to the operator logic, the hardware chip being configured to execute at least part of the expression set in parallel.

[0148] Disclosed herein is a computer-readable storage medium having computer program code recorded thereon, which, when executed by at least one processor, causes the at least one processor to perform a method, the method comprising: receiving query information for processing a query over a network; loading a data set associated with the query into a shared memory by a first processing architecture; accessing the data set from the shared memory by a second processing architecture, the first processing architecture, the second processing architecture, and the shared memory being integrated into a hardware chip; processing the query information based on the data set accessed from the shared memory using the second processing architecture to generate a query result; and providing the query result over the network.

[0149] In one implementation of the above computer-readable storage medium, the first processing architecture includes a central processing unit (CPU), and the second processing architecture includes a graphics processing unit (GPU).

[0150] In another implementation of the above computer-readable storage medium, accessing the data includes accessing the data through direct memory access to the shared memory using the second processing architecture.

[0151] In another implementation of the above computer-readable storage medium, the query information includes an executable file, and the executable file is generated based on a machine learning framework that converts the query into an executable file.

[0152] VI. Conclusion

[0153] References in the specification to "one embodiment," "an embodiment," and "an example embodiment" indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered within the knowledge of those skilled in the art to affect such particular feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0154] In the discussion, unless otherwise stated, adjectives that modify the conditional or relational characteristics of one or more features of the implementation of the present disclosure should be understood to mean that the condition or characteristic is defined within an acceptable tolerance range for the implementation operation of the intended application. In addition, if the performance of an operation is described herein as being "responsive to" one or more factors, it should be understood that the one or more factors may be considered as the sole contributing factors that cause the operation to occur, or may be considered as contributing factors together with one or more additional factors that cause the operation to occur, and it should be understood that the operation may occur at or at any time after the establishment of the one or more factors. In addition, if "based on" is used to indicate that an effect is caused by a specified cause, it should be understood that the effect is not required to be caused by the specified cause alone, and any number of possible additional causes may also contribute to the effect. Therefore, as used herein, the term "based on" should be understood to be equivalent to the term "at least based on."

[0155] Many example embodiments have been described above. Any section / subsection headings provided herein are not intended to be limiting. Embodiments are described throughout this document, and any type of embodiment may be included under any section / subsection. Furthermore, embodiments disclosed in any section / subsection may be combined in any manner with any other embodiment described in the same section / subsection and / or in different sections / subsections.

[0156] Furthermore, the example embodiments have been described above with respect to one or more operational examples. Such operational examples describe one or more specific implementations of the example embodiments; however, the embodiments described herein are not limited to these specific implementations.

[0157] Moreover, in accordance with the described embodiments and techniques, any component of a system, computing device, server, device management service, virtual machine provider, application and / or data storage device and its functions can be activated to operate / execute based on other operations, functions, actions, etc., including the initialization, completion and / or execution of operations, functions and actions, etc.

[0158] In some example embodiments, one or more of the operations of the flowcharts described herein may not be performed. Moreover, operations may be performed in addition to or instead of the operations of the flowcharts described herein. Furthermore, in some example embodiments, one or more of the operations of the flowcharts described herein may be performed out of order, in an alternating order, or partially (e.g., or completely) concurrently with each other or other operations.

[0159] The embodiments described herein and / or any other systems, subsystems, devices, and / or components disclosed herein may be implemented in hardware (e.g., hardware logic / circuitry), or any combination of hardware and software (e.g., computer program code configured to be executed in one or more processors or processing devices) and / or firmware.

[0160] Although various embodiments have been described above, it should be understood that they are presented by way of example only and not limitation. It will be apparent to those skilled in the relevant art that various changes in form and detail may be made without departing from the spirit and scope of the embodiments. Therefore, the breadth and scope of the embodiments should not be limited by any of the foregoing exemplary embodiments.

Claims

1. A system for processing a query, the system comprising: processor; as well as a memory device storing program code configured to cause the processor to: receiving query information for processing the query via a network; loading, by the first processing architecture, a data set associated with the query into a shared memory; accessing the data set from the shared memory by a second processing architecture, wherein the first processing architecture, the second processing architecture, and the shared memory are integrated into a hardware chip; processing the query information based on the data set accessed from the shared memory using the second processing architecture to generate a query result; as well as The query result is provided via the network. 2 . The system of claim 1 , wherein the first processing architecture and the second processing architecture are implemented in a processing chip of a gaming console.

3. The system of claim 1, wherein the first processing architecture comprises a central processing unit (CPU) and the second processing architecture comprises a graphics processing unit (GPU).

4. The system of claim 1, wherein the query comprises a Structured Query Language (SQL) query. 5 . The system of claim 1 , wherein the program code is configured to cause the processor to access the data through direct memory access to the shared memory using the second processing architecture. 6 . The system of claim 5 , wherein the accessing of the data does not include transmitting the data between the first processing architecture and the second processing architecture over a communication bus.

7. The system of claim 1 , wherein the query information comprises an executable file, wherein the executable file is generated by: optimizing the query using a library to generate a query plan; traversing the query plan to generate a query program, the query program including operator logic for each of a plurality of operators; and The executable file is generated for the hardware chip based at least on a set of expressions corresponding to the operator logic, the hardware chip being configured to execute at least a portion of the set of expressions in parallel.

8. A method for processing a query, comprising: receiving query information for processing the query via a network; loading, by the first processing architecture, a data set associated with the query into a shared memory; accessing the data set from the shared memory by a second processing architecture, wherein the first processing architecture, the second processing architecture, and the shared memory are integrated into a hardware chip; processing the query information based on the data set accessed from the shared memory using the second processing architecture to generate a query result; as well as The query result is provided via the network.

9. The method of claim 8, wherein the first processing architecture and the second processing architecture are implemented in a processing chip of a gaming console.

10. The method of claim 8, wherein the first processing architecture comprises a central processing unit (CPU) and the second processing architecture comprises a graphics processing unit (GPU).

11. The method of claim 8, wherein the query comprises a Structured Query Language (SQL) query.

12. The method of claim 8, wherein the accessing the data comprises accessing the data via direct memory access to the shared memory using the second processing architecture.

13. The method of claim 8, wherein the query information comprises an executable file, the executable file being generated based on a machine learning framework that converts the query into the executable file.

14. The method according to claim 8, wherein the query information comprises an executable file, and the executable file is generated by: optimizing the query using a library to generate a query plan; traversing the query plan to generate a query program, the query program including operator logic for each of a plurality of operators; and The executable file is generated for the hardware chip based at least on a set of expressions corresponding to the operator logic, the hardware chip being configured to execute at least a portion of the set of expressions in parallel. 15 . A computer-readable storage medium having program instructions recorded thereon, the program instructions performing the method according to claim 8 when executed by a processor.

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