Reducing inductor peak current in DCDC digital controllers

Abstract

In an example, a voltage converter includes a pulse generator (134). The voltage converter also includes a high side transistor (106) having a gate coupled to the pulse generator (134), a source coupled to a first voltage terminal (116), and a drain coupled to an output node (110). The voltage converter includes a low-side transistor (108) having a gate coupled to the pulse generator (134), a source coupled to a second voltage terminal (118), and a drain coupled to the output node (110). The voltage converter includes a charge lookup table (130) coupled to the pulse generator (134), wherein the charge lookup table (130) is configured to provide a charge duration. The voltage converter includes a discharge lookup table (132) coupled to the pulse generator (134), wherein the discharge lookup table (132) is configured to provide a discharge duration. The voltage converter also includes a latch (128) coupled to the charge lookup table (130), wherein the latch (128) is configured to store an indication of a supply voltage.

Description

Background Art

[0001] A direct current (DC) to DC voltage converter receives an input voltage and converts it to an output voltage to drive a load. A DC-DC converter can be used as an on-chip voltage regulator in a microcontroller. A DC-DC converter can have higher power conversion efficiency than a low-dropout regulator, which reduces power consumption. Some systems with DC-DC converters, such as wireless transceivers, may need to meet power consumption requirements. Summary of the Invention

[0002] According to at least one example of the present disclosure, a voltage converter includes a pulse generator. The voltage converter further includes a high-side transistor having a gate coupled to the pulse generator, a source coupled to a first voltage terminal, and a drain coupled to an output node. The voltage converter includes a low-side transistor having a gate coupled to the pulse generator, a source coupled to a second voltage terminal, and a drain coupled to the output node. The voltage converter further includes a charge lookup table coupled to the pulse generator, wherein the charge lookup table is configured to provide a charge duration. The voltage converter includes a discharge lookup table coupled to the pulse generator, wherein the discharge lookup table is configured to provide a discharge duration. The voltage converter further includes a latch coupled to the charge lookup table, wherein the latch is configured to store an indication of a power supply voltage.

[0003] According to at least one example of the present disclosure, a method includes receiving a power-aware trigger in a voltage converter. The method includes performing a power-aware measurement in response to receiving the power-aware trigger, wherein the power-aware measurement determines a power supply voltage level. The method also includes storing an indication of the power supply voltage level in a latch. The method includes receiving a signal at a pulse generator to increase an output voltage of the voltage converter. The method also includes reading, by the pulse generator, the indication of the power supply voltage level stored in the latch. The method includes charging an output voltage using the pulse generator based at least in part on the indication of the power supply voltage level.

[0004] According to at least one example of the present disclosure, a system includes a pulse generator and a power-aware trigger generator, the power-aware trigger generator configured to trigger a power-aware measurement, wherein the power-aware measurement determines the difference between a power supply voltage level and an output voltage. The system also includes a high-side transistor having a gate coupled to the pulse generator, a source coupled to a first voltage terminal, and a drain coupled to an output node. The system also includes a low-side transistor having a gate coupled to the pulse generator, a source coupled to a second voltage terminal, and a drain coupled to the output node, wherein the high-side transistor and the low-side transistor generate the output voltage. The system also includes a charge lookup table coupled to the pulse generator, wherein the charge lookup table is configured to provide a charge duration based on the power-aware measurement and a peak current setting. The system also includes a discharge lookup table coupled to the pulse generator, wherein the discharge lookup table is configured to provide a discharge duration based on the peak current setting. The system also includes a latch coupled to the charge lookup table, wherein the latch is configured to store the power-aware measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a circuit schematic diagram of a system for controlling an inductor peak current in a DC-DC converter according to various examples.

[0006] Figure 2 is a collection of waveforms for DC-DC converters according to various examples.

[0007] Figure 3 is a block diagram of a system for controlling inductor peak current in a DC-DC converter according to various examples.

[0008] Figure 4 is a flow chart of a method for controlling an inductor peak current in a DC-DC converter according to various examples.

[0009] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (functionally and / or structurally) features. DETAILED DESCRIPTION

[0010] A DC-DC converter may need to meet industrial or commercial efficiency standards. In some DC-DC converters, a digital controller drives high-side transistors and low-side transistors that provide power to the inductive load. After the inductor charging phase begins, the DC-DC converter performs a power awareness (SA) measurement. The SA measurement includes a health check of a voltage supply, such as a battery. The SA measurement is performed so that the controller within the DC-DC converter can maintain the peak inductor current at a constant value, regardless of the power supply or battery voltage level during the inductor charging phase. In order to maintain a constant peak inductor current value, the SA measurement provides the DC-DC converter with multiple charging pulses used during the charging phase. However, during the time it takes to perform the SA measurement, the inductor current rises due to the controller charging the inductor. If the SA measurement takes too long, the rise in the inductor current results in lower power conversion efficiency.

[0011] In the examples herein, the SA measurement is decoupled from the inductor charging phase. Specifically, the DC-DC converter described herein triggers the SA measurement to determine the power supply voltage health at regular intervals, independent of the inductor charging phase performed by the DC-DC converter. The trigger rate for the SA measurement can be any suitable value and can be configurable. The SA measurement value is latched each time the SA measurement is performed, and the controller checks the latched SA value to determine the number of charging pulses or charging cycles for the inductor charging phase. Because the latched SA value is used during the inductor charging phase rather than performing the SA measurement, the charging time of the inductor can be as low as one clock cycle and is not dependent on the timing of the SA measurement.

[0012] In the examples presented here, the DC-DC converter achieves higher efficiency for a given inductor value compared to previous systems. This improved efficiency allows for lower device active power and Bluetooth Low Energy (BLE) radio transmit and receive power consumption targets. The solution also enables the use of smaller inductor values ​​for the DC-DC converter, as the peak current is adjustable. This also reduces bill of materials costs due to the use of smaller inductors. The SA trigger rate can be adjusted based on the type and variation of the power supply used. For example, a system with a noisy or inconsistent power supply may have a higher SA trigger rate than a system with a more stable power supply.

[0013] Figure 11 is a circuit diagram of a system 100 for controlling the peak current of an inductor in a DC-DC converter according to various examples herein. System 100 includes a digital controller 102 and an analog-to-digital converter (ADC) 104. System 100 includes a high-side transistor 106, a low-side transistor 108, and a switch output node (SW_OUT) 110. High-side transistor 106 and low-side transistor 108 can be field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), or any other suitable type of transistor. In this example, high-side transistor 106 is a p-type FET, and low-side transistor 108 is an n-type FET.

[0014] System 100 also includes an inductor 112 and a capacitor 114. Inductor 112 and capacitor 114 may be external to a device (such as a microchip or integrated circuit) that includes other components in system 100. In one example, inductor 112 may be coupled to SW_OUT node 110 via a device pin. An output voltage V may be provided between inductor 112 and capacitor 114. DDR In one example, the inductor 112 is approximately 10 microhenries (μH) and the capacitor 114 is approximately 10 microfarads (μF). In other examples, smaller value inductors, such as 4.7 μH or 2.2 μH, may be used because the peak current is adjustable. This helps reduce the overall material cost as described above. The system 100 also includes providing a voltage V BAT voltage terminal 116. In one example, V BAT The system 100 also includes a second voltage terminal that can be coupled to ground 118. The high-side transistor 106 has a source coupled to the voltage terminal 116, a drain coupled to the SW_OUT node 110, and a gate (or control terminal) coupled to the digital controller 102. The low-side transistor 108 has a source coupled to ground 118, a drain coupled to the SW_OUT node 110, and a gate (or control terminal) coupled to the digital controller 102.

[0015] The SA ADC 104 includes a voltage reference generator 120, a SA comparator (SA COMP) 122, and a SA ADC finite state machine (FSM) 124. In one example, the SA ADC FSM 124 is in the digital controller 102. The SA ADC FSM 124 may include any hardware, software, or digital logic configured to implement the actions described herein. The SA ADC FSM 124 generates an output code (described below) based on input received from the SA COMP 122. In other examples, the functions of the SA ADC FSM 124 may be performed by software, digital logic, circuitry, etc. The voltage reference generator 120 includes a circuit that receives a voltage V BATThe input and reference voltage V REF In one example, V REF The voltage reference generator 120 can be an internal bandgap reference voltage. BAT Voltage provided V REF The SACOMP 122 includes a voltage converter that receives the voltage V from the voltage reference generator 120. REF The first comparator input (eg, non-inverting input) of SA COMP 122 includes a first comparator input (eg, non-inverting input) receiving a voltage V DDR The second comparator input (eg, inverting input) is V DDR is the voltage provided by the system 100 at the output between the inductor 112 and the capacitor 114. SA COMP 122 includes a comparator output coupled to the SA ADC FSM 124. SACOMP 122 converts the voltage V REF With V DDR The voltage difference is compared and the difference is provided to the SA ADC FSM 124. The SA ADC FSM 124 receives the voltage difference and generates a code indicating the voltage difference. The voltage difference is V DDR should be raised to match V REF The code may be stored and used as described below to determine the voltage provided by the pulse generator 134 to match V DDR Increase to V REF The amount of charging pulses.

[0016] The digital controller 102 includes an ADC trigger generation block 126, a latch 128, a charge lookup table (CHG LUT) 130 (e.g., a data structure stored in memory), a discharge LUT (DSG LUT) 132 (e.g., a data structure stored in memory), and a pulse generator 134. The ADC trigger generation block 126 includes a first input that receives a high-speed clock (e.g., a 48 MHz clock in one example). This clock can be the system clock or can be generated by the system clock. The ADC trigger generation block 126 includes a second input that receives an SA trigger (SA_TRIG) signal 136. The ADC trigger generation block 126 includes an output that provides an ADC trigger signal 138, which is provided to the SA ADC FSM 124 and the latch 128. The latch 128 also receives a signal from the SA ADC FSM 124. This signal is SA_ADC_OUT 125. The SA ADC FSM 124 receives V from the SA COMP 122. REF With V DDR The difference between the two values ​​is calculated, and then the SA ADC FSM 124 provides the code SA_ADC_OUT 125 to the latch 128. The SA ADC FSM 124 may include a code corresponding to V REFWith V DDR The SAADC FSM 124 can store various difference codes between the two, and the ... REF With V DDR The correct code, SA_ADC_OUT 125, is selected based on the difference between the two codes and provided to latch 128. In one example, SA_ADC_OUT 125 is an eight-bit code, but in other examples, codes of other sizes may be useful. Latch 128 stores the SA_ADC_OUT 125 code, which may be provided to CHG LUT 130 by any suitable internal circuitry. CHG LUT 130 also receives a peak current code (IPEAK_CODE) 140. IPEAK_CODE 140 may be any number of bits, and the code may be stored in CHG LUT 130. IPEAK_CODE 140 indicates to pulse generator 134 the peak allowable current through inductor 112 during charging operation. In an example, the user may set the peak allowable current. CHG LUT 130 is coupled to pulse generator 134 and provides an output to pulse generator 134. DSG LUT 132 also receives IPEAK_CODE 140. The DSG LUT 132 is also coupled to a pulse generator 134 and provides an output to the pulse generator 134. Based on the code and data stored in the CHGLUT 130 and the DSG LUT 132, the pulse generator 134 provides a P_CTRL signal 142 to the gate of the high-side transistor 106. The pulse generator 134 provides an N_CTRL signal 144 to the gate of the low-side transistor 108. During charging and discharging operations, the control signals 142 and 144 turn on and off the high-side transistor 106 and the low-side transistor 108, respectively. In one example, based on the code SA_ADC_OUT 125 and the IPEAK_CODE 140, the pulse generator 134 sends an appropriate number of pulses (e.g., control signals 142 and 144) to perform the step-up V DDR Until V DDR With V REF Matched charge and discharge operations.

[0017] The system 100 further includes a DCDC comparator (DCDC COMP) 146. The DCDC COMP 146 includes a circuit that receives V REF The first comparator input (eg, non-inverting input) receives V DDR The second comparator input (eg, the inverting input) of , and the comparator output that produces the DCDC_COMP_OUT signal 148. The DCDC_COMP_OUT signal 148 is provided to the pulse generator 134. This signal triggers a DC-DC charging pulse of the pulse generator 134, as described below.

[0018] System 100 also includes a zero-crossing comparator (ZC COMP) 150. ZC COMP 150 includes a first comparator input (e.g., a non-inverting input) coupled to SW_OUT node 110 and a second comparator input (e.g., an inverting input) coupled to ground 118. ZC COMP 150 generates a ZCC_OUT signal 152 at the comparator output. ZCC_OUT signal 152 is provided to DSG LUT 132. ZC COMP 150 also receives a clock (CLK) signal 154 from pulse generator 134. In an example, CLK signal 154 may enable ZC COMP 150.

[0019] In an example operation, V BAT The range is 1.7V to 3.8V. In this example, the system 100 regulates the output voltage V DDR To provide approximately 1.5V at the load. DCDC COMP 146 is an analog comparator. DCDC COMP 146 converts the output voltage V DDR is compared with a predetermined threshold, such as an internal bandgap reference V REF (approximately 1.5V in this example). System 100 operates to provide at least V DDR Therefore, if V DDR Equal to or higher than V REF , then the DCDC charging cycle is not performed by the pulse generator 134 because V DDR Provides at least the target voltage to the load. In some instances, if no charging operation is performed, V DDR will eventually decrease over time. However, if V DDR Lower than V REF , you need to increase V DDR If V DDR Lower than V REF , the DCDC_COMP_OUT 148 signal triggers the DCDC operation at the pulse generator 134. The pulse generator 134 provides signals P_CTRL 142 and N_CTRL 144 to the high-side transistor 106 and the low-side transistor 108, respectively, to turn the transistors on and off and perform charging and discharging operations until V DDR Reach V REF In one example, the pulse generator 134 may include a state machine ( Figure 1 ) to receive the DCDC_COMP_OUT 148 signal.

[0020] To charge the inductor 112, the top switch (high-side transistor 106) is turned on using P_CTRL 142. If the high-side transistor 106 is turned on, current flows through the inductor 112 and V DDR Increase (e.g., charging operation). If P_CTRL 142 is on, N_CTRL 144 is off, so the bottom switch (low-side transistor 108) is off. During the discharge operation, P_CTRL 142 is off and N_CTRL 144 is on. Therefore, during the discharge period, the high-side transistor 106 is off and the low-side transistor 108 is on. At this time, current flows through the inductor 112 and then flows through the low-side transistor 108 to ground 118 to discharge the inductor 112, thereby reducing V DDR .

[0021] For charging operations, the amount of time that the high-side transistor 106 is turned on is based on a value read by the pulse generator 134 from the CHG LUT 130. Specifically, after the pulse generator 134 receives the DCDC_COMP_OUT 148 signal (which triggers the pulse generator 134 to control the high-side transistor 106 and the low-side transistor 108), the pulse generator 134 reads a value from the CHG LUT 130 to determine how long to keep P_CTRL 142 turned on. The digital controller 102 includes any suitable hardware, software, or digital logic for performing the actions described herein. The selection from the CHG LUT 130 depends on two inputs: the peak current setting IPEAK_CODE 140 and the SA_ADC_OUT 125 signal provided by the latch 128. The CHG LUT 130 stores the duration that the high-side transistor 106 remains on during the charging operation. The duration is based at least in part on the peak inductor current and V DDR With V BAT For the discharge operation, the time during which the low-side transistor 108 is turned on depends on the IPEAK_CODE 140 and can be read from the DSG LUT 132 by the pulse generator 134 .

[0022] For charging operations, the previous system performs a SA ADC measurement at the start of the charging operation. The SA ADC measurement performs a health check to determine if the battery is healthy enough to perform a charging operation. BAT One purpose is to keep the peak current flowing through the inductor 112 at a constant value with V BATA constant value that is independent of the level. In these previous systems, performing a SA ADC measurement takes a specific number of clock cycles (e.g., 11 clock cycles). When performing a SA ADC measurement, the current through the inductor increases due to the pulse generator performing a charging operation. Therefore, due to the time it takes to complete the SA ADC measurement, the minimum peak current through the inductor can be as high as 55 mA. This high peak current limits the efficiency of the DC-DC converter.

[0023] In the examples described herein, rather than performing SA ADC measurements at the start of each charging operation, SA ADC measurements are triggered at regular intervals via the SA_TRIG signal 136. These regular intervals are independent of the charging operation. In one example, software (e.g., provided by the digital controller 102 or Figure 2 The rate at which the SA ADC measurements are triggered (executed by another processor or controller not shown) can control the rate. The rate may depend on the nature of the power supply and its variations. In an example, a digital counter-based approach is implemented in controller 102, which pre-scales the source clock based on the SA ADC measurement rate to generate a periodic trigger (e.g., a 48 MHz clock provided to ADC trigger generation block 126). The trigger rate can be configured to any value or predetermined interval (e.g., every 1 microsecond (μs), 2 μs, 5 μs, 10 μs, etc.). In one example, the trigger rate is user-configurable. Whenever an SA ADC value is found, it is stored in latch 128. During charging operation, the latched value in latch 128 is read by CHGLUT 130 to determine the number of charge cycles for the configured peak current setting (IPEAK_CODE 140). Because the latched value is used instead of performing a new SA ADC measurement, the charge time can be as low as one cycle and is independent of the SA ADC measurement time.

[0024] In one example, CHG LUT 130 stores a set of different values. In one example, IPEAK_CODE 140 can be a 3-bit setting (eight different values). The user can set IPEAK_CODE 140 and fix the maximum peak current that can flow into inductor 112. For each of the eight peak current setting combinations and the SA_ADC_OUT 125 code, pulse generator 134 or other logic or circuitry selects a charge value from CHG LUT 130 when a charging operation is initiated. A similar process occurs for the discharge duration using DSG LUT 132. Therefore, the charge time is based on the SA_ADC_OUT 125 code and IPEAK_CODE 140. The discharge time from DSG LUT 132 is based on IPEAK_CODE 140. LUTs 130 and 132, respectively, store times that determine how long the high-side transistor 106 and low-side transistor 108 are turned on for charging and discharging operations.

[0025] System 100 also includes a ZC COMP 150. In an example, after a discharge operation and a short delay (e.g., 20 ns), ZC COMP 150 is turned on by pulse generator 134 or by another signal from controller 102. In one example, CLK 154 can turn on ZC COMP 150. If the current through inductor 112 crosses zero, the output (ZCC_OUT 152) of ZC COMP 150 switches. Thus, ZC COMP 150 detects whether the inductor 112 current is above or below zero at the end of the discharge operation. A high ZCC_OUT 152 indicates that the inductor 112 current is positive, and a low ZCC_OUT 152 indicates that the inductor 112 current is negative. ZCC_OUT 152 is provided to DSG LUT 132. If ZCC_OUT 152 is high, the discharge time is increased by one clock cycle for the next discharge operation by updating DSG LUT 132. If ZCC_OUT 152 is low, the discharge time is reduced by one clock cycle for the next discharge operation by updating DSG LUT 132. The operation of ZC COMP 150 allows the inductor 112 current to move closer to zero for each subsequent discharge cycle.

[0026] As compared to Figure 1As described, the SA ADC measurement is triggered to check the voltage supply health at regular intervals independently of the inductor charging operation. The trigger rate can be configurable, as described above. If the voltage supply changes rapidly, a faster trigger rate can be selected. The SA ADC measurement output value is latched at the end of each measurement. The CHG LUT 130 reads the latched value (in latch 128) to determine the number of charging cycles for a given peak current setting (IPEAK_CODE 140). In the examples herein, the charging time can be as little as one cycle and is independent of the time taken for the SA ADC measurement. In one example, using a 4.7 μH inductor and a 10 milliampere (mA) load current, the efficiency can be improved from 80.9% to 86.4%.

[0027] Figure 2 is a collection of waveforms 200 for a DC-DC converter according to various examples herein. Waveforms 200 are the waveforms described above with respect to Figure 1 Example waveforms of the different signals described.

[0028] Figure 2 A clock signal (CLK) 202 is included. Figure 2 Also included is a SA_TRIG signal 204 and a SA_ADC_OUT code 206 . Figure 2 A charge time (CHG_TIME) 208 and a discharge time (DSG_TIME) 210 are included, which indicate the number of clock cycles for the charge and discharge operations described above, respectively. Figure 2 Also included is a load current (L_CURRENT) 212 , which is the current through the inductor 112 .

[0029] In this example, the charge and discharge times (and therefore the inductor 112 current) are decoupled from the SA ADC measurement. At time t0, the charging operation begins, and L_CURRENT 212 begins to rise. In this example, the charge time 208 is 5, so the charging operation lasts for 5 clock cycles (CLK 202). At the beginning of the charging operation, the charge time 208 is retrieved from the CHG LUT 130, and the CHG LUT 130 retrieves the SA_ADC_OUT code from the latch 128. In this example, the charge time 208 remains at 5 because the power supply voltage is stable. In this example, the SA_ADC_OUT code is 0 at time t0 (waveform 206).

[0030] At time t1, the discharge operation begins, and L_CURRENT 212 begins to decrease. DSG_TIME is 8 (waveform 210), so the discharge operation will last for 8 clock cycles. At time t5, the discharge operation is complete, and another charge operation begins. At time t5, L_CURRENT 212 begins to rise. CHG_TIME 208 is still 5 clock cycles at time t5, so this charge operation also lasts for 5 clock cycles. At time t6, another discharge operation begins, and L_CURRENT 212 begins to decrease.

[0031] In this example, at time t3, the discharge time is updated from 8 clock cycles to 7 clock cycles. As described above, ZC COMP 150 increases or decreases the discharge time by one clock cycle for the next discharge operation by updating DSG LUT 132. In this example, the updated discharge time occurs at time t3. Therefore, for the next discharge cycle (starting at time t6), the discharge cycle will last for 7 clock cycles.

[0032] Figure 2 The SA trigger operation (waveform 204) is also shown. SA_TRIG is decoupled from the charge and discharge cycles and occurs at a time specified by the trigger rate (e.g., every 1 μs, 2 μs, etc.). In this example, the SA trigger operation occurs at time t2, as shown in waveform 204. Figure 2 As shown in FIG, the charge and discharge cycles of waveform 212 are independent of the timing of the SA trigger in waveform 204. The SA trigger in waveform 204 initiates the SA ADC measurement, which checks the health of the voltage supply and updates the SA_ADC_OUT 125 code stored in latch 128. Here, SA_ADC_OUT (waveform 206) is updated at time t4. In this example, the SA_ADC_OUT value remains at 0 at time t4, indicating that the voltage supply is stable compared to the previous SA_ADC_OUT value. Therefore, the charge time (waveform 208) remains at time t6 for 5 clock cycles. If the health of the voltage supply has changed and the SA_ADC_OUT value has also changed (e.g., from 0 to 1), the charge time will be updated to the new charge time at time t6.

[0033] Figure 2 This example demonstrates that the SA ADC measurement and SA_ADC_OUT 125 code are updated independently of the charge and discharge operations. The charge and discharge operations use the clock cycle counts stored in the LUTs 130 and 132, respectively. The charge time is read from the CHG LUT 130 at the beginning of each charge cycle, without waiting for the SA ADC measurement to complete. This example improves the efficiency of the DC-DC converter.

[0034] Figure 3 is a block diagram of a system 300 for controlling peak inductor current in a DC-DC converter according to various examples herein. Some components of the system 300 are described above with respect to Figure 1 Description, and like numbers represent like components.

[0035] System 300 includes a controller 102 and a SA ADC 104. In one example, the components in controller 102 can be implemented in hardware, software, or digital logic. Controller 102 includes a latch 128, a lookup table (LUTS) 302, and a pulse generator 134. Latch 128 stores the SA_ADC_OUT code provided by SA ADC 104. LUTS 302 can include charge and discharge times, which can be stored in any number of tables in any suitable format. Pulse generator 134 provides pulses to high-side (HS) transistor 106 and low-side (LS) transistor 108. The number of pulses used for charging and discharging operations is found in LUTS 302. HS 106 and LS 108 provide current to load 304, which can be an inductive load.

[0036] Figure 4 4 is a flow chart of a method 400 for controlling an inductor peak current in a DC-DC converter according to various examples herein. The steps of method 400 may be performed in any suitable order. In some examples, any suitable hardware or digital logic may perform method 400. In some examples, the components described above in system 100 may perform method 400.

[0037] Method 400 begins at 410, where the voltage converter receives a power sense (SA) trigger. In one example, the SA trigger (e.g., SA_TRIG 126) is provided at predetermined intervals, such as every 1 μs. Any suitable software, digital hardware, processor, or controller can provide the SA trigger.

[0038] Method 400 continues at 420, where, in response to receiving a power-aware trigger, SA ADC 104 performs a power-aware measurement, wherein the power-aware measurement determines the power supply voltage level. In one example, SA ADC 104 determines a code that provides an indication of the health of the power supply or battery voltage. The code may be based on the difference between the power supply voltage and the output voltage of the DC-DC converter. The code is used to select a number of charge cycles for the DC-DC converter. In one example, the code may be SA_ADC_OUT 125.

[0039] Method 400 continues at 430 where an indication of the power supply voltage level is stored in a latch. In one example, the latch can be latch 128, and in one example, the stored indication can be SA_ADC_OUT 125.

[0040] Method 400 continues at 440 where a pulse generator receives a signal to increase the output voltage of the voltage converter. In one example, the pulse generator can be pulse generator 134. The pulse generator can receive the signal because the output voltage has dropped below a predetermined threshold.

[0041] Method 400 continues at 450, where the pulse generator reads the indication of the power supply voltage level stored in the latch. In one example, the pulse generator can retrieve the charge cycle number from a lookup table, such as CHG LUT 130. CHG LUT 130 can read the indication of the power supply voltage level stored in latch 128 and then provide the charge cycle number to the pulse generator, where the charge cycle number is based at least in part on the indication of the power supply voltage level.

[0042] Method 400 continues at 460, where the pulse generator charges the output voltage based at least in part on the indication of the power supply voltage level. The pulse generator charges the output voltage with a specific number of charging pulses or charging cycles based on the indication of the power supply voltage level as described above. In one example, the number of charging pulses may also be based at least in part on a peak current code, such as IPEAK_CODE 140.

[0043] In the example presented herein, SA ADC measurements are triggered to check the voltage supply health at regular intervals, independent of the inductor charging operation. This allows the DC-DC converter to achieve higher efficiency for a specific inductor value. The improved efficiency helps achieve lower device active power and meet power consumption targets. The solution also enables the DC-DC converter to use smaller inductor values, as the peak current can be adjusted by the user. The SA trigger rate can also be adjusted based on the type and variation of the power supply used in the end application.

[0044] As used herein, the term "coupled" may encompass any connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first instance, device A is directly connected to device B; or (b) in a second instance, device A is coupled to device B through an intermediate component C, if the intermediate component C does not modify the functional relationship between device A and device B, such that device B is controlled by device A via the control signal provided by device A.

[0045] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may occur through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0046] Circuits or devices described herein as including certain components may alternatively be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources to form the described structure during manufacture or after manufacture, for example, by an end user and / or a third party.

[0047] Although certain components may be described herein as belonging to a specific process technology, these components may be exchanged for components of other process technologies. The circuits described herein may be reconfigured to include replaced components to provide functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0048] The use of the phrase "ground" in the foregoing description encompasses chassis ground, ground line ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection suitable or applicable to the teachings of this specification. Throughout this specification, unless otherwise indicated, the term "approximately," "substantially," or "substantially" preceding a parameter means within a range of + / - 10% of the parameter. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. A voltage converter comprising: Pulse generator; a high-side transistor having a gate coupled to the pulse generator, a source coupled to the first voltage terminal, and a drain coupled to the output node; a low-side transistor having a gate coupled to the pulse generator, a source coupled to a second voltage terminal, and a drain coupled to the output node; a charge lookup table coupled to the pulse generator, wherein the charge lookup table is configured to provide a charge duration; a discharge lookup table coupled to the pulse generator, wherein the discharge lookup table is configured to provide a discharge duration; as well as A latch is coupled to the charge lookup table, wherein the latch is configured to store an indication of a power supply voltage.

2. The voltage converter according to claim 1 , further comprising: A trigger generator is configured to trigger the measurement of the power supply voltage.

3. The voltage converter according to claim 1 , further comprising: A comparator having a comparator output, a first comparator input, and a second comparator input, wherein the first comparator input is coupled to the output node, the second comparator input is coupled to a voltage reference generator, and the comparator output is coupled to the pulse generator.

4. The voltage converter according to claim 1 , further comprising: a comparator having a comparator output, a first comparator input, and a second comparator input, wherein the first comparator input is coupled to the output node, the second comparator input is coupled to the supply voltage, and the comparator output is configured to generate a difference between the supply voltage and an output voltage at the output node.

5. The voltage converter according to claim 1 , further comprising: A comparator having a comparator output, a first comparator input, and a second comparator input, wherein the first comparator input is coupled to the drain of the low-side transistor, the second comparator input is coupled to ground, and the comparator output is coupled to the discharge lookup table. 6 . The voltage converter of claim 1 , wherein the charge lookup table provides the charge duration based at least in part on a peak current setting and the supply voltage. 7 . The voltage converter of claim 1 , wherein the discharge lookup table provides the discharge duration based at least in part on a peak current setting.

8. A method comprising: receiving a power sense trigger in a voltage converter; In response to receiving the power aware trigger, performing a power aware measurement, wherein the power aware measurement determines a power supply voltage level; storing an indication of the supply voltage level in a latch; receiving, at a pulse generator, a signal that increases an output voltage of the voltage converter; reading, by the pulse generator, the indication of the power supply voltage level stored in the latch; as well as The output voltage is charged with the pulse generator based at least in part on the indication of the supply voltage level.

9. The method of claim 8, wherein charging the output voltage comprises turning on a transistor coupled to the pulse generator.

10. The method of claim 8, wherein the pulse generator charges the output voltage for a duration, wherein the duration is based at least in part on the indication of the supply voltage level. The method of claim 10 , wherein the duration is based at least in part on a peak current setting.

12. The method according to claim 8, further comprising: The output voltage is discharged with the pulse generator based at least in part on a peak current setting.

13. The method of claim 12, wherein discharging the output voltage comprises turning on a transistor coupled to the pulse generator. The method of claim 8 , wherein the power awareness trigger is received at predetermined intervals.

15. The method of claim 8, further comprising: The signal to increase the output voltage is received in response to the output voltage falling below a predetermined threshold.

16. The method of claim 8, wherein the indication of the supply voltage level comprises a difference between the supply voltage level and the output voltage.

17. The method of claim 8, wherein the power-aware trigger is decoupled from the pulse generator.

18. A system comprising: Pulse generator; a power-aware trigger generator configured to trigger a power-aware measurement, wherein the power-aware measurement determines a difference between a power supply voltage level and an output voltage; a high-side transistor having a gate coupled to the pulse generator, a source coupled to the first voltage terminal, and a drain coupled to the output node; a low-side transistor having a gate coupled to the pulse generator, a source coupled to a second voltage terminal, and a drain coupled to the output node, wherein the high-side transistor and the low-side transistor generate the output voltage; a charging lookup table coupled to the pulse generator, wherein the charging lookup table is configured to provide a charging duration based on the power-aware measurement and a peak current setting; a discharge lookup table coupled to the pulse generator, wherein the discharge lookup table is configured to provide a discharge duration based on the peak current setting; as well as A latch is coupled to the charging lookup table, wherein the latch is configured to store the power-aware measurement.

19. The system of claim 18, wherein the pulse generator is configured to charge the output voltage for the charging duration. 20 . The system of claim 18 , wherein the pulse generator is configured to charge the output voltage by turning on the high-side transistor.

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