Method for improving warping degree of silicon wafer

Abstract

The invention relates to the technical field of semiconductor material production, in particular to a method for improving the warping degree of a silicon wafer, which comprises the following steps of: optimizing an LPCVD (Low Pressure Chemical Vapor Deposition) process: reducing the film forming temperature to a target temperature range to reduce the film forming grain size, the grain boundary area, the interface energy and the grain boundary stress so as to reduce the warping degree of the silicon wafer; siH4 flow and film forming pressure are adjusted, the deposition rate is controlled, and stress concentration caused by too fast deposition is avoided; for a product with the LPCVD polycrystalline film thickness larger than or equal to 8000, the flatness is tested before LPCVD, a negative BOW product is turned over to be changed into positive Bow, and the flatness of the product is improved through the stress compensation effect in the deposition process; for a high-flatness product subjected to single-face grinding machining, annealing heat treatment is added after LPCVD, part of pressure is released, and the warp value of the product is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor material production, and in particular to a method for improving the warpage of a silicon wafer. Background Art

[0002] Silicon wafer warpage refers to the degree of bending and deformation of a silicon wafer under load. Silicon wafer warpage is typically characterized by the warp and bow parameters. In semiconductor manufacturing, wafer warpage (warp and bow) is a key factor affecting device performance and yield. Excessive warp and bow can lead to difficulties in photolithography alignment, uneven thin film deposition, and poor bonding, ultimately impacting device performance and reliability.

[0003] During silicon wafer processing, LPCVD significantly impacts wafer warpage. During high-temperature deposition, the difference in thermal expansion coefficients between the film and the wafer generates stress within the wafer. This stress in the polycrystalline film can lead to worsened warp and bow after wafer processing. As the deposited film thickness increases, the warpage of the wafer increases.

[0004] The present invention aims to optimize the processing technology and process flow for products processed by back-side LPCVD, thereby improving the warpage of silicon wafers. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies in the background technology and provide a method for improving the warpage of silicon wafers, thereby optimizing the processing technology and process flow and improving the warpage of silicon wafers.

[0006] The technical solution of the present invention is: A method for improving silicon wafer warpage, comprising: LPCVD process optimization: Lower the film formation temperature to the target temperature range to reduce the film grain size, grain boundary area, interfacial energy, and grain boundary stress, thereby reducing silicon wafer warpage; adjust the SiH4 flow rate and film formation pressure to control the deposition rate and avoid stress concentration caused by excessive deposition; For products with LPCVD polycrystalline film thickness ≥8000 Å, flatness is tested before LPCVD. Products with negative bow are flipped to become positive bow. The stress compensation effect during the deposition process is used to improve product flatness. For high-flatness products that have been processed by single-sided grinding, annealing heat treatment is added after LPCVD to release some of the pressure and reduce the warp value of the product.

[0007] Preferably, in the LPCVD process optimization, the target temperature range is controlled at 645±10°C, the SiH4 gas flow rate is 0.13-0.19 L / min, the film forming pressure is 15-35 Pa, and the deposition time is 20-60 min.

[0008] Preferably, the annealing heat treatment temperature is 650±30° C., and the heat treatment time is 30 min.

[0009] Compared with the prior art, the present invention has the following advantages: The present invention optimizes LPCVD process parameters, deposits on the reverse side of the negative BOW product, improves product flatness, anneals the single-sided ground product to reduce the warp value, and can effectively improve the warpage of the silicon wafer.

[0010] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments of the present invention. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 Schematic diagram of the processing process of a product with negative BOW in an embodiment of the present invention.

[0013] Figure 2 1 is a schematic diagram of the change in Warp value after heat treatment of a single-sided CVD-ground product in an embodiment of the present invention. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0015] This embodiment provides a method for improving silicon wafer warpage, which aims to optimize the processing technology and process flow for products processed by back-side LPCVD, thereby improving silicon wafer warpage, including: 1. LPCVD process optimization: The film formation temperature is appropriately lowered, the film grain size becomes smaller, the grain boundary area is small, the interfacial energy is reduced, and the grain boundary stress is reduced, thereby reducing the warpage of the silicon wafer. At the same time, the deposition rate is controlled by adjusting the SiH4 flow rate and film formation pressure to avoid stress concentration caused by excessive deposition. The film formation temperature is controlled at 645±10℃, and the SiH4 gas flow rate, film formation pressure and deposition time are adjusted according to actual production conditions. In one embodiment, the SiH4 gas flow rate is 0.13-0.19L / min, the film formation pressure is 15-35Pa, and the deposition time is 20-60min. 2. For products with LPCVD polycrystalline film thickness ≥8000 Å, as the thickness of the film increases, the deformation becomes more serious, which has a greater impact on the BOW value, such as Figure 1 As shown, for such products, before LPCVD, the flatness is tested and the product with negative BOW is flipped over by a flipping device to become positive BOW. By utilizing the stress compensation effect during the deposition process, a product with higher flatness can be obtained. 3. For products with high flatness, the process flow will increase single-sided grinding. Single-sided grinding will generate residual stress on the machined surface, while the unmachined surface remains unchanged. The uneven stress will cause a significant increase in warp. Therefore, for products with single-sided grinding, annealing heat treatment is added after LPCVD to release some of the pressure, which will significantly reduce warp. The temperature and time of annealing heat treatment are adjusted according to actual production conditions. In one embodiment, the annealing heat treatment temperature is 650±30℃ and the heat treatment time is 30min. Figure 2 As shown in the figure, after single-side grinding of the LPCVD product, heat treatment is added, and the warp is reduced by about 16μm.

[0016] The above description is merely a preferred embodiment of the present invention. For those skilled in the art, the present invention may be modified and varied in various ways. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A method for improving the warpage of a silicon wafer, characterized in that: include: LPCVD process optimization: Lower the film formation temperature to the target temperature range to reduce the film grain size, grain boundary area, interfacial energy, and grain boundary stress, thereby reducing silicon wafer warpage; adjust the SiH4 flow rate and film formation pressure to control the deposition rate and avoid stress concentration caused by excessive deposition; For products with LPCVD polycrystalline film thickness ≥8000 Å, flatness is tested before LPCVD. Products with negative bow are flipped to become positive bow. The stress compensation effect during the deposition process is used to improve product flatness. For high-flatness products that have been processed by single-sided grinding, annealing heat treatment is added after LPCVD to release some of the pressure and reduce the warp value of the product.

2. The method for improving silicon wafer warpage according to claim 1, wherein: In the LPCVD process optimization, the target temperature range is controlled at 645±10℃, the SiH4 gas flow rate is 0.13-0.19L / min, the film forming pressure is 15-35Pa, and the deposition time is 20-60min.

3. The method for improving silicon wafer warpage according to claim 1, wherein: Annealing heat treatment temperature is 650±30℃, and heat treatment time is 30min.

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