FPGA aging box adaptive frequency detection system and method

Abstract

The invention discloses an adaptive frequency detection system and method for an FPGA aging box, and belongs to the technical field of electronic measurement. The channel selection and frequency measurement functions of 64 paths of measured signals are realized by using the upper computer, the ARM processor, the FPGA device and the channel selection module. Wherein the upper computer sends out a frequency detection instruction and selects a channel to be detected; the ARM processor completes information interaction between the upper computer and the FPGA; the FPGA receives the signals and then controls the channel selection module, and the re-inspection signals are input to the FPGA after being selected; the FPGA obtains frequency information through a self-adaptive frequency detection algorithm and transmits the frequency information back to the upper computer, and the upper computer converts the frequency information into real measurement frequency and then displays the real measurement frequency. According to the self-adaptive frequency detection algorithm, the frequency measurement modes can be automatically switched according to the measured frequency, the measurement errors of low frequency and high frequency are reduced, the frequency measurement range is expanded, and the reliability of the dynamic aging test is improved.

Description

Technical Field

[0001] The invention relates to an FPGA burn-in box self-adaptive frequency detection system and method, belonging to the technical field of electronic measurement. Background Art

[0002] Complex integrated circuits like FPGAs are widely used in high-end manufacturing fields such as weaponry, precision manufacturing, and aerospace. Screening tests are necessary to ensure the reliability of these integrated circuits. Dynamic burn-in testing using an FPGA burn-in chamber is a crucial step in component screening.

[0003] FPGA burn-in boxes detect the correct frequency of their return signals to determine if the device has experienced any failures during use. Currently, FPGA burn-in boxes use a single frequency measurement method, which has a limited frequency range. Errors can be large when the frequency is too high or too low, making the FPGA burn-in test unreliable.

[0004] Common frequency measurement methods include frequency measurement, period measurement, and equal-precision measurement. The frequency measurement method counts the clock periods of the clock signal under test within a fixed time, resulting in large errors when measuring low-frequency signals. The period measurement method measures the period of the clock signal under test, but the measurement error is large for high-frequency signals with smaller periods. The equal-precision measurement method counts the clock periods of the clock signal under test and the calibration clock signal within a fixed time, performs multiple measurements, and statistically analyzes the results. However, measuring signals of different frequencies requires manual setting of different time intervals, resulting in low measurement efficiency. Existing measurement methods cannot simultaneously meet the measurement requirements of both high and low frequencies, or are complex to operate and have low measurement efficiency. Summary of the Invention

[0005] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and provide an FPGA burn-in box adaptive frequency detection system and method for meeting the frequency detection requirements during reliability screening of FPGA high-end complex integrated circuits.

[0006] The technical solution of the present invention is: in the first aspect, an FPGA burn-in box adaptive frequency detection system comprises:

[0007] The host computer sends frequency detection instructions and channel selection instruction codes to the ARM processor according to external instructions; and calculates the actual measurement frequency based on the obtained frequency information;

[0008] The ARM processor parses the frequency detection instruction and channel selection instruction code and sends them to the FPGA frequency counter module; it also periodically sends a frequency read request signal to the FPGA frequency counter module, reads back the frequency information measured by the FPGA frequency counter module, and forwards it to the host computer;

[0009] The FPGA frequency counter module, after receiving the frequency detection instruction, controls the channel selection module to select the measured signal according to the channel selection instruction code, and periodically detects the frequency of the selected measured signal, updating the output frequency information after each detection cycle; and returns the current frequency information to the ARM processor according to the read frequency request signal sent by the ARM processor;

[0010] The channel selection module selects the measured signal for return detection according to the channel selection instruction code.

[0011] Furthermore, the frequency information includes high and low frequency signal flags and frequency measurement count information, and the frequency measurement count information is used to calculate the actual measured frequency.

[0012] Furthermore, the frequency information is 16-bit parallel data, wherein the most significant bit is a high-frequency or low-frequency identification bit. When the most significant bit is 1, it indicates that the measurement check signal is identified as a high-frequency signal; when the most significant bit is 0, it indicates that the measurement check signal is identified as a low-frequency signal.

[0013] Furthermore, after the FPGA frequency counting module turns on the frequency detection function and enters the frequency counting state, it outputs frequency information in each detection cycle; the detection method is continuous measurement, that is, it automatically enters the next detection cycle after outputting the frequency information, and updates the output frequency information after each detection cycle.

[0014] Furthermore, the FPGA frequency counting module periodically detects the frequency of the selected measured signal and makes a judgment:

[0015] When the number of cycles of the measured signal is greater than the preset value, it is determined to be a high-frequency signal output, the high and low frequency flags are set to 1, and the number of cycles of the measured signal is used as the frequency measurement counting information;

[0016] Otherwise, it is determined to be a low-frequency signal. Then the system time between two adjacent rising edges of the measured signal is measured, the high and low frequency flags are set to 0, and the system time is used as the frequency measurement counting information.

[0017] When the interval between the rising edges of two adjacent measured signals exceeds the preset maximum value, the high and low frequency flags are set to 0, and 0 is used as the frequency measurement count information;

[0018] After the judgment is completed, the frequency measurement count information and the high and low frequency identification bits are used as frequency information and wait for reading back.

[0019] Furthermore, the host computer and the ARM processor interact with each other via the TCP protocol.

[0020] Furthermore, the channel selection module adopts a structure that combines one 4-to-1 data selector and four 8-to-1 data selectors; the four input signals of the 4-to-1 data selector are respectively the outputs of the four 8-to-1 data selectors; the upper two control signals are connected to the control port of the 4-to-1 data selector to control the selection of the four 8-to-1 data selectors; the lower three control signals are simultaneously connected to the control ports of the four 8-to-1 data selectors to control the selection of 8-way return check signals respectively; and a 5-bit control signal is realized to select 32-way return check signals.

[0021] In a second aspect, an FPGA burn-in box adaptive frequency detection method implemented according to the FPGA burn-in box adaptive frequency detection system includes:

[0022] During the device aging process, select the channel in the host computer and start frequency detection;

[0023] The host computer sends a detection enable signal and channel information to the ARM processor, which parses the information and forwards it to the FPGA frequency counting module.

[0024] After receiving the start detection enable signal, the FPGA frequency counting module sends the channel information to the channel selection module to select the specified channel;

[0025] The FPGA frequency counter module periodically detects the frequency of the selected measured signal and makes a judgment: when the number of cycles of the measured signal is greater than the preset value, it is judged as a high-frequency signal output, the high and low frequency flags are set to 1, and the number of cycles of the measured signal is used as the frequency measurement count information; otherwise, it is judged as a low-frequency signal, and the system time between two adjacent rising edges of the measured signal is measured, the high and low frequency flags are set to 0, and the system time is used as the frequency measurement count information; when the interval time between the rising edges of two adjacent measured signals exceeds the preset maximum value, the high and low frequency flags are set to 0, and 0 is used as the frequency measurement count information; after the judgment is completed, the frequency measurement count information and the high and low frequency flags are used as frequency information and wait for readback;

[0026] After the ARM processor sends a read frequency request signal, the frequency information is transmitted to the host computer via the ARM processor;

[0027] The host computer receives the frequency information. When the high and low frequency identification bits are 1, the measured frequency f=N / T is calculated based on the frequency measurement count information. h ; When the high and low frequency flags are 0, according to the system clock frequency f s , the measured frequency f=1 / f s N; when the frequency information is all 0, the measured frequency is 0; N is the frequency measurement count information;

[0028] The host computer displays the measured frequency based on the calculation.

[0029] In a third aspect, a computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the FPGA burn-in box adaptive frequency detection method are implemented.

[0030] In a fourth aspect, an FPGA burn-in box adaptive frequency detection device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the FPGA burn-in box adaptive frequency detection method are implemented.

[0031] The advantages of the present invention compared with the prior art are:

[0032] (1) The present invention adopts an adaptive frequency detection algorithm, automatically switches the frequency measurement method according to the frequency, ensures the measurement accuracy of high and low frequencies of the signal, and effectively improves the range of measurable frequency of the signal.

[0033] (2) The present invention can automatically measure the frequency of the feedback signal and display it on the upper computer interface. It is easy to operate, the detection method is continuous measurement, and the measurement results are fed back in real time, which can improve the work efficiency of the FPGA refining box operator. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0035] Figure 1 This is a system block diagram of the FPGA aging box adaptive frequency detection system of the present invention;

[0036] Figure 2 This is a flow chart of the adaptive frequency detection of the FPGA burn-in box of the present invention. DETAILED DESCRIPTION

[0037] In order to better understand the above technical solution, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0038] The following is a further detailed description of an FPGA burn-in box adaptive frequency detection system provided by an embodiment of the present invention in conjunction with the accompanying drawings. Figure 1,The specific implementation methods may include: host computer, ARM processor, FPGA frequency counting and channel selection module;

[0039] The host computer sends a frequency detection instruction to the ARM processor and selects the channel to be detected; the ARM processor module parses the command code from the host computer and sends the channel to be detected to the FPGA module; after receiving the command code, the FPGA controls the channel selection module, and the return detection signal is input into the FPGA after selection; the FPGA obtains the frequency information through the adaptive frequency detection algorithm, and transmits it back to the host computer through the ARM, and the host computer converts the frequency information into the actual measured frequency and displays it.

[0040] The host computer module's software interface includes options for starting frequency detection and selecting a channel. It interacts with the ARM processor and calculates the actual measured frequency based on the acquired frequency information, displaying it on the host computer interface. The frequency information received by the host computer module must include high and low frequency signal flags and frequency measurement count information, which can be converted into the actual measured frequency using an algorithm.

[0041] The ARM processor completes the signal forwarding function between the upper and lower computers, receives the instruction code of the upper computer module to start detection and channel selection and forwards it to the FPGA module. After setting the interval time, it sends a read frequency request signal to the FPGA, reads back the frequency information measured by the FPGA and forwards it to the upper computer.

[0042] After receiving the frequency detection start signal, the FPGA frequency counter module activates the frequency detection function and enters the frequency counting state, outputting frequency information after one detection cycle. The detection method is continuous measurement, meaning that after outputting frequency information, it automatically enters the next detection cycle and updates the output frequency information after each detection cycle. The frequency counting process uses an adaptive frequency detection algorithm. A high-frequency signal measurement method is used at the beginning of each detection cycle. After the measurement is completed, it determines whether the measured signal is a high-frequency signal. If it is a high-frequency signal, the measurement result is directly output and the next detection cycle is entered, improving detection efficiency. If it is a low-frequency signal, the measurement method is changed and the next detection cycle is entered after the measurement is completed. After receiving the ARM processor's frequency read request signal, the measurement result and high and low frequency signal identifiers are returned.

[0043] The channel selection module selects 64 return detection signals under FPGA control. The input is 64 test signals, and the output is 2 signals connected to the FPGA port.

[0044] In the solution provided in the embodiment of the present invention, Figure 1 As shown, the overall system of this method includes a host computer, an ARM processor, an FPGA module and a channel selection module, wherein two sets of channel selection modules are configured, each of which can select 32 channels of measured signals. At the same time, two sets of frequency counting modules are configured in the FPGA program to measure the frequency of the output signals of the two channel selection modules respectively.

[0045] The host computer module's software interface includes options for starting frequency detection and selecting a channel, and interacts with the ARM processor via the TCP protocol. The host computer module receives frequency information as 16-bit parallel data, with the highest bit representing the high and low frequency identification bits. When the highest bit is 1, it indicates that the measurement return signal is identified as a high-frequency signal; when the highest bit is 0, it indicates that the measurement return signal is identified as a low-frequency signal. The actual measurement frequency is calculated using the corresponding algorithm and displayed on the host computer interface.

[0046] The ARM processor receives the instruction code from the host computer module to start detection and communication selection, and sends the frequency detection start signal and channel signal to the FPGA through the 16-bit data line and enable control signal respectively. After setting the interval time, it sends a read frequency request signal to the FPGA, reads back the frequency information measured by the FPGA and forwards it to the host computer.

[0047] After receiving the frequency detection start signal, the FPGA frequency counter module activates the frequency detection function and outputs the measured frequency value. The frequency counting process utilizes an adaptive frequency detection algorithm and is divided into two phases. The first phase is the high-frequency signal detection phase, which uses a frequency measurement method. A set time interval is set using the FPGA system clock. The rising edges of the measured signal are sampled using the FPGA system clock and all rising edges within the time interval are counted. High and low frequency count flags are set. If the value is greater than the value, the measured signal is determined to be a high-frequency signal and the measured frequency is output, followed by detection for the next cycle. If the value is less than the value, the measured signal is determined to be a low-frequency signal and the second phase begins. The second phase is the low-frequency signal detection phase. The rising edges of the measured signal are sampled using the FPGA system clock and the system time between two adjacent rising edges is counted. Based on the system clock frequency and the measured frequency, the value is output, followed by detection for the next cycle. A maximum detection period is set. If the interval between two rising edges of the measured signal exceeds the value, the device under test is deemed to have no output and the data sent is 0. The output or output is 15-bit parallel data, which is combined with the high and low frequency identification bits to form 16-bit data and stored. It is passed to the host computer after waiting for the ARM readback instruction. The highest bit is the high and low frequency identification bit. When it is "1", it represents a high frequency signal, and when it is "0", it represents a low frequency signal.

[0048] The channel selection module combines one 4-to-1 data selector with four 8-to-1 data selectors. The four input signals of the 4-to-1 data selector are the outputs of the four 8-to-1 data selectors. The upper two control signals are connected to the control ports of the 4-to-1 data selector to control the selection of the four 8-to-1 data selectors. The lower three control signals are simultaneously connected to the control ports of the four 8-to-1 data selectors to control the selection of eight return check signals. This allows a 5-bit control signal to select 32 return check signals.

[0049] Based on Figure 1 The same inventive concept, the present invention also provides an FPGA burn-in box adaptive frequency detection method. Figure 2 As shown in the figure, the specific implementation process of the FPGA aging box adaptive frequency detection process is as follows:

[0050] (1) During the device aging process, select the channel in the host computer and click to start frequency detection;

[0051] (2) The host computer sends a start detection enable signal and channel information to the ARM processor, and the ARM processor forwards the corresponding information to the FPGA;

[0052] (3) After receiving the start detection enable signal, the FPGA turns on the frequency counting module, sends the channel information to the channel selection module, and selects the specified channel;

[0053] (4) The FPGA module uses an adaptive frequency detection algorithm. When the number of cycles of the measured signal within the time interval is greater than the high and low frequency number flags, it is determined to be a high-frequency signal output, and the high and low frequency flags are 1; otherwise, it is determined to be a low-frequency signal, and the high and low frequency flags of the system time between two adjacent rising edges of the measured signal are 0; if it is too large, the measured signal frequency is determined to be 0;

[0054] (5) After ARM sends the read-back frequency instruction, the frequency information is transmitted to the host computer via ARM;

[0055] (6) After the host computer receives the frequency information, when the high and low frequency identification bits are 1, the measured frequency f = N / T can be calculated from the frequency measurement count information N. h ; When the high and low frequency flags are 0, according to the system clock frequency f s , we can calculate the measured frequency f=1 / f s N; When the received information is all 0, the measured frequency is 0.

[0056] (7) The host computer displays the measured frequency on the host computer interface according to the frequency.

[0057] The present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed on a computer, cause the computer to execute Figure 2 The method described.

[0058] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0059] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0060] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0061] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0062] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

[0063] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. An FPGA aging box adaptive frequency detection system, characterized in that: include: The host computer sends frequency detection instructions and channel selection instruction codes to the ARM processor according to external instructions; and calculating the actual measurement frequency based on the acquired frequency information; The ARM processor parses the frequency detection instruction and channel selection instruction code and sends them to the FPGA frequency counting module; And periodically send a frequency reading request signal to the FPGA frequency counting module, and read back the frequency information measured by the FPGA frequency counting module and forward it to the host computer; The FPGA frequency counter module, after receiving the frequency detection instruction, controls the channel selection module to select the measured signal according to the channel selection instruction code, and periodically detects the frequency of the selected measured signal, updating the output frequency information after each detection cycle; and returns the current frequency information to the ARM processor according to the read frequency request signal sent by the ARM processor; The channel selection module selects the measured signal for return detection according to the channel selection instruction code.

2. The FPGA burn-in box adaptive frequency detection system according to claim 1, characterized in that: The frequency information includes high and low frequency signal flags and frequency measurement count information, and the frequency measurement count information is used to calculate the actual measurement frequency.

3. The FPGA burn-in box adaptive frequency detection system according to claim 2, characterized in that: The frequency information is 16-bit parallel data, where the highest bit is the high and low frequency identification bit. When the highest bit is 1, it indicates that the measurement return signal is identified as a high frequency signal. When the highest bit is 0, it indicates that the measurement return signal is identified as a low frequency signal.

4. The FPGA burn-in box adaptive frequency detection system according to claim 1, characterized in that: After the FPGA frequency counting module turns on the frequency detection function and enters the frequency counting state, it outputs frequency information in each detection cycle; the detection mode is continuous measurement, that is, it automatically enters the next detection cycle after outputting the frequency information, and updates the output frequency information after each detection cycle.

5. The FPGA burn-in box adaptive frequency detection system according to claim 4, characterized in that: The FPGA frequency counting module periodically detects the frequency of the selected measured signal and makes a judgment: When the number of cycles of the measured signal is greater than the preset value, it is determined to be a high-frequency signal output, the high and low frequency flags are set to 1, and the number of cycles of the measured signal is used as the frequency measurement counting information; Otherwise, it is determined to be a low-frequency signal. Then the system time between two adjacent rising edges of the measured signal is measured, the high and low frequency flags are set to 0, and the system time is used as the frequency measurement counting information. When the interval between the rising edges of two adjacent measured signals exceeds the preset maximum value, the high and low frequency flags are set to 0, and 0 is used as the frequency measurement count information; After the judgment is completed, the frequency measurement count information and the high and low frequency identification bits are used as frequency information and wait for reading back.

6. The FPGA burn-in box adaptive frequency detection system according to claim 1, characterized in that: The host computer and the ARM processor interact with each other via the TCP protocol.

7. The FPGA burn-in box adaptive frequency detection system according to claim 1, characterized in that: The channel selection module adopts a structure combining a 4-to-1 data selector and four 8-to-1 data selectors; the four input signals of the 4-to-1 data selector are the outputs of the four 8-to-1 data selectors respectively; the upper two control signals are connected to the control port of the 4-to-1 data selector to control the selection of the four 8-to-1 data selectors; the lower three control signals are simultaneously connected to the control ports of the four 8-to-1 data selectors to control the selection of the 8-way return check signals respectively; A 5-bit control signal is used to select 32 return check signals.

8. The FPGA burn-in box adaptive frequency detection method implemented by the FPGA burn-in box adaptive frequency detection system according to claim 2, characterized in that: include: During the device aging process, select the channel in the host computer and start frequency detection; The host computer sends a detection enable signal and channel information to the ARM processor, which parses the information and forwards it to the FPGA frequency counting module. After receiving the start detection enable signal, the FPGA frequency counting module sends the channel information to the channel selection module to select the specified channel; The FPGA frequency counter module periodically detects the frequency of the selected measured signal and makes a judgment: when the number of cycles of the measured signal is greater than the preset value, it is judged as a high-frequency signal output, the high and low frequency flags are set to 1, and the number of cycles of the measured signal is used as the frequency measurement count information; otherwise, it is judged as a low-frequency signal, and the system time between two adjacent rising edges of the measured signal is measured, the high and low frequency flags are set to 0, and the system time is used as the frequency measurement count information; when the interval time between the rising edges of two adjacent measured signals exceeds the preset maximum value, the high and low frequency flags are set to 0, and 0 is used as the frequency measurement count information; after the judgment is completed, the frequency measurement count information and the high and low frequency flags are used as frequency information and wait for readback; After the ARM processor sends a read frequency request signal, the frequency information is transmitted to the host computer via the ARM processor; The host computer receives the frequency information. When the high and low frequency identification bits are 1, the measured frequency f=N / T is calculated based on the frequency measurement count information. h ; When the high and low frequency flags are 0, according to the system clock frequency f s , the measured frequency f=1 / f s N; when the frequency information is all 0, the measured frequency is 0; N is the frequency measurement count information; The host computer displays the measured frequency based on the calculation.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 8 are implemented.

10. An FPGA burn-in box adaptive frequency detection device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to claim 8 are implemented.

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