BMS master-slave board testing method and system based on BMS-HIL

Abstract

The invention discloses a BMS master-slave board detection method based on BMS-HIL, and the method comprises the steps: electrifying master-slave boards and BMS detection equipment, building CAN communication between the master-slave boards and an upper computer, initializing a communication interface and a voltage channel, carrying out the matching and selection of master-slave board detection items on the upper computer according to the detection demands, and starting the detection. The upper computer sends instructions corresponding to detection items to the master and slave boards, the master and slave boards execute the instructions and then feed back results to the upper computer, the upper computer judges the detection results, and detection of the master and slave boards is completed; the master-slave board detection items comprise master-slave board basic function detection, mainboard chip detection and mainboard electrical function detection; according to the invention, the integrated detection capability is improved; manual intervention of multi-node data analysis and logic judgment is not needed, the test period is shortened, the time cost is reduced, and the detection efficiency is optimized; enhancing multi-dimensional function verification; the test reliability is enhanced; and flow standardization and expandability are realized.

Description

Technical Field

[0001] The present invention relates to a BMS master-slave board testing method and system based on BMS-HIL, belonging to the technical field of battery energy storage. Background Art

[0002] As a core technology in the new energy vehicle and energy storage sectors, the battery management system (BMS) provides real-time monitoring of battery voltage, current, temperature, and other parameters, optimizing charge and discharge control strategies, balancing the battery pack's state of charge, and implementing protection against abnormal operating conditions such as overcharge, overdischarge, and overcurrent. The system architecture typically consists of a monitoring unit, a control unit, a balancing unit, a protection unit, and a communication interface. The monitoring unit collects single-cell data through a distributed sensor network, while the control unit makes global decisions based on algorithms.

[0003] The master-slave BMS adopts a layered architecture design, with the main board responsible for global coordination and policy execution, while the slave board is deployed at the battery module level to perform data collection and local control. Existing detection technologies have significant limitations in the verification process for master-slave BMS: main board functional testing requires independent communication protocol verification, algorithm logic verification, and system-level protection mechanism triggering, while slave board testing requires verifying the sampling accuracy, balancing capabilities, and thermal management response of each individual battery within the module one by one. This discrete detection mode leads to a linear extension of the test cycle in large-scale production scenarios, low equipment reuse rate, and insufficient simulation coverage of multi-node collaborative working conditions, making it difficult to meet the production line rhythm requirements.

[0004] Especially in high-throughput manufacturing environments, traditional methods require separate master board test platforms and slave board automated test lines, resulting in redundant equipment investment and siloed test data. Furthermore, the lack of an integrated test solution for dynamic verification of master-slave board coupling further restricts comprehensive evaluation of test efficiency and system reliability. Summary of the Invention

[0005] Purpose of the invention: In view of the shortcomings of the prior art, the present invention provides a BMS master-slave board testing method and system based on BMS-HIL. By integrating the detection items of the master and slave boards, the present invention can meet the production line rhythm requirements and improve the detection efficiency.

[0006] Technical solution: A BMS master-slave board detection method based on BMS-HIL, including the following steps:

[0007] The master and slave boards and BMS testing equipment are powered on, CAN communication is established between the master and slave boards and the host computer, the communication interface and voltage channel are initialized, and the master and slave board testing items are selected on the host computer according to the testing requirements and the testing is started. The host computer sends instructions for the corresponding testing items to the master and slave boards. After the master and slave boards execute the instructions, they feed back the results to the host computer. The host computer determines the test results and completes the master and slave board testing. The master and slave board testing items include master and slave board basic function testing, mainboard chip testing, and mainboard electrical function testing.

[0008] If you select the master and slave board basic function test, that is, the voltage and current acquisition accuracy and relay control function of the main board are tested, and the voltage and temperature acquisition accuracy of the slave board are tested; the host computer judges the test results. If the test results of the main board or the slave board fail, the basic function of the main board or the slave board is judged to be abnormal, and the test results are recorded; if the test results of the main board and the slave board are both qualified, the basic functions of the master and slave boards are judged to be normal;

[0009] If you select the motherboard chip test, the motherboard chip will be tested for storage capacity, Flash function, and system time function. The host computer will judge the test results. If any test result fails, the motherboard chip will be judged to be abnormal and the test results will be recorded. If all the test results are qualified, the motherboard chip will be judged to be normal.

[0010] If the mainboard electrical function test is selected, the mainboard chip will be subjected to insulation function test, variable temperature power test, and SOC calibration function test; the host computer will judge the test results. If any test result fails, the corresponding function of the mainboard test will be judged to be abnormal, and the test results will be recorded. If all the test results are qualified, the mainboard electrical function will be judged to be up to standard.

[0011] The preferred option is to test the motherboard voltage acquisition accuracy as follows:

[0012] The host computer sets the target voltage value, sends a control instruction to simulate the target voltage value to the BMS detection device, and sends a total voltage reading request to the mainboard via the CAN bus. After the mainboard completes the total voltage acquisition, it feeds back the CAN response message containing the total voltage data to the host computer. The host computer compares the current voltage value with the target voltage value based on the feedback, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the mainboard voltage acquisition function is normal. If it does not, it is determined that the mainboard voltage acquisition function is abnormal.

[0013] The mainboard current acquisition accuracy test is as follows:

[0014] The host computer sets the target charge / discharge current value, charges or discharges the battery, and sends a current reading request to the mainboard via the CAN bus. The mainboard feeds back the CAN response message containing the current data to the host computer. The host computer compares the current value fed back with the target charge / discharge current value, calculates the current difference, and determines whether it meets the accuracy standard. If it does, it is determined that the mainboard's current collection function is normal. If not, it is determined that the mainboard's current collection function is abnormal.

[0015] The voltage acquisition accuracy test from the board specifically includes static voltage detection, overcharge voltage detection, and over-discharge voltage detection for single cells;

[0016] The static voltage detection is as follows:

[0017] The host computer sets the target voltage value, sends a control instruction to simulate the target voltage value to the BMS detection equipment, and sends a single-cell voltage reading request to the main board through the CAN bus. After the slave board completes the single-cell voltage acquisition, the main board feeds back the CAN response message containing the single-cell voltage data to the host computer. The host computer compares the current voltage value fed back with the target voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the static voltage acquisition function of the slave board is normal. If it does not, it is determined that the static voltage acquisition function of the slave board is abnormal.

[0018] The overcharge voltage detection is as follows:

[0019] Set the overcharge voltage value and charge the battery. When the battery reaches the limit voltage value, the host computer sends a request to the main board via the CAN bus to read the single cell voltage and real-time alarm status. After the slave board completes the single cell voltage acquisition, the main board feeds back a CAN response message containing the single cell voltage data and real-time alarm status to the host computer. The host computer compares the current voltage value fed back with the set overcharge voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the overcharge voltage acquisition function of the slave board is normal. If it does not, it is determined that the overcharge voltage acquisition function of the slave board is abnormal. At the same time, the CAN message containing the real-time alarm status returned by the main board is parsed to check whether the main board can correctly determine the overcharge status flag and report it when the limit voltage value is reached.

[0020] The over-discharge voltage detection is as follows:

[0021] Set the over-discharge voltage value and discharge the battery. When the battery reaches the limit voltage value, the host computer sends a request to the main board via the CAN bus to read the single cell voltage and real-time alarm status. After the slave board completes voltage acquisition, the main board feeds back a CAN response message containing the single cell voltage data and real-time alarm status to the host computer. The host computer compares the current voltage value fed back with the set over-discharge voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the slave board over-discharge voltage acquisition function is normal. If it does not, it is determined that the slave board over-discharge voltage acquisition function is abnormal. At the same time, the CAN message containing the real-time alarm status returned by the main board is parsed to check whether the main board can correctly determine the over-discharge status flag and report it when the limit voltage value is reached.

[0022] The specific detection of the temperature acquisition accuracy from the board is as follows:

[0023] The host computer sets the target temperature value and loads the RT table of the relationship between thermistor resistance and temperature. It sends a control instruction to simulate the temperature value to the BMS detection device and sends a temperature reading request to the main board through the CAN bus. After the slave board completes temperature acquisition, the main board feeds back a CAN response message containing temperature data to the host computer. The host computer compares the current temperature value with the target temperature value based on the feedback, calculates the temperature difference, and determines whether it meets the accuracy standard. If it does, it is determined that the slave board temperature acquisition function is normal. If it does not, it is determined that the slave board temperature acquisition function is abnormal.

[0024] Preferably, the mainboard relay control function detection specifically includes mainboard IN port detection and mainboard OUT port detection;

[0025] The specific detection of the motherboard OUT port is as follows:

[0026] The host computer initializes the relay status and sends a control command to disconnect the relay to the mainboard via the CAN bus. The mainboard outputs a high-level signal through the OUT port to drive the relay to disconnect. The host computer reads back the relay status through the BMS detection device. If it detects that the relay has been successfully disconnected, it is determined that the control function of the mainboard OUT port is normal; otherwise, it is determined that the control of the mainboard OUT port is abnormal.

[0027] The motherboard IN port detection is as follows:

[0028] The host computer initializes the relay status and sends a control instruction to close the relay to the BMS detection device. After the BMS detection device controls the relay to close, the mainboard reads back the relay status through the IN port. If a low-level signal is read, it is determined that the reading function of the mainboard IN port is normal; otherwise, it is determined that the reading function of the mainboard IN port is abnormal.

[0029] Preferably, the storage capacity detection is specifically:

[0030] Set the standard capacity value, and the host computer sends a FRAM storage detection request command to the main board through the CAN bus. After receiving the command message, the main board completes the storage capacity detection operation and feeds back a response message containing the storage capacity information to the host computer. The host computer compares the actual storage capacity value fed back with the standard storage capacity value. If the actual storage capacity value is consistent with the standard storage capacity value, it is determined that the storage capacity of the FRAM chip is normal. If not, it is determined to be abnormal.

[0031] Preferably, the Flash function detection is specifically:

[0032] The host computer sends a Flash erase request command to the main board via the CAN bus. After the main board executes the erase operation, it sends a CAN response message containing the erase completion to the host computer.

[0033] After the host computer receives the CAN response message of the erase completion, it sends a Flash write request instruction to the main board. The instruction contains the target address and the data to be written. After the main board completes the write operation, it feeds back the CAN response message of the write completion to the host computer.

[0034] After the host computer receives the CAN response message of the written data, it sends a Flash read request to the main board, specifying the read address range as the write address range. The main board performs the read operation and feeds back a CAN response message containing the read completion and the read write data to the host computer.

[0035] The host computer compares the read write data with the data to be written. If the data are completely consistent, it is determined that the Flash function is normal and the erase, write and read operations are qualified; if the data are inconsistent, it is determined that the Flash function is abnormal and there is an erase failure, write failure or read error.

[0036] Preferably, the system time function detection is specifically:

[0037] The host computer sends a system time query request to the mainboard through the CAN bus. The mainboard feeds back a CAN response message of the system time to the host computer. The host computer compares the read system time with the current time. If they are inconsistent, it is determined that the mainboard system time function is abnormal. If they are consistent, the host computer sends a 60-second power-off instruction to the BMS detection device to simulate a power-off scenario. After waiting for power to be restored, it sends a system time query request to the mainboard and compares it with the current time again to calculate the time difference. If the time difference is within the preset range, that is, within 60 seconds, it is determined that the mainboard system time function is normal, otherwise it is determined that the mainboard system time function is abnormal.

[0038] Preferably, the insulation function test is specifically:

[0039] The host computer sets the total voltage and insulation resistance value and sends an insulation resistance reading request to the main board via the CAN bus. After the main board completes the insulation resistance calculation using the voltage division method, it feeds back a CAN response message containing the actual total voltage (i.e., the voltage value of the insulation positive electrode to the insulation negative electrode) and the actual insulation resistance (i.e., the resistance value of the insulation positive electrode and the insulation negative electrode to the ground respectively) to the host computer. The actual total voltage is compared with the set total voltage to calculate the voltage difference.

[0040] Compare the actual insulation positive and insulation negative resistance values ​​to ground with the set insulation resistance values ​​one by one, and calculate the resistance difference. If both are within the total voltage and insulation resistance accuracy range, the insulation function is judged to be normal. If any one does not meet the requirements, the insulation function is judged to be abnormal, that is, the acquisition of total voltage, insulation positive and insulation negative resistance has failed.

[0041] The preferred option is to test the variable temperature power as follows:

[0042] Set the temperature range to be measured and select the temperature values ​​to be measured in turn. At the same temperature to be measured, set the initial SOC state of the battery pack to 100% to ensure that the system is in a fully charged state. If the SOC is less than 100%, charge it to 100%, set the discharge current to discharge, and send a read request for real-time current, temperature, allowable current, and power data to the mainboard through the CAN bus. The mainboard will calculate the allowable current and power. After the slave board completes temperature acquisition, the mainboard returns a CAN response message to the host computer.

[0043] When the SOC drops to 0%, the charging current is set to start charging, and a read request for real-time current, temperature, allowable current, and power data is sent to the mainboard via the CAN bus. The mainboard calculates the allowable current and power. After the slave board completes temperature acquisition, the mainboard returns a CAN response message to the host computer.

[0044] After the current temperature is measured, reselect the next temperature and repeat the above steps until all temperatures within the temperature range are measured.

[0045] The host computer analyzes the real-time current, temperature, allowable current, and power data, and compares them with the standard limit power calculation results. If they are the same, it is determined that the power limit function is normal. Otherwise, it is determined that the power limit function is abnormal, and there are abnormal temperature collection, inaccurate SOC changes, and abnormal power limit function.

[0046] Preferably, the SOC calibration function test is specifically as follows:

[0047] Set the voltage value and charging current to charge the battery to put it in an overvoltage state, then set the discharge current to discharge it, send a real-time voltage and current reading request to the mainboard through the CAN bus, and record the discharge time. After the mainboard calculates the discharge capacity, it returns a CAN response message containing real-time voltage, current, and capacity data to the host computer, and compares them with the results obtained by the set values. If they are the same, it is determined that the SOC calibration function is normal, otherwise the SOC calibration function is abnormal.

[0048] A system for implementing a BMS master-slave board detection method based on BMS-HIL includes a host computer, a BMS detection device, a main board and a slave board with bidirectional data interaction connection, wherein the host computer and the main board exchange data via a CAN bus, the host computer and the BMS detection device exchange data via a switch, and the master and slave boards exchange data via a CAN bus.

[0049] The BMS detection equipment includes a virtual battery unit, a constant current source unit, an insulation resistance test unit, a temperature simulation unit, an I / O port drive detection unit, and a CAN communication unit;

[0050] The mainboard includes a power interface, a battery pack terminal voltage interface, a current acquisition interface, a mainboard OUT port, a mainboard IN port, and a communication interface;

[0051] The slave board includes a communication interface and a sampling interface capable of both temperature sampling and voltage sampling.

[0052] Beneficial effects: By constructing a BMS-HIL-based detection system, the present invention achieves synchronized and coordinated verification of master and slave board function detection. The host computer uniformly schedules the detection process and can dynamically configure test items for the basic functions, chip performance, and electrical characteristics of the master and slave boards, effectively solving the equipment redundancy and test islanding problems caused by discrete detection, significantly improving equipment reuse and test scenario coverage integrity, and enhancing integrated detection capabilities.

[0053] Adopting modular detection strategies and automated judgment mechanisms, the system implements closed-loop control of master-slave board command issuance, data collection, and result feedback via the CAN bus, eliminating the need for manual intervention in multi-node data analysis and logical judgment, significantly shortening the test cycle. Especially in high-throughput production scenarios, it can meet production line cycle requirements, reduce time costs, and optimize detection efficiency.

[0054] Based on virtual battery cells and operating condition simulation technology, complex functions such as voltage / temperature acquisition accuracy, relay control response, chip storage stability, and dynamic power limiting are simultaneously verified. Through overcharge / over-discharge voltage detection and real-time alarm flag analysis, the correlation between protection mechanisms and data acquisition is verified, ensuring the effectiveness of system-level safety logic and strengthening multi-dimensional functional verification.

[0055] The introduction of HIL hardware-in-the-loop technology allows for accurate reproduction of battery pack operating limits through insulation resistance testing, variable temperature power simulation, and SOC calibration functional testing. Combined with real-time comparison of master and slave board interaction data, this technology can expose potential flaws in the collaborative operation of hardware and algorithms, providing a multi-dimensional assessment basis for system reliability and enhancing test reliability.

[0056] The inspection process utilizes parameterized configuration and standardized judgment rules, supporting flexible combination and expansion of inspection items. The host computer quickly locates abnormal conditions by parsing CAN messages, providing structured data support for production line quality traceability and process improvement. It adapts to the upgraded inspection requirements of different BMS architectures, achieving process standardization and scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0058] Figure 1 It is the overall flow chart of the present invention;

[0059] Figure 2 This is a flow chart of the mainboard voltage acquisition accuracy detection of the present invention;

[0060] Figure 3 This is a flow chart of the mainboard current acquisition accuracy detection of the present invention;

[0061] Figure 4 This is a flow chart of static voltage detection of a single battery of a slave board according to the present invention;

[0062] Figure 5 This is a flow chart of the slave board overcharge voltage detection of the present invention;

[0063] Figure 6 This is a flow chart of the slave board over-discharge voltage detection of the present invention;

[0064] Figure 7 This is a flow chart of the accuracy detection of temperature acquisition from a board according to the present invention;

[0065] Figure 8 This is a flow chart of the motherboard OUT port detection of the present invention;

[0066] Figure 9 This is a flow chart of the motherboard IN port detection of the present invention;

[0067] Figure 10 This is a flow chart of storage capacity detection of the present invention;

[0068] Figure 11 This is a flow chart of the Flash function detection of the present invention;

[0069] Figure 12 This is a flow chart of the system time function detection of the present invention;

[0070] Figure 13 This is a flow chart of the insulation function test of the present invention;

[0071] Figure 14 This is a flow chart of the variable temperature power test of the present invention;

[0072] Figure 15 This is a flow chart of the SOC calibration function test of the present invention;

[0073] Figure 16 It is a system structure diagram of the present invention;

[0074] Figure 17 This is a schematic diagram of the mainboard structure of the present invention;

[0075] Figure 18 This is a schematic diagram of the slave plate structure of the present invention;

[0076] Figure 19 This is a schematic diagram of the master-slave board connection of the present invention. DETAILED DESCRIPTION

[0077] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0078] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present invention.

[0079] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0080] like Figure 1 As shown, a BMS master-slave board detection method based on BMS-HIL includes the following steps:

[0081] The master and slave boards and BMS testing equipment are powered on, CAN communication is established between the master and slave boards and the host computer, the communication interface and voltage channel are initialized, and the master and slave board testing items are selected on the host computer according to the testing requirements and the testing is started. The host computer sends instructions for the corresponding testing items to the master and slave boards. After the master and slave boards execute the instructions, they feed back the results to the host computer. The host computer determines the test results and completes the master and slave board testing. The master and slave board testing items include master and slave board basic function testing, mainboard chip testing, and mainboard electrical function testing.

[0082] If you select the master and slave board basic function test, that is, the voltage and current acquisition accuracy and relay control function of the main board are tested, and the voltage and temperature acquisition accuracy of the slave board are tested; the host computer judges the test results. If the test results of the main board or the slave board fail, the basic function of the main board or the slave board is judged to be abnormal, and the test results are recorded; if the test results of the main board and the slave board are both qualified, the basic functions of the master and slave boards are judged to be normal;

[0083] If you select the motherboard chip test, the motherboard chip will be tested for storage capacity, Flash function, and system time function. The host computer will judge the test results. If any test result fails, the motherboard chip will be judged to be abnormal and the test results will be recorded. If all the test results are qualified, the motherboard chip will be judged to be normal.

[0084] If the mainboard electrical function test is selected, the mainboard chip will be subjected to insulation function test, variable temperature power test, and SOC calibration function test; the host computer will judge the test results. If any test result fails, the corresponding function of the mainboard test will be judged to be abnormal, and the test results will be recorded. If all the test results are qualified, the mainboard electrical function will be judged to be up to standard.

[0085] like Figure 2 As shown, the mainboard voltage acquisition accuracy test is specifically as follows:

[0086] The host computer sets the target voltage value, sends a control instruction of the simulated target voltage value to the BMS detection equipment, and sends a total voltage reading request to the main board through the CAN bus. After the main board completes the total voltage acquisition, it feeds back the CAN response message containing the total voltage data to the host computer. The host computer compares the current voltage value with the target voltage value based on the feedback, calculates the voltage difference, and determines whether it meets the accuracy standard. If it meets the standard, it is determined that the main board voltage acquisition function is normal. If it does not meet the standard, it is determined that the main board voltage acquisition function is abnormal. The specific accuracy standard is: within a sampling period of ≤100ms, if the set target voltage value is less than 500V, then the sampling error ≤5V indicates that the function is normal, otherwise it is abnormal; if the set target point voltage value is ≥500V, then the sampling error ≤1% indicates that the function is normal, otherwise it is abnormal.

[0087] like Figure 3 As shown, the mainboard current acquisition accuracy test is specifically as follows:

[0088] The host computer sets the target charge / discharge current value, charges or discharges the battery, and sends a current reading request to the mainboard via the CAN bus. The mainboard feeds back the CAN response message containing the current data to the host computer. The host computer compares the current value fed back with the target charge / discharge current value, calculates the current difference, and determines whether it meets the accuracy standard. If it does, the mainboard current acquisition function is normal; if it does not, the mainboard current acquisition function is abnormal. The specific accuracy standard is: within a sampling period of ≤50ms, if the set target current value is less than 200A, then a sampling error of ≤2A indicates that the function is normal, otherwise it is abnormal; if the set target point voltage value is ≥200A, then a sampling error of ≤1% indicates that the function is normal, otherwise it is abnormal.

[0089] The voltage acquisition accuracy test from the board specifically includes static voltage detection, overcharge voltage detection, and over-discharge voltage detection for single cells;

[0090] like Figure 4 As shown in the figure, static voltage detection is specifically as follows:

[0091] The host computer sets the target voltage value, sends a control instruction of the simulated target voltage value to the BMS detection equipment, and sends a single voltage reading request to the main board through the CAN bus. After the slave board completes the single voltage acquisition, the main board feeds back the CAN response message containing the single voltage data to the host computer. The host computer compares the current voltage value with the target voltage value based on the feedback, calculates the voltage difference, and determines whether it meets the accuracy standard. If it meets the standard, it is determined that the static voltage acquisition function of the slave board is normal. If it does not meet the standard, it is determined that the static voltage acquisition function of the slave board is abnormal. The accuracy standard is: within a sampling period of ≤100ms, if the set target voltage value is less than 5V, the sampling error is ≤0.005V, indicating that the function is normal, otherwise it is abnormal; if the set target point voltage value is between 5-15V, the sampling error is ≤0.2%, indicating that the function is normal, otherwise it is abnormal.

[0092] like Figure 5 As shown in the figure, the overcharge voltage detection is as follows:

[0093] The overcharge voltage value is set and the battery is charged. When the battery reaches the limit voltage, the host computer sends a request to the main board via the CAN bus to read the cell voltage and real-time alarm status. After the slave completes the cell voltage acquisition, the main board sends a CAN response message containing the cell voltage data and real-time alarm status to the host computer. The host computer compares the current voltage value with the set overcharge voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, the slave overcharge voltage acquisition function is normal; if it does not, the slave overcharge voltage acquisition function is abnormal. At the same time, the host computer parses the CAN message containing the real-time alarm status returned by the main board to check whether the main board can correctly detect and report the overcharge status flag when the limit voltage is reached. The accuracy standard is: within a sampling period of ≤100ms, if the set target voltage value is less than 5V, the sampling error is ≤0.005V, indicating that the function is normal; otherwise, it is abnormal. If the set target voltage value is between 5-15V, the sampling error is ≤0.2%, indicating that the function is normal; otherwise, it is abnormal.

[0094] like Figure 6 As shown in the figure, the over-discharge voltage detection is specifically as follows:

[0095] The over-discharge voltage value is set and the battery is discharged. When the battery reaches the limit voltage, the host computer sends a request to the mainboard via the CAN bus to read the cell voltage and real-time alarm status. After the slave completes voltage acquisition, the mainboard sends a CAN response message containing the cell voltage data and real-time alarm status to the host computer. The host computer compares the current voltage value with the set over-discharge voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, the slave over-discharge voltage acquisition function is normal; if it does not, it is abnormal. At the same time, the host computer parses the CAN message containing the real-time alarm status returned by the mainboard to check whether the mainboard can correctly determine and report the over-discharge status flag when the limit voltage is reached. The accuracy standard is: within a sampling period of ≤100ms, if the set target voltage value is less than 5V, a sampling error of ≤0.005V indicates that the function is normal; otherwise, it is abnormal. If the set target voltage value is between 5-15V, a sampling error of ≤0.2% indicates that the function is normal; otherwise, it is abnormal.

[0096] like Figure 7 As shown, the accuracy test of the temperature acquisition from the board is as follows:

[0097] The host computer sets the target temperature value and loads the RT table of the relationship between thermistor resistance and temperature. It sends a control instruction to simulate the temperature value to the BMS detection device and sends a temperature reading request to the main board via the CAN bus. After the slave board completes temperature acquisition, the main board feeds back a CAN response message containing the temperature data to the host computer. The host computer compares the current temperature value with the target temperature value based on the feedback, calculates the temperature difference, and determines whether it meets the accuracy standard. If it does, it is determined that the slave board temperature acquisition function is normal. If it does not, it is determined that the slave board temperature acquisition function is abnormal. The accuracy standard is: within a sampling period of ≤1s, if the set target temperature value T is between -20 and 65℃, then a sampling error of ≤1℃ indicates that the function is normal, otherwise it is abnormal; if the set target temperature value T is between -40℃≤T<-20℃℃, 65<T≤125℃, then a sampling error of ≤2℃ indicates that the function is normal, otherwise it is abnormal.

[0098] The mainboard relay control function test specifically includes the mainboard IN port test and the mainboard OUT port test;

[0099] like Figure 8 As shown, the motherboard OUT port detection is specifically as follows:

[0100] The host computer initializes the relay status and sends a control command to disconnect the relay to the mainboard via the CAN bus. The mainboard outputs a high-level signal through the OUT port to drive the relay to disconnect. The host computer reads back the relay status through the BMS detection device. If it detects that the relay has been successfully disconnected, it is determined that the control function of the mainboard OUT port is normal; otherwise, it is determined that the control of the mainboard OUT port is abnormal.

[0101] like Figure 9 As shown, the motherboard IN port detection is specifically as follows:

[0102] The host computer initializes the relay status and sends a control instruction to close the relay to the BMS detection device. After the BMS detection device controls the relay to close, the mainboard reads back the relay status through the IN port. If a low-level signal is read, it is determined that the reading function of the mainboard IN port is normal; otherwise, it is determined that the reading function of the mainboard IN port is abnormal.

[0103] like Figure 10 As shown, the storage capacity detection is specifically as follows:

[0104] Set the standard capacity value, and the host computer sends a FRAM storage detection request command to the main board through the CAN bus. After receiving the command message, the main board completes the storage capacity detection operation and feeds back a response message containing the storage capacity information to the host computer. The host computer compares the actual storage capacity value fed back with the standard storage capacity value. If the actual storage capacity value is consistent with the standard storage capacity value, it is determined that the storage capacity of the FRAM chip is normal. If not, it is determined to be abnormal.

[0105] like Figure 11 As shown, the Flash function detection is specifically as follows:

[0106] The host computer sends a Flash erase request command to the main board via the CAN bus. After the main board executes the erase operation, it sends a CAN response message containing the erase completion to the host computer.

[0107] After the host computer receives the CAN response message of the erase completion, it sends a Flash write request instruction to the main board. The instruction contains the target address and the data to be written. After the main board completes the write operation, it feeds back the CAN response message of the write completion to the host computer.

[0108] After the host computer receives the CAN response message of the written data, it sends a Flash read request to the main board, specifying the read address range as the write address range. The main board performs the read operation and feeds back a CAN response message containing the read completion and the read write data to the host computer.

[0109] The host computer compares the read write data with the data to be written. If the data are completely consistent, it is determined that the Flash function is normal and the erase, write and read operations are qualified; if the data are inconsistent, it is determined that the Flash function is abnormal and there is an erase failure, write failure or read error.

[0110] like Figure 12 As shown, the system time function detection is specifically as follows:

[0111] The host computer sends a system time query request to the mainboard through the CAN bus. The mainboard feeds back a CAN response message of the system time to the host computer. The host computer compares the read system time with the current time. If they are inconsistent, it is determined that the mainboard system time function is abnormal. If they are consistent, the host computer sends a 60-second power-off instruction to the BMS detection device to simulate a power-off scenario. After waiting for power to be restored, it sends a system time query request to the mainboard and compares it with the current time again to calculate the time difference. If the time difference is within the preset range, that is, within 60 seconds, it is determined that the mainboard system time function is normal, otherwise it is determined that the mainboard system time function is abnormal.

[0112] like Figure 13 As shown, the insulation function test is specifically as follows:

[0113] The host computer sets the total voltage and insulation resistance value and sends an insulation resistance reading request to the main board via the CAN bus. After the main board completes the insulation resistance calculation using the voltage division method, it feeds back a CAN response message containing the actual total voltage (i.e., the voltage value of the insulation positive electrode to the insulation negative electrode) and the actual insulation resistance (i.e., the resistance value of the insulation positive electrode and the insulation negative electrode to the ground respectively) to the host computer. The actual total voltage is compared with the set total voltage to calculate the voltage difference.

[0114] Compare the actual insulation positive and insulation negative resistance values ​​to ground with the set insulation resistance values ​​one by one, and calculate the resistance difference. If both are within the total voltage and insulation resistance accuracy range, the insulation function is judged to be normal. If any one does not meet the requirements, the insulation function is judged to be abnormal, that is, the acquisition of total voltage, insulation positive and insulation negative resistance has failed.

[0115] like Figure 14 As shown in the figure, the variable temperature power test is as follows:

[0116] Set the temperature range to be measured and select the temperature values ​​to be measured in turn. At the same temperature to be measured, set the initial SOC state of the battery pack to 100% to ensure that the system is in a fully charged state. If the SOC is less than 100%, charge it to 100%, set the discharge current to discharge, and send a read request for real-time current, temperature, allowable current, and power data to the mainboard through the CAN bus. The mainboard will calculate the allowable current and power. After the slave board completes temperature acquisition, the mainboard returns a CAN response message to the host computer.

[0117] When the SOC drops to 0%, the charging current is set to start charging, and a read request for real-time current, temperature, allowable current, and power data is sent to the mainboard via the CAN bus. The mainboard calculates the allowable current and power. After the slave board completes temperature acquisition, the mainboard returns a CAN response message to the host computer.

[0118] After the current temperature is measured, reselect the next temperature and repeat the above steps until all temperatures within the temperature range are measured.

[0119] The host computer analyzes the real-time current, temperature, allowable current, and power data, and compares them with the standard limit power calculation results. If they are the same, it is determined that the power limit function is normal. Otherwise, it is determined that the power limit function is abnormal, and there are abnormal temperature collection, inaccurate SOC changes, and abnormal power limit function.

[0120] like Figure 15 As shown, the SOC calibration function test is specifically as follows:

[0121] Set the voltage value and charging current to charge the battery to put it in an overvoltage state, then set the discharge current to discharge it, send a real-time voltage and current reading request to the mainboard through the CAN bus, and record the discharge time. After the mainboard calculates the discharge capacity, it returns a CAN response message containing real-time voltage, current, and capacity data to the host computer, and compares them with the results obtained by the set values. If they are the same, it is determined that the SOC calibration function is normal, otherwise the SOC calibration function is abnormal.

[0122] like Figure 16-Figure 19 As shown, a system for implementing a BMS master-slave board detection method based on BMS-HIL includes a host computer, a BMS detection device, a main board and a slave board with bidirectional data interaction connection, wherein the host computer and the main board exchange data via a CAN bus, the host computer and the BMS detection device exchange data via a switch, and the master and slave boards exchange data via a CAN bus.

[0123] The BMS detection equipment includes a virtual battery unit, a constant current source unit, an insulation resistance test unit, a temperature simulation unit, an I / O port drive detection unit, and a CAN communication unit;

[0124] The mainboard includes a power interface, a battery pack terminal voltage interface, a current acquisition interface, a mainboard OUT port, a mainboard IN port, and a communication interface;

[0125] The slave board includes a communication interface and a sampling interface capable of both temperature sampling and voltage sampling.

[0126] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0127] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A BMS master-slave board detection method based on BMS-HIL, characterized by: The following steps are involved: The master and slave boards and BMS testing equipment are powered on, CAN communication is established between the master and slave boards and the host computer, the communication interface and voltage channel are initialized, and the master and slave board testing items are selected on the host computer according to the testing requirements and the testing is started. The host computer sends instructions for the corresponding testing items to the master and slave boards. After the master and slave boards execute the instructions, they feed back the results to the host computer. The host computer determines the test results and completes the master and slave board testing. The master and slave board testing items include master and slave board basic function testing, mainboard chip testing, and mainboard electrical function testing. If you select the master and slave board basic function test, that is, the voltage and current acquisition accuracy and relay control function of the main board are tested, and the voltage and temperature acquisition accuracy of the slave board are tested; the host computer judges the test results. If the test results of the main board or the slave board fail, the basic function of the main board or the slave board is judged to be abnormal, and the test results are recorded; if the test results of the main board and the slave board are both qualified, the basic functions of the master and slave boards are judged to be normal; If you select the motherboard chip test, the motherboard chip will be tested for storage capacity, Flash function, and system time function. The host computer will judge the test results. If any test result fails, the motherboard chip will be judged to be abnormal and the test results will be recorded. If all the test results are qualified, the motherboard chip will be judged to be normal. If the mainboard electrical function test is selected, the mainboard chip will be subjected to insulation function test, variable temperature power test, and SOC calibration function test; the host computer will judge the test results. If any test result fails, the corresponding function of the mainboard test will be judged to be abnormal, and the test results will be recorded. If all the test results are qualified, the mainboard electrical function will be judged to be up to standard.

2. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The mainboard voltage acquisition accuracy test is as follows: The host computer sets the target voltage value, sends a control instruction to simulate the target voltage value to the BMS detection device, and sends a total voltage reading request to the mainboard via the CAN bus. After the mainboard completes the total voltage acquisition, it feeds back the CAN response message containing the total voltage data to the host computer. The host computer compares the current voltage value with the target voltage value based on the feedback, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the mainboard voltage acquisition function is normal. If it does not, it is determined that the mainboard voltage acquisition function is abnormal. The mainboard current collection accuracy test is as follows: The host computer sets the target charge / discharge current value, charges or discharges the battery, and sends a current reading request to the mainboard via the CAN bus. The mainboard feeds back the CAN response message containing the current data to the host computer. The host computer compares the current value fed back with the target charge / discharge current value, calculates the current difference, and determines whether it meets the accuracy standard. If it does, it is determined that the mainboard's current collection function is normal. If not, it is determined that the mainboard's current collection function is abnormal. The voltage acquisition accuracy test from the board specifically includes static voltage detection, overcharge voltage detection, and over-discharge voltage detection for single cells; The static voltage detection is as follows: The host computer sets the target voltage value, sends a control instruction to simulate the target voltage value to the BMS detection equipment, and sends a single-cell voltage reading request to the main board through the CAN bus. After the slave board completes the single-cell voltage acquisition, the main board feeds back the CAN response message containing the single-cell voltage data to the host computer. The host computer compares the current voltage value fed back with the target voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the static voltage acquisition function of the slave board is normal. If it does not, it is determined that the static voltage acquisition function of the slave board is abnormal. The overcharge voltage detection is as follows: Set the overcharge voltage value and charge the battery. When the battery reaches the limit voltage value, the host computer sends a request to the main board via the CAN bus to read the single cell voltage and real-time alarm status. After the slave board completes the single cell voltage acquisition, the main board feeds back a CAN response message containing the single cell voltage data and real-time alarm status to the host computer. The host computer compares the current voltage value fed back with the set overcharge voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the overcharge voltage acquisition function of the slave board is normal. If it does not, it is determined that the overcharge voltage acquisition function of the slave board is abnormal. At the same time, the CAN message containing the real-time alarm status returned by the main board is parsed to check whether the main board can correctly determine the overcharge status flag and report it when the limit voltage value is reached. The over-discharge voltage detection is as follows: Set the over-discharge voltage value and discharge the battery. When the battery reaches the limit voltage value, the host computer sends a request to the main board via the CAN bus to read the single cell voltage and real-time alarm status. After the slave board completes voltage acquisition, the main board feeds back a CAN response message containing the single cell voltage data and real-time alarm status to the host computer. The host computer compares the current voltage value fed back with the set over-discharge voltage value, calculates the voltage difference, and determines whether it meets the accuracy standard. If it does, it is determined that the slave board over-discharge voltage acquisition function is normal. If it does not, it is determined that the slave board over-discharge voltage acquisition function is abnormal. At the same time, the CAN message containing the real-time alarm status returned by the main board is parsed to check whether the main board can correctly determine the over-discharge status flag and report it when the limit voltage value is reached. The specific detection of the temperature acquisition accuracy from the board is as follows: The host computer sets the target temperature value and loads the RT table of the relationship between thermistor resistance and temperature. It sends a control instruction to simulate the temperature value to the BMS detection device and sends a temperature reading request to the main board through the CAN bus. After the slave board completes temperature acquisition, the main board feeds back a CAN response message containing temperature data to the host computer. The host computer compares the current temperature value with the target temperature value based on the feedback, calculates the temperature difference, and determines whether it meets the accuracy standard. If it does, it is determined that the slave board temperature acquisition function is normal. If it does not, it is determined that the slave board temperature acquisition function is abnormal.

3. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The mainboard relay control function test specifically includes the mainboard IN port test and the mainboard OUT port test; The specific detection of the motherboard OUT port is as follows: The host computer initializes the relay status and sends a control command to disconnect the relay to the mainboard via the CAN bus. The mainboard outputs a high-level signal through the OUT port to drive the relay to disconnect. The host computer reads back the relay status through the BMS detection device. If it detects that the relay has been successfully disconnected, it is determined that the control function of the mainboard OUT port is normal; otherwise, it is determined that the control of the mainboard OUT port is abnormal. The motherboard IN port detection is as follows: The host computer initializes the relay status and sends a control command to close the relay to the BMS detection device. After the BMS detection device controls the relay to close, the mainboard reads back the relay status through the IN port. If a low-level signal is read, it is determined that the mainboard IN port reading function is normal. Otherwise, it is determined that the reading function of the motherboard IN port is abnormal.

4. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The storage capacity detection is specifically as follows: Set the standard capacity value, and the host computer sends a FRAM storage detection request command to the main board through the CAN bus. After receiving the command message, the main board completes the storage capacity detection operation and feeds back a response message containing the storage capacity information to the host computer. The host computer compares the actual storage capacity value fed back with the standard storage capacity value. If the actual storage capacity value is consistent with the standard storage capacity value, it is determined that the storage capacity of the FRAM chip is normal. If not, it is determined to be abnormal.

5. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The Flash function detection is specifically as follows: The host computer sends a Flash erase request command to the main board via the CAN bus. After the main board executes the erase operation, it sends a CAN response message containing the erase completion to the host computer. After the host computer receives the CAN response message of the erase completion, it sends a Flash write request instruction to the main board. The instruction contains the target address and the data to be written. After the main board completes the write operation, it feeds back the CAN response message of the write completion to the host computer. After the host computer receives the CAN response message of the written data, it sends a Flash read request to the main board, specifying the read address range as the write address range. The main board performs the read operation and feeds back a CAN response message containing the read completion and the read write data to the host computer. The host computer compares the read write data with the data to be written. If the data are completely consistent, it is determined that the Flash function is normal and the erase, write and read operations are qualified; if the data are inconsistent, it is determined that the Flash function is abnormal and there is an erase failure, write failure or read error.

6. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The system time function detection is specifically as follows: The host computer sends a system time query request to the mainboard through the CAN bus. The mainboard feeds back a CAN response message of the system time to the host computer. The host computer compares the read system time with the current time. If they are inconsistent, it is determined that the mainboard system time function is abnormal. If they are consistent, the host computer sends a 60-second power-off instruction to the BMS detection device to simulate a power-off scenario. After waiting for power to be restored, it sends a system time query request to the mainboard and compares it with the current time again to calculate the time difference. If the time difference is within the preset range, that is, within 60 seconds, it is determined that the mainboard system time function is normal. Otherwise, it is determined that the mainboard system time function is abnormal.

7. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The insulation function test is specifically as follows: The host computer sets the total voltage and insulation resistance value and sends an insulation resistance reading request to the main board via the CAN bus. After the main board completes the insulation resistance calculation using the voltage division method, it feeds back a CAN response message containing the actual total voltage (i.e., the voltage value of the insulation positive electrode to the insulation negative electrode) and the actual insulation resistance (i.e., the resistance value of the insulation positive electrode and the insulation negative electrode to the ground respectively) to the host computer. The actual total voltage is compared with the set total voltage to calculate the voltage difference. Compare the actual insulation positive and insulation negative resistance values ​​to ground with the set insulation resistance values ​​one by one, and calculate the resistance difference. If both are within the total voltage and insulation resistance accuracy range, the insulation function is judged to be normal. If any one does not meet the requirements, the insulation function is judged to be abnormal.

8. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The specific test of variable temperature power is as follows: Set the temperature range to be measured and select the temperature values ​​to be measured in sequence. At the same temperature to be measured, set the initial SOC state of the battery pack to 100% to ensure that the system is in a fully charged state. If the SOC is less than 100%, charge it to 100%, set the discharge current for discharge, and send a read request for real-time current, temperature, allowable current, and power data to the mainboard via the CAN bus, waiting for the mainboard to calculate the allowable current and power; After the slave board completes temperature acquisition, the main board returns a CAN response message to the host computer. When the SOC drops to 0%, the charging current is set to start charging, and a read request for real-time current, temperature, allowable current, and power data is sent to the mainboard via the CAN bus, and the mainboard calculates the allowable current and power; After the slave board completes temperature acquisition, the main board returns a CAN response message to the host computer. After the current temperature is measured, reselect the next temperature and repeat the above steps until all temperatures within the temperature range are measured. The host computer analyzes the real-time current, temperature, allowable current, and power data, and compares them with the standard limit power calculation results. If they are the same, it is determined that the power limit function is normal; otherwise, it is determined that the power limit function is abnormal.

9. The BMS master-slave board detection method based on BMS-HIL according to claim 1, characterized in that: The SOC calibration function test is specifically as follows: Set the voltage value and charging current to charge the battery to put it in an overvoltage state, then set the discharge current to discharge it, send a real-time voltage and current reading request to the mainboard through the CAN bus, and record the discharge time. After the mainboard calculates the discharge capacity, it returns a CAN response message containing real-time voltage, current, and capacity data to the host computer, and compares them with the results obtained by the set values. If they are the same, it is determined that the SOC calibration function is normal, otherwise the SOC calibration function is abnormal.

10. A system for implementing the BMS master-slave board detection method based on BMS-HIL according to any one of claims 1 to 9, characterized in that: It includes a host computer, a BMS detection device, a main board and a slave board with two-way data interaction connection. The host computer and the main board exchange data through the CAN bus, the host computer and the BMS detection device exchange data through the switch, and the master and slave boards exchange data through the CAN bus. The BMS detection equipment includes a virtual battery unit, a constant current source unit, an insulation resistance test unit, a temperature simulation unit, an I / O port drive detection unit, and a CAN communication unit; The mainboard includes a power interface, a battery pack terminal voltage interface, a current acquisition interface, a mainboard OUT port, a mainboard IN port, and a communication interface; The slave board includes a communication interface and a sampling interface capable of both temperature sampling and voltage sampling.

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