Practical device for providing and detecting high-speed digital signals

Abstract

The invention provides a practical device for providing and detecting high-speed digital signals, and belongs to the technical field of integrated circuit testing. Comprising an equipment box body, and a main control module, a signal generation module, a dynamic resource allocation module, a parameter detection module and an auxiliary module are installed in the equipment box body. According to the invention, an ADATE318 chip is configured by setting an SPI interface of the main control module; a CRC check unit is matched to ensure zero error of data transmission, so that high-precision control, multifunctional signal generation, rapid channel switching, high-precision detection, data integrity check, dynamic gain adjustment, time-frequency domain feature extraction, heterogeneous calculation and resource scheduling, system stability optimization and transient interference suppression are achieved; according to the invention, the characteristics of high-precision measurement, high-precision measurement, high-precision measurement, eye diagram analysis, time sequence evaluation, wide-range voltage output and the like are provided, a dynamic clamping circuit is integrated through a signal generation module, multi-gear current output (reflection suppression is greater than or equal to 40dB) from + / -2 [mu] A to + / -40mA is supported and set, threshold voltage closed-loop calibration is realized through an SAR algorithm, and the measurement speed is increased by 50%.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a practical device for providing and detecting high-speed digital signals. Background Art

[0002] Semiconductor chip: A semiconductor device that can achieve a certain function by etching and wiring on a semiconductor sheet. It is not just silicon chips, but also common semiconductor materials such as gallium arsenide and germanium.

[0003] A semiconductor chip digital test card is disclosed in the Chinese invention patent application disclosure specification CN114002584A. Although the semiconductor chip digital test card adopts Intel's CY10FPGA and the interface chip E818AFH to achieve 128-channel high density and 50MHz high-speed output; uses the OPA277 op amp to complete the multi-speed PPMU; is completely independently developed and can partially replace imports; it is a low-cost solution, but the integration is low: the design of this solution requires the use of multiple FPGAs and other integrated chips, which consumes more hardware resources, and the data error is large: the lowest gear is ±20uA, which cannot meet the error accuracy requirements of industrial-grade applications, and the speed is low: in the digital signal output mode, it can only provide a transmission rate of 50Mhz, which cannot cope with occasions requiring high-speed digital signal processing. Therefore, the present application provides a practical device for providing and detecting high-speed digital signals to meet the needs. Summary of the Invention

[0004] (1) Technical problems solved

[0005] In response to the shortcomings of the existing technology, the present invention provides a practical device for providing and detecting high-speed digital signals, which solves the problems of low integration, large errors, and only being able to provide a transmission rate of 50Mhz in the digital signal output mode, and being unable to cope with the problems requiring high-speed digital signal processing.

[0006] (2) Technical solution

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] A practical device for providing and detecting high-speed digital signals, comprising a device housing, wherein a main control module, a signal generation module, a dynamic resource allocation module, a parameter detection module, and an auxiliary module are installed inside the device housing, a power supply and a line slot are installed on an upper portion of one side of the device housing, and a cover plate is installed on one side of the device housing;

[0009] The main control module is implemented based on FPGA and configures the VIL, VIH, VOL, and VOH registers of the ADATE318 chip through the SPI interface to set the high and low level voltage values ​​(V OH =2.5V,V OL =0.8V) and the logic comparison threshold of the DI input terminal (V IH =1.8V,V IL =0.5V), error compensation satisfies ∈≤0.01%·V ref , and the SPI clock phase matches the SCLK falling edge latch timing requirements;

[0010] The signal generation module integrates PPMU function, writes register settings via SPI to set the ±2μA to ±40mA flow range, and drives the DAC to generate the threshold voltage The output voltage / current is measured using the successive approximation method (SAR) to achieve analog parameter measurement of chip pins. Five current ranges are configurable through the SPI interface: ±40mA, ±1mA, ±100μA, ±10μA, and ±2μA, supporting chip pin parameter testing.

[0011] The dynamic resource allocation module integrates a relay drive circuit to switch the DUT channel to the HVOUT high-voltage channel, providing VHH drive capability (0.0V-13.5V), supporting flash memory test applications, and the switching response time t switch ≤10μs;

[0012] The parameter detection module adopts Michelson interferometer calibration technology, and the voltage resolution meets Supports dual-channel data transmission (I2C+SPI) and CRC check, with an error δ≤0.1%.

[0013] Preferably, the main control module integrates a bus protocol rule verification unit to verify the data logic consistency through a preset verification instruction set to meet

[0014] D i To send data, D′ i To receive data, the data integrity is checked through XOR operation.

[0015] Preferably, the signal generating module includes a gain regulator, the R f is the feedback resistor (1kΩ-10kΩ), R i The input resistance dynamically adjusts the differential signal differential mode amplification factor The threshold voltage is synchronously transmitted to the main control module.

[0016] Preferably, the parameter detection module is embedded in the time-frequency domain feature extraction unit, and the signal characteristic parameters are extracted by fast Fourier transform (FFT). Matching the preset type library realizes the signal loss alarm under the multi-level specification, wherein N is the number of sampling points, and the number of points is 1024 or 2048.

[0017] Preferably, the dynamic resource allocation module supports heterogeneous computing architecture, and the task allocation efficiency meets The LBT mechanism (Listen Before Talk) is used to achieve multi-channel parallel testing in unlicensed frequency bands, with spectrum utilization rate p≥90%;

[0018] Where T atomic is the atomic task processing time, T total For the total task time, the LBT mechanism optimizes resource scheduling.

[0019] Preferably, the auxiliary module integrates a phase margin optimization unit, R0 is the output stage equivalent impedance, the typical value is 50Ω, C0 is the compensation capacitor, the capacitance range is 10pF-100nF, and the system stability is improved by adjusting the main pole frequency. The main pole frequency is adjusted by the folded sleeve OTA structure. Increase response speed.

[0020] Preferably, the signal generation module integrates a dynamic clamping circuit to suppress transient interference during high voltage switching, with a signal reflection suppression of α≥40dB. Transient voltage spikes are absorbed by dynamic clamping to reduce signal reflection interference.

[0021] Preferably, a probe interface is installed in the auxiliary module, and the probe interface supports an eye diagram analysis function, with an eye diagram opening of full UI ≥ 85% and a jitter tolerance σ ≤ 10%;

[0022] Where UI is the eye diagram unit interval, σ is the jitter standard deviation, and signal timing quality is evaluated through high-speed sampling.

[0023] Preferably, the VHH driving capability of the dynamic resource allocation module is achieved by integrating DAC and gain regulator, and the output voltage satisfies where R f =10kΩ,R i =1kΩ, R f / R i =10kΩ / 1kΩ resistor network matching accuracy requirement, error compensation accuracy ≤0.05%, high voltage channel drive combined with DAC and resistor network to achieve wide range voltage output.

[0024] Preferably, in the Michelson interferometer calibration technology of the parameter detection module, the voltage resolution is improved to sub-microvolt level through high-precision interference calibration, the calibration coefficient k is calibrated to 1.2-1.8 through experiments, and the number of interferences n≥1000.

[0025] Compared with the prior art, the present invention has at least the following beneficial effects:

[0026] In the above solution, the VIL, VIH, VOL, and VOH registers of the ADATE318 chip are configured through the SPI interface of the main control module. In conjunction with the CRC check unit, error-free data transmission is ensured. Features include high-precision control, multifunctional signal generation, fast channel switching, high-precision detection, data integrity verification, dynamic gain adjustment, time-frequency domain feature extraction, heterogeneous computing and resource scheduling, system stability optimization, transient interference suppression, eye diagram analysis and timing evaluation, and a wide range of voltage output. This provides an efficient, stable, and accurate test solution.

[0027] The signal generation module integrates a dynamic clamping circuit, supporting multiple current output levels from ±2μA to ±100nA (reflection suppression ≥40dB). Threshold voltage closed-loop calibration is achieved through the SAR algorithm, increasing measurement speed by 50%. Quantitative evaluation of GHz signal quality is achieved through phase margin and eye diagram analysis.

[0028] In summary, the present invention has the advantages of ultra-high-speed signal output, single-chip solution, high integration, and can significantly reduce hardware design resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of a practical device for providing and detecting high-speed digital signals;

[0030] Figure 2 A schematic diagram of the internal structure of a practical device box for providing and detecting high-speed digital signals;

[0031] Figure 3 A schematic diagram of a flow chart of a practical device for providing and detecting high-speed digital signals;

[0032] Figure 4 The figure is a schematic diagram of the working process of each module of a practical device for providing and detecting high-speed digital signals.

[0033] [reference numerals]

[0034] 1. Equipment box; 2. Main control module; 3. Signal generation module; 4. Dynamic resource allocation module; 5. Parameter detection module; 6. Auxiliary module; 7. Power supply; 8. Line trough.

[0035] As shown in the figure, in order to clearly implement the structure of the embodiment of the present invention, specific structures and devices are marked in the figure, but this is only for illustrative purposes and is not intended to limit the present invention to the specific structure, device and environment. According to specific needs, ordinary technicians in this field can adjust or modify these devices and environments. DETAILED DESCRIPTION

[0036] The following describes in detail a practical device for providing and detecting high-speed digital signals provided by the present invention, with reference to the accompanying drawings and specific embodiments. It is also noted that, to provide a more detailed description, the following embodiments are best and preferred embodiments, and those skilled in the art may employ alternative implementations for known techniques. Furthermore, the accompanying drawings are intended only to provide a more detailed description of the embodiments and are not intended to limit the present invention.

[0037] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes such specific features, structures, or characteristics. In addition, when specific features, structures, or characteristics are described in conjunction with an embodiment, it is within the knowledge of persons skilled in the relevant art to implement such features, structures, or characteristics in conjunction with other embodiments (whether or not explicitly described).

[0038] In general, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular sense, or can be used to describe a combination of features, structures, or characteristics in the plural sense. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but can instead, depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0039] It will be understood that the meanings of “on,” “over,” and “above” in the present invention should be interpreted in the broadest manner, so that “on” means not only “directly on” something but also includes the meaning of being “on” something with intervening features or layers, and “on” or “above” means not only “on” or “above” something but also includes the meaning of being “on” or “above” something with no intervening features or layers.

[0040] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein for descriptive convenience to describe the relationship of one element or feature to another element or features, as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways, and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0041] like Figure 1 and Figure 4 As shown, an embodiment of the present invention provides a practical device for providing and detecting high-speed digital signals, including a device housing 1, wherein a main control module 2, a signal generation module 3, a dynamic resource allocation module 4, a parameter detection module 5, and an auxiliary module 6 are installed inside the device housing 1, a power supply 7 and a line slot 8 are installed on the upper portion of one side of the device housing 1, and a cover plate is installed on one side of the device housing 1;

[0042] The main control module 2 is implemented based on FPGA and configures the VIL, VIH, VOL, and VOH registers of the ADATE318 chip through the SPI interface to set the high and low level voltage values ​​(V OH =2.5V,V OL =0.8V) and the logic comparison threshold of the DI input terminal (V IH =1.8V,V IL =0.5V), error compensation satisfies ∈≤0.01%·V ref , and the SPI clock phase matches the SCLK falling edge latch timing requirements;

[0043] The signal generation module 3 integrates the PPMU function, writes register settings via SPI to set the ±2μA to ±40mA flow range, and drives the DAC to generate a threshold voltage The output voltage / current is measured using the successive approximation method (SAR) to achieve analog parameter measurement of chip pins. Five current ranges are configurable through the SPI interface: ±40mA, ±1mA, ±100μA, ±10μA, and ±2μA, supporting chip pin parameter testing.

[0044] The dynamic resource allocation module 4 integrates a relay drive circuit to switch the DUT channel to the HVOUT high-voltage channel, providing VHH drive capability (0.0V-13.5V), supporting flash memory test applications, and the switching response time t switch ≤10μs;

[0045] The parameter detection module 5 adopts Michelson interferometer calibration technology, and the voltage resolution meets Supports dual-channel data transmission (I2C+SPI) and CRC check, with an error δ≤0.1%.

[0046] Preferably, the main control module 2 integrates a bus protocol rule verification unit to verify the data logic consistency through a preset verification instruction set to meet

[0047] D i To send data, D i ' is to receive data and verify the data integrity through XOR operation.

[0048] The main control module 2 dynamically adjusts the input / output level threshold through SPI, and combines FPGA timing compensation to achieve high-speed signal processing. The PPMU configures the gear status through registers and combines DAC and SAR algorithms to complete high-precision parameter acquisition. The relay module realizes fast switching of high-voltage channels to meet the concurrency requirements of multiple tasks. The parameter detection module improves the resolution through interferometer calibration, and dual-channel redundant transmission ensures data reliability.

[0049] The signal generating module 3 includes a gain regulator, the R f is the feedback resistor (1kΩ-10kΩ), R i The input resistance dynamically adjusts the differential signal differential mode amplification factor The threshold voltage is synchronously transmitted to the main control module 2, D i To send data, D′ i To receive data, the data integrity is checked through XOR operation.

[0050] The parameter detection module 5 is embedded in the time-frequency domain feature extraction unit, and extracts the signal characteristic parameters through the fast Fourier transform (FFT) Matching the preset type library realizes signal loss alarm under multi-level specifications, wherein N is the number of sampling points, which is 1024 or 2048, and the abnormal signal is quickly identified through frequency domain analysis.

[0051] The dynamic resource allocation module 4 supports heterogeneous computing architecture, and the task allocation efficiency meets The LBT mechanism (Listen Before Talk) is used to achieve multi-channel parallel testing in unlicensed frequency bands, with spectrum utilization rate p≥90%;

[0052] Where T atomic is the atomic task processing time, T total For the total task time, the LBT mechanism optimizes resource scheduling.

[0053] The auxiliary module 6 integrates a phase margin optimization unit, R0 is the output stage equivalent impedance, with a typical value of 50Ω, C0 is the compensation capacitor, with a capacitance range of 10pF-100nF, and the system stability is improved by adjusting the main pole frequency. The main pole frequency is adjusted through the folded sleeve OTA structure. Increase response speed.

[0054] The signal generation module 3 integrates a dynamic clamping circuit to suppress transient interference during high-voltage switching, with a signal reflection suppression of α≥40dB. Dynamic clamping absorbs transient voltage spikes to reduce signal reflection interference.

[0055] A probe interface is installed in the auxiliary module 6, and the probe interface supports eye diagram analysis function, with eye diagram opening full UI ≥ 85% and jitter tolerance σ ≤ 10%;

[0056] Where UI is the eye diagram unit interval, σ is the jitter standard deviation, and signal timing quality is evaluated through high-speed sampling.

[0057] The VHH driving capability of the dynamic resource allocation module 4 is achieved by integrating DAC and gain regulator, and the output voltage satisfies where R f =10kΩ,R i =1kΩ, R f / R i =10kΩ / 1kΩ resistor network matching accuracy requirement, error compensation accuracy ≤0.05%, high voltage channel drive combined with DAC and resistor network to achieve wide range voltage output.

[0058] In the Michelson interferometer calibration technology of the parameter detection module 5, the voltage resolution is improved to the sub-microvolt level through high-precision interference calibration, the calibration coefficient k is calibrated to 1.2-1.8 through experiments, and the number of interferences n≥1000.

[0059] Power supply 7 powers each module. The FPGA controls the VIL and VIH registers in the ADATE318 via the SPI interface to set the high and low voltage levels in DO. The VOH and VOL registers are used to perform a logical comparison of the input signal level in DI. This enables rapid processing of high-speed digital signals. The PPMU function changes the gear setting by writing data into the registers, then drives the DAC to set the comparison threshold. Successive approximation is used to measure and output voltage or current, enabling analog parameter measurement of the chip pins.

[0060] The experimental data table of this embodiment is as follows:

[0061]

[0062] The technical solution provided by the present invention is as follows: the device is started and initialized;

[0063] Initialize the FPGA and ADATE318 chip: Configure the SPI interface registers, including VIL, VIH, VOL, and VOH, to set the high and low voltage values ​​of the DO output and the logic comparison threshold of the DI input.

[0064] Signal Generation Module (PPMU function): Sets the current range, drives the DAC to generate the threshold voltage, and uses the successive approximation method (SAR) for measurement.

[0065] Dynamic resource allocation module: switches the DUT channel to the HVOUT high-voltage channel through the relay drive circuit, provides VHH drive capability, and supports the LBT mechanism for multi-channel parallel testing.

[0066] Parameter detection module: Use Michelson interferometer calibration technology to measure voltage and transmit data through dual channels (I 2 C+SPI) and perform CRC check, and can also perform time-frequency image analysis (FFT) to extract signal features.

[0067] Phase margin optimization and dynamic clamping: Optimize phase margin by adjusting the dominant pole frequency and use a dynamic clamping circuit to suppress transient interference.

[0068] Eye diagram analysis and jitter tolerance evaluation: Perform eye diagram analysis on the signal to evaluate the eye opening and jitter tolerance.

[0069] Result output and storage: Output and store measurement results and analysis data.

[0070] End: The device completes the current task and enters standby mode or prepares for the next measurement.

[0071] The present invention encompasses any alternatives, modifications, equivalents, and solutions that fall within the spirit and scope of the present invention. To provide a thorough understanding of the present invention, specific details are described in detail below in connection with the preferred embodiments of the present invention, but those skilled in the art will be able to fully understand the present invention without these detailed descriptions. Furthermore, to avoid unnecessary confusion regarding the essence of the present invention, well-known methods, processes, procedures, components, and circuits have not been described in detail.

[0072] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A practical device for providing and detecting high-speed digital signals, characterized in that The device comprises a device box (1), wherein a main control module (2), a signal generation module (3), a dynamic resource allocation module (4), a parameter detection module (5) and an auxiliary module (6) are installed inside the device box (1), a power supply (7) and a line trough (8) are installed on the upper part of one side of the device box (1), and a cover plate is installed on one side of the device box (1); The main control module (2) is implemented based on FPGA and configures the VIL, VIH, VOL, and VOH registers of the ADATE318 chip through the SPI interface to set the high and low level voltage values ​​(V OH =2.5V,V OL =0.8V) and the logic comparison threshold of the DI input terminal (V IH =1.8V,V IL =0.5V), error compensation satisfies ∈≤0.01%·V ref , and the SPI clock phase matches the SCLK falling edge latch timing requirements; The signal generation module (3) integrates the PPMU function, writes register settings via SPI to set the ±2μA to ±40mA flow range, and drives the DAC to generate a threshold voltage Use the successive approximation method (SAR) to measure output voltage / current and realize analog parameter measurement of chip pins; The dynamic resource allocation module (4) integrates a relay drive circuit, switches the DUT channel to the HVOUT high-voltage channel, provides VHH drive capability (0.0V-13.5V), supports flash memory test applications, and has a switching response time t switch ≤10μs; The parameter detection module (5) adopts Michelson interferometer calibration technology, and the voltage resolution meets Supports dual-channel data transmission (I2C+SPI) and CRC check, with an error δ≤0.1%.

2. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that The main control module (2) integrates a bus protocol rule verification unit, which verifies the data logic consistency through a preset verification instruction set to meet D i To send data, D′ i To receive data, the data integrity is checked through XOR operation.

3. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: The signal generating module (3) includes a gain regulator, the R f is the feedback resistor (1kΩ-10kΩ), R i The input resistance dynamically adjusts the differential signal differential mode amplification factor The threshold voltage is synchronously transmitted to the main control module (1).

4. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: The parameter detection module (5) is embedded in the time-frequency domain feature extraction unit, and extracts the signal feature parameters through fast Fourier transform (FFT) Matching the preset type library realizes the signal loss alarm under the multi-level specification, wherein N is the number of sampling points, and the number of points is 1024 or 2048.

5. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: The dynamic resource allocation module (4) supports heterogeneous computing architecture, and the task allocation efficiency meets The LBT mechanism (Listen Before Talk) is used to achieve multi-channel parallel testing in unlicensed frequency bands, with spectrum utilization rate p≥90%; Where T atomic is the atomic task processing time, T total For the total task time, the LBT mechanism optimizes resource scheduling.

6. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: The auxiliary module (6) integrates a phase margin optimization unit, R0 is the output stage equivalent impedance, with a typical value of 50Ω, C0 is the compensation capacitor, with a capacitance range of 10pF-100nF, and the system stability is improved by adjusting the main pole frequency. The main pole frequency is adjusted by the folded sleeve OTA structure. Increase response speed.

7. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: The signal generation module (3) integrates a dynamic clamping circuit to suppress transient interference during high-voltage switching, and the signal reflection suppression α≥40dB. The transient voltage spike is absorbed by dynamic clamping to reduce signal reflection interference.

8. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: A probe interface is installed in the auxiliary module (6), and the probe interface supports an eye diagram analysis function, with an eye diagram opening full UI ≥ 85% and a jitter tolerance σ ≤ 10%; Where UI is the eye diagram unit interval, σ is the jitter standard deviation, and signal timing quality is evaluated through high-speed sampling.

9. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: The VHH driving capability of the dynamic resource allocation module (4) is achieved by integrating DAC and gain regulator, and the output voltage satisfies where R f =10kΩ,R i =1kΩ, R f / R i =10kΩ / 1kΩ resistor network matching accuracy requirement, error compensation accuracy ≤0.05%, high voltage channel drive combined with DAC and resistor network to achieve wide range voltage output.

10. The practical device for providing and detecting high-speed digital signals according to claim 1, characterized in that: In the Michelson interferometer calibration technology of the parameter detection module (5), the voltage resolution is improved to the sub-microvolt level through high-precision interference calibration, the calibration coefficient k is calibrated to 1.2-1.8 through experiments, and the number of interferences n is ≥1000.

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