Low-power-consumption SOC optimization method and system

Abstract

The invention provides a low-power-consumption SOC optimization method and system. The method comprises the following steps: periodically sampling interface states of a plurality of interfaces; periodically determining a joint weight, wherein the joint weight is used for indicating the relevance among the interfaces; determining the relevance between the interfaces and the behaviors based on the corresponding relation between the interface states of the plurality of historical interfaces and the actual behaviors; determining a prediction behavior of the current period based on the relevance between the interface and the behavior, the interface state of the current period and the joint weight of the current period; and determining a target clock domain and a target power supply domain based on the prediction behavior of the current period, the first corresponding relation and the second corresponding relation, and triggering a control strategy of a power supply and a clock based on the target clock domain and the target power supply domain. Under different working modes, power supply, clock and data storage strategies of multiple modules are dynamically coordinated, system-level power consumption optimization is achieved, and meanwhile rapid wakeup and data integrity are ensured.

Description

Technical Field

[0001] The present application relates to the field of SOC, and in particular to a low-power SOC optimization method and system. Background Art

[0002] In embedded systems and mobile devices, the collaborative operation of multiple modules (such as the CPU, DDR, SRAM, and peripherals) complicates power management. Existing technologies typically employ independent strategies, such as clock gating to reduce dynamic power consumption, power domain management to shut down inactive modules, and data compression to reduce power to storage units. However, these approaches all suffer from low resource utilization: for example, dedicated buses are used only for specific tasks and lack deep integration with other low-power strategies (such as clock gating and power domain management), failing to maximize energy efficiency. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a low-power SOC optimization method and system to improve resource utilization.

[0004] In a first aspect, the present invention provides a low-power SOC optimization method, wherein the SOC includes multiple clock domains and multiple power domains; the SOC maintains a first correspondence between clock domains and behaviors and a second correspondence between power domains and behaviors; the SOC includes multiple interfaces, and the interfaces include GPIO interfaces; the method includes:

[0005] Periodically sampling the interface states of the plurality of interfaces;

[0006] Periodically determining a joint weight, where the joint weight is used to indicate the association between the interfaces;

[0007] Determining the relevance between the interface and the behavior based on the historical correspondence between the interface states of the plurality of interfaces and the actual behavior;

[0008] Determine the predicted behavior for the current period based on the correlation between the interface and the behavior, the interface status of the current period, and the joint weight of the current period;

[0009] Based on the predicted behavior of the current cycle, the first corresponding relationship, and the second corresponding relationship, a target clock domain and a target power domain are determined, and a power and clock control strategy is triggered based on the target clock domain and the target power domain.

[0010] In a second aspect, the present invention provides a low-power SOC optimization system, wherein the SOC includes multiple clock domains and multiple power domains; the SOC maintains a first correspondence between clock domains and behaviors and a second correspondence between power domains and behaviors; the SOC includes multiple interfaces, wherein the interfaces include GPIO interfaces; the optimization system includes:

[0011] A collection module, used for periodically sampling the interface status of a plurality of said interfaces;

[0012] A first determining module, configured to periodically determine a joint weight, wherein the joint weight is used to indicate a correlation between the interfaces;

[0013] a second determining module, configured to determine the relevance between the interface and the behavior based on a historical correspondence between the interface states of the plurality of interfaces and the actual behavior;

[0014] A prediction module, configured to determine a predicted behavior for the current period based on the correlation between the interface and the behavior, the interface state for the current period, and a joint weight for the current period;

[0015] The control module is used to determine the target clock domain and the target power domain based on the predicted behavior of the current cycle, the first corresponding relationship, and the second corresponding relationship, and trigger the power and clock control strategy based on the target clock domain and the target power domain.

[0016] The embodiment of the present application provides a low-power SOC optimization method and system. By periodically sampling the interface status of multiple interfaces; periodically determining the joint weight, the joint weight is used to indicate the correlation between each of the interfaces; based on the historical correspondence between the interface status of multiple interfaces and the actual behavior, the correlation between the interface and the behavior is determined; based on the correlation between the interface and the behavior, the interface status of the current cycle and the joint weight of the current cycle, the predicted behavior of the current cycle is determined; based on the predicted behavior of the current cycle, the first correspondence, and the second correspondence, the target clock domain and the target power domain are determined, and the power and clock control strategy is triggered based on the target clock domain and the target power domain. In different working modes, the power, clock and data storage strategies of multiple modules are dynamically coordinated to achieve system-level power consumption optimization while ensuring fast wake-up and data integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flowchart of a low-power SOC optimization method provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of a low-power SOC optimization system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0021] Figure 1 This is a flow chart of a low-power SOC optimization method provided by an embodiment of the present application. The SOC includes multiple clock domains and multiple power domains. Both the power domain and the clock domain include a parent domain and child domains. Each parent domain corresponds to one or more child domains, each parent domain corresponds to a master switch, and each child domain corresponds to a child switch. The parent power domain includes the core computing domain, storage domain, communication domain, sensor domain, and display domain. The parent clock domain includes the main clock domain, storage clock domain, communication clock domain, and sensor clock domain.

[0022] Among them, the core computing domains are: CPU and GPU (high power consumption, requiring dynamic frequency regulation).

[0023] Storage domain: DDR, SRAM (medium power consumption, self-refresh on demand).

[0024] Sensor domain: GPIO, I2C (low power, keep listening).

[0025] Example:

[0026] User interaction behavior: The core domain is boosted to 1.0V, and the storage domain is reduced to 0.7V.

[0027] Idle behavior: GPU is turned off and the memory domain enters self-refresh (0.7V).

[0028] Clock domain division:

[0029] Main clock domain: CPU, GPU (high frequency, such as 2.0 GHz).

[0030] Communication clock domain: UART, SPI (medium frequency, such as 100MHz).

[0031] Sensor clock domain: GPIO, ADC (low frequency, such as 10MHz).

[0032] Example:

[0033] Predicted behavior: User interaction: CPU frequency increased to 2.0GHz, screen refresh rate set to 60Hz.

[0034] Predicted behavior: Idle: Main clock throttled to 200MHz, sensor clock gated (periodic sampling only).

[0035] The SOC maintains a first correspondence between a clock domain and a behavior and a second correspondence between a power domain and a behavior. The SOC includes multiple interfaces, including a GPIO interface.

[0036] The second corresponding relationship may be as described in Table 1 below:

[0037] Table 1

[0038] Power parent domain Power subdomain Default state Behavioral Association Core computing domain CPU, GPU, NPU Active (1.0V) User interaction, high-performance tasks Storage Domain DDR, low-power SRAM Retention (0.7V) Data access requirements communication domain I2C, SPI, UART Active (1.0V) Sensor data transmission and reception, peripheral control Sensor Domain GPIO (buttons, environmental sensors) Low-Power (0.9V) Environmental monitoring, wake-up detection Display Field Screen driver, backlight Off (0V) User-initiated interaction

[0039] The first corresponding relationship may be as described in Table 2 below:

[0040] Table 2

[0041] Clock domain Included modules Default frequency Behavioral Association Main clock domain CPU, GPU 2.0GHz User interaction, computationally intensive tasks Storage clock domain DDR controller, SRAM 1.2GHz Data access operations Communication clock domain I2C, SPI, UART 100MHz Peripheral data transmission Sensor clock domain GPIO interface, ADC 10MHz Sensor sampling

[0042] like Figure 1 As shown, the method includes:

[0043] S110: Periodically sample interface statuses of multiple interfaces.

[0044] The interface status can refer to the active or idle state of the interface.

[0045] Active interfaces are generally transmitting data (such as a GPIO button being pressed or a UART receiving data).

[0046] An idle interface is generally an interface with no data transmission (for example, a sensor is not triggered or a screen is not operated).

[0047] The sampling period refers to the time interval at which the system periodically detects the interface status (for example, sampling every 100 ms).

[0048] The sampling process can be when the interface state changes (such as GPIO edge trigger), triggering the interrupt service routine (ISR), recording the state and updating the register. For example, when the user presses the GPIO button, the ISR changes the interface state from 0 to 1.

[0049] You can also use a timer to periodically read the interface register status (for example, querying every 100ms whether an I2C sensor has returned data). For example, you can read the I2C interface status of a temperature and humidity sensor once per second.

[0050] S120 , periodically determining a joint weight, where the joint weight is used to indicate the association between the interfaces.

[0051] In practice, the joint weight can be determined based on historical interaction data between interfaces. For example, if two interfaces are frequently active simultaneously across multiple behaviors, their joint weight is high, indicating a strong correlation between the two interfaces. This correlation can be used to predict the activity state of the interfaces in future behaviors, thereby optimizing power and clock management.

[0052] To more accurately determine the joint weight, we can also consider the time decay effect between interfaces. That is, if two interfaces have not been active together for a long time, the correlation between them may weaken. This time decay effect can be simulated by introducing parameters such as the time decay weight and the decay rate.

[0053] The joint weight W can be determined based on the following formula ij (t), this formula combines the time decay effect and the recent collaborative mode to ensure real-time and low-overhead requirements. It can quickly reduce the weight of long-term uncoordinated interfaces and avoid outdated data from interfering with predictions. The larger the value, the smaller the weight. The sliding window collaboration item is used to capture the recent collaboration rules of the interface pair. High-frequency co-occurrence is given a high weight to adapt to short-term behavioral pattern changes:

[0054] ;

[0055] in, : time decay weight;

[0056] : Decay rate; it can control the decay speed and can efficiently handle time-sensitive problems (such as =0.1 slow decay, =1.0 with a sharp decay).

[0057] : The last period in which interfaces i and j were jointly active;

[0058] T: The total number of cycles, which can be determined according to actual needs; it can balance real-time performance and noise suppression (a larger T means stronger noise immunity; a smaller T means faster response).

[0059] (Related to the time decay effect) This is to assign dynamic weights to historical events, meaning that the longer the time since the last joint activity, the more significant the weight decay;

[0060] (Related to recent collaboration patterns) This is the frequency with which interfaces i and j were simultaneously active over the past T cycles, indicating the strength of their recent association.

[0061] pass and Balances weighting of historical decay with recent statistics.

[0062] The combination with the highest prediction accuracy can be selected on the validation set through grid search or Bayesian optimization.

[0063] S130 , determining the correlation between the interface and the behavior based on the historical correspondence between the interface states of the plurality of interfaces and the actual behavior.

[0064] Correlation coefficient It can be determined based on the following formula

[0065] ;

[0066] Correlation coefficient It can also be determined based on the following formula:

[0067] ;

[0068] in:

[0069] i, j represents the interface number index;

[0070] : the kth behavior, m is the number of behaviors, k∈m;

[0071] p ijk Indicates that interfaces i and j are active at the same time and trigger actions within the historical period T The conditional probability of

[0072] N is the total number of statistical cycles (the recommended range is 100-1000 sampling cycles);

[0073] d ijk is the attenuation factor (range 0.9-0.99), which is used to reduce the weight of early historical data;

[0074] T interval Indicates the interval coefficient between the current cycle and the reference cycle (when the sliding window mechanism is adopted, T interval = current cycle number - window start cycle number);

[0075] This formula dynamically adjusts the correlation strength in two dimensions: in the time dimension, through the exponential decay factor d ijk Implement a gradual forgetting mechanism for historical data to ensure that the system can adapt to changes in usage patterns; in the spatial dimension, through the conditional probability p ijk Capture the cooperative activation pattern between interfaces. For example, when the GPIO button (interface i=5) and the SPI screen interface (j=8) present p in the user interaction scene (k=1) 5,8,1 =0.93, indicating that the linkage between the two interfaces can be used as an important feature to predict user interaction behavior.

[0076] In specific implementation, the correlation coefficient matrix can be constructed through the following steps:

[0077] Initialize the three-dimensional matrix C[m][n][n] and set the initial weights according to the mapping relationship between the interface numbers and the parent domains (e.g., sensor domain interface group S = {9, 10, 11}, display domain interface group D = {7, 8}).

[0078] Collect statistics on interface status joint active events within a sliding time window (recommended length: 50-200 cycles):

[0079] When interfaces i and j are both in the Active state and the system executes behavior Bk, the counter CT ijk +=1; when any interface is active but no action is triggered, the counter CT ijk =0.5 (penalty term);

[0080] Every time T calibrate Recalculate p for 10 to 20 cycles (10 to 20 cycles is recommended) ijk and d ijk :

[0081] p ijk =CT ijk / Σ(CT::k);

[0082] d ijk =1-(current epoch -last activeepochijk ) / N decay ;

[0083] where N decay is the decay period constant (default 100);

[0084] Normalize the coefficient matrix to ensure ΣC::k∈[0,1];

[0085] p ijk Indicates the proportion of a specific value by using the local value CT ijk It is compared with the sum of the overall values ​​and is used to measure the weight of the local in the global.

[0086] CT ijk Is a local value.

[0087] Σ(CT::k) represents the sum calculation of the counter values.

[0088] d ijk Represents a decay value that changes over time and is used to measure the freshness or activity of an event or state.

[0089] current epoch Represents the current time point or timestamp, used to dynamically calculate time-related variables.

[0090] N decay Represents the decay factor, which controls the speed of time decay. The larger the value, the slower the decay; the smaller the value, the faster the decay.

[0091] Application example: In the user interaction scenario, when the C 5,8,1 =0.87, and the joint weight W 5,8 When (t)=0.92, the linkage of these two interfaces will significantly improve the prediction probability of user interaction behavior. In the idle scenario, if the C 12,3,idle =0.05, indicating that the active state of these two interfaces is negatively correlated with the idle behavior.

[0092] Next, the system dynamically adjusts the weights of each interface in predicting user behavior based on the calculated correlation coefficient matrix. Highly correlated interface combinations are given higher weights to more accurately predict user behavior. Furthermore, the system continuously updates the correlation coefficient matrix based on historical data to adapt to changing usage patterns.

[0093] During implementation, the system also incorporates other factors, such as user habits and contextual information, to further improve prediction accuracy. For example, if a user frequently performs a specific operation, the system will prioritize interface combinations related to that operation, thereby improving prediction accuracy.

[0094] S140 , determining a predicted behavior for the current period based on the correlation between the interface and the behavior, the interface state for the current period, and the joint weight for the current period.

[0095] If the probability of the target behavior occurring in the current cycle is greater than a first threshold and the difference between the probability of the target behavior and other behaviors occurring in the current cycle is greater than a second threshold, the predicted behavior in the current cycle is determined to be the target behavior.

[0096] The probability of each behavior in the current cycle can be determined based on the following formula:

[0097] ;

[0098] in, : the kth behavior, m is the number of behaviors, k∈m;

[0099] : The state of the interface in the current cycle t; where S(t)=[s1(t),s2(t),...,s n (t)];

[0100] : Behavior B k In the current cycle t, behavior B k probability of occurrence;

[0101] : Behavior B k The correlation coefficient between interface i and interface j is as follows, where n is the number of interfaces, i∈n, i∈n;

[0102] : The joint weight of interface i and interface j in the current period t.

[0103] The parameters α, β, T, θ can be k As the action space of reinforcement learning, a Markov decision process is constructed to perform parameter optimization.

[0104] The state space of the Markov decision process is the interface active frequency, power consumption level, temperature, and remaining power.

[0105] In some embodiments, the SOC includes a temperature sensor.

[0106] The second threshold Δθ may be determined based on the following formula:

[0107] ;

[0108] Where μ is the mean of all behaviors and σ is the standard deviation of all behaviors.

[0109] S150 , determining a target clock domain and a target power domain based on the predicted behavior of the current cycle, the first corresponding relationship, and the second corresponding relationship, and triggering a power and clock control strategy based on the target clock domain and the target power domain.

[0110] The predicted behavior can be mapped to the target clock domain using the first correspondence, and the mapping can be achieved through a lookup table or a lookup algorithm based on the first correspondence. Simultaneously, the predicted behavior can be mapped to the target power domain using the second correspondence, and the mapping can also be achieved through a lookup table or a lookup algorithm based on the first correspondence.

[0111] After determining the target clock domain and target power domain, the corresponding power and clock control strategies can be triggered, such as adjusting the output frequency of the clock generator, switching the power state of the power management unit (PMU), and adjusting the voltage level. Throughout the process, power and clock adjustments are coordinated to avoid timing issues or performance degradation.

[0112] For example, the interface characteristics of the predicted user interaction behavior may be: GPIO button high level + SPI screen data flow > 10KB / s. Based on the first and second correspondences, the target clock domain and target power domain corresponding to the predicted behavior are determined. The following policy actions can be performed on the target clock domain and target power domain:

[0113] Power supply: The core computing domain is boosted to 1.0V and the display domain is turned on.

[0114] Clock: CPU frequency increased to 2.0GHz, screen refresh rate 60Hz.

[0115] The interface characteristics monitored by the predicted behavior sensor can be an I2C temperature and humidity sensor that triggers a +GPIO interrupt pulse every 2 seconds. Based on the first and second correspondences, the target clock domain and target power domain corresponding to the predicted behavior are determined. The following policy actions can be performed on the target clock domain and target power domain:

[0116] Power supply: The communication domain maintains 0.9V, and the sensor domain is stepped down to 0.8V.

[0117] Clock: SPI frequency is reduced to 50MHz, and GPIO gated clock is enabled with 10MHz sampling.

[0118] The interface feature of the predicted idle behavior can be considered as no activity on all interfaces within 5 minutes. Based on the first correspondence and the second correspondence, the target clock domain and target power domain corresponding to the predicted behavior are determined. The following policy actions can be performed on the target clock domain and target power domain:

[0119] Power supply: The storage domain is reduced to 0.7V and the core computing domain is shut down.

[0120] Clock: DDR enters self-refresh mode (1.2GHz→200MHz), sensor clock is gated.

[0121] After implementing the power and clock control strategy, monitor the system's power consumption and performance to ensure optimal power consumption while meeting behavioral requirements. If system power consumption exceeds a preset threshold or performance falls short of expectations, adjust the control strategy and re-determine the target clock and power domains until a balance between power consumption and performance is achieved.

[0122] As user behavior patterns change, the activity and relevance of interfaces will also adjust accordingly. The system must continuously monitor interface status, including transitions in active interfaces, changes in coordination patterns between interfaces, and migrations in behavior patterns. For example, when transitioning from user interaction mode to idle mode, the interface status may change from high activity to low activity or no activity.

[0123] When a significant change in the interface state or behavior pattern is detected, the system needs to re-evaluate the correlation between the interface and the behavior (such as recalculating the correlation coefficient C ijk ) and the joint weight W ij (t). This ensures that the prediction model can capture changes in user behavior in real time and avoids the interference of outdated data on the prediction results.

[0124] Based on the updated associations and weights, the system needs to re-determine the target clock and power domains and trigger the corresponding power and clock control policies. For example, if the user's behavior changes from data-intensive tasks to simple environmental monitoring, the system needs to reduce the voltage and frequency of the core computing domain and turn off unnecessary interface power to maximize power savings.

[0125] Through continuous monitoring and dynamic adjustment, the system can ensure real-time optimization of power consumption and performance while meeting user behavior needs, thereby improving overall energy efficiency.

[0126] The system periodically repeats the above steps to adjust power management and clock configuration in real time according to the dynamic changes in user behavior to adapt to different usage scenarios and achieve dual guarantees of low power consumption and high performance.

[0127] In addition, this SOC also has adaptive learning capabilities, which can continuously optimize the correlation evaluation model and behavior prediction algorithm between interfaces based on user usage habits, improve prediction accuracy and response speed, and provide users with a smoother and more energy-saving usage experience.

[0128] In the implementation examples, this SOC has been successfully applied to low-power smart terminals such as smartphones, tablets, and wearable devices, effectively extending device battery life while ensuring a smooth user experience. In the future, with the continuous optimization of algorithms and the upgrading of hardware technology, the performance and power consumption of this SOC will be further improved, providing strong support for the development of the Internet of Things, edge computing and other fields.

[0129] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a low-power SOC optimization device is given below. Optionally, the low-power SOC optimization can adopt the above Figure 2 For further information, please refer to Figure 2 , Figure 2 This is a functional module diagram of a low-power SOC optimization device provided by an embodiment of the present invention. It should be noted that the basic principles and technical effects of the low-power SOC optimization device provided by this embodiment are the same as those of the above embodiments. For the sake of simplicity, for parts not mentioned in this embodiment, please refer to the corresponding content in the above embodiments. The low-power SOC optimization device includes:

[0130] Figure 2 This is a schematic diagram of a low-power SOC optimization system structure provided by an embodiment of the present application. The SOC includes multiple clock domains and multiple power domains; the SOC maintains a first correspondence between clock domains and behaviors and a second correspondence between power domains and behaviors; the SOC includes multiple interfaces, including a GPIO interface; the optimization system includes:

[0131] The acquisition module 201 is used to periodically sample the interface status of multiple interfaces;

[0132] A first determining module 202 is configured to periodically determine a joint weight, where the joint weight indicates the association between the interfaces;

[0133] The second determining module 203 is configured to determine the relevance between the interface and the behavior based on the correspondence between the interface states of the plurality of interfaces and the actual behavior in history;

[0134] Prediction module 204, configured to determine a predicted behavior for the current period based on the association between the interface and the behavior, the interface state for the current period, and the joint weight for the current period;

[0135] The control module 205 is configured to determine a target clock domain and a target power domain based on the predicted behavior of the current cycle, the first corresponding relationship, and the second corresponding relationship, and trigger a power and clock control strategy based on the target clock domain and the target power domain.

[0136] In some embodiments, the SOC also includes a temperature sensor.

[0137] In some embodiments, the power domain and the clock domain both include a parent domain and a child domain, each parent domain corresponds to one or more child domains, each parent domain corresponds to a main switch, and each child domain corresponds to a child switch; the parent power domain includes a core computing domain, a storage domain, a communication domain, a sensor domain, and a display domain; the parent clock domain includes a main clock domain, a storage clock domain, a communication clock domain, and a sensor clock domain.

[0138] Optionally, the modules can be stored in a memory in the form of software or firmware, or embedded in the operating system (OS) optimized for the low-power SOC, and executed by a processor. Furthermore, the data and program code required to execute the modules can be stored in the memory.

[0139] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a portion of code, and the module, program segment or a portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0140] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0141] If the functions are implemented in the form of software modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, electronic device, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0142] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A low-power SOC optimization method, characterized in that: The SOC includes multiple clock domains and multiple power domains; the SOC maintains a first correspondence between clock domains and behaviors and a second correspondence between power domains and behaviors; the SOC includes multiple interfaces, and the interfaces include GPIO interfaces; the method includes: Periodically sampling the interface states of the plurality of interfaces; Periodically determining a joint weight, where the joint weight is used to indicate the association between the interfaces; Determining the relevance between the interface and the behavior based on the historical correspondence between the interface states of the plurality of interfaces and the actual behavior; Determine the predicted behavior for the current period based on the correlation between the interface and the behavior, the interface status of the current period, and the joint weight of the current period; Based on the predicted behavior of the current cycle, the first corresponding relationship and the second corresponding relationship, a target clock domain and a target power domain are determined, and a power and clock control strategy is triggered based on the target clock domain and the target power domain.

2. The method according to claim 1, characterized in that If the probability of the target behavior occurring in the current cycle is greater than a first threshold and the difference between the probability of the target behavior and other behaviors occurring in the current cycle is greater than a second threshold, the predicted behavior in the current cycle is determined to be the target behavior.

3. The method according to claim 2, characterized in that The probability of each behavior in the current period is determined based on the following formula: ； in, : the kth behavior, m is the number of behaviors, k∈m; : The status of the interface in the current period t; : Behavior B k In the current cycle t, behavior B k probability of occurrence; : Behavior B k The correlation coefficient between interface i and interface j, n is the number of interfaces, i∈n; : The joint weight of interface i and interface j in the current period t.

4. The method according to claim 3, characterized in that W is determined based on the following formula ij (t): ； in, : time decay weight; : decay rate; : The last period in which interfaces i and j were jointly active; T: total number of cycles.

5. The method according to claim 4, characterized in that The parameters α, β, T, θ k As the action space of reinforcement learning, a Markov decision process is constructed to perform parameter optimization.

6. The method according to claim 5, characterized in that The state space of the Markov decision process is the interface active frequency, power consumption level, temperature, and remaining power.

7. The method according to claim 6, characterized in that The SOC includes a temperature sensor.

8. The method according to claim 2, characterized in that The second threshold Δθ is determined based on the following formula: ； Where μ is the mean of all behaviors and σ is the standard deviation of all behaviors.

9. The method according to claim 1, characterized in that The power domain and clock domain both include a parent domain and a child domain, each parent domain corresponds to one or more child domains, each parent domain corresponds to a main switch, and each child domain corresponds to a child switch; the parent power domain includes a core computing domain, a storage domain, a communication domain, a sensor domain, and a display domain; the parent clock domain includes a main clock domain, a storage clock domain, a communication clock domain, and a sensor clock domain.

10. A low-power SOC optimization system, characterized in that: The SOC includes multiple clock domains and multiple power domains; the SOC maintains a first correspondence between clock domains and behaviors and a second correspondence between power domains and behaviors; the SOC includes multiple interfaces, and the interfaces include GPIO interfaces; the optimization system includes: A collection module, used for periodically sampling the interface status of a plurality of said interfaces; A first determining module, configured to periodically determine a joint weight, wherein the joint weight is used to indicate a correlation between the interfaces; a second determining module, configured to determine the relevance between the interface and the behavior based on a historical correspondence between the interface states of the plurality of interfaces and the actual behavior; A prediction module, configured to determine a predicted behavior for the current period based on the correlation between the interface and the behavior, the interface state for the current period, and a joint weight for the current period; The control module is used to determine the target clock domain and the target power domain based on the predicted behavior of the current cycle, the first corresponding relationship and the second corresponding relationship, and trigger the power and clock control strategy based on the target clock domain and the target power domain.

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