Circuit and control method for preventing accidental triggering of hard drive soft destruction

Abstract

This application discloses a circuit and control method for preventing accidental triggering of hard drive soft erase, relating to the field of hard drive soft erase technology. The circuit includes an erase button, a complex programmable logic module (CPL) module, and a transmission module. The CPL module confirms erase by pressing the erase button again within a preset time threshold after the original erase button is pressed. Upon confirmation, it outputs an erase control signal to the hard drive, triggering the erase operation. This eliminates the need for a protective cover to prevent accidental triggering, significantly reducing operational complexity. Operators can quickly and accurately trigger the hard drive erase button. Furthermore, the protective cover does not damage the overall appearance of the hard drive, affecting the aesthetics of the device, nor does it increase the design, manufacturing, and installation costs of the protective cover. Even if the protective cover is damaged or lost, the hard drive erase button will not be exposed, thus preserving its protective function.

Description

Technical Field

[0001] This application relates to the field of hard disk soft destruction technology, and in particular to circuits and control methods for preventing accidental triggering of hard disk soft destruction. Background Technology

[0002] In today's digital age, data has become one of the most valuable assets for businesses and individuals. Hard drives, as primary storage devices, carry massive amounts of critical information, making the secure handling of this data a crucial issue. Compared to physical destruction, logical destruction can save on the costs associated with physical hard drive disposal. Theoretically, after logical destruction, hard drives can still be recycled or reused, reducing the generation of electronic waste.

[0003] Traditional logical disk destruction methods typically use a protective cover for physical isolation to prevent accidental triggering of the disk destroy button. This reduces the risk of accidental triggering of the disk destroy button even in the event of system malfunction or interference. However, in emergency situations, the protective cover may increase the complexity of the operation, making it difficult for operators to quickly and accurately trigger the disk destroy button. Summary of the Invention

[0004] This application provides a circuit and control method for preventing accidental triggering of hard drive soft destruction, so as to at least solve the problem in the related technology that the protective cover increases the complexity of operation, making it impossible for operators to quickly and accurately trigger the hard drive destruction button.

[0005] This application provides a circuit to prevent accidental triggering of hard disk soft erase, comprising:

[0006] The destroy button receives and outputs a destroy signal and a destroy confirmation signal based on a preset operation.

[0007] The complex programmable logic module is connected to the destroy button. When a destroy signal is received, it is used to detect whether a destroy confirmation signal is received within a preset time threshold, and when a destroy confirmation signal is received within the preset time threshold, it outputs a destroy control signal.

[0008] The transmission module is connected to both the complex programmable logic module and the hard disk. It is used to receive the destruction control signal and then turn on to transmit the destruction control signal to the hard disk.

[0009] This application also provides a control method for a circuit that prevents accidental triggering of hard disk soft-wipe, the method being applied to the aforementioned circuit for preventing accidental triggering of hard disk soft-wipe, the method comprising:

[0010] When the complex programmable logic module receives a destruction signal, it checks whether a destruction confirmation signal has been received within a preset time threshold.

[0011] If a destruction confirmation signal is received within the preset time threshold, a destruction control signal is output to the transmission module.

[0012] The control transmission module is activated after receiving the destruction control signal to transmit the destruction control signal to the hard drive.

[0013] This application allows the complex programmable logic module to confirm destruction by pressing the destroy button again within a preset time threshold after the initial destroy button is pressed, and then outputting a destroy control signal to the hard drive upon confirmation, triggering the destruction operation. This eliminates the need for a protective cover to prevent accidental triggering, significantly reducing operational complexity. Operators can quickly and accurately trigger the hard drive's destroy button without compromising the overall appearance of the hard drive or the aesthetics of the device, and without increasing the design, manufacturing, and installation costs of the protective cover. Furthermore, even if the protective cover is damaged or lost, the hard drive's destroy button will not be exposed, thus preserving its protective function. Attached Figure Description

[0014] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a traditional circuit designed to prevent accidental triggering of hard drive soft destruction.

[0016] Figure 2 This application provides a circuit for preventing accidental triggering of hard drive soft destruction.

[0017] Figure 3 Another circuit for preventing accidental triggering of hard disk soft destruction is provided in the embodiments of this application;

[0018] Figure 4 A flowchart illustrating a control method for a circuit designed to prevent accidental triggering of hard drive soft-killing, as provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0020] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] In today's digital age, data has become one of the most valuable assets for businesses and individuals. Hard drives, as the primary storage devices, carry massive amounts of critical information, making the secure handling of this data a crucial issue. Logical hard drive destruction, as an efficient and relatively economical solution, has emerged to address this need. It can quickly render the data on a hard drive unrecoverable without physical damage, thus protecting sensitive information from leakage.

[0023] Compared to physical destruction, logical destruction can save on the costs associated with physical hard drive destruction. Theoretically, after logical destruction, the hard drive can still be recycled or reused, reducing electronic waste. However, in server or storage systems, accidentally triggering logical destruction can lead to the loss of business data, impacting normal business operations. Furthermore, data recovery after logical destruction is typically very difficult, with a low success rate even using professional data recovery tools or services.

[0024] Existing hard drive soft destruction design methods, such as Figure 1 As shown, when the destroy button triggers the destroy signal, the MCU (Microcontroller Unit) or BMC (Baseboard Management Controller) receives the trigger signal from the destroy button via GPIO, lights up the indicator light, and simultaneously notifies the hard drive to start the destroy action via GPIO.

[0025] Traditional logical disk erasure methods typically use protective covers for physical isolation to prevent accidental triggering of the disk erasure button. Even in the event of system malfunction or interference, this reduces the risk of accidental button activation. However, in emergency situations, protective covers can increase operational complexity, making it difficult for operators to quickly and accurately trigger the disk erasure button. Furthermore, if the protective cover is damaged or lost, the disk erasure button may be exposed, rendering it unprotected. Additionally, protective covers can detract from the overall appearance of the hard drive, affecting the device's aesthetics, and increase the design, manufacturing, and installation costs of the cover.

[0026] Embodiments of this application provide a circuit to prevent accidental triggering of hard drive soft erase, such as... Figure 2 As shown, the circuit for preventing accidental triggering of hard drive soft wipe includes:

[0027] The destroy button receives and outputs a destroy signal based on a preset operation.

[0028] Specifically, refer to Figure 2 The destroy button is SW1. The destroy button outputs a destroy signal based on a press operation. The destroy button sends the destroy signal triggered when the user presses it to the complex programmable logic module 10. The user presses the destroy button to generate a destroy signal, and pressing the destroy button again within a preset time threshold after pressing it generates a destroy confirmation signal. By confirming the destruction by pressing the destroy button again within the preset time threshold, there is no need to install a protective cover to prevent accidental triggering; that is, if the destroy button is pressed accidentally, the destruction operation will not be triggered. Optionally, the destroy button can also be other devices that trigger the destruction information.

[0029] Complex programmable logic module 10 is connected to the destroy button and is used to detect whether the destroy signal is received again within a preset time threshold when the destroy signal is received, and output the destroy control signal when the destroy signal is received again within the preset time threshold.

[0030] Specifically, when the destroy button is pressed, the complex programmable logic module 10 receives a destroy signal. If the destroy button is pressed again within a preset time threshold after the initial press, and the complex programmable logic module 10 receives the destroy signal again within the preset time threshold after receiving the initial destroy signal, it determines this as a destroy confirmation signal. Upon detecting the received destroy confirmation signal, the complex programmable logic module 10 outputs a destroy control signal. Optionally, the complex programmable logic module 10 can be a CPLD (Complex Programmable Logic Device) module.

[0031] For example, the preset time threshold can be 5 seconds. It can also be any set duration.

[0032] The transmission module 20 is connected to the complex programmable logic module 10 and the hard disk, respectively, and is used to receive the destruction control signal and then turn on to transmit the destruction control signal to the hard disk.

[0033] Specifically, the complex programmable logic module 10 outputs multiple destruction control signals. The transmission module 20 receives these signals simultaneously. The transmission module 20 only turns on when all the destruction control signals simultaneously meet its conduction condition, thus greatly improving the reliability and security of the destruction process. Optionally, the transmission module 20 can be a transmission gate. The hard drive is designed with a soft destruction function.

[0034] This application provides a circuit to prevent accidental triggering of hard drive soft erase. A complex programmable logic module 10 confirms erase by pressing the erase button again within a preset time threshold after the erase button is pressed. Upon confirmation, a erase control signal is output to the hard drive, triggering the erase operation. This eliminates the need for a protective cover to prevent accidental triggering, significantly reducing operational complexity. Operators can quickly and accurately trigger the hard drive erase button. Furthermore, the protective cover does not damage the hard drive's overall appearance, affecting the device's aesthetics, nor does it increase the design, manufacturing, and installation costs of the cover. Even if the protective cover is damaged or lost, the hard drive erase button will not be exposed, thus preserving its protective function.

[0035] In one alternative implementation, such as Figure 3 As shown, the complex programmable logic module 10 includes:

[0036] The complex programmable logic device 11 has a first terminal connected to a destroy button and a first preset reference voltage, a second terminal connected to a first control terminal of a transmission module, a third terminal connected to a second control terminal of a transmission module, and a fourth terminal connected to a transmission terminal of a transmission module.

[0037] Specifically, the complex programmable logic device 11 is a CPLD (Complex Programmable Logic Device). The first terminal of the CPLD 11 is GPIO0, through which a destroy signal is received. The second terminal of the CPLD 11 is GPIO1, the third terminal is GPIO2, and the fourth terminal is GPIO3. The first control signal is output through GPIO1, and the second control signal is output through GPIO2. GPIO (General Purpose Input / Output) can output high and low levels or read the status of pins.

[0038] Specifically, the destroy button provides a destroy signal, which is initially high with a logic value of 1. When pressed, the signal is pulled low, becoming low with a logic value of 0. The CPLD receives the destroy signal and is triggered to proceed to the next action. When the complex programmable logic device 11 detects that the destroy button has been pressed, the CPLD starts a timer. If the button is not confirmed again within a preset time threshold, the destroy operation is automatically canceled.

[0039] Specifically, the complex programmable logic device 11 is responsible for logic control. It receives the signal transmitted after the destroy button is triggered via the input pin GPIO0 to confirm whether to execute the destroy action. Then, it controls the on / off switch of the transmission module via the output pins GPIO1 / GPIO2 / GPIO3 of the preset control logic, thereby controlling the hard drive destruction operation. In addition, when the destroy button is detected to be pressed, the CPLD starts a timer. If it is not confirmed again within a few seconds, the destruction operation is automatically canceled.

[0040] Specifically, the destruction control signals include signals output from the second, third, and fourth terminals of the complex programmable logic device 11. The complex programmable logic device 11 simultaneously outputs destruction control signals through the second, third, and fourth terminals, and the transmission module 20 is only turned on when multiple destruction control signals simultaneously meet the conduction conditions of the transmission module 20.

[0041] For example, when the destroy button is pressed for the first time (low-high), the CPLD detects the rising edge of GPIO0, starts an internal timer, and begins waiting for the destroy button to be pressed a second time. At this time, after the CPLD obtains the state of GPIO0, it controls GPIO2 to toggle. The CPLD can use a clock-driven process to implement this frequency division counting and level toggle operation. The CPLD code will count to the point where the frequency division factor is decremented by 1 and then toggle the state of GPIO2, changing it from 0 to 1 or from 1 to 0.

[0042] If the user presses the button again within 5 seconds (high-low), the CPLD detects a falling edge trigger on GPIO0. At this time, the CPLD controls GPIO1 to output a low-level signal, which will turn off the first indicator light, control GPIO2 to output a high-level signal, and then the CPLD controls GPIO3 to output a low-level signal.

[0043] It should be noted that the states are defined by CPLD codes. The high and low level states corresponding to the pressing and releasing of a button are inputs. The CPLD then makes different output responses to these inputs and displays them to the user through indicator lights.

[0044] In one alternative implementation, such as Figure 3 As shown, the transmission module 20 includes two switching transistors connected in parallel;

[0045] The two switching transistors connected in parallel include:

[0046] The first switch transistor T1 has its control terminal connected to the second terminal of the complex programmable logic device 11 and the second preset reference voltage, the first terminal of the first switch transistor T1 is connected to the fourth terminal of the complex programmable logic device 11, and the second terminal of the first switch transistor T1 is connected to the third preset reference voltage and the hard disk, wherein the first switch transistor T1 is a P-type transistor.

[0047] The second switch T2 has its control terminal connected to the third terminal and the ground terminal of the complex programmable logic device 11, its first terminal connected to the fourth terminal of the complex programmable logic device 11, and its second terminal connected to the hard disk. The second switch T2 is an N-type transistor.

[0048] Specifically, the two switching transistors connected in parallel can be CMOS (Complementary Metal Oxide Semiconductor).

[0049] Specifically, a transmission gate is constructed using two parallel-connected switching transistors: a first switching transistor T1 and a second switching transistor T2. The first switching transistor T1 is a P-channel enhancement-mode MOSFET (Metal-Oxide-Semiconductor Transistor), i.e., a PMOS, and the second switching transistor T2 is an N-channel enhancement-mode MOSFET, i.e., an NMOS. Their gates have complementary control signals: GPIO1 is low when GPIO2 is high. The PMOS characteristic is that the drain (D) and source (S) are connected when VG < VS, meaning the first switching transistor T1 is on when GPIO1 is low. The NMOS characteristic is that the drain (D) and source (S) are connected when VG > VS, meaning the second switching transistor T2 is on when GPIO2 is high. The sources of the first switching transistor T1 and the second switching transistor T2 are connected, serving as the output and input terminals of the transmission gate. In other words, by utilizing the complementary conduction characteristics of the first switching transistor T1 and the second switching transistor T2, the overall on-resistance is relatively stable and low.

[0050] For example, when transmitting a high level, the on-resistance of the NMOS increases, but the on-resistance of the PMOS is small and stable; when transmitting a low level, the on-resistance of the PMOS increases, but the on-resistance of the NMOS is small and stable, thereby ensuring the stability of the overall on-resistance and improving the efficiency and quality of signal transmission.

[0051] Furthermore, if a single NMOS or PMOS is used, the disadvantage is that when the NMOS transmits a high level, the output high level will be lowered by a threshold voltage, resulting in signal distortion; when the PMOS transmits a low level, the output low level will be raised by a threshold voltage, also causing signal distortion. However, the transmission gate utilizes the complementary characteristics of NMOS and PMOS. When transmitting a high level, the PMOS is turned on and the NMOS is turned off, so there is no threshold loss for the high level; when transmitting a low level, the NMOS is turned on and the PMOS is turned off, so there is also no threshold loss for the low level. This enables complete signal transmission and ensures signal integrity and accuracy.

[0052] It should be noted that when the transmission gate is on, GPIO3 is pulled low, and the low-level signal is transmitted to the hard drive, triggering the hard drive's logical destruction function. This puts the hard drive's data or control circuits in a low-level state, thus implementing the logical destruction operation. When the transmission gate is off, the path between GPIO3 and GPIO4 is cut off, and the hard drive's logical destruction signal remains high. The hard drive continues to operate normally, and the data and control circuits are unaffected. This prevents accidental destruction of the hard drive due to external interference or misoperation, protecting the hard drive's data security.

[0053] In one alternative implementation, such as Figure 2 As shown, the circuit for preventing accidental triggering of hard drive soft wipe also includes:

[0054] The status display module 30 is connected to the complex programmable logic module 10 and is used to display the current destruction status.

[0055] Specifically, the circuit for preventing accidental soft hard drive destruction includes three operating modes: idle state, destruction preparation state, and destruction execution state. When the destroy button is pressed, the state machine switches from the "idle state" to the "destruction preparation state." Pressing the button again causes the state machine to enter the "destruction execution state" and perform the destruction operation. The current destruction status is displayed through the status display module 30, thereby improving the reliability of the destruction operation.

[0056] Optionally, the status display module 30 may also have a timer display panel to prompt the preset time threshold in a countdown manner.

[0057] In one alternative implementation, such as Figure 3 As shown, the status display module 30 includes:

[0058] The first indicator light is connected to the complex programmable logic module.

[0059] The complex programmable logic module is used to control the first indicator light to illuminate when a destruction signal is received.

[0060] In one alternative implementation, such as Figure 3 As shown, the status display module also includes:

[0061] The second indicator light is connected to the complex programmable logic module 10.

[0062] The complex programmable logic module is used to control the second indicator light to turn off when a destruction signal is received;

[0063] The complex programmable logic module 10 is used to control the second indicator light to flash when a destruction confirmation signal is received;

[0064] The complex programmable logic module 10 is used to control the second indicator light to illuminate when a destruction confirmation signal is received.

[0065] For example, under normal circumstances, when the destroy button is not pressed, GPIO0 is in a high-level state by default due to the pull-up circuit. After the complex programmable logic device 11 obtains that the destroy button is in a high-level state, it pulls GPIO1 high, illuminating the first indicator light, and simultaneously pulls GPIO2 low, extinguishing the second indicator light. At this time, the transmission module 20 is in the off state. Pulling GPIO3 high, GPIO4 is in a high-level state by default, and the hard drive will not trigger the destroy action. At this time, it is in an "idle state", the first indicator light is always on, and the second indicator light is off.

[0066] When a user plans to perform a soft hard drive destruction, they will press the destroy button for the first time. At this time, GPIO0 is pulled low, and the complex programmable logic device 11 obtains that the state of the destroy button is high-low. It outputs a toggle level at a frequency of 2KHz to GPIO2, and the second indicator light starts to flash to indicate to the user that the button has been pressed. At the same time, a 5-second timer starts counting.

[0067] At this point, the device is in the destruction preparation state; the second indicator light is flashing, and the first indicator light is off.

[0068] If a button is pressed a second time (low-high-low-high) within 5 seconds, a destruction operation is performed. GPIO2 is pulled low, the first indicator light goes out, and GPIO2 is pulled high, the second indicator light illuminates, and the transmission module is in the ON state. Pulling GPIO3 low will also pull GPIO4 low because the transmission gate is ON, triggering the hard drive destruction action. At this time, the destruction is in progress, the second indicator light is constantly on, the first indicator light goes out, and the transmission gate opens. It is worth noting that after the hard drive is unplugged and reinserted, it will return to the idle state.

[0069] If the destroy button is not detected to be pressed a second time (remaining high) within 5 seconds, or if the button is still pressed (remaining low) after 5 seconds, the complex programmable logic device 11 will consider it a malfunction and cancel the operation. It will pull GPIO1 high to light up the first indicator light, pull GPIO2 low to turn off the second indicator light, and pull GPIO3 high, returning the hard drive to an idle state. This two-trigger detection mechanism provides a buffer time for the user, avoiding irreversible operations caused by malfunctions.

[0070] Only when GPIO1 is low, GPIO2 is high, and GPIO3 is low will GPIO4 be successfully pulled to 0V. Therefore, when the CPLD hangs, the states of GPIO1 / GPIO12 / GPIO13 are uncertain, the transmission gate cannot be fully turned on, and even if GPIO4 is pulled low, there will still be a certain voltage value, which cannot reach 0V. Even if the CPLD hangs, the hard drive's soft erase function will not be triggered. In other words, GPIO1, GPIO12, and GPIO13 are multiple control signals included in the erase control signal.

[0071] In one alternative implementation, such as Figure 3 As shown, the complex programmable logic module 10 includes:

[0072] The first resistor R1 has its first end connected to the first preset reference voltage and its second end connected to the destroy button.

[0073] Specifically, the first resistor R1 and the first preset reference resistor constitute a pull-up circuit, providing a high level in the idle state.

[0074] In one alternative implementation, such as Figure 3 As shown, the transmission module 20 includes:

[0075] The second resistor R2 has its first end connected to the second preset reference voltage and its second end connected to the control terminal of the first switching transistor T1.

[0076] The third resistor R3 has its first end connected to the third preset reference voltage and its second end connected to the second end of the first switching transistor T1.

[0077] The fourth resistor R4 has its first end connected to the control terminal of the second switch T2, and its second end connected to the ground terminal.

[0078] Specifically, the second resistor R2 and the second preset reference voltage form a pull-up circuit, and the third resistor R3 and the third preset reference voltage form a pull-up circuit. The fourth resistor R4 and the ground terminal form a pull-down circuit. The first resistor R1, the second resistor R2, and the third resistor R3 are set to a default high level, and the fourth resistor R4 is set to a default low level.

[0079] Embodiments of this application also provide a control method for a circuit that prevents accidental triggering of hard disk soft erase, such as... Figure 4 As shown, the method is applied to the circuit described above to prevent accidental triggering of hard drive soft wipe. The method includes:

[0080] Step 1: When the complex programmable logic module receives a destruction signal, it checks whether a destruction confirmation signal has been received within a preset time threshold.

[0081] Step 2: If a destruction confirmation signal is received within the preset time threshold, a destruction control signal is output to the transmission module;

[0082] Step 3: After receiving the destruction control signal, the control transmission module is turned on to transmit the destruction control signal to the hard drive.

[0083] Specifically, the input of the complex programmable logic module is high when it is idle, low when it receives a destroy signal, and high again when the destroy button is pressed again, thereby determining whether a destroy confirmation signal has been received.

[0084] Specifically, the complex programmable logic module is in an "idle state" before receiving the destruction signal. When the destruction button is pressed, the state machine switches from the "idle state" to the "destruction preparation state". When the button is pressed again, the state machine enters the "destruction execution state" and performs the destruction operation.

[0085] In an optional implementation, the method further includes:

[0086] Step (1): When the complex programmable logic module receives the destruction signal, it controls the first indicator light to light up and the second indicator light to flash;

[0087] Step (2): If a destruction confirmation signal is received within the preset time threshold, the first indicator light is turned off and the second indicator light is turned on.

[0088] refer to Figure 4 When the destroy button is not pressed, it is in an idle state. At this time, GPIO0 is a high input level, GPIO1 outputs a high level to light up the first indicator light (i.e., LED1), GPIO2 outputs a low level to turn off the second indicator light (i.e., LED2), GPIO3 outputs a high level, and GPIO4 remains at a high level.

[0089] When the destroy button is pressed, the system enters the destroy preparation state. GPIO0 is input low, GPIO1 outputs high, the first indicator light remains on, GPIO2 outputs a changing level, the second indicator light flashes, GPIO3 outputs high, and GPIO4 inputs high. After a 5-second countdown, when GPIO0 inputs a high-low-high level sequence, the destroy action is initiated. At this time, GPIO1 outputs low, the first indicator light turns off, GPIO2 outputs high, the second indicator light remains on, GPIO3 outputs low, the transmission gate is activated, GPIO4 is pulled low, and the hard drive begins the destroy process.

[0090] When it is determined that the destruction action will not be performed, GPIO1 outputs a high level, the first indicator light stays on, GPIO2 outputs a low level, the second indicator light goes out, GPIO3 outputs a high level, the transmission gate remains closed, and GPIO4 remains high, entering the idle state.

[0091] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0092] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0093] The circuit and control method for preventing accidental triggering of hard drive soft erase, as provided in this application, have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A circuit for preventing accidental triggering of hard drive soft erase, characterized in that, include: A destroy button, which receives and outputs a destroy signal and a destroy confirmation signal based on a preset operation. A complex programmable logic module, which is connected to the destroy button, is used to detect whether a destroy confirmation signal is received within a preset time threshold when a destroy signal is received, and to output a destroy control signal when a destroy confirmation signal is received within the preset time threshold. A transmission module, which is connected to the complex programmable logic module and the hard disk respectively, is used to receive a destruction control signal and then turn on to transmit the destruction control signal to the hard disk; The complex programmable logic module outputs multiple destruction control signals. When the multiple destruction control signals simultaneously meet the conduction condition of the transmission module, the transmission module is turned on. The complex programmable logic module includes: A complex programmable logic device (CPLD) is provided, wherein a first terminal of the CPLD is connected to the destroy button and a first preset reference voltage, a second terminal of the CPLD is connected to the first control terminal of the transmission module, a third terminal of the CPLD is connected to the second control terminal of the transmission module, and a fourth terminal of the CPLD is connected to the transmission terminal of the transmission module. The transmission module includes two switching transistors connected in parallel. The two switching transistors connected in parallel include: The first switching transistor has its control terminal connected to the second terminal of the complex programmable logic device and the second preset reference voltage, its first terminal connected to the fourth terminal of the complex programmable logic device, and its second terminal connected to the third preset reference voltage and the hard disk. The first switching transistor is a P-type transistor. The second switch is a type N-type transistor. Its control terminal is connected to the third terminal and the ground terminal of the complex programmable logic device (CPLD). Its first terminal is connected to the fourth terminal of the CPLD. Its second terminal is connected to the hard disk.

2. The circuit for preventing accidental triggering of hard drive soft erase as described in claim 1, characterized in that, The circuit for preventing accidental triggering of hard drive soft destruction also includes: A status display module, which is connected to the complex programmable logic module, is used to display the current destruction status.

3. The circuit for preventing accidental triggering of hard drive soft erase according to claim 2, characterized in that, The status display module includes: A first indicator light is connected to the complex programmable logic module. The complex programmable logic module is used to control the first indicator light to illuminate when a destruction signal is received.

4. The circuit for preventing accidental triggering of hard drive soft erase according to claim 3, characterized in that, The status display module also includes: The second indicator light is connected to the complex programmable logic module. The complex programmable logic module is used to control the second indicator light to flash when a destruction signal is received; The complex programmable logic module is used to control the second indicator light to illuminate when a destruction confirmation signal is received.

5. The circuit for preventing accidental triggering of hard drive soft erase according to claim 1, characterized in that, The complex programmable logic module includes: A first resistor, the first end of which is connected to the first preset reference voltage, and the second end of which is connected to the destroy button.

6. The circuit for preventing accidental triggering of hard drive soft erase according to claim 1, characterized in that, The transmission module includes: The second resistor has a first end connected to the second preset reference voltage and a second end connected to the control terminal of the first switching transistor. The third resistor has its first end connected to the third preset reference voltage and its second end connected to the second end of the first switching transistor. The fourth resistor has its first end connected to the control terminal of the second switching transistor and its second end connected to the ground terminal.

7. A control method for a circuit to prevent accidental triggering of hard drive soft erase, characterized in that, The method is applied to the circuit for preventing accidental triggering of hard disk soft destruction as described in any one of claims 1 to 6, the method comprising: When the complex programmable logic module receives a destruction signal, it checks whether a destruction confirmation signal has been received within a preset time threshold. If a destruction confirmation signal is received within the preset time threshold, a destruction control signal is output to the transmission module. After receiving the destruction control signal, the control transmission module is turned on to transmit the destruction control signal to the hard disk.

8. The control method for the circuit preventing accidental triggering of hard disk soft erase according to claim 7, characterized in that, The method further includes: When the complex programmable logic module receives a destruction signal, it controls the first indicator light to illuminate and the second indicator light to flash. If a destruction confirmation signal is received within a preset time threshold, the first indicator light will be turned off, and the second indicator light will be turned on.

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