Circuit design verification method and device, verification equipment and storage medium

Abstract

The invention provides a circuit design verification method and device, verification equipment and a storage medium. The circuit design verification method comprises the steps of obtaining a target function module in response to completion of design of the target function module in a plurality of function modules to be included in a physical module; based on the target function module, the initial layout of the physical module and a physical module netlist, module physical constraint information of the target function module is determined, the target function module is different from existing function modules in the initial layout in circuit logic, and the physical module netlist comprises communication relations among the function modules in the physical module; and performing time sequence evaluation on the target function module based on the module physical constraint information to verify a circuit design corresponding to the target function module. According to the circuit design verification method, independent time sequence evaluation of any functional module in the physical modules is realized, and the circuit design verification process is accelerated.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a circuit design verification method and apparatus, a verification device, and a storage medium. Background Art

[0002] In the design of integrated circuits, due to the large number of circuit modules and the complex interrelationships between the circuit modules, a long iteration cycle (several days to several weeks) is often required for the design verification of the integrated circuit. In addition, due to the high performance requirements of the integrated circuit, multiple rounds of iterative optimization are often required for verification, which further lengthens the iteration cycle and seriously affects the iteration efficiency and delivery of the entire product. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a circuit design verification method, which includes: in response to the completion of the design of a target functional module among multiple functional modules to be included in a physical module, obtaining the target functional module; determining module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and the physical module netlist, wherein the target functional module is different from the functional modules already in the initial layout in terms of circuit logic, and the physical module netlist includes the communication relationship between the functional modules in the physical module; and performing timing evaluation on the target functional module based on the module physical constraint information to verify the circuit design corresponding to the target functional module.

[0004] At least one embodiment of the present disclosure further provides a circuit design verification device, comprising: an acquisition unit, a determination unit, and a verification unit. The acquisition unit is configured to acquire a target functional module in response to the completion of the design of a target functional module among multiple functional modules to be included in the physical module; the determination unit is configured to determine the module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and the physical module netlist, wherein the target functional module is different from the functional modules already in the initial layout in terms of circuit logic, and the physical module netlist includes the communication relationship between the functional modules in the physical module; and the verification unit is configured to perform a timing evaluation on the target functional module based on the module physical constraint information to verify the circuit design corresponding to the target functional module.

[0005] At least some embodiments of the present disclosure also provide a verification device, comprising: at least one memory and at least one processor, wherein the at least one memory is configured to store computer-executable instructions; and at least one processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the at least one processor, implement the circuit design verification method provided by any embodiment of the present disclosure.

[0006] At least some embodiments of the present disclosure further provide a non-transitory storage medium that non-transitory stores computer-executable instructions. When the computer-executable instructions are executed by at least one processor, the circuit design verification method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0008] Figure 1 A schematic flow chart of a verification method is shown;

[0009] Figure 2 A schematic diagram of a circuit design verification process provided by at least one embodiment of the present disclosure is shown;

[0010] Figure 3 A schematic diagram illustrating an exemplary flow chart of circuit design verification provided by at least one embodiment of the present disclosure is shown;

[0011] Figure 4 (a) shows an exemplary schematic diagram of an initial physical boundary range provided by at least one embodiment of the present disclosure;

[0012] Figure 4 (b) shows an exemplary schematic diagram of an occupied first pane provided by at least one embodiment of the present disclosure;

[0013] Figure 4 (c) shows an exemplary schematic diagram of a target physical boundary range provided by at least one embodiment of the present disclosure;

[0014] Figure 5 An exemplary schematic diagram of a pane provided by at least one embodiment of the present disclosure is shown;

[0015] Figure 6 An exemplary flow chart of determining a target physical boundary range provided by at least one embodiment of the present disclosure is shown;

[0016] Figure 7 An exemplary schematic diagram of determining pin information provided by at least one embodiment of the present disclosure is shown;

[0017] Figure 8 An exemplary flow chart for determining pin information provided by at least one embodiment of the present disclosure is shown;

[0018] Figure 9 A schematic diagram of a circuit design verification process provided by at least one embodiment of the present disclosure is shown;

[0019] Figure 10 A block diagram of a circuit design verification device provided by at least one embodiment of the present disclosure is shown;

[0020] Figure 11 A block diagram illustrating a verification device provided by at least one embodiment of the present disclosure is shown; and

[0021] Figure 12 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0023] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0024] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components. When any component of an embodiment of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0025] As the scale of integrated circuit design continues to expand, especially for large and complex chips, front-end design engineers need to collaborate with back-end design engineers to complete chip design in order to meet the timing requirements of high-performance designs. Each front-end design engineer typically implements the specific functions of the functional module (module) they are responsible for using a hardware description language (Verilog or HDL) and delivers the functional module design code (referred to as code, such as register transfer level code, RTL); each back-end design engineer is typically responsible for physically integrating and verifying the physical module (tile) they are responsible for in the chip (for example, performing physical logic synthesis on the physical module to conduct timing evaluation of the physical module). Before the official production of large and complex chips, front-end design engineers need to modify and optimize the design based on the timing of the back-end physical implementation to ensure that the chip can meet the expected performance indicators.

[0026] Physical logic synthesis is a step in the design process of large integrated circuits (such as chips). It can combine the logical design of the circuit (placement and routing) and the physical information of the corresponding circuit (chip size, pin location, layout planning information, etc.) to generate a netlist of the corresponding circuit.

[0027] There are two main scenarios for front-end design engineers to verify chip designs:

[0028] (1) If problems are found in the code delivered by the front-end design engineer during the front-end verification process (such as functional logic verification of functional modules), the code needs to be corrected (such as functional logic correction) and the timing evaluation needs to be re-performed.

[0029] (2) The code delivered by the front-end design engineer has passed the front-end verification, but during the back-end physical implementation verification, it was found that the physical module where the functional module is located cannot complete timing convergence. It is necessary to find the corresponding functional module with the problem from the physical module, modify and optimize the code, and re-evaluate the timing.

[0030] Figure 1 A flow chart of a verification method is shown. Figure 1For example, in the traditional verification process, after the front-end engineer completes the design of the functional module he is responsible for (such as Module X), he delivers the code Module Xv (step 101). He then needs to wait until the design of other functional modules in the physical module is completed (for example, after obtaining Another.v in step 102) before performing SOC (chip system) integration together (step 103). After integration, a physical code file Tile Xv corresponding to the physical module is obtained from the integrated code of the entire chip (step 104). Physical logic synthesis is performed on the physical code file Tile Xv together with the physical constraint information corresponding to the physical module (e.g., the physical module design exchange format file Tile X.def obtained in step 105). This generates a netlist Tile X.netlist for the physical module (step 107). Physical design (Tile X PD) of the physical module is then performed (step 108). A timing evaluation is performed on the physical module (e.g., static timing analysis (Tile X STA) in step 109). This results in a timing evaluation (Module X STA) for the functional module corresponding to Module X in the physical module (step 110).

[0031] Due to differences in design scale and structure, a physical module often contains multiple functional modules, and the spatial layout relationships are relatively complex. Therefore, after completing the design of a functional module, the front-end design engineer needs to wait for the code design of other functional modules in the physical module to be completed before integrating the physical module into the chip system (SOC) as a whole. After receiving the code for the entire chip after SOC integration, the back-end design engineer needs to first flatten the entire chip structure through top-level design and perform global optimization. This is then divided into different physical code files (such as Tile Xv) according to different physical modules. Further physical implementation of the corresponding physical modules is then carried out (such as physical logic synthesis, physical design PD, and static timing analysis Tile X STA, etc.).

[0032] Therefore, during the chip design verification process, front-end design engineers, who are responsible for designing functional modules, need a long time (several days to weeks) to determine the timing of their functional modules in physical implementation (e.g., whether they can meet timing requirements). In the design of high-performance, large, and complex chips, the chip design iteration cycle is further extended due to the need for more rounds of front-end and back-end iterative optimization. This seriously affects the efficiency of chip design iterations and chip production, resulting in excessively long chip delivery cycles.

[0033] The inventors of this disclosure noticed that during the chip design verification process, front-end design engineers hope to quickly know the timing of the functional modules they designed during physical implementation (on the chip) after submitting the code, so as to discover the timing problems of the functional modules as soon as possible. Figure 1 The verification method shown in the figure is difficult for front-end designers to obtain the timing evaluation results of the physical modules in the (chip) physical implementation in a timely manner due to the time and information gap between the front-end and back-end of the chip design, as well as the complexity caused by the mutual logical dependencies of the various functional modules in the chip. This affects the efficiency of the design optimization of the functional modules they are responsible for.

[0034] The inventors of the present disclosure have noticed that a circuit design verification method is needed to solve the problems existing in the above-mentioned verification methods, so that front-end design engineers can obtain the timing status of the functional modules they are responsible for during physical implementation after the design of the corresponding functional modules is completed, without having to wait for the design of other functional modules in the same physical module to be completed, thereby shortening the circuit design verification cycle.

[0035] At least one embodiment of the present disclosure provides a circuit design verification method, which comprises: obtaining the target functional module in response to completion of the design of a target functional module among multiple functional modules to be included in a physical module; determining module physical constraint information of the target functional module based on the target functional module, an initial layout of the physical module, and a physical module netlist, wherein the target functional module is different from various functional modules already in the initial layout in terms of circuit logic, and the physical module netlist includes communication relationships between various functional modules in the physical module; and performing a timing evaluation on the target functional module based on the module physical constraint information to verify the circuit design corresponding to the target functional module.

[0036] In the circuit design verification method of the above-mentioned embodiment of the present disclosure, since the corresponding module physical constraint information can be directly obtained for a determined target functional module, timing evaluation can be independently performed on the target functional module even when there are logical dependencies with other functional modules in the physical module, thus achieving a separate timing evaluation for any functional module in the physical module. This eliminates the need to perform an overall timing evaluation of the physical module each time, and module physical constraint information can be obtained at the functional module level, accelerating the circuit design verification process, improving circuit design quality, and shortening the circuit R&D cycle.

[0037] Furthermore, when the above scenario (1) occurs, the front-end design engineer can also take into account the timing of the physical implementation when considering modifying the functional logic of the functional module, so as to make functional logic modifications with the least impact on the timing, thereby improving the efficiency of the design optimization of the functional module. Furthermore, since after the functional module design is completed, the front-end design engineer can verify it by himself to ensure that the delivered functional module passes the timing evaluation, then when the back-end design engineer obtains each functional module for physical implementation, integration and verification, there is no need to rework it to the front-end, further improving efficiency.

[0038] The various embodiments of the present disclosure will be described below with reference to specific examples.

[0039] like Figure 2 As shown, in some embodiments of the present disclosure, the circuit design verification method includes steps S20-S22.

[0040] Step S20: in response to the completion of the design of a target functional module among the multiple functional modules to be included in the physical module, the target functional module is acquired.

[0041] Step S21: Determine module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and the physical module netlist.

[0042] The target functional module is different from the functional modules already in the initial layout in terms of circuit logic, and the physical module netlist includes the communication relationship between the functional modules in the physical module.

[0043] Step S22: performing a timing evaluation on the target functional module based on the module physical constraint information to verify the circuit design corresponding to the target functional module.

[0044] The target functional module is any functional module among the multiple functional modules to be included in the physical module. The target functional module can be a functional module to be included in the physical module but not yet included in the initial layout, or a functional module included in the initial layout but with circuit logic modifications.

[0045] For example, the target functional module can be implemented using functional module design code. The functional module design code (hereinafter referred to as code) can be code that implements the specific functions of the functional module (Module) in a hardware description language (Verilog or HDL). For example, the functional module design code can be RTL (Register Transfer Level) code. It should be noted that the above implementation of the target functional module is only an example, and the specific implementation of the target functional module is not limited in this disclosure.

[0046] The target functional module design completion may be the completion of the functional design of the target functional module (e.g., code writing completion) or the completion of the modification of the target functional module (e.g., code modification completion). For example, the code modification may be updating the functional logic or modifying the timing of the target functional module.

[0047] The initial layout is the layout of the physical module that corresponds to the target functional module before the design is completed. Since the iteration of each functional module of the chip is gradual during the development of an integrated circuit (such as a chip), adjustments and optimizations can be made based on the design layout of the initial layout, thereby gradually achieving timing convergence (meeting timing requirements) of the chip. For example, since there is a certain degree of continuity in the physical constraints between the previous and next versions of the chip design (such as the initial layout and the layout after the initial layout), when optimizing the target functional module, the module physical constraint information of the target functional module can be determined based on the physical implementation of the physical module in the previous version (such as the initial layout), thereby performing a timing evaluation on the target functional module.

[0048] Since the physical module includes multiple functional modules and there may be logical dependencies between the functional modules, for example, there may be situations where several functional modules in the physical module need to communicate with each other to jointly implement the same complete function, therefore, when determining the module physical constraint information of the target functional module, the communication relationship between other functional modules and the target functional module can be determined through the physical module netlist (Tile netlist) that records the communication relationship between the functional modules in the physical module.

[0049] In some embodiments of the present disclosure, the module physical constraint information includes the target physical boundary range of the target functional module and the pin information of the target functional module; in this case, the above-mentioned circuit design verification method includes: determining the target physical boundary range based on the target functional module and the initial layout; determining the pin information based on the target physical boundary range and the physical module netlist.

[0050] For example, after the target functional module is loaded into the initial layout, the module physical constraint information of the target functional module can be reversely obtained by deducting other modules outside the target functional module in the initial layout. For example, after the target functional module is loaded into the initial layout, the boundary range that does not belong to the target functional module in the initial layout can be deducted to determine the target physical boundary range. For example, after the target functional module is loaded into the initial layout, the timing path information unrelated to the target functional module can be deducted based on the physical module netlist to determine the pin information based on the target physical boundary range.

[0051] For example, circuit design verification can be performed on a target functional module that is of interest to a project (with iteration and modification requirements). Figure 3An exemplary flow chart of a circuit design verification provided by at least one embodiment of the present disclosure is shown below. Figure 3 The above situation is described in detail.

[0052] The physical design information of the physical module can be obtained based on the initial layout (step 301), wherein the physical design information includes the size of the initial layout of the physical module, the placement of each standard unit in the initial layout, the timing path information (Route) between each functional module in the initial layout, and the pin information of each functional module in the initial layout.

[0053] For example, the target functional modules to be acquired (e.g., the target functional modules with iteration / modification requirements for the project in step 302) can be selected based on the module list in the physical module. For example, the target functional modules can be determined based on their identifiers. The module list records which functional modules are included in the initial layout of the physical module, including, for example, the identifiers (names) of the functional modules.

[0054] Based on the acquired target functional module, a target physical boundary range of the target functional module on the initial layout can be determined (step 303). Subsequently, based on the target physical boundary range and the physical module netlist, the pin information of the target functional module can be determined (step 304), thereby determining the module physical constraint information of the target functional module. For example, the target physical boundary range can be the physical boundary range corresponding to the target functional module determined in the initial layout based on the functional module design code that implements the target functional module using a layout tool. The layout tool can be, for example, an electronic design automation (EDA) tool, or other tool capable of performing integrated circuit layout processing. The present disclosure does not limit the specific layout tool.

[0055] For example, a corresponding file including module physical constraint information may be output (step 305 ), for example, a module design exchange format file (eg, Module A.def) of the target functional module may be output.

[0056] In some cases, since the position distribution of the standard cells of the target functional module is often irregular, the target physical boundary range obtained directly based on the target functional module is often irregular. This will cause very complex polygonal areas to be captured when using layout tools (such as EDA) to capture the target functional module, thereby affecting the processing of the layout tool.

[0057] In some embodiments of the present disclosure, the circuit design verification method includes: determining an initial physical boundary range of the target functional module in an initial layout using a layout tool according to the target functional module; optimizing the initial physical boundary range to determine a target physical boundary range.

[0058] In order to avoid the difficulty of layout tool processing due to the complex boundaries of the target functional module, the boundary range obtained by directly loading the target functional module into the initial layout after the design is completed can be used as the initial physical boundary range. By optimizing the initial boundary range, the target physical boundary range with a relatively regular boundary range can be determined, making it faster and more accurate to use the layout tool to process the target functional module.

[0059] In some embodiments of the present disclosure, an initial layout including an initial physical boundary range is divided into multiple panes, and a first pane is a pane among the multiple panes that overlaps with the initial physical boundary range. In this case, the circuit design verification method includes:

[0060] The corresponding occupation status of each first pane is determined according to the size of the overlapped portion between each first pane and the initial physical boundary range, where the occupation status includes occupied and unoccupied.

[0061] The correction quantity and correction direction of the second pane are determined according to the occupied first pane and the initial physical boundary range, wherein the second pane is a pane among the multiple panes used to correct the boundary range formed by the occupied first pane.

[0062] A target physical boundary range is determined based on the second pane and the occupied first pane.

[0063] The shape of the pane may be, for example, a square, a rectangle, etc., which is not limited in the present disclosure.

[0064] Take the target functional module as Module A as an example, Figure 4 (a) shows an exemplary schematic diagram of an initial physical boundary range provided by at least one embodiment of the present disclosure; Figure 4 (b) shows an exemplary schematic diagram of an occupied first pane provided by at least one embodiment of the present disclosure.

[0065] like Figure 4 As shown in (a) of FIG, the initial layout of the physical module Tile Axx includes the irregular initial physical boundary range O-Module A (shaded area) of the target functional module Module A. For example, the initial layout including the initial physical boundary range O-Module A can be divided into multiple panes of the same size. After the panes are divided, as shown in FIG. Figure 4The initial physical boundary range O-Module A shown in (a) overlaps with some of the multiple panes, and these panes including the initial physical boundary range O-Module A are the first panes.

[0066] For example, the occupancy status of each first pane can be determined based on the size of the initial physical boundary range included in each first pane (i.e., the size of the overlapped portion with the initial physical boundary range). For example, the occupancy status can be determined by judging whether the size of the overlapped portion reaches a certain preset occupancy ratio. For example, the first pane corresponding to the overlapped portion that reaches the preset occupancy ratio can be marked as occupied, and the first pane corresponding to the overlapped portion that does not reach the preset occupancy ratio can be marked as unoccupied. Figure 4 As shown in (b), after the occupation status is marked, the occupied first pane F-Module A is determined.

[0067] For example, the correction quantity and correction direction of the second pane can be determined according to the occupied first pane and the initial physical boundary range. The second pane is a pane among multiple panes used to correct the boundary range formed by the occupied first pane.

[0068] The correction number includes the number of second panes to be corrected for the bounding range formed by the occupied first pane and the corresponding correction operation (increase or decrease). For example, the correction number can be an integer, such as a positive integer indicating the number of second panes to be added to the occupied first pane and a negative integer indicating the number of second panes to be subtracted from the occupied first pane. For example, a correction number of -1 can indicate that one second pane is subtracted from the occupied first pane, while a correction number of +1 can indicate that one second pane is added to the occupied first pane.

[0069] The correction direction indicates where the second pane corresponding to the correction amount is to be corrected within the boundary range formed by the occupied first pane.

[0070] In some embodiments of the present disclosure, the circuit design verification method includes:

[0071] In response to the correction quantity indication, the corresponding number of second panes is reduced on the basis of the occupied first pane, and the occupancy status of the second pane is marked as unoccupied; or, in response to the correction quantity indication, the corresponding number of second panes is added on the basis of the occupied first pane, and the occupancy status of the second pane is marked as occupied; the panes corresponding to the target functional module with the occupancy status of unoccupied are shielded to determine the target physical boundary range.

[0072] exist Figure 4(c) shows an exemplary schematic diagram of a target physical boundary range provided by at least one embodiment of the present disclosure.

[0073] For example, the correction quantity of the second pane is 0, and the target physical boundary range of the target functional module Module A is the same as that of the occupied first pane F-Module A, such as Figure 4 As shown in (c) in the figure, the target physical boundary range of the target functional module Module A can be separated in the initial layout. For example, the occupancy status of the panes in the separated layout corresponding to the target functional module can be masked, and the occupancy status of the panes can be marked as unoccupied panes (i.e., the occupancy status of the panes corresponding to the target functional module can be masked). For example, the unoccupied panes can be masked with a masking mark (such as the grid portion shown in the figure, which can also be masked with red blockage, etc.). After masking, the remaining unmasked panes are the target physical boundary range of Module A. For example, after masking, a module design exchange format file (e.g., Module A.def) including the target physical boundary range of the target functional module can be output.

[0074] Figure 5 An exemplary schematic diagram of a pane provided by at least one embodiment of the present disclosure is shown.

[0075] For example Figure 5 The pane shown is the first pane. The pane height (hereinafter also referred to as the pane length) of the first pane is Y, the pane width of the first pane is X, and the boxes in the first pane are locations that can accommodate standard cells. For example, the total area of ​​standard cells that can be accommodated in the first pane can be recorded as S win (For example Figure 5 The sum of the areas of all white boxes and dark boxes in the first pane can be recorded as S std (For example Figure 5 The area of ​​all dark boxes in the figure is denoted as Q. The circuit design verification method includes:

[0076] In response to S std / S win ≥Q, mark the occupancy state of the first pane as occupied; or, in response to S std / S win <Q, marks the occupation state of the first pane as unoccupied.

[0077] The preset standard cell occupancy rate Q can be preset, and the specific setting value and setting method are not limited in this disclosure. Since the size of each pane in the multiple panes is the same, the area of ​​the other panes in the multiple panes is equal to the standard cell area that can be accommodated in the first pane, which is S. win .

[0078] For example, the actual occupancy in the first pane can be recorded as P, P = S std / S win The occupancy status of the corresponding first pane is determined by comparing the actual occupancy rate P in each first pane with the preset standard unit occupancy rate Q. The occupancy status indicates whether the corresponding first pane is occupied by the target functional module.

[0079] For example, if the overlapped portion in one of the first panes includes N standard cells (Std Cell), where N is a positive integer, the total area of ​​the standard cells corresponding to the overlapped portion of the initial physical boundary range is S std = S std 1 +S std 2 + ... + S std N.

[0080] For example, the occupancy state can be marked by an occupancy value, for example, by an occupancy value F, where occupancy value F=1 indicates that the device is occupied and occupancy value F=0 indicates that the device is not occupied. win , the standard cell area S corresponding to the size of the overlapped portion of the first window pane and the initial physical boundary range std and occupancy value F, determine the residual area S of each of the n first panes fix_n , where n is a positive integer.

[0081] For example, the preset standard unit occupancy rate Q is set to 0.5. If the actual occupancy rate P of a first pane is ≥ 0.5, the occupancy value of the first pane is recorded as F = 1, indicating that the first pane has been occupied by the target functional module; if the actual occupancy rate P of a first pane is < 0.5, the occupancy value of the first pane is recorded as F = 0, indicating that the first pane is not occupied by the target functional module.

[0082] Record the residual area S of each first window fix_n , where n is the number of first panes and n is a positive integer. For example, the residual area S of the first pane is fix_n = S std - ( S win * F ).

[0083] For example, according to the above formula, when the first window pane is occupied, the residual area S of the first window pane isfix_n is a negative number, and the value of the residual area represents the sum of the areas of the standard cells that do not belong to the target functional module in the first pane; when the first pane is occupied, the residual area S of the first pane is fix_n is a positive number, and the value of the residual area represents the sum of the areas of the standard cells belonging to the target functional module in the first window pane.

[0084] According to the residual area of ​​each first window, determine the total residual area S fix_sum , where the residual area sum S fix_sum = S fix_1 + S fix_2 + ... + S fix_n .

[0085] According to the residual area sum S fix_sum , determines the amount of correction for the second pane.

[0086] The sum of residual areas S fix_sum It can represent the difference between the boundary range formed by the occupied first pane and the real physical boundary range (initial physical boundary range) of the target functional module, so that when the difference range is large, the boundary range formed by the occupied first pane is corrected by using the corresponding correction amount of the second pane.

[0087] In some embodiments of the present disclosure, the circuit design verification method further includes: determining the average area S of the standard cells of each pane in the physical module. avg ; According to the sum of residual areas S fix_sum The average area of ​​the standard unit S avg The modulo calculation result of determines the correction amount of the second window pane.

[0088] Average area of ​​standard unit S avg The average utilization rate U of the standard cells in the physical module can be std_avg The area of ​​the first pane is determined by multiplying the area of ​​the first pane by the area of ​​the first pane, which is equal to the pane height of the first pane being Y multiplied by the pane width of the first pane being X. The average area of ​​the standard unit is S avg = U std_avg * X * Y.

[0089] For example, the average area S of the standard cells of each pane in the physical module can be avg and the sum of the residual areas S fix_sum The remainder after the modulo operation is rounded to an integer to determine the corrected number of the second window pane. For example, the corrected number of the second window pane is recorded as C fix , then the correction quantity C fix = Round (S fix_sum % S avg), “%” is the modulo symbol.

[0090] For example, the circuit design verification method further includes: according to the arrangement of the occupied first panes in the first direction and the second direction, determining the direction with the fewer occupied first panes in the first direction and the second direction as the correction direction of the second pane.

[0091] The first and second directions are different directions in which the panes are arranged in the initial layout. For example, the first direction can be horizontal and the second direction can be vertical; or the first direction can be vertical and the second direction can be horizontal. The specific directions referred to by the first and second directions are related to the arrangement direction of the multiple panes divided in the initial layout, and this disclosure does not limit them.

[0092] The following uses the horizontal and vertical directions as examples to illustrate the determination of the second pane correction direction. For example, within the boundary range formed by the occupied first pane, the maximum number of windows of the horizontally arranged first pane is C H The maximum number of windows in the first pane arranged vertically is C V .

[0093] For example, C H >C V , it can be determined that the second panes corresponding to the corrected number are added to the longitudinal edge of the occupied first pane, and the maximum number of windows of the corrected longitudinally arranged first panes is updated to C V_fix = C V + C fix .

[0094] For example, C V >C F , it can be determined that the second panes corresponding to the corrected number are added to the horizontal edge of the occupied first pane, and the maximum number of windows of the corrected horizontally arranged first panes is updated to C H_fix = C H + C fix .

[0095] By determining the number of corrections for the second window pane based on the sum of the residual areas, the area difference between the determined target physical boundary range and the initial physical boundary range can be made very small (the error is approximately within one window pane), and the irregularity of the initial physical boundary range is optimized, so that the discrete arrangement in the irregular initial physical boundary range becomes regular, reducing the difficulty of the layout tool in processing the target functional model, thereby avoiding the layout tool's erroneous processing and ensuring the consistency of the obtained module physical constraint information with the actual physical constraint information during the actual design of the target functional module.

[0096] For example, the sizes of the multiple panes are determined according to the number of panes divided in the initial layout and the area ratio of the target functional module in the physical module.

[0097] For example, when determining the target physical boundary range of a target functional module, a layout tool (e.g., an EDA tool) may determine the target physical boundary range within a certain number of panes to achieve the desired processing effect. For example, the number of panes may be determined to be within a range of 40 to 80 to achieve the desired processing effect. For example, if the number of panes in the multiple panes is labeled j, the number of panes in the multiple panes may be set to 60.

[0098] For example, the ideal number of standard cells in a physical module is about 3 million. The proportion of the functional module to be verified (such as the target functional module) in the entire physical module is recorded as k. For example, the proportion of the target functional module in the entire physical module is k=0.2.

[0099] For example, the height-to-width ratio of a standard cell can be determined based on empirical data on different standard cell sizes. For example, the width of a standard cell can be determined to be approximately 4 times its height. For example, the window pane size and standard cell size can be set such that the window pane height Y is equal to x times the standard cell height. Based on the equation x*(x / 4)*j / k = 3,000,000 (3 million), we can solve for x = 200, meaning the window pane height is equal to 200 times the standard cell height, and the window pane width is equal to 200 times the standard cell width.

[0100] Through the pane size determination method of the above embodiment, the pane size can be adaptively adjusted according to the sizes of different standard cells, so that the pane size division can better meet the boundary optimization requirements of the target functional module.

[0101] Figure 6 An exemplary flow chart of determining a target physical boundary range provided by at least one embodiment of the present disclosure is shown below. Figure 6 The flowchart shown is used as an example to illustrate the overall process of determining the target physical boundary range.

[0102] First, divide the physical module into multiple panes with length and width of X and Y respectively, and determine the area of ​​any pane as S win (Step 601 ), for example, determining a first pane among multiple panes according to an initial physical boundary range of a target functional module Module A.

[0103] Traverse all standard cells in the first pane and calculate the sum of the areas S of all standard cells of the functional module in the first pane. std = S std 1 + Sstd 2 +… S std N (step 602).

[0104] For example, the preset standard cell occupancy rate Q is set to 0.5, and the S is determined for each first window pane. std / S win (P)≥0.5 (Q) (step 603).

[0105] The occupancy status of the first pane is marked by the occupancy value according to the judgment result. If not, the occupancy value of the corresponding first pane is set to 0 (not occupied) in step 604; if so, the occupancy value F of the corresponding first pane is set to 1 (occupied) in step 605.

[0106] After the occupancy status of all first panes is marked, the residual area of ​​each first pane is determined: S fix_n = S std – (S win * F) (step 606).

[0107] After that, determine the difference between the boundary range formed by the occupied first pane and the actual physical boundary range of the target functional module (initial physical boundary range), that is, the sum of the residual areas: S fix_sum = S fix_1 + S fix_2 + ... +S fix_n . Determine the corrected amount for the second pane: C fix =S fix_sum % S avg , filling in the positions in the horizontal and vertical directions where the number of second panes corresponding to the corrected number is smaller than that of the first panes (step 607 ).

[0108] For example, if the number in the horizontal direction of the occupied first pane is greater than the number in the vertical direction, it can be determined that the second pane with the corresponding corrected number will be added to the vertical edge of the occupied first pane. For example, if the number in the vertical direction of the occupied first pane is greater than the number in the horizontal direction, it can be determined that the second pane with the corresponding corrected number will be added to the horizontal edge of the occupied first pane.

[0109] Afterwards, in response to the correction quantity indication, the number of second panes is reduced based on the occupied first panes by a corresponding number, and the occupation state of the second pane is marked as unoccupied.

[0110] Alternatively, in response to the correction quantity indication, a corresponding number of second panes is added based on the occupied first panes, and the occupation status of the second panes is marked as occupied.

[0111] At this time, the target physical boundary range can be determined based on the second pane and the occupied first pane. Since the panes in the target physical boundary range corresponding to the target functional module have all been marked as occupied after the above steps, the part including the occupied panes corresponding to the target functional module can be separated in the initial layout, and the corresponding unoccupied panes in the separated part can be marked with a blockage mark, thereby determining the target physical boundary range of the target functional module (step 608).

[0112] For example, a module design exchange format file Module A.def of the target functional module may be output, wherein the file includes the target physical boundary range of the target functional module.

[0113] In some embodiments of the present disclosure, the above-mentioned circuit design verification method also includes: determining the timing path information between the target functional module and other functional modules in the physical module based on the physical module netlist, wherein the timing path information includes the timing path from the input to the register and / or the timing path from the register to the output; and determining the pin information of the target functional module based on the target physical boundary range and the timing path information.

[0114] Since the physical module netlist records the communication relationship between the target functional module and other functional modules, the timing path information between the target functional module and other functional modules can be determined.

[0115] For example, the input-to-register timing path and / or register-to-output timing path between the target functional module and other functional modules can be obtained to determine where each timing path overlaps within the target physical boundary range, thereby planning the pin position of the target functional module and determining the pin information of the target functional module based on the pin position.

[0116] In some embodiments of the present disclosure, the above-mentioned circuit design verification method also includes: obtaining a target physical edge of a target physical boundary range; determining the pin information of the target functional module based on the intersection of the timing path from the input to the register and / or the timing path from the register to the output and the target physical edge.

[0117] Pin information is used to determine the interfaces that other modules must pass through when communicating with the target functional module. Once this information is determined, timing evaluation of the target functional module will yield more accurate and realistic results. This avoids ignoring the locations of the target functional module's actual communication pins during timing evaluation, which can lead to overly optimistic and meaningless timing evaluation results. For example, ignoring the necessary interfaces shortens the timing path for communication between other modules and the target functional module's internal registers (for example, bypassing the necessary interfaces through a straight line), resulting in an inaccurate and overly optimistic timing evaluation that lacks practical reference value.

[0118] Figure 7 An exemplary schematic diagram of determining pin information provided by at least one embodiment of the present disclosure is shown; Figure 8 An exemplary flow chart of determining pin information provided by at least one embodiment of the present disclosure is shown below. Figure 7 and Figure 8 Provide detailed explanation.

[0119] like Figure 7 As shown, the target physical boundary range of a target functional module (such as Module A) is as follows ( Figure 7 Taking the shaded area shown in the figure as an example, the target physical edge of the target physical boundary range is recorded as Boundary, and the endpoints of the target physical edge include endpoint a (x1, y1), endpoint b (x2, y2), endpoint c (x3, y3) and endpoint d (x4, y4). For example, Figure 7 The target physical edge in can be recorded as Boundary (x1,y1)-(x2,y2)-(x3,y3)-(x4,y4), that is, the edge formed by the lines connecting endpoints a(x1,y1), endpoint b(x2,y2), endpoint c(x3,y3) and endpoint d(x4,y4).

[0120] There are two timing paths from the target functional module Module A to other modules, namely the timing path from register to output reginA-pinA-regoutA and the timing path from input to register reginB-pinB-regoutB.

[0121] For example, one can Figure 8 After obtaining the target physical boundary range of the target functional module, all timing path information from the target functional module to other functional modules can be obtained (step 801). For example, the above-mentioned Figure 7 Two timing paths are shown.

[0122] Then, the position of the starting register of each timing path can be obtained (step 802), for example, the position of the starting and ending registers of these paths on the initial layout can be obtained, for example, the coordinates reginA(x 1A ,y 1A ),regoutA(x 2A ,y 2A ) and reginB(x 1B ,y 1B ), regoutB(x 2B ,y 2B ).

[0123] Then, the edge of the target physical boundary range can be determined as the target physical edge of the target functional module. For example, the target physical edge can be determined by connecting the coordinates of the endpoints of the target physical boundary range. Figure 7 The target physical edge in Boundary (x1,y1)-(x2,y2)-(x3,y3)-(x4,y4).

[0124] Determine the intersection of the boundary and the timing path corresponding to the start register, and use the intersection as the pin coordinate of the target functional module, for example, the pin coordinate pinA(x 3A ,y 3A ) and pin coordinates pinB(x 3B ,y 3B ), and determine the pin coordinates as the pin information of the target functional module (step 803).

[0125] For example, all pin information corresponding to the target functional module may be used to generate a pin design exchange format file Pin A.def of the target functional module, and the file may be output (step 804 ).

[0126] By using the timing path connection corresponding to the revelation register and the target physical edge to perform cross-point operations, the pin information of the target physical module is constructed efficiently and quickly.

[0127] For example, the above-mentioned circuit design verification method also includes: performing physical logic synthesis based on the module physical constraint information to generate a target functional module netlist; performing timing evaluation based on the target functional module netlist and the module physical constraint information to obtain a timing evaluation result; wherein the timing evaluation result is used to verify whether the circuit design corresponding to the target functional module meets expectations.

[0128] For example, the expectation may be whether the circuit design can achieve timing convergence, whether the circuit design meets the delay requirements, etc. The specific expectation for the circuit design can be set differently according to different circuit conditions, and the present disclosure does not limit this.

[0129] For example, in the physical logic synthesis phase, a target functional module netlist corresponding to the target functional module is generated based on the logic design corresponding to the target functional module and the module physical constraint information of the target functional module.

[0130] For example, if the circuit corresponding to the target functional module does not meet expectations, it means that the target functional module needs to be adjusted, for example, the functional module design code that implements the target functional module can be modified. The modified target functional module can also continue to be verified using the circuit design verification method of any of the above embodiments of the present disclosure until it meets expectations.

[0131] Figure 9 A schematic diagram of a circuit design verification process provided by at least one embodiment of the present disclosure is shown.

[0132] like Figure 9 As shown, after the design of the target functional module Module A is completed, physical logic synthesis is performed together (step 903) based on the obtained functional module design code Module Av of Module A (step 901), the module design exchange format file ModuleA.def including the target physical boundary range, and the pin design exchange format file Pin A.def including the pin information of the target functional module (step 902).

[0133] After physical logic synthesis, the target functional module netlist Module A netlist is generated (step 904), after which the physical design (PD, Physical Design) of the target functional module Module A can be performed (step 905) and the timing evaluation of the target functional module Module A can be performed (for example, STA, Static Timing Analysis, static timing analysis in step 906). This eliminates the need for the traditional verification process to wait for other functional modules when verifying a target functional module in the physical module, and also eliminates the steps of physical logic synthesis, physical design, and timing evaluation at the physical module level in the traditional verification process. This allows for direct acquisition of accurate timing evaluation of the target functional module to verify whether the circuit design corresponding to the target functional module meets expectations. In this way, the verification efficiency and iteration speed at the functional module level are greatly improved.

[0134] At least one embodiment of the present disclosure further provides a circuit design verification device, Figure 10 A schematic block diagram of a circuit design verification device provided by at least one embodiment of the present disclosure is shown below. Figure 10 Provide detailed explanation.

[0135] The circuit design verification apparatus 1000 includes an acquisition unit 1010 , a determination unit 1020 , and a verification unit 1030 .

[0136] The acquiring unit 1010 is configured to acquire a target functional module in response to completion of design of a target functional module among a plurality of functional modules to be included in the physical module.

[0137] The determination unit 1020 is configured to determine the module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module and the physical module netlist, wherein the target functional module is different from the functional modules already in the initial layout in terms of circuit logic, and the physical module netlist includes the communication relationship between the functional modules in the physical module.

[0138] The verification unit 1030 is configured to perform a timing evaluation on the target functional module based on the module physical constraint information to verify the circuit design corresponding to the target functional module.

[0139] For example, the module physical constraint information includes the target physical boundary range of the target functional module and the pin information of the target functional module; the determination unit 1020 is also configured to determine the target physical boundary range based on the target functional module and the initial layout; and determine the pin information based on the target physical boundary range and the physical module netlist.

[0140] For example, the determining unit 1020 is further configured to determine an initial physical boundary range of the target functional module in the initial layout using a layout tool according to the target functional module; optimize the initial physical boundary range, and determine the target physical boundary range.

[0141] For example, an initial layout including an initial physical boundary range is divided into multiple panes, and the first pane is a pane among the multiple panes that overlaps with the initial physical boundary range; the determination unit 1020 is also configured to determine the corresponding occupancy status of each first pane according to the size of the overlapping portion between each first pane and the initial physical boundary range, wherein the occupancy status includes occupied and unoccupied; determine the correction quantity and correction direction of the second pane according to the first pane with an occupied occupancy status and the initial physical boundary range, wherein the second pane is a pane among the multiple panes used to correct the boundary range formed by the occupied first pane; determine the target physical boundary range according to the second pane and the occupied first pane.

[0142] For example, the total area of ​​standard cells that can be accommodated in the first pane is S win The sum of the standard cell areas corresponding to the size of the overlapped portion of the first window pane and the initial physical boundary range is S std , the preset standard cell occupancy rate Q of the first pane; the determination unit 1020 is further configured to respond to S std / S win ≥Q, mark the occupancy state of the first pane as occupied, or in response to S std / S win <Q, marks the occupation state of the first pane as unoccupied.

[0143] For example, the occupancy state is marked by an occupancy value F, where occupancy value F=1 indicates that the space is occupied, and occupancy value F=0 indicates that the space is not occupied. The determining unit 1020 is further configured to determine the space according to the total area S of the standard cells that can be accommodated in the first pane. win , the sum of the standard cell areas S corresponding to the size of the overlapped portion of the first window pane and the initial physical boundary range std and occupancy value F, determine the residual area S of each of the n first panes fix_n , where n is a positive integer; according to the residual area of ​​each first window pane, determine the total residual area S fix_sum , where the residual area sum S fix_sum = S fix_1 + S fix_2 + ... + S fix_n ; According to the sum of residual areas S fix_sum , determines the amount of correction for the second pane.

[0144] For example, the determining unit 1020 is further configured to determine the standard unit average area S of each pane in the physical module. avg ; According to the sum of residual areas S fix_sum The average area of ​​the standard unit S avg The modulo calculation result of determines the correction amount of the second window pane.

[0145] For example, the determining unit 1020 is further configured to determine the direction with fewer occupied first panes in the first and second directions as the corrected direction of the second pane according to the arrangement of the occupied first panes in the first and second directions.

[0146] For example, the determination unit 1020 is also configured to reduce the corresponding number of second panes based on the occupied first pane in response to the correction quantity indication, and mark the occupancy status of the second pane as unoccupied; or increase the corresponding number of second panes based on the occupied first pane in response to the correction quantity indication, and mark the occupancy status of the second pane as occupied; shield the panes whose occupancy status is unoccupied corresponding to the target functional module to determine the target physical boundary range.

[0147] In some embodiments of the present disclosure, the sizes of the multiple panes are determined according to the number of panes divided in the initial layout and the area ratio of the target functional module in the physical module.

[0148] For example, the determination unit 1020 is also configured to determine the timing path information between the target functional module and other functional modules in the physical module based on the physical module netlist, wherein the timing path information includes the timing path from the input to the register and / or the timing path from the register to the output; and determine the pin information of the target functional module based on the target physical boundary range and the timing path information.

[0149] For example, the determination unit 1020 is further configured to obtain a target physical edge of a target physical boundary range; determine the pin information of the target functional module based on the intersection of the timing path from input to register and / or the timing path from register to output with the target physical edge.

[0150] For example, the verification unit 1030 is also configured to perform physical logic synthesis based on the module physical constraint information to generate a target functional module netlist; perform timing evaluation based on the target functional module netlist and the module physical constraint information to obtain a timing evaluation result; wherein the timing evaluation result is used to verify whether the circuit design corresponding to the target functional module meets expectations.

[0151] The technical effects of the circuit design verification device of the above embodiment of the present disclosure are the same as the technical effects of the above circuit design verification method, and therefore will not be described in detail.

[0152] Figure 11 A block diagram of a verification device provided by at least one embodiment of the present disclosure is shown.

[0153] At least one embodiment of the present disclosure further provides a verification device, such as Figure 11 As shown, the verification device 1100 includes at least one memory 1110 and at least one processor 1120 .

[0154] The memory 1110 is configured to store computer-executable instructions.

[0155] The processor 1120 is configured to execute computer-executable instructions. When the computer-executable instructions are executed by at least one processor, the circuit design verification method provided by any embodiment of the present disclosure is implemented.

[0156] The memory 1110 may include, for example, a semiconductor memory unit, such as a dynamic random access memory (DRAM), a random access memory (RAM), or a static random access memory (SRAM), or any other memory with a storage function.

[0157] The processor 1120 may be, for example, any processing circuit with processing capabilities implemented through hardware or firmware, such as a central processing unit (CPU) or a coprocessor, a microcontroller unit (MCU), or a digital signal processor (DSP). For example, the coprocessor may be an accelerator (e.g., a graphics accelerator or a digital signal processing unit), a graphics processing unit (GPU), a programmable logic array, or any other processor with instruction execution capabilities. The embodiments of the present disclosure do not limit the implementation of the at least one memory 1110 and the at least one processor 1120.

[0158] The technical effects of the verification device of the above embodiment of the present disclosure are the same as the technical effects of the above circuit design verification method, and therefore will not be described in detail.

[0159] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, the circuit design verification method provided by at least one embodiment of the present disclosure is implemented.

[0160] Figure 12 Schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Figure 12 As shown, the non-transitory storage medium 1200 can non-transitory store computer-executable instructions 1210 , which, when executed by a computer, implement the circuit design verification method provided by any embodiment of the present disclosure.

[0161] Regarding this disclosure, the following points need to be explained:

[0162] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0163] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0164] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A circuit design verification method, comprising: In response to the completion of design of a target functional module among the multiple functional modules to be included in the physical module, acquiring the target functional module; Determining module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and a physical module netlist, wherein the target functional module is different from each functional module in the initial layout in terms of circuit logic, and the physical module netlist includes communication relationships between each functional module in the physical module; A timing evaluation is performed on the target functional module based on the module physical constraint information to verify a circuit design corresponding to the target functional module.

2. The circuit design verification method according to claim 1, wherein: The module physical constraint information includes a target physical boundary range of the target functional module and pin information of the target functional module; The determining of the module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and the physical module netlist includes: Determining the target physical boundary range according to the target functional module and the initial layout; The pin information is determined according to the target physical boundary range and the physical module netlist.

3. The circuit design verification method according to claim 2, wherein: The step of determining the target physical boundary range according to the target functional module and the initial layout includes: According to the target functional module, determining an initial physical boundary range of the target functional module in the initial layout using a layout tool; The initial physical boundary range is optimized to determine the target physical boundary range.

4. The circuit design verification method according to claim 3, wherein: The initial layout including the initial physical boundary range is divided into a plurality of panes, and the first pane is a pane that overlaps with the initial physical boundary range among the plurality of panes; The optimizing the initial physical boundary range and determining the target physical boundary range includes: Determining the corresponding occupancy status of each first pane according to the size of the overlapped portion between each first pane and the initial physical boundary range, wherein the occupancy status includes occupied and unoccupied; determining, based on the first pane whose occupancy state is occupied and the initial physical boundary range, a correction quantity and correction direction of a second pane, wherein the second pane is a pane among the plurality of panes used to correct the boundary range formed by the occupied first pane; The target physical boundary range is determined according to the second pane and the occupied first pane.

5. The circuit design verification method according to claim 4, wherein: The total area of ​​standard cells that can be accommodated in the first pane is S win The sum of the standard cell areas corresponding to the size of the overlapped portion of the first window pane and the initial physical boundary range is S std , a preset standard cell occupancy rate Q of the first pane; The determining the target physical boundary range according to the second pane and the occupied first pane includes: In response to S std / S win ≥Q, marking the occupancy state of the first pane as occupied, or In response to S std / S win <Q, marking the occupation state of the first pane as unoccupied.

6. The circuit design verification method according to claim 5, wherein: The occupancy state is marked by an occupancy value F, wherein the occupancy value F=1 indicates that the space is occupied, and the occupancy value F=0 indicates that the space is not occupied; The determining, based on the first window pane having an occupied status and the initial physical boundary range, the correction amount and correction direction of the second window pane includes: According to the total area S of the standard cells that can be accommodated in the first pane win , the sum of the standard cell areas S corresponding to the size of the overlapped portion of the first window pane and the initial physical boundary range std and the occupancy value F, determine the residual area S of each of the n first panes fix_n , where n is a positive integer; According to the residual area of ​​each of the first panes, the residual area sum S is determined. fix_sum , where the residual area sum S fix_sum = S fix_1 + S fix_2 + ... + S fix_n ; According to the residual area sum S fix_sum , determine the revised amount of the second pane.

7. The circuit design verification method according to claim 6, wherein: The residual area sum S fix_sum , determining a revised quantity for the second pane, comprising: Determine the average standard unit area S of each pane in the physical module avg ; According to the residual area sum S fix_sum The average area of ​​the standard unit S avg The modulo calculation result is used to determine the correction quantity of the second window pane.

8. The circuit design verification method according to claim 7, wherein: The determining, based on the first window pane having an occupied status and the initial physical boundary range, the correction amount and correction direction of the second window pane includes: According to the arrangement of the occupied first panes in the first direction and the second direction, a direction in which the number of the occupied first panes arranged is smaller in the first direction and the second direction is determined as a correction direction of the second pane.

9. The circuit design verification method according to claim 4, wherein: The determining the target physical boundary range according to the second pane and the occupied first pane includes: In response to the correction quantity indicating that the second pane is reduced by a corresponding quantity based on the occupied first pane, the occupation state of the second pane is marked as unoccupied; or In response to the correction quantity indication, the second pane is increased by a corresponding number based on the occupied first pane, and the occupation status of the second pane is marked as occupied; The panes corresponding to the target functional module and whose occupation status is unoccupied are shielded to determine the target physical boundary range.

10. The circuit design verification method according to claim 4, wherein: The sizes of the multiple panes are determined according to the number of panes divided in the initial layout and the area ratio of the target functional module in the physical module.

11. The circuit design verification method according to claim 2, wherein: The determining the pin information according to the target physical boundary range and the physical module netlist includes: Determining timing path information between the target functional module and other functional modules in the physical module based on the physical module netlist, wherein the timing path information includes a timing path from input to register and / or a timing path from register to output; The pin information of the target functional module is determined based on the target physical boundary range and the timing path information.

12. The circuit design verification method according to claim 11, wherein: The determining the pin information of the target functional module based on the target physical boundary range and the timing path information includes: Obtaining a target physical edge of the target physical boundary range; The pin information of the target functional module is determined according to an intersection point between the timing path from the input to the register and / or the timing path from the register to the output and the target physical edge.

13. The circuit design verification method according to any one of claims 1 to 12, wherein: Performing a timing evaluation on the target functional module based on the module physical constraint information to verify a circuit design corresponding to the target functional module includes: Perform physical logic synthesis based on the module physical constraint information to generate a target functional module netlist; Performing timing evaluation based on the target functional module netlist and the module physical constraint information to obtain a timing evaluation result; The timing evaluation result is used to verify whether the circuit design corresponding to the target functional module meets expectations.

14. A circuit design verification device comprising: an acquiring unit configured to acquire a target functional module in response to completion of design of a target functional module among a plurality of functional modules to be included in the physical module; a determining unit configured to determine module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and a physical module netlist, wherein the target functional module is different from each functional module in the initial layout in terms of circuit logic, and the physical module netlist includes communication relationships between each functional module in the physical module; The verification unit is configured to perform a timing evaluation on the target functional module based on the module physical constraint information to verify a circuit design corresponding to the target functional module.

15. A verification device comprising: at least one memory configured to store computer-executable instructions; as well as At least one processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the at least one processor, implement the circuit design verification method according to any one of claims 1-13.

16. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein: When the computer-executable instructions are executed by at least one processor, the circuit design verification method according to any one of claims 1 to 13 is implemented.

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