Static time sequence analysis method and device, electronic equipment and storage medium

Abstract

The invention provides a static time sequence analysis method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the voltage drop analysis of at least one logic unit on a target time sequence path, obtaining an original voltage drop file, and carrying out the voltage drop analysis of at least one logic unit from the original voltage drop file according to the reading information indicated by a reading command of a static time sequence analysis tool, acquiring a signal overturning direction of each logic unit and a dynamic voltage drop corresponding to the signal overturning direction, and according to a data form indicated by a write-in command of a static time sequence analysis tool, generating a target voltage drop file from the signal overturning direction and the dynamic voltage drop according to the data form, and performing static time sequence analysis on the target voltage drop file by adopting a static time sequence analysis tool. Required information is read out and written into the generated target voltage drop file in a tool command form, redundant information is abandoned, the information can be directly called in a static time sequence analysis tool, and the execution efficiency and iteration speed of static time sequence analysis are improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a static timing analysis method, device, electronic device, and storage medium. Background Art

[0002] As chip design processes become increasingly advanced, the impact of dynamic voltage drop on high-performance chips is becoming more and more obvious. Therefore, during static timing analysis, it is necessary to consider the impact of dynamic voltage drop on timing after it is added to chip units.

[0003] In related technologies, when analyzing the impact of dynamic voltage drop on static timing analysis, it is necessary to read various types of voltage drop information within a period of time into a static timing analysis tool in text form to obtain analysis results.

[0004] However, using current related technical methods, the file reading time will increase exponentially as the chip design scale increases, resulting in a significant reduction in the execution efficiency of static timing analysis. Summary of the Invention

[0005] In view of this, the embodiments of the present application provide a static timing analysis method, device, electronic device and storage medium to solve the problem that the file reading time increases exponentially with the increase of chip design scale, resulting in a significant reduction in the execution efficiency of static timing analysis.

[0006] In a first aspect, an embodiment of the present application provides a static timing analysis method, comprising:

[0007] Performing voltage drop analysis on at least one logic unit on a target timing path to obtain an original voltage drop file, wherein the original voltage drop file includes: various voltage drop information of each logic unit;

[0008] Obtaining, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool;

[0009] According to the data format indicated by the write command of the static timing analysis tool, the signal flip direction and the dynamic voltage drop are adjusted according to the data format to generate a target voltage drop file;

[0010] The static timing analysis tool is used to perform static timing analysis on the target voltage drop file.

[0011] In an optional embodiment, the original voltage drop file includes: a plurality of voltage drop information of each logic unit in a plurality of respective timing cycles;

[0012] The acquiring, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool, includes:

[0013] Obtaining, from the original voltage drop file, the signal flipping direction and the dynamic voltage drop of each logic unit within the respective plurality of timing cycles according to the read information indicated by the read command;

[0014] The step of generating a target voltage drop file by flipping the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool includes:

[0015] The signal inversion direction, the dynamic voltage drop, and the period identifier of the corresponding timing period are written into the target array indicated by the data format to generate the target voltage drop file.

[0016] In an optional embodiment, writing the signal flip direction, the dynamic voltage drop, and the period identifier of the corresponding timing period into the target array indicated by the data format to generate the target voltage drop file includes:

[0017] Using the unit name of each logical unit as the array element name of the target array;

[0018] Using the signal flip direction, the dynamic voltage drop, and the period identifier of the corresponding timing period as array element values ​​of the target array;

[0019] The target voltage drop file is generated according to the target array.

[0020] In an optional implementation, the using the signal inversion direction, the dynamic voltage drop, and the period identifier of the corresponding timing period as the array element value of the target array includes:

[0021] Using the period identifier of the corresponding timing period and the signal flip direction as keywords of a dictionary, and using the dynamic voltage drop as a value of the keyword;

[0022] Use the dictionary as the array element value of the target array.

[0023] In an optional embodiment, before obtaining the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file according to the reading information indicated by the read command of the static timing analysis tool, the method further includes:

[0024] Filtering out information irrelevant to the logic units in the original voltage drop file, and listing the unit names of the logic units to obtain a unit name list;

[0025] The acquiring, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool, includes:

[0026] According to the read information indicated by the read command, the signal flip direction and the dynamic voltage drop of each logic unit in the unit name list are sequentially read from the filtered original voltage drop file.

[0027] In an optional embodiment, before generating a target voltage drop file by flipping the direction of the signal and generating the dynamic voltage drop file in accordance with the data format indicated by the write command of the static timing analysis tool, the method further includes:

[0028] determining a target logic unit from the at least one logic unit according to the dynamic voltage drop;

[0029] The step of generating a target voltage drop file by flipping the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool includes:

[0030] According to the data format indicated by the write command, the signal direction of the target logic unit and the dynamic voltage drop of the target logic unit are flipped according to the data format to generate the target voltage drop file.

[0031] In an optional embodiment, the dynamic voltage drop includes: a maximum dynamic voltage drop, a minimum dynamic voltage drop, and an average dynamic voltage drop;

[0032] The step of generating a target voltage drop file by flipping the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool includes:

[0033] Matching the average dynamic voltage drop from the dynamic voltage drops;

[0034] According to the data format indicated by the write command, the signal direction is flipped and the average dynamic voltage drop is adjusted according to the data format to generate the target voltage drop file.

[0035] In an optional implementation, the performing static timing analysis on the target voltage drop file using the static timing analysis tool includes:

[0036] Using the static timing analysis tool, according to the target voltage drop file, the signal flip direction and the dynamic voltage drop are obtained;

[0037] According to the dynamic voltage drop, voltage reverse labeling is performed on each logic unit in the signal flipping direction to perform static timing analysis.

[0038] In an optional implementation, the using the static timing analysis tool to obtain the signal flip direction and the dynamic voltage drop according to the target voltage drop file includes:

[0039] The static timing analysis tool is used to read the array element value of the target array from the target voltage drop file, and the signal flip direction and the dynamic voltage drop are obtained according to the array element value of the target array.

[0040] In a second aspect, an embodiment of the present application further provides a static timing analysis device, comprising:

[0041] an analysis module, configured to perform voltage drop analysis on at least one logic unit on a target timing path to obtain an original voltage drop file, wherein the original voltage drop file includes: various voltage drop information of each logic unit;

[0042] an acquisition module, configured to acquire, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool;

[0043] a generating module, configured to generate a target voltage drop file by flipping the direction of the signal and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool;

[0044] The analysis module is further configured to perform static timing analysis on the target voltage drop file using the static timing analysis tool.

[0045] In a third aspect, an embodiment of the present application further provides an electronic device comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory through the bus, and the processor executes the machine-readable instructions to execute any one of the methods described in the first aspect.

[0046] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in any one of the first aspects is executed.

[0047] The present application provides a static timing analysis method, apparatus, electronic device, and storage medium. The method includes: performing voltage drop analysis on at least one logic unit on a target timing path to obtain an original voltage drop file; obtaining the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file according to the read information indicated by the read command of the static timing analysis tool; generating a target voltage drop file according to the data format indicated by the write command of the static timing analysis tool, converting the signal flip direction and the dynamic voltage drop into data format; and performing static timing analysis on the target voltage drop file using the static timing analysis tool. The required information is read out and written into the generated target voltage drop file in the form of a tool command, which discards redundant information and can be directly called in the static timing analysis tool, thereby improving the execution efficiency and iteration speed of the static timing analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 1 ;

[0050] Figure 2 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 2 ;

[0051] Figure 3 A schematic diagram of a target array provided in an embodiment of the present application;

[0052] Figure 4 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 3 ;

[0053] Figure 5 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 4 ;

[0054] Figure 6 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 5 ;

[0055] Figure 7 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 6 ;

[0056] Figure 8 A schematic diagram of a specific target voltage drop file generation process provided in an embodiment of the present application;

[0057] Figure 9 A schematic diagram of the structure of a static timing analysis device provided in an embodiment of the present application;

[0058] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0060] As the impact of dynamic voltage drop on timing becomes increasingly prominent, in each link of the physical design sign-off check, when the static timing analysis is close to convergence, it is necessary to introduce the impact of dynamic voltage drop in the static timing analysis to make the static timing analysis results more realistic and reliable.

[0061] During implementation, a power consumption and voltage analysis tool (which also has voltage drop analysis capabilities) must generate raw voltage drop files for all millions of logic cells in the design. This raw voltage drop file must then be read into a static timing analysis tool. For a design with over three million logic cells, for example, a 20-cycle raw voltage drop file for all logic cells would take up approximately 30GB of disk space. Reading this file into the static timing analysis tool and generating the specified data structure would take over two hours, an unacceptable amount of disk space and file read-in time.

[0062] Based on this, before performing static timing analysis, this application uses tool commands to read the required information from the original voltage drop file and write it into the generated target voltage drop file. Compared with the original voltage drop file, the target voltage drop file discards redundant information, avoids information redundancy and repetition, greatly reduces the file size, and can be directly called in the static timing analysis tool, thereby improving the execution efficiency and iteration speed of static timing analysis.

[0063] Figure 1 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 1 The execution subject of this embodiment may be an electronic device, such as a device capable of static timing analysis.

[0064] like Figure 1 As shown, the method may include:

[0065] S101 : Perform voltage drop analysis on at least one logic unit on a target timing path to obtain an original voltage drop file.

[0066] The target timing path is a timing path of the chip, and the target timing path has at least one logic unit, such as a register, an inverter, a buffer, etc.

[0067] In some embodiments, after physical layout is performed based on the chip's netlist file, a power analysis tool is launched and used to perform voltage drop analysis on at least one logic unit on the chip's target timing path, generating a raw voltage drop file. The raw voltage drop file includes various voltage drop information for each logic unit. Power analysis tools typically also include voltage drop analysis functionality.

[0068] Various voltage drop information may include: the maximum voltage drop of each logic unit during the simulation period, the maximum voltage drop of each logic unit in its time window, the maximum voltage drop of each logic unit in its actual flip time, the number of timing cycles of each logic unit, the maximum and minimum average values ​​of voltage drops in the time window of the rising and falling edges of each logic unit in each timing cycle (that is, the maximum dynamic voltage drop, minimum dynamic voltage drop, and average dynamic voltage drop in the signal flip direction in each timing cycle), the maximum and minimum average values ​​of voltage drops in the actual flip time of the rising and falling edges of the unit, power supply information, grounding information, etc.

[0069] S102 : Obtain the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file according to the read information indicated by the read command of the static timing analysis tool.

[0070] The read command of the static timing analysis tool is an embedded command of the static timing analysis tool, and the read information indicated by the read command may include the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction.

[0071] After starting the static timing analysis tool, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction are read from the original voltage drop file according to the read information indicated by the read command of the static timing analysis tool. The dynamic voltage drop is the dynamic voltage drop generated based on the signal flip direction of each logic unit. The signal flip direction includes a rising edge direction and a falling edge direction. The signal flip direction is represented by "1" or "0", "1" represents the rising edge direction, and "0" represents the falling edge direction.

[0072] Dynamic voltage drop refers to the voltage drop caused by the increase in transient current peaks due to the simultaneous switching of a large number of transistors and combinational logic circuits during normal circuit operation. Specifically, each logic cell experiences a voltage drop at the moment of a signal flip, either due to a rising edge flip or a falling edge flip.

[0073] It is worth noting that the voltage drop information in this article is represented by the actual supply voltage output by the power consumption analysis tool. The difference between the preset ideal supply voltage and the dynamic voltage drop corresponding to the signal flipping direction of each logic unit is determined as the actual supply voltage of each logic unit in the signal flipping direction. In other words, the dynamic voltage drop of each logic unit is represented by the actual supply voltage.

[0074] S103 , generating a target voltage drop file by reversing the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool.

[0075] Among them, the write command of the static timing analysis tool is an embedded command of the static timing analysis tool. The data format indicated by the write command can be, for example, an array format. After starting the preset timing analysis tool, the signal flip direction and dynamic voltage drop are written in this data format to generate a target voltage drop file. The target voltage drop file includes: the signal flip direction and dynamic voltage drop of each logic unit under this data format.

[0076] S104. Use a static timing analysis tool to perform static timing analysis on the target voltage drop file.

[0077] When performing static timing analysis, the target voltage drop file is read into the static timing analysis tool, and the signal flip direction and dynamic voltage drop of each logic unit are read from the target voltage drop file. Based on the dynamic voltage drop, the voltage of each logic unit is reversed in the signal flip direction to obtain the timing analysis results.

[0078] In this embodiment, the required information is read from the original voltage drop file and written into the generated target voltage drop file in the form of tool commands. Compared with the original voltage drop file, the target voltage drop file discards redundant information, avoids information redundancy and repetition, and greatly reduces the file size. In addition, due to the use of embedded commands of the static timing analysis tool, it can be directly called in the static timing analysis tool, thereby improving the execution efficiency and iteration speed of the static timing analysis.

[0079] Figure 2 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 2 ,like Figure 2 As shown, in an optional embodiment, the above step S102, according to the read information indicated by the read command of the static timing analysis tool, obtains the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file, which may include:

[0080] S201 , according to the read information indicated by the read command, obtain the signal flip direction and dynamic voltage drop of each logic unit in its own multiple timing cycles from the original voltage drop file.

[0081] The original voltage drop file includes various voltage drop information of each logic unit in its own multiple timing cycles.

[0082] The read information indicated by the read command may include: the signal flip direction and dynamic voltage drop of each logic unit within its own timing cycle. Since different logic units may belong to different frequency clock domains, the timing cycles of different logic units may be different (including different cycle lengths and different numbers of cycles).

[0083] According to the read information indicated by the read command, the signal flip directions of each logic unit in the respective multiple timing cycles and the dynamic voltage drops corresponding to the signal flip directions are read from the original voltage drop file.

[0084] In some embodiments, the read command includes a num_cycles() command and a for…in…rang() command, and the read information indicated by the num_cycles command (i.e., the number of timing cycles) is used to read the number of respective timing cycles of each logic unit from the original voltage drop file, wherein the number of respective timing cycles of each logic unit is multiple, that is, each logic unit has multiple respective timing cycles, and the read information indicated by the for…in…rang() command is used to loop through each timing cycle of each logic unit to read the signal flip direction and dynamic voltage drop of each logic unit in the respective multiple timing cycles from the original voltage drop file.

[0085] The above step S103, generating a target voltage drop file by reversing the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool, may include:

[0086] S202 : Write the signal inversion direction, dynamic voltage drop, and period identifier of the corresponding timing period into the target array indicated by the data format to generate a target voltage drop file.

[0087] The target voltage drop file includes a target array corresponding to each logic unit, which includes the signal flip direction, dynamic voltage drop and the period identifier of the corresponding timing period, wherein the period identifier of the corresponding timing period is used to indicate the timing period corresponding to the signal flip direction and dynamic voltage drop.

[0088] In an optional embodiment, the above step S202 of writing the signal flip direction, dynamic voltage drop, and period identifier of the corresponding timing period into the target array indicated by the data format to generate the target voltage drop file may include:

[0089] The unit name of each logical unit is used as the array element name of the target array;

[0090] The signal flip direction, dynamic voltage drop and period identifier of the corresponding timing period are used as array element values ​​of the target array;

[0091] Generate a target voltage drop file based on the target array.

[0092] The unit name of each logic unit is used as the element name of the target array, and the signal flip direction, dynamic voltage drop and period identifier of each logic unit in the corresponding timing period are written into the target array as array element values. A target voltage drop file is generated based on the target array, and the target voltage drop file includes: the target array corresponding to each logic unit.

[0093] In an optional implementation, using the signal flip direction, the dynamic voltage drop, and the period identifier of the corresponding timing period as the array element value of the target array may include:

[0094] The cycle identifier and the signal flip direction of the corresponding timing cycle are used as the key of the dictionary in the target array, and the dynamic voltage drop is used as the value of the key;

[0095] Pass the dictionary as the array element value of the destination array.

[0096] Among them, the array element value is a dictionary, and the period identifier and signal flip direction of the corresponding timing period are used as the keywords of the dictionary in the target array, and the dynamic voltage drop is used as the value of the keyword. The period identifier is expressed in integer form, the number of periods is expressed in integer form, and the signal flip direction is expressed as "1" or "0". "1" indicates the rising edge direction, and "0" indicates the falling edge direction. The period identifier and the signal flip direction are connected with "_".

[0097] Taking the target array dvd_info as an example, the dynamic voltage drop of each logic unit at the rising or falling edge in the corresponding timing cycle is used as the array element value of dvd_info in the form of a dictionary. The array element name is the unit name of the logic unit:

[0098] set dvd info(inst_name_1)"0_1 0.79356 0_0 0.793157……20_00.78312120_1 0.795369"

[0099] set dvd info(inst_name_2)"0_1 0.79463 0_0 0.79472……20_0 0.7867420_10.797452"

[0100] …

[0101] set dvd info(inst_name_n+1)"0_1 0.79052 0_0 0.798653...20_00.78803220_1 0.795483"

[0102] In which, inst_name_1, inst_name_2, ..., inst_name_n+1 respectively represent the first logical unit named inst_name_1, the second logical unit named inst_name_2, and the n+1th logical unit named inst_name_n+1.

[0103] 0_1 0.79356 indicates that the dynamic voltage drop of the first logic unit named inst_name_1 in the rising edge direction of the first timing cycle is 0.79356, 0_0 0.793157 indicates that the dynamic voltage drop of this logic unit in the falling edge direction of the first timing cycle is 0.793157, 20_0 0.783121 indicates that the dynamic voltage drop of this logic unit in the falling edge direction of the 21st timing cycle is 0.783121, and 20_1 0.795369 indicates that the dynamic voltage drop of this logic unit in the rising edge direction of the 21st timing cycle is 0.795369. Similarly, 0_1 0.79052 means that the dynamic voltage drop of the logic unit with the n+1th unit name inst_name_n+1 in the rising edge direction of the first timing cycle is 0.79052, and 20_10.795483 means that the dynamic voltage drop of this logic unit in the rising edge direction of the 21st timing cycle is 0.795483.

[0104] In some embodiments, the write command includes inst_info=”set dvd_info(“+instance+”)\””\, inst_info=inst_info+str(i)+”_1”+str(rise_voltage)+””, inst_info=inst_info+str(i)+”_0”+str(fall_voltage)+””. The command inst_info=”set dvd_info(“+instance+”)\””\, inst_info=inst_info+str(i)+”_0”+str(fall_voltage)+”” can be used. dvd_info("+instance+")\""\, to indicate that the data is stored in the dictionary. If the flip direction of the logic unit involves the rising edge and the falling edge, the command "inst_info=inst_info+str(i)+"_1"+str(rise_voltage)+""+str(i)+"_0"+str(fall_voltage)+"" can be used to store the dynamic voltage drop in the rising edge direction and the dynamic voltage drop in the falling edge direction in the dictionary. If the flip direction of the logic unit is only the rising edge direction, the command inst_info=inst_info+str(i)+"_1"+str(rise_voltage)+"" can be used to store the dynamic voltage drop in the rising edge direction in the dictionary. If the flip direction of the logic unit is only the falling edge direction, the command inst_info=inst_info+str(i)+"_0"+str(fall_voltage)+"" can be used to store the dynamic voltage drop in the falling edge direction in the dictionary. Among them, the extracted dynamic voltage drop can be in the form of a python string.

[0105] Figure 3A schematic diagram of a target array provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the dynamic voltage drop is represented by the actual supply voltage. For each logic unit, the unit name of the logic unit is used as the array element name of the target array, the cycle number (the cycle identifier corresponding to the timing cycle) and the signal flip direction are used as the keywords of the dictionary in the target array, the voltage information (dynamic voltage drop) is used as the value of the keyword, and the dictionary is used as the array element value of the target array. That is, the array element value is a dictionary formed by the voltage information (actual supply voltage) within multiple timing cycles. Figure 3 It includes n logical units, one logical unit corresponds to one target array, Figure 3 The logic unit 2 is taken as an example for illustration.

[0106] It is worth noting that by defining a data structure (data form) combining an array and a dictionary, this data structure is implemented based on the tool command language (TCL) provided by the static timing analysis tool. In addition, after using the num_cycles() command, you can also use the embedded command inst_info=inst_info=”\”” of the static timing analysis tool to ensure that the TCL syntax format is correct. Finally, you can also use the print() function to output the target array as a target voltage drop file.

[0107] In this embodiment, based on the data format indicated by the TCL command (write command), namely "set dvd_info(inst_name) "0_0v1 0_1v2...", the required information is written into the target voltage drop file in the form of a tool command. The required data format can be obtained by directly executing the write command, which greatly shortens the time for reading in information and speeds up the iteration speed of static timing analysis. In addition, due to the use of the embedded commands of the static timing analysis tool, the execution efficiency of the static timing analysis tool is extremely high. Information that originally took more than 2 hours to read can be written into the specified data format within 1 minute, and there is no need to perform information extraction, thus saving disk space.

[0108] Figure 4 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 3 ,like Figure 4 As shown, in an optional embodiment, before the above step S102, according to the read information indicated by the read command of the static timing analysis tool, obtaining the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file, the method may further include:

[0109] S301 , filtering out information irrelevant to each logic unit in the original voltage drop file, and tabulating the unit name of each logic unit to obtain a unit name list.

[0110] Among them, information irrelevant to each logic unit may include power supply information (VDD) and ground information (VSS). The information irrelevant to each logic unit in the original voltage drop file is filtered out to reduce redundant information interference, and the unit name of each logic unit in the filtered original voltage drop file is listed to obtain a unit name list.

[0111] In some embodiments, the embedded commands of the static timing analysis tool include vim operation instructions, which use vim operation instructions to filter out power supply information and grounding information from the original voltage drop file, retain only information related to each logic unit, and delete all spaces to ensure that the complete unit name of each logic unit is left at the end, and use python's list format as the input of all instantiated unit lists of the script to list and obtain the unit name list "a=[……]".

[0112] Accordingly, the above step S102, which obtains the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file according to the read information indicated by the read command of the static timing analysis tool, may include:

[0113] S302 : Read the signal flip direction and dynamic voltage drop of each logic unit in the unit name list in sequence from the filtered original voltage drop file according to the read information indicated by the read command.

[0114] According to the read information indicated by the read command and according to the unit name list, the signal flip direction and dynamic voltage drop of each logic unit are read in sequence from the filtered original voltage drop file.

[0115] In some embodiments, the reading commands include get_voltage_stats() and get_cycle_over_tw() commands. Based on the unit name list, a "for...in...:" loop is used to read the dynamic voltage drop of each logic unit on the rising or falling edge within its respective multiple timing cycles from the filtered original voltage drop file through get_voltage_stats() and get_cycle_over_tw() commands. In addition, the str function can be used to convert the dynamic voltage drop into a string format that can be matched using a regular expression.

[0116] In some embodiments, if some logic cells cannot capture dynamic voltage drops, Python may output a PobeEmor error, interrupting the program. To prevent this, use the "try..except..." format to ensure the program is not interrupted abnormally and output the problematic data to a file using the print function (a text output function in Python). This phenomenon is caused by incomplete input design data and library data. Complete the input and the error will be avoided.

[0117] Figure 5 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 4 ,like Figure 5 As shown, in an optional embodiment, before generating a target voltage drop file by flipping the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool in step S103, the method may further include:

[0118] S401 : Determine a target logic unit from at least one logic unit according to a dynamic voltage drop.

[0119] During voltage drop analysis, logic cells with a dynamic voltage drop of 0 may be output. Since the dynamic voltage drop is the difference between the preset ideal supply voltage and the actual supply voltage, a dynamic voltage drop of 0 indicates that the actual supply voltage is equal to the preset ideal supply voltage. Logic cells with a dynamic voltage drop of 0 are meaningless for static timing analysis. That is, logic cells with a dynamic voltage drop of 0 do not experience a signal flip in the corresponding timing period and are considered not to be recorded. Therefore, the regular matching module embedded in the static timing analysis tool can be used to eliminate logic cells with a dynamic voltage drop of 0 from at least one logic cell based on the dynamic voltage drop of each logic cell to obtain a target logic cell, wherein the dynamic voltage drop of the target logic cell is not 0.

[0120] Accordingly, the above step S103, which generates a target voltage drop file by reversing the signal direction and the dynamic voltage drop in the data format according to the data format indicated by the write command of the static timing analysis tool, may include:

[0121] S402 : According to the data format indicated by the write command, the signal inversion direction of the target logic unit and the dynamic voltage drop of the target logic unit are in the data format to generate a target voltage drop file.

[0122] The signal flip direction and the dynamic voltage drop are written in a data format to generate a target voltage drop file, which includes the signal flip direction and the dynamic voltage drop of the target logic unit in the data format.

[0123] It is worth noting that the dynamic voltage drop of each logic unit within its respective timing cycle includes four situations: the dynamic voltage drop in the rising edge direction is 0, the dynamic voltage drop in the falling edge direction is 0, the dynamic voltage drop in both the rising and falling edge directions is 0, and the dynamic voltage drop in both the rising and falling edge directions is not 0. By identifying the dynamic voltage drop of each logic unit within its respective multiple timing cycles, the timing cycles in which the dynamic voltage drop is 0 are filtered out, and the dynamic voltage drop of the timing cycles in which the dynamic voltage drop of each logic unit is not 0, the corresponding signal inversion direction, and the cycle identifier of the timing cycle are written into the target array to generate a target voltage drop file.

[0124] Figure 6 The static timing analysis method provided in this application embodiment is shown in FIG. Figure 5 ,like Figure 6 As shown, in an optional embodiment, the dynamic voltage drop includes: a maximum dynamic voltage drop, a minimum dynamic voltage drop, and an average dynamic voltage drop.

[0125] The above step S103, generating a target voltage drop file by reversing the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool, may include:

[0126] S501 : Match an average dynamic voltage drop from the dynamic voltage drops.

[0127] In some embodiments, a regular expression embedded in a static timing analysis tool is used to describe the field of the average dynamic voltage drop. Taking the rising edge as an example, the rising edge field "rise: Min: xxxxx Mean: xxx Count" (corresponding to the minimum dynamic voltage drop and the average dynamic voltage drop, respectively) is obtained through regular matching. The field of the average dynamic voltage drop is then distinguished by a regular expression, and the voltage value corresponding to the field of the average dynamic voltage drop is matched. Finally, the voltage value is processed using the float() and format() functions (floating-point functions and standard format processing functions in Python) to obtain the average dynamic voltage drop. In order to reduce the difficulty and length of script writing, a python function definition can also be used, and the matching voltage value is used as the function return value as the average dynamic voltage drop.

[0128] S502 : According to the data format indicated by the write command, the signal flip direction and the average dynamic voltage drop are converted into the data format to generate a target voltage drop file.

[0129] The signal flip direction and the average dynamic voltage drop are written in data format to generate a target voltage drop file, which includes the signal flip direction and the average dynamic voltage drop of the target logic unit in the data format.

[0130] In this embodiment, static timing analysis is performed by matching the average dynamic voltage drop, which ensures that the static timing analysis is more accurate.

[0131] Figure 7 Schematic diagram of the static timing analysis method provided in this application embodiment Figure 6 ,like Figure 7 As shown, in an optional embodiment, the above step S104, using a static timing analysis tool to perform static timing analysis on the target voltage drop file, may include:

[0132] S601. Use a static timing analysis tool to obtain a signal flip direction and a dynamic voltage drop according to a target voltage drop file.

[0133] In some embodiments, a source command embedded in a static timing tool (a command for executing file reading in the tool) is used to read the signal flip direction and dynamic voltage drop of each logic unit from a target voltage drop file.

[0134] In an optional embodiment, the above step S601, using a static timing analysis tool to obtain the signal flip direction and dynamic voltage drop according to the target voltage drop file, may include:

[0135] A static timing analysis tool is used to read the array element value of the target array from the target voltage drop file, and the signal flip direction and the dynamic voltage drop are obtained according to the array element value of the target array.

[0136] Among them, the embedded commands of the static timing analysis tool also include the array names command (a command that returns the names of all elements of an array in the form of a list), the array get command (an array value command that returns the value of the array element), and the dict get command (a dictionary value command that returns the value of a keyword). A timing cycle is taken as the current analysis condition, and the array names command is used to traverse all logic units using the foreach (a loop statement in TCL) statement. The array get command is used to read the array element value of the target array from the target voltage drop file, wherein the data element value includes the keyword of the dictionary connected by an underscore, and the keyword includes the period identifier and signal flip direction of the corresponding timing cycle. The dict get command is used to retrieve the keyword value as the dynamic voltage drop corresponding to the logic unit in the signal direction, wherein the dynamic voltage drop is characterized by the actual power supply voltage.

[0137] S602 : Based on the dynamic voltage drop, perform voltage inversion on each logic unit in the signal flipping direction to perform static timing analysis.

[0138] The difference between the preset ideal supply voltage and the dynamic voltage drop of each logic unit is determined as the actual supply voltage of each logic unit in the signal flipping direction.

[0139] If the signal flip direction is the rising edge direction, the actual supply voltage of the logic unit in the signal flip direction is the rising edge voltage. The rising edge voltage refers to the actual transient supply voltage on the logic unit when the signal flips from 0 to 1. If the signal flip direction is the falling edge direction, the actual supply voltage of the logic unit in the signal flip direction is the falling edge voltage. The falling edge voltage refers to the actual transient supply voltage on the logic unit when the signal flips from 1 to 0.

[0140] According to the actual supply voltage, the voltage of each logic unit is reversed in the signal flip direction. That is, the supply voltage of each logic unit in the signal flip direction is set to the actual supply voltage. After the supply voltage of all logic units is successfully set, static timing analysis is performed on the target timing path to obtain the timing analysis results.

[0141] It is worth noting that, by characterizing the dynamic voltage drop with the actual supply voltage, the voltage of each logic unit can be directly reverse-labeled in the signal flipping direction based on the dynamic voltage drop to perform static timing analysis.

[0142] In some embodiments, for each timing cycle of the logic unit, voltage back-labeling may be performed on the logic unit in the signal flipping direction within each timing cycle according to the dynamic voltage drop of each timing cycle to perform static timing analysis.

[0143] Among them, the embedded commands of the static timing analysis tool also include the "set voltage" command (voltage setting command). For the current timing cycle of each logic unit, the "set voltage" command is used to set the voltage of each logic unit. After all logic units are set successfully, static timing analysis is performed. Then, for the next timing cycle of each logic unit, the above process is repeated to complete the static timing analysis of all timing cycles.

[0144] It is worth noting that the voltage on the target timing path needs to take the supply voltage at the corresponding rising or falling edge. At the clock input end, the rising edge needs to be reversed each time it passes through an inverter. For example, after passing through a buffer or clock gating, the flip direction of the edge taken is the same as the flip direction of the previous level logic unit of this logic unit. If it passes through an inverter or a device with a signal inversion function, the signal flip direction is opposite to the flip direction of the previous level logic unit of this logic unit, starting from the clock input end until it reaches the clock input end of the register. Therefore, the voltage value of the logic unit on the clock path in each timing cycle needs to take the value of its corresponding flip direction. Therefore, the dynamic voltage drop of the rising edge and the dynamic voltage drop of the falling edge of the logic unit in each timing cycle need to be indicated in the target voltage drop file.

[0145] In this embodiment, since the embedded commands of the static timing analysis tool are used to read and write the target voltage drop file from the original voltage drop file, it can be directly called in the static timing analysis tool when performing static timing analysis, thereby improving the execution efficiency and iteration speed of the static timing analysis.

[0146] The generation process of the target voltage drop file provided by this solution is described below with reference to a specific embodiment.

[0147] Figure 8 A schematic diagram of a specific target voltage drop file generation process provided in an embodiment of the present application is shown as follows: Figure 8 As shown, the following steps are included:

[0148] Step 1: Use power analysis tools to analyze the voltage drop of each logic unit.

[0149] Step 2: Use vim operation instructions to list and obtain a unit name list (python list).

[0150] Step 3: Traverse the unit name list and determine whether the list traversal is complete.

[0151] If the list traversal is completed, the target voltage file is output and the process ends.

[0152] Step 4: If the traversal is not completed, obtain the dynamic voltage drop of the logic unit.

[0153] Step 5: Determine whether the tool reports an error.

[0154] If an error is reported, return to step 4 and re-acquire the dynamic voltage drop of the logic unit.

[0155] Step 6: If no error is reported, obtain the flip cycle of the logic unit.

[0156] The flip cycle of a logic unit is the timing period during which the logic unit undergoes a logic change.

[0157] Step 7: Determine whether the obtained dynamic voltage drop of the logic unit is within the flip cycle.

[0158] Step 8: If it is within the reversal period, the dynamic voltage drop within the reversal period is obtained through regular matching.

[0159] Step 9: Determine whether the dynamic voltage drop is 0.

[0160] If it is 0, return to step 7 and continue.

[0161] Step 10: If it is not 0, obtain the average dynamic voltage drop through regular matching.

[0162] Step 11: Write the target voltage drop file using a data structure combining an array and a dictionary.

[0163] Step 12: Execute the above steps 1 to 11 for the next logical unit.

[0164] Figure 9 This is a structural diagram of a static timing analysis device provided in an embodiment of the present application, which can be integrated into an electronic device.

[0165] like Figure 9 As shown, the device may include:

[0166] An analysis module 701 is configured to perform voltage drop analysis on at least one logic unit on a target timing path to obtain an original voltage drop file, wherein the original voltage drop file includes: various voltage drop information of each logic unit;

[0167] An acquisition module 702 is configured to acquire the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file according to the read information indicated by the read command of the static timing analysis tool;

[0168] A generating module 703 is configured to generate a target voltage drop file by reversing the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool;

[0169] The analysis module 701 is further configured to perform static timing analysis on the target voltage drop file using a static timing analysis tool.

[0170] In an optional embodiment, the original voltage drop file includes: a plurality of voltage drop information of each logic unit in a plurality of respective timing cycles;

[0171] The acquisition module 702 is specifically configured to:

[0172] According to the read information indicated by the read command, the signal flip direction and dynamic voltage drop of each logic unit in each of the plurality of timing cycles are obtained from the original voltage drop file;

[0173] According to the data format indicated by the write command of the static timing analysis tool, the signal flip direction and dynamic voltage drop are converted into a target voltage drop file according to the data format, including:

[0174] The signal inversion direction, dynamic voltage drop, and period identifier of the corresponding timing period are written into the target array indicated by the data format to generate a target voltage drop file.

[0175] In an optional implementation, the acquisition module 702 is specifically configured to:

[0176] The unit name of each logical unit is used as the array element name of the target array;

[0177] The signal flip direction, dynamic voltage drop and period identifier of the corresponding timing period are used as array element values ​​of the target array;

[0178] Generate a target voltage drop file based on the target array.

[0179] In an optional implementation, the acquisition module 702 is specifically configured to:

[0180] The cycle identifier and the signal flip direction of the corresponding timing cycle are used as the dictionary key, and the dynamic voltage drop is used as the value of the key;

[0181] Pass the dictionary as the array element value of the destination array.

[0182] In an optional implementation, the acquisition module 702 is further configured to:

[0183] Filter out the information irrelevant to each logic unit in the original voltage drop file, and list the unit names of each logic unit to obtain a unit name list;

[0184] The acquisition module 702 is specifically configured to:

[0185] According to the read information indicated by the read command, the signal flip direction and the dynamic voltage drop of each logic unit in the unit name list are sequentially read from the filtered original voltage drop file.

[0186] In an optional implementation, the acquisition module 702 is further configured to:

[0187] determining a target logic cell from at least one logic cell according to the dynamic voltage drop;

[0188] The acquisition module 702 is specifically configured to:

[0189] According to the data format indicated by the write command, the signal direction of the target logic unit and the dynamic voltage drop of the target logic unit are flipped according to the data format to generate a target voltage drop file.

[0190] In an optional embodiment, the dynamic voltage drop includes: a maximum dynamic voltage drop, a minimum dynamic voltage drop, and an average dynamic voltage drop;

[0191] The generation module 703 is specifically configured to:

[0192] Matching the average dynamic voltage drop from the dynamic voltage drop;

[0193] According to the data format indicated by the write command, the signal inversion direction and the average dynamic voltage drop are adjusted according to the data format to generate a target voltage drop file.

[0194] In an optional implementation, the analysis module 701 is specifically configured to:

[0195] Use static timing analysis tools to obtain signal flip direction and dynamic voltage drop based on the target voltage drop file;

[0196] Based on the dynamic voltage drop, the voltage of each logic unit is reversed in the signal flip direction to perform static timing analysis.

[0197] In an optional implementation, the analysis module 701 is specifically configured to:

[0198] A static timing analysis tool is used to read the array element value of the target array from the target voltage drop file, and the signal flip direction and the dynamic voltage drop are obtained according to the array element value of the target array.

[0199] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference can be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0200] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Figure 10 As shown, the device may include: a processor 801, a memory 802 and a bus 803. The memory 802 stores machine-readable instructions executable by the processor 801. When the electronic device is running, the processor 801 communicates with the memory 802 through the bus 803, and the processor 801 executes the machine-readable instructions to perform the above method.

[0201] In the embodiment of the present application, the computer program can also execute other machine-readable instructions when run by the processor to execute other methods described in the embodiment. For the specific execution method steps and principles, please refer to the description of the embodiment and will not be repeated here.

[0202] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0203] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0204] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0205] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0206] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0207] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed in the present application, or make equivalent replacements for some of the technical features thereof. However, these modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A static timing analysis method, characterized in that: include: Performing voltage drop analysis on at least one logic unit on a target timing path to obtain an original voltage drop file, wherein the original voltage drop file includes: various voltage drop information of each logic unit; Obtaining, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool; According to the data format indicated by the write command of the static timing analysis tool, the signal flip direction and the dynamic voltage drop are adjusted according to the data format to generate a target voltage drop file; The static timing analysis tool is used to perform static timing analysis on the target voltage drop file.

2. The method according to claim 1, characterized in that The original voltage drop file includes: various voltage drop information of each logic unit in its respective multiple timing cycles; The acquiring, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool, includes: Obtaining, from the original voltage drop file, the signal flipping direction and the dynamic voltage drop of each logic unit within the respective plurality of timing cycles according to the read information indicated by the read command; The step of generating a target voltage drop file by flipping the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool includes: The signal inversion direction, the dynamic voltage drop, and the period identifier of the corresponding timing period are written into the target array indicated by the data format to generate the target voltage drop file.

3. The method according to claim 2, characterized in that Writing the signal flip direction, the dynamic voltage drop, and the period identifier of the corresponding timing period into the target array indicated by the data format to generate the target voltage drop file includes: Using the unit name of each logical unit as the array element name of the target array; Using the signal flip direction, the dynamic voltage drop, and the period identifier of the corresponding timing period as array element values ​​of the target array; The target voltage drop file is generated according to the target array.

4. The method according to claim 3, characterized in that The step of using the signal flip direction, the dynamic voltage drop, and the period identifier of the corresponding timing period as the array element value of the target array includes: Using the period identifier of the corresponding timing period and the signal flip direction as keywords of a dictionary, and using the dynamic voltage drop as a value of the keyword; Use the dictionary as the array element value of the target array.

5. The method according to claim 1, wherein Before obtaining the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction from the original voltage drop file according to the read information indicated by the read command of the static timing analysis tool, the method further includes: Filtering out information irrelevant to the logic units in the original voltage drop file, and listing the unit names of the logic units to obtain a unit name list; The acquiring, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool, includes: According to the read information indicated by the read command, the signal flip direction and the dynamic voltage drop of each logic unit in the unit name list are sequentially read from the filtered original voltage drop file.

6. The method according to claim 1, characterized in that Before generating a target voltage drop file by flipping the direction of the signal and generating the target voltage drop file by adjusting the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool, the method further includes: determining a target logic unit from the at least one logic unit according to the dynamic voltage drop; The step of generating a target voltage drop file by flipping the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool includes: According to the data format indicated by the write command, the signal direction of the target logic unit and the dynamic voltage drop of the target logic unit are flipped according to the data format to generate the target voltage drop file.

7. The method according to claim 1, characterized in that The dynamic voltage drop includes: maximum dynamic voltage drop, minimum dynamic voltage drop and average dynamic voltage drop; The step of generating a target voltage drop file by flipping the signal direction and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool includes: Matching the average dynamic voltage drop from the dynamic voltage drops; According to the data format indicated by the write command, the signal direction is flipped and the average dynamic voltage drop is adjusted according to the data format to generate the target voltage drop file.

8. The method according to claim 3, characterized in that The performing static timing analysis on the target voltage drop file using the static timing analysis tool includes: Using the static timing analysis tool, according to the target voltage drop file, the signal flip direction and the dynamic voltage drop are obtained; According to the dynamic voltage drop, voltage reverse labeling is performed on each logic unit in the signal flipping direction to perform static timing analysis.

9. The method according to claim 8, characterized in that The adopting the static timing analysis tool to obtain the signal flip direction and the dynamic voltage drop according to the target voltage drop file includes: The static timing analysis tool is used to read the array element value of the target array from the target voltage drop file, and the signal flip direction and the dynamic voltage drop are obtained according to the array element value of the target array.

10. A static timing analysis device, characterized in that: include: an analysis module, configured to perform voltage drop analysis on at least one logic unit on a target timing path to obtain an original voltage drop file, wherein the original voltage drop file includes: various voltage drop information of each logic unit; an acquisition module, configured to acquire, from the original voltage drop file, the signal flip direction of each logic unit and the dynamic voltage drop corresponding to the signal flip direction according to the read information indicated by the read command of the static timing analysis tool; a generating module, configured to generate a target voltage drop file by flipping the direction of the signal and the dynamic voltage drop according to the data format indicated by the write command of the static timing analysis tool; The analysis module is further configured to perform static timing analysis on the target voltage drop file using the static timing analysis tool.

11. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and the processor executes the machine-readable instructions to perform the method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is executed.

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